The “Ground” Myth
Bruce Archambeault, Ph.D.
IBM Distinguished Engineer, IEEE Fellow
barch@us.ibm.com
18 November 2008
IEEE
Introduction
• Electromagnetics can be scary
– Universities LOVE messy math
• EM is not hard, unless you want to do the
messy math
• Goal:
– Intuitive understanding
– Understand the basic fundamentals
– Understand how to read the math
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Bruce Archambeault, PhD
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Overview
•
•
•
•
•
•
•
What does the derivative mean?
What does integration mean?
Weird vector notation
In the beginning – Faraday and Maxwell
Inductance
“Ground”
Primary cause of EMI problems on
PCBs
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Derivative
• How fast is something
changing?
d
[something ]
dt
d
[something ]
dx
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Changing with
respect to time
Changing with respect
to position (x)
Bruce Archambeault, PhD
5
Partial Derivative
• How fast is something changing for
one variable?
∂
[something (t , x)]
∂t
∂
[something (t , x)]
∂x
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Changing with respect
to time (as ‘x’ is
constant)
Changing with respect
to position (x) (as time
is constant)
Bruce Archambeault, PhD
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Integration
• Simply the sum of parts (when the parts
are very small)
– Line Integral --- sum of small line segments
– Surface Integral -- sum of small surface
patches
– Volume Integral -- sum of small volume blocks
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Line Integral
(find the length of the path)
‘piece’ of E field
dl
stop →
V = − ∫ ( E • dl )
start
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Line Integral -- Closed
Circumference = ∫ path around box
=
x =l
y=w
x =0
y =0
x =0
y =0
x =l
y=w
∫ dx + ∫ dy + ∫ dx + ∫ dy
y
x
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Line Integral -- Closed
• Closed line integrals
find the path length
• And/or the amount of
some quantity along
that closed path length
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Surface Integral
(find the area of the surface)
Area = ∫ da
da = dx ∗ dy
Area = ∫∫ dx ∗ dy
As dx and dy become
smaller and smaller, the
area is better calculated
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Volume Integral
(find the volume of an object)
Volume = ∫ dv
dv = dx ∗ dy ∗ dz
Volume = ∫∫∫[dx ∗ dy ∗ dz ]
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Electromagnetics
In the Beginning
• Electric and Magnetic effects not
connected
• Electric and magnetic effects were due to
‘action from a distance’
• Faraday was the 1st to propose a
relationship between electric lines of force
and time-changing magnetic fields
– Faraday was very good at experiments and
‘figuring out’ how things work
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Maxwell
• Maxwell was
impressed with
Faraday’s ideas
• Discovered the
mathematical link
between the “electro”
and the “magnetic”
• Scotland’s greatest
contribution to the
world (next to Scotch)
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“Maxwell’s Equations”
• Maxwell’s original work included 20
equations!
• Heaviside reduced them to the existing
four equations
– Heaviside refused to call the equations his
own
• Hertz is credited with proving they are
correct
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Maxwell’s Equations
are NOT Hard!
∂D
∇×H = J +
∂t
∂B
∇×E = −
∂t
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Maxwell’s Equations are not Hard!
• Change in H-field across space ¡ Change
in E-field (at that point) with time
• Change in E-field across space ¡ Change
in H-field (at that point) with time
• (Roughly speaking, and ignoring
constants)
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Current Flow
• Most important concept of EMC
• Current flow through metal changes as
frequency increases
• DC current
– Uses entire conductor
– Only resistance inhibits current
• High Frequency
– Only small part of conductor (near surface) is used
– Resistance is small part of current inhibitor
– Inductance is major part of current inhibitor
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Skin Depth
• High frequency current flows only near the
metal surface at high frequencies
1
δ=
π fμσ
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Frequency
60 Hz
1 KHz
10 KHz
100 KHz
1 MHz
10 MHz
100 MHz
1 GHz
Bruce Archambeault, PhD
Skin Depth
260 mils
82 mils
26 mils
8.2 mils
2.6 mils
0.82 mils
0.26 mils
0.0823 mils
Skin Depth
8.5 mm
2.09 mm
0.66 mm
0.21 mm
0.066 mm
0.021 mm
0.0066 mm
0.0021 mm
19
Inductance
• Current flow through metal =>
inductance!
• Fundamental element in EVERYTHING
• Loop area first order concern
• Inductive impedance increases with
frequency and is MAJOR concern at
high frequencies
X L = 2πfL
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Current Loop => Inductance
Courtesy of Elya Joffe
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Inductance Definition
• Faraday’s Law
∂B
∫ E ⋅ dl = − ∫∫ ∂t ⋅ dS
• For a simple rectangular loop
Area = A
V
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B
∂B
V = −A
∂t
The minus sign means that the induced
voltage will work against the current that
originally created the magnetic field!
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Self Inductance
• Isolated circular loop
⎞
⎛ 8a
L ≈ μ 0 a⎜⎜ ln − 2 ⎟⎟
⎠
⎝ r0
• Isolated rectangular loop
2
⎛
⎞
p
1
p
+
+
2μ0 a ⎜
1
1
2 ⎟
L=
ln
1+ p
+ −1 + 2 −
⎜ 1+ 2
⎟
p
p
π
⎝
⎠
Note that inductance is directly influenced
by loop AREA and only less influenced by
conductor size!
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p=
length of side
wire radius
23
Partial Inductance
• Simply a way to break the overall loop
into pieces in order to find total
inductance
L2
L1
L3
L4
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L total=Lp11+ Lp22 + Lp33 + Lp44 - 2Lp13 - 2Lp24
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Important Points About
Inductance
• Inductance is everywhere
• Loop area most important
• Inductance is everywhere
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Decoupling Capacitor Mounting
• Keep as to planes as close to capacitor
pads as possible
Via Separation
Inductance Depends
on Loop AREA
Height above Planes
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Via Configuration Can Change
Inductance
SMT Capacitor
Via
Best
The “Good”
Capacitor Pads
The “Bad”
Better
The “Ugly”
Really “Ugly”
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Comparison of Decoupling Capacitor Impedance
100 mil Between Vias & 10 mil to Planes
1000
1000pF
100
0.01uF
Impedance (ohms)
0.1uF
1.0uF
10
1
0.1
0.01
1.0E+06
1.0E+07
1.0E+08
1.0E+09
1.0E+10
Frequency (Hz)
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Comparison of Decoupling Capacitor
Via Separation Distance Effects
Via Separation
10 mils
0603 Typical
Minimum
Dimensions
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Connection Inductance for Typical
Capacitor Configurations
Distance into board
to planes (mils)
0805 typical/minimum
(148 mils between via
barrels)
0603
typical/minimum
(128 mils between via
barrels)
0402 typical/minimum
(106 mils between via
barrels)
10
1.2 nH
1.1 nH
0.9 nH
20
1.8 nH
1.6 nH
1.3 nH
30
2.2 nH
1.9 nH
1.6 nH
40
2.5 nH
2.2 nH
1.9 nH
50
2.8 nH
2.5 nH
2.1 nH
60
3.1 nH
2.7 nH
2.3 nH
70
3.4 nH
3.0 nH
2.6 nH
80
3.6 nH
3.2 nH
2.8 nH
90
3.9 nH
3.5 nH
3.0 nH
100
4.2 nH
3.7 nH
3.2 nH
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‘Ground’
• Ground is a place where
potatoes and carrots thrive!
• ‘Earth’ or ‘reference’ is more descriptive
• Original use of “GROUND”
• Inductance is everywhere
X L = 2πfL
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What we Really Mean when we
say ‘Ground’
•
•
•
•
November 2008
Signal Reference
Power Reference
Safety Earth
Chassis Shield Reference
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‘Ground’ is NOT a Current Sink!
• Current leaves a driver on a trace and
must return (somehow) to its source
• This seems basic, but it is often forgotten,
and is most often the cause of EMC
problems
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‘Grounding’ Needs Low Impedance
at Highest Frequency
• Steel Reference Plate
– 4 milliohms/sq @ 100KHz
– 40 milliohms/sq @ 10 MHz
– 400 milliohms/sq @ 1 GHz
• A typical via is about 2
nH
–
–
–
–
November 2008
@ 100 MHz
@ 500 MHz
@ 1000 MHz
@ 2000 MHz
Z = 1.3 ohms
Z = 6.5 ohms
Z = 13 ohms
Z = 26 ohms
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Where did the Term “GROUND”
Originate?
• Original Teletype connections
• Lightning Protection
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Ground/Earth
Teletype
Receiver
Teletype
Transmitter
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Ground/Earth
Teletype
Receiver
Teletype
Transmitter
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Lightning striking house
FIG 7
Lightning
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Lightning effect without rod
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Lightning effect with rod
Lightning
Lightning rod
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What we Really Mean when we
say ‘Ground’
•
•
•
•
Signal Reference
Power Reference
Safety Earth
Chassis Shield Reference
Circuit
“Ground”
November 2008
Chassis
“Ground”
D
A
Digital
“Ground”
Analog
“Ground”
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Schematic with return current
shown
IC1
Signal trace currents
IC2
IC3
Return currents on ground
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Actual Current Return is 3-Dimensional
Signal Trace
IC
Ground Vias
BOARD STACK UP:
Signal Trace
Ground Via IC
CURRENT LOCATION:
Signal Trace
Ground Layer
Ground Layer
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Ground Layer
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Low Frequency Return Currents
Take Path of Least Resistance
Driver
Receiver
Ground Plane
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High Frequency Return Currents Take
Path of Least Inductance
Driver
Receiver
Ground Plane
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PCB Example for Return Current
Impedance
Trace
GND Plane
22” trace
10 mils wide, 1 mil thick, 10 mils above GND plane
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PCB Example for Return Current
Impedance
Trace
GND Plane
Shortest DC path
For longest DC path, current returns under trace
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MoM Results for Current Density
Frequency = 1 KHz
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MoM Results for Current Density
Frequency = 1 MHz
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U-shaped Trace Inductance
PowerPEEC Results
0.6
0.55
0.5
inductance (uH)
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
1.0E+03
1.0E+04
1.0E+05
1.0E+06
1.0E+07
1.0E+08
Frequency (Hz)
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Traces/nets over a Reference Plane
Microstrip Transmission Line
Signal Trace
Reference Planes
Dielectric
Stripline Transmission Line
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Traces/nets and Reference Planes
in Many Layer Board Stackup
Signal Traces
Reference Planes
(Power, “Ground”, etc.)
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Microstrip Electric/Magnetic Field Lines
(8mil wide trace, 8 mils above plane, 65 ohm)
Electric Field Lines
Vcc
Courtesy of Hyperlynx
November 2008
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Microstrip Electric/Magnetic Field Lines
Common Mode
8 mil wide trace, 8 mils above plane, 65/115 ohm)
Electric Field Lines
Vcc
Courtesy of Hyperlynx
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Microstrip Electric/Magnetic Field Lines
Differential Mode
8 mil wide trace, 8 mils above plane, 65/115 ohm)
Electric Field Lines
Vcc
Courtesy of Hyperlynx
November 2008
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Electric/Magnetic Field Lines
Symmetrical Stripline
GND
Vcc
Courtesy of Hyperlynx
November 2008
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Electric/Magnetic Field Lines
Symmetrical Stripline (Differential)
GND
Vcc
Courtesy of Hyperlynx
November 2008
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Electric/Magnetic Field Lines
Asymmetrical Stripline
Vcc
GND
Courtesy of Hyperlynx
November 2008
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Electric/Magnetic Field Lines
Asymmetrical Stripline (Differential)
Courtesy of Hyperlynx
November 2008
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What About Pseudo-Differential
Nets?
• So-called differential traces are NOT truly
differential
– Two complementary single-ended drivers
• Relative to ‘ground’
– Receiver is differential
• Senses difference between two nets (independent
of ‘ground’)
• Provides good immunity to common mode noise
• Good for signal quality/integrity
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Pseudo-Differential Nets Current in
Nearby Plane
• Balanced/Differential currents have
matching current in nearby plane
– No issue for discontinuities
• Any unbalanced (common mode) currents
have return currents in nearby plane that
must return to source!
– All normal concerns for single-ended nets
apply!
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Pseudo-Differential Nets
• Not really ‘differential’, since more closely
coupled to nearby plane than each other
• Slew and rise/fall variation cause common
mode currents!
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Differential Voltage Pulse with Skew
1 Gbit/sec with 95 psec rise/fall time
1.2
1
Voltage
0.8
Complementary -- Line1
Complementary -- Line 2
Skew=2ps
Skew=6ps
Skew = 10ps
Skew = 20ps
Skew = 30ps
Skew =40ps
Skew =50ps
Skew =60ps
0.6
0.4
0.2
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Time (nsec)
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64
Common Mode Voltage
From Differential Voltage Pulse with Skew
1 Gbit/sec with 95 psec rise/fall time
0.6
Balanced
Skew=2ps
Skew=6ps
Skew =10ps
Skew =20ps
Skew =30ps
Skew =40ps
Skew =50ps
0.4
Voltage
0.2
0
-0.2
-0.4
-0.6
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Time (nsec)
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Common Mode Current
From Differential Voltage Pulse with Skew
1 Gbit/sec with 95 psec Rise/fall Time
100
80
60
Balanced
Skew=2ps
Skew=6ps
Skew =10ps
Skew =20ps
Skew =30ps
Skew =40ps
Skew =50ps
Skew =60ps
40
Level (ma)
20
0
-20
-40
-60
-80
-100
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Time (nsec)
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66
Common Mode Current
From Differential Voltage Pulse with Skew
1 Gbit/sec with 95 psec Rise/fall Time
150
Skew=2ps
Skew=6ps
Skew =10ps
Skew =20ps
Skew =30ps
Skew =40ps
Skew =50ps
Skew =60ps
140
130
Level (dBuA)
120
110
100
90
80
70
60
50
1.E+08
1.E+09
1.E+10
1.E+11
Frequency (Hz)
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Differential Voltage Pulse with Rise/Fall Variation/Unbalance
1 Gbit/sec with 95 psec Nominal Rise/Fall Time
1.2
1
Level (volts)
0.8
Original Pulse rise=95ps
Complementary Pulse Rise=90ps
Complementary Pulse Rise=80ps
Complementary Pulse Rise=105ps
Complementary Pulse Rise=115ps
0.6
0.4
0.2
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Time (ns)
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Common Mode Voltage
From Differential Voltage Pulse with Various Rise/Fall Unbalance
1 Gbit/sec with 95 psec Nominal Rise/Fall Time
0.2
0.15
0.1
Voltage
0.05
0
-0.05
Complementary Pulse Rise=90ps
-0.1
Complementary Pulse Rise=80ps
Complementary Pulse Rise=105ps
-0.15
Complementary Pulse Rise=115ps
-0.2
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Time (ns)
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Common Mode Current
From Differential Voltage Pulse with Various Rise/Fall Unbalance
1 Gbit/sec with 95 psec Nominal Rise/fall Time
60
40
Current (ma)
20
0
-20
Complementary Pulse Rise=90ps
Complementary Pulse Rise=80ps
Complementary Pulse Rise=105ps
Complementary Pulse Rise=115ps
-40
-60
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Time (ns)
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Common Mode Current
From Differential Voltage Pulse with Various Rise/Fall Unbalance
1 Gbit/sec with Nominal 95 psec Rise/fall Time
90
85
Complementary Pulse Rise=90ps
Complementary Pulse Rise=80ps
Complementary Pulse Rise=105ps
Complementary Pulse Rise=115ps
80
Level (dBua)
75
70
65
60
55
50
1.E+08
1.E+09
1.E+10
1.E+11
Frequency (Hz)
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Antenna Structures
Dipole antenna
Non-Dipole antenna
PCB GND planes
November 2008
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Board-to-Board Differential Pair
Issues
PC
Connecto
r
B
Pl
an
e
2
Micros
trip
Microstrip
V
PCB Plan
e
November 2008
1
Bruce Archambeault, PhD
Ground-to-Ground
noise
73
Example Measured Differential
Individual Signal-to-GND
500 mV P-P (each)
Individual Differential
Signals ADDED
Common Mode Noise
170 mV P-P
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74
Measured GND-to-GND Voltage
205 mV P-P
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75
Pin Assignment Controls
Inductance for CM signals
37.17 nH
(a)
16.85 nH
(c)
20.97 nH
(d)
Signal Pin
November 2008
25.21 nH
(b)
Related Ground Pins
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76
Different pins within Same Pair may
have Different Loop Inductance for CM
“Ground” pins
Differential pair
4
3
pin 1 -- 26.6nH
2
1
pin 2 -- 23.6nH
pin 3 -- 31.8nH
pin 4 -- 28.8nH
November 2008
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77
Pseudo-Differential Net Summary
• Small amounts of skew can cause
significant common mode current
• Small amount of rise/fall time deviation
can cause significant amount of common
mode current
• Discontinuities (vias, crossing split planes,
etc) and convert significant amount of
differential current into common mode
current
November 2008
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78
Return Current vs. “Ground”
• For high frequency signals, “Ground” is a
concept that does not exist
• The important question is “where does
the return current flow?”
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79
Referencing Nets
(Where does the Return Current Flow??)
• Microstrip/Stripline across split in
reference plane
• Microstrip/Stripline through via (change
reference planes)
• Mother/Daughter card
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80
Microstrip/Stripline Across Split
in Reference Plane
• Don’t Cross Splits with Critical Signals!!!
– Bad practice
– Stitching capacitor required across split to
allow return current flow
• must be close to crossing
• must have low inductance
• limited frequency effect --- due to inductance
– Major source of Common Mode current!
November 2008
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81
Splits in Reference Plane
•
•
•
•
Power planes often have splits
Return current path interrupted
Consider spectrum of clock signal
Consider stitching capacitor
impedance
• High frequency harmonics not
returned directly
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82
Split Reference Plane Example
PWR
GND
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Split Reference Plane Example
With Stitching Capacitors
Stitching Capacitors
Allow Return
current to Cross
Splits ???
PWR
GND
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84
Capacitor Impedance
Measured Impedance of .01 uf Capacitor
100.0
Impednace (ohms)
10.0
1.0
0.1
1.E+06
1.E+07
1.E+08
1.E+09
Frequency (Hz)
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85
Frequency Domain Amplitude of Intentional Current Harmonic Amplitude
From Clock Net
160
140
level (dBuA)
120
100
80
60
40
0
200
400
600
800
1000
1200
1400
1600
1800
2000
freq (MHz)
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MoM Microstrip Model Current
Distribution Example
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MoM Microstrip Model Current
Distribution Example
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Emissions From Board
• Far field emissions not important unless it
is an unshielded product
• Near field emissions above board ARE
important
• Example of emissions from board with
critical net crossing split reference plane
November 2008
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89
Near Field Radiation from Microstrip on Board
with Split in Reference Plane
Comparison of Maximum Radiated E-Field for Microstrip
With and without Split Ground Reference Plane
120
110
Maximum Radiated E-Field (dBuv/m)
100
90
80
70
No-Split
60
Split
50
40
30
20
10
100
1000
Frequency (MHz)
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90
With “Perfectly Connected” Stitching Capacitors
Across Split
Comparison of Maximum Radiated E-Field for Microstrip
With and without Split Ground Reference Plane and Stiching Capacitors
120
110
Maximum Radiated E-Field (dBuv/m)
100
90
80
70
60
No-Split
50
Split
Split w/ one Cap
40
Split w/ Two Caps
30
20
10
100
1000
Frequency (MHz)
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91
Stitching Caps with Via Inductance
Comparison of Maximum Radiated E-Field for Microstrip
With and without Split Ground Reference Plane and Stiching Capacitors
120
110
Maximum Radiated E-Field (dBuv/m)
100
90
80
70
60
No-Split
Split
Split w/ one Cap
Split w/ Two Caps
Split w/One Real Cap
Split w/Two Real Caps
50
40
30
20
10
100
1000
Frequency (MHz)
November 2008
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92
Example of Common-Mode Noise Voltage Across Split Plane
Vs. Stitching Capacitor Distance to Crossing Point
25
20
Gap Voltage
15
100MHz
200MHz
300MHz
400MHz
500MHz
600MHz
700MHz
800MHz
900MHz
1000MHz
10
5
0
0
200
400
600
800
1000
1200
1400
1600
1800
2000
Distance (mils)
November 2008
Bruce Archambeault, PhD
93
Are Stitching Capacitors
Effective ???
• YES, at low frequencies
• No, at high frequencies
• Need to limit the high frequency current
spectrum
• Need to avoid split crossings with ALL
critical signals
November 2008
Bruce Archambeault, PhD
94
Pin Field Via Keepouts??
d
s
Return current path
deviation minimal
Return Current must go around
entire keep out area --- just as bad
as a slot
Recommend s/d > 1/3
November 2008
Bruce Archambeault, PhD
95
Changing Reference Planes
Six-Layer PCB Stackup Example
Signal Layer
Plane
Signal Layer
Signal Layer
Plane
Signal Layer
November 2008
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96
Microstrip/Stripline through via
(change reference planes)
Via
November 2008
Trace
Bruce Archambeault, PhD
97
How can the Return Current Flow
When Signal Line Goes Through Via??
What happens to Return Current
in this Region?
Return Current
November 2008
Bruce Archambeault, PhD
98
How can the Return Current Flow
When Signal Line Goes Through
Via??
• Current can NOT go from one side of the
plane to the other through the plane
– skin depth
• Current must go around plane at via hole,
through decoupling capacitor, around second
plane at the second via hole!
• Use displacement current between planes
November 2008
Bruce Archambeault, PhD
99
Return Current Across
Reference Plane Change
What happens to Return Current in
this Region?
Reference Planes
Displacement Current
Return Current
November 2008
Trace Current
Bruce Archambeault, PhD
100
Return Current Across
Reference Plane Change
With Decoupling Capacitor
Decoupling Capacitor
Displacement Current
Reference
Planes
Return Current
November 2008
Bruce Archambeault, PhD
101
Return Current Across
Reference Plane Change
With Decoupling Capacitor (on Top)
Decoupling Capacitor
Common-Mode Current
Displacement Current
Reference Planes
Return Current
November 2008
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102
Location of Decoupling
Capacitors (Relative to Via) is
Important!
• One Decoupling Capacitor at 0.5”
• Two Decoupling Capacitors at 0.5”
• Two Decoupling Capacitors at 0.25”
November
June 20072008
Bruce Archambeault, PhD
103103
RF Current @ 700 MHz with One
Capacitor 0.5” from Via
November
June 20072008
Bruce Archambeault, PhD
104104
RF Current @ 700 MHz with One
Capacitor 0.5” from Via
(expanded view)
November
June 20072008
Bruce Archambeault, PhD
105105
RF Current @ 700 MHz with Two
Capacitors 0.5” from Via
November
June 20072008
Bruce Archambeault, PhD
106106
RF Current @ 700 MHz with One
Capacitor 0.5” from Via
(Expanded view)
November
June 20072008
Bruce Archambeault, PhD
107107
RF Current @ 700 MHz with Two
Capacitors 0.25” from Via
November
June 20072008
Bruce Archambeault, PhD
108108
RF Current @ 700 MHz with Two
Capacitors 0.25” from Via
(expanded view)
November
June 20072008
Bruce Archambeault, PhD
109109
RF Current @ 700 MHz with One
REAL Capacitor 0.5” from Via
November
June 20072008
Bruce Archambeault, PhD
110110
RF Current @ 700 MHz with Two
REAL Capacitors 0.5” from Via
November
June 20072008
Bruce Archambeault, PhD
111111
RF Current @ 700 MHz with Two
REAL Capacitors 0.25” from Via
November
June 20072008
Bruce Archambeault, PhD
112112
Possible Routing Options
Six-Layer Board
Bad
Signal Layer
Reference Plane
Signal Layer
Signal Layer
Signal Layer
Reference Plane
Bad
Signal Layer
Reference Plane
Signal Layer
Signal Layer
Signal Layer
Reference Plane
Good
Signal Layer
Reference Plane
Signal Layer
Signal Layer
Signal Layer
November 2008
Bruce Archambeault, PhD
Reference Plane
113
Compromise Routing Option for
Many Layer Boards
Good Compromise
Vcc1
Gnd
Reference
Plane
Lot’s of Decoupling caps
near ASIC
November 2008
Bruce Archambeault, PhD
114
Typical Driver/Receiver Currents
VCC
switch
IC
driver
IC load
VDC
Z0, vp
CL
GND
logic 0-to-1
logic 1-to-0
VCC
VCC
IC load
IC
driver
IC
driver
charge
Z0, vp
IC load
Z0, vp
VCC
GND
November 2008
discharge
0V
GND
Bruce Archambeault, PhD
115
Suppose The Trace is Routed Next
to Power (not Gnd)
Vcc1
TEM Transmission
Line Area
Vcc1
“Fuzzy” Return
Path Area
“Fuzzy” Return
Path Area
Return Path Options:
-- Decoupling Capacitors
-- Distributed Displacement Current
November 2008
Bruce Archambeault, PhD
116
Suppose The Trace is Routed Next
to a DIFFERENT Power (not Gnd)
TEM Transmission
Line Area
Vcc1
Vcc2
“Fuzzy” Return
Path Area
“Fuzzy” Return
Path Area
Return Path Options:
-- Decoupling Capacitors ??? May not be any nearby!!
-- Distributed Displacement Current – Increased current spread!!!
November 2008
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117
Via Summary
9 Route critical signals on either side of ONE
reference plane
9 Drop critical signal net to selected layer close
to driver/receiver
9 Many decoupling capacitors to help return
currents
9 Do NOT change reference planes on critical
nets unless ABSOLUTELY NECESSARY!!
9 Make sure at least 2 decoupling capacitors
within 0.2” of via with critical signals
November 2008
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118
Mother/Daughter Board
Connector Crossing
• Critical Signals must be referenced to
same plane on both sides of the connector
November 2008
Bruce Archambeault, PhD
119
Mother/Daughter Board
Connector Crossing
Connector
Signal Path
GND
PWR
Signal Layers
November 2008
Bruce Archambeault, PhD
120
Return Current from Improper
Referencing Across Connector
Decoupling
Capacitors
Displacement
Current
Connector
Signal Path
Return current
GND
PWR
Signal Layers
November 2008
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121
Return Current from Proper
Referencing Across Connector
Connector
Signal Path
GND
PWR
Return current
November 2008
Signal Layers
Bruce Archambeault, PhD
122
How Many “Ground” Pins Across
Connector ???
• Nothing MAGICAL about “ground”
• Return current flow!
• Choose the number of power and “ground”
pins based on the number of signal lines
referenced to power or “ground” planes
• Insure signals are referenced against
same planes on either side of connector
November 2008
Bruce Archambeault, PhD
123
Think about Return Currents!!
9Reference plane should be continuous
under all critical traces
9When Vias are necessary make sure there
are two close decoupling capacitors
9When crossing a connector to a second
board, make sure the critical trace is
referenced to the same reference plane as
the primary board
November 2008
Bruce Archambeault, PhD
124
Ground-Reference Plane Noise
(Voltage Difference Across Plane)
• Connection of large PC ‘ground’ planes
to chassis important
– ESD current can result in voltage difference
across ‘ground’ plane
– Looks like input pulse to circuits
– More connection to chassis will reduce this
voltage difference
November 2008
Bruce Archambeault, PhD
125
Connection to Chassis
PCB gnd plane
Good connection in
I/O area important
for emissions
control!!
Chassis
Screw post
Connection to chassis away
from I/O area NOT important
for emissions control
November 2008
Bruce Archambeault, PhD
126
Connection to Chassis
for ESD Control
PCB gnd plane
Chassis
Screw post
Distributed Connection to chassis
away from I/O area very
important for ESD control
November 2008
Bruce Archambeault, PhD
127
Contacts for Chassis
Connection
Want this!
Screw head contact pad
on top of PC Board
Screw head
NOT this!
Copper pad
November 2008
Vias to “Ground” plane
Bruce Archambeault, PhD
128
Model for Current Simulations
PCB gnd plane
Screw post
Trace Source
Chassis
ESD Voltage
Between Chassis and
gnd plane
Trace Load
November 2008
Bruce Archambeault, PhD
129
Comparison of Trace Load Noise Voltage
for 1 Kv ESD Pulse from PCB GND to Chassis
2
No Connection to Chassis
One connection to Chassis (Near I/O)
Four Connections to Chassis (Near I/O)
Eight Connections to Chassis
16 Connections to Chassis
20 Connections to Chassis
1.5
Load Voltage (volts)
1
0.5
0
-0.5
-1
-1.5
0
0.5
1
1.5
2
2.5
3
3.5
Time (ns)
November 2008
Bruce Archambeault, PhD
130
Comparison of Trace Load Noise Voltage
for 1 Kv ESD Pulse from PCB GND to Chassis
2.5
2
1.5
No Connection to Chassis
Load Voltage (volts)
1
One connection to Chassis (Near I/O)
0.5
Four Connections to Chassis (Near I/O)
Eight Connections to Chassis
0
16 Connections to Chassis
-0.5
20 Connections to Chassis
-1
Eight Connections to Chassis (4 @
each end)
-1.5
-2
-2.5
-3
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Time (ns)
November 2008
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131
Current Flow w/One Screw Post
November 2008
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132
Current Flow w/Eight Screw Posts
November 2008
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133
Current Flow w/20 Screw Posts
November 2008
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134
Current Flow w/Eight Screw Posts (4 each end)
November 2008
Bruce Archambeault, PhD
135
Number ONE Problem
• Intentional signal return
current
November 2008
Bruce Archambeault, PhD
136
Where to Go for More?
• Limited selection of EMC design books
– Beware of some popular books!!!
– “PCB Design for Real-World EMI Control” (good choice)
• Bruce Archambeault
• EMC ‘experts’
– Experience is important
– Again, beware ---- ask questions and understand WHY
• Cookbooks do not work! Every case is
special and different
November 2008
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137