7.11. The current source shown in Fig 7.44 are to be designed for Ix = Iy = 0.6 mA. If VB1 = 1.1 V, VB2 = 1.0 V, λ = 0.1 V–1 and L1 = L2 = 0.25 μm, calculate W1 and W2. Calculate output resistances of these current sources. Ix Solution n 0.6 mA 2 (VGS Vtn ) 2 n C0 W1 2 L1 W1 200 106 (1.1 0.4) 2 196W1 6 2 0.25 10 W1 3 m. (Vin Vtn ) 2 Similarly Iy n 2 W2 200 106 (1 0.4)2 144W2 2 0.25 106 0.6 mA W2 4 m. 144 (VGS Vt )2 Output resistances Rout1 = Rout2 1 1 16.67 k. I D 0.1 0.6 103 7.15. For the circuit shown in Fig 7.48, (W/L)1 = 4/0.15, (W/L)2 = 10/0.2, λ1 = 0.1 V–1 and λ2 = 0.12 V–1, determine the inversion point Vin (= VB) for VX = 0.8 V. Solution At inversion point, IDM1 = IDM2 and both are in saturation. So, W W n Cox (Vgs Vtn ) 2 p Cox (VDD Vin Vtp ) 2 L n L p 200 10 6 4 10 (VB 0.4)2 100 10 6 (1.8 VB 0.4) 2 0.15 0.2 VB 1.301V. 19. For the circuit shown in Fig. 7.52, calculate Rout for given data. I D = 1mA(W / L)2 = 5 / 1 (W / L )1 = 10 / 1, l2 = 0.1V-1 , l1 = 0.1 V-1. Solution Diode-connected load M2 rO 2 = 1 lID = 1 0.1 ´ 10-3 = 10 kW. Similarly rO1 = 1 = 10 kW. l ID 5 g m2 = 2 ´ 200 ´ 10-6 ´ ´ 1 ´ 10-3 = 0.00141S. 1 and So, Rout = 1 rO 2 rO1 = 709 10 kΩ 10 kΩ ; 709 W. gm 2 7.22. For the circuit of Fig.7.55, find voltage gain (λ ≠ 0). I D 1.5mA (W / L) 1 10/1 (W / L) 1 2 0.1V Solution rO1 rO 2 2 15 / 1 1 1 1 6.67 k I D 0.1 1.5 103 g m2 2 100 106 15 1.5 103 0.00212S 1 10 1.5 103 0.00173S 1 So, we know from theory of CS stage with diode-connected MOS device, 1 Av g m 2 rO1 rO 2 g m1 1 0.00212 667k 6.67k 0.00173 0.00212(578) g m1 2 100 106 1.22 V/V. 7.23. The CS stage shown in Fig 7.56 must achieve a gain of 7. If (W/L)2 = 2/0.18, compute required value of (W/L)1. Solution We know that I D2 æ 1 ö AV = - gm1 ç r01 r02 ÷ ç gm ÷ è 2 ø æ 1 ö ; - gm1 ç ÷. ç gm ÷ è 2ø m C æW ö m C æW ö = n 0 ´ ç ÷ (VGS - VT )2 = n 0 ´ ç ÷ (VGS - VT ) 2 2 2 è L ø2 è L ø2 200 ´ 10 -6 2 ´ (1.8 - 0.4) 2 ´ 0.18 2 = 2.17 mA. = I D2 I D2 = I D1 . So, 2 æW ö ´ 2.17 ´ 10-3 gm2 = 2 ´ mn C0 ´ ç ÷ ´ I D2 = 2 ´ 200 ´ 10-6 ´ 0.18 è L ø2 = 0.00311S. æW ö g m1 = 2 ´ 200 ´ 10 -6 ´ ç ÷ ´ 2.17 ´ 10-3 è L ø1 æW ö Þ g m1 = 868 ´ 10 -9 ´ ç ÷ . è L ø1 æ 1 ö æW ö é 1 ù AV = - g m1 ç ÷ Þ 7 = 868 ´ 10 -9 ç ÷ ´ ê ú. ç gm ÷ L 0.00311 è ø ë û 1 è 2ø W æ ö Squaring = 49 = 868 ´ 10-9 ´ ç ÷ ´ [103.3K] è L ø1 æW ö Þ ç ÷ = 546. è L ø1 7.25. For the circuit shown in Fig.7.58, determine the gate voltage at which M1 operates at the edge of saturation. Solution We know at the edge of saturation of M1 (VGS Vt ) VDS . Here, (Vin 0) VGS . So, (Vin Vt ) VDS . Therefore, VDS VDD I D RD 1.8 I D RD . As (Vin Vt ) 1.8 I D RD Gate voltage Vin 1.8 I D RD Vt 7.26. For the circuit shown in Fig. 7.59, which should give gain of 5 with a bias current of 0.5 mA. Assume a drop of 250 mV across RS and λ = 0. (a) If RD = 2 kΩ, determine the required value of (W/L). (b) If (W/L) = 40/0.18, determine the value of RD. Solution (a) RD = 2 kΩ We know, AV g m RD 5 g m (2k ) g m 2.5 mS. In solution W ID L W 2 200 106 0.5 103 L g m 2n C0 2.5 103 Vout 1.8 2 103 0.5 103 1.8 1 0.8 V. VDS Vout 250 mV 0.8 V 0.25 V 0.55 V. We have VT = 0.4 V VDS VT M 1 in saturation. (b) W/L = 40/0.18, RD = ? ID n C0 2 W 200 106 40 (VGS Vt )2 0.5 103 (VDS )2 L 2 0.18 VDS 0.15 V. KVL drain source 1.8 0.5 103 RD VDS 250 mV 0. RD 2.8 kΩ. 29. The circuit in fig 7.62 has bias current of 0.8 mA. If RD = 1.5 kW, l = 0.1V -1 , compute required value of W/L for gate voltage of 1 V. What is voltage gain of circuit? Solution I D = 0.8 mA, RD = 1.5 kW, l =0.1V -1. KVL from drain-source is given by VDD - I D RD - Vout = 0 That is, 1.8 - 0.1 ´ 10-3 ´ 1.5 ´ 103 - Vout = 0. Þ Vout = 1.8 - 1.2 = 0.6 V = VDS . ID = 200 ´ 10-6 W × ´ (0.6)2 = 0.8mA L L 2 2 0.8 ´ 10-3 ´ 2 Þ W /L = = 22.22 ; 23. (0.6) 2 ´ 200 ´ 10-6 mn C0 W ´ (VGS - Vt )2 = gm = 2 ´ 200 ´ 10-6 ´ 23.0 ´ 0.8 ´ 10-3 = 7360 ´ 10-9 = 0.00085 1 = 0.85 ms. Gain = g m RD = 0.85 ´ 10 -3 ´ 1.5 kW =1.275 V/V.