8051 Microcontroller
Features of 8051
Feature
Quantity
ROM
4K Bytes
RAM
128 Bytes
Timer
2
I/O Pins
32
Serial Port
1
Interrupt Sources
6
Simplified Architecture of 8051
Description of Sub Units
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PC- Program Counter
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DPTR- Data Pointer register
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A 16 bit register to hold the program memory address of the instruction being currently fetched.
Increments continuously to point to the next instruction, unless there is change in the program flow
path.
A 16-bit register to hold the external data memory address of the data being currently fetched or to be
fetched in indirect addressing mode.
ACC-Accumulator
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An 8-bit register to save an operand for an ALU or data transfer operation and is also used to
accumulate result after an ALU operation.
Description of Sub Units
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B- B register
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ALU- Arithmetic logic unit
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A unit to perform an arithmetic and logical operation at an instance as per the instruction to be executed
and give result.
PSW- Processor Status Word
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An 8-bit register to save a second operand for the ALU and also accumulate the result after ALU
operation for multiplication or division.
A register to save the bits of different flags.
P0- Port P0
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An 8-bit port for the I/Os in a single chip mode and for the data bus-cum- lower order address in the
expanded mode.
Description of Sub Units
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P2- Port 2
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P1- Port 1
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An 8-bit port for the I/Os in a single chip mode and for the higher order address in the expanded mode
An 8-bit port for the I/Os in a single chip mode and a few device operations related bits in certain 8051
family variants in the expanded mode.
P3- Port 3
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An 8-bit port for the I/Os in a single chip mode and the serial interface (SI) bits , timer T0 and T1
inputs, Interrupts INT0 and INT1 inputs , RD and WR for the memory read-write in the expanded
mode.
Description of Sub Units
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SI- Serial Interface Device
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T0 and T1- Timers T0 and T1
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Timing devices in 8051 family using four registers TH1, TH0, TL1, and TL0.
SFRs- Special Function Registers
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Serial device for full duplex UART serial I/O operations through the set of two pins of P3, RxD and
TxD and for the half duplex synchronous communication of the bits through the same set of pins,
DATA and CLOCK.
All registers the SP, PSW, A, B, IE, IP, SCON, TCON, SMOD, SBUF, PCON, , TL0, TH0,TL1, TH1 are
called SFRs
ROM- Read only Program memory
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Masked ROM EPROM or flash EEPROM of 4kB in 8051 classic family.
Description of Sub Units
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Internal RAM- Internal Random Access Memory
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Register banks- Four set of registers
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To enable use of external memory addresses to external ROM.
RST- Reset Pin
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Pins to the crystal in the oscillator circuit, usually 12 MHz
EA- External Enable
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Four register banks each of 8 registers and these are also part of the internal RAM.
XTAL1 and XTAL2 – Pins to the Crystal
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For read and write the 128 B memory is indirectly and directly addressable in address space.
Reset circuit input and also reset few output cycles to the external peripheral devices to let processor
reset and synchronize with devices.
INT 0 and INT 1- Interrupt pins
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Active low two external interrupts.
Description of Sub Units
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VCC and GND- Voltage supply pi and ground pin
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PSEN - Program Store Enable
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Active low when reading the external program memory bytes
RD-Read
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For 5 V supply and ground connections respectively.
Active low when reading the byte from external data memory.
WR - Write
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Active low when writing the byte to external data memory
Pin Configuration
Memory Organization
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The 8051 has two types of memory and these are
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Program Memory (ROM)
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It is used to permanently save the program being executed, while
Data Memory (RAM)
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Program Memory and
Data Memory
It is used for temporarily storing data and intermediate results created and used during the operation of
the microcontroller.
Depending on the model in use at most a few Kb of ROM and 128 or 256 bytes of
RAM is used
8051 Microcontroller has both Internal ROM and Internal RAM.
If the internal memory is inadequate, you can add external memory using suitable
circuits.
Program Memory
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In 8051 Microcontroller, the code or instructions to be executed are stored in the
Program Memory, which is also called as the ROM of the Microcontroller.
The original 8051 Microcontroller by Intel has 4KB of internal ROM.
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The address space is 0000H to 0FFFH.
If the address space i.e., the program addresses exceed this value, then the CPU will automatically fetch
the code from the external Program Memory.
■ For this, the External Access Pin (EA Pin) must be pulled HIGH
■ When the EA Pin is low, the CPU first fetches instructions from the Internal Program Memory in
the address range of 0000H to 0FFFH
■ if the memory addresses exceed the limit, then the instructions are fetched from the external
ROM in the address range of 1000H to FFFFH.
Program Memory
Program Memory
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There is another way to fetch the instructions:
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Ignore the Internal ROM and fetch all the instructions only from the External Program Memory
(External ROM).
For this scenario, the EA Pin must be connected to GND.
In this case, the memory addresses of the external ROM will be from 0000H to FFFFH.
Data Memory or Internal RAM
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The Data Memory or RAM of the 8051 Microcontroller stores temporary data and
intermediate results that are generated and used during the normal operation of the
microcontroller.
Original Intel’s 8051 Microcontroller had 128B of internal RAM.
But almost all modern variants of 8051 Microcontroller have 256B of RAM.
Data Memory or Internal RAM
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The 8051 micro controller has a total of 128 bytes of internal RAM.
The 128 bytes of RAM inside the 8051 are assigned addresses 00H to 7FH
Divided into three different groups:
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A total of 32 bytes from location s 00H to 1FH are set aside for register banks and the stacks.
A total of 16 bytes from locations 20H to 2FH are set aside for bit addressable read/write memory.
A total of 80 bytes from locations 30H to 7FH are used for read and write storage, or what is normally
called a scratch pad.
■ These 80 locations of RAM are widely used for the purpose of storing data and parameters by
8051 programmers.
Data Memory or Internal RAM
Register banks in the 8051
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A total of 32 bytes of RAM are set aside for the register banks an stack.
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32 bytes are divided into 4 banks of registers in which each bank has 8 registers, R0-R7.
■ RAM locations from 0 to 7 are set aside for bank 0 of R0-R7 where R0 is RAM location 0, R2 is
location 2 and so on.
■ The second bank of registers R0-R7 start RAM location 08 and goes to location 1FH.
■ The third bank of R0-R7 starts at memory location 10 H and goes to location 17H.
■ Finally RAM location 18H to 1FH are set aside for the fourth bank of R0-R7.
RAM allocation in the 8051
Bit
Addressable
Memory
Single Bit Instructions
Bit Memory Map
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The bit addresses 00 – 7FH are assigned to RAM locations of 20 – 2FH.
The bit addresses 80 – 87H are assigned to the PO port.
The bit addresses 88 – 8FH are assigned to the TCON register.
The bit addresses 90 – 97H are assigned to the PI port.
The bit addresses 98 – 9FH are assigned to the SCON register.
The bit addresses AO – A7H are assigned to the P2 port.
The bit addresses A8 – AFH are assigned to the IE register.
The bit addresses BO – B7H are assigned to the P3 port.
The bit addresses B8 – BFH are assigned to IP.
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The bit addresses CO – CFH are not assigned.
The bit addresses DO – D7H are assigned to the PSW register.
The bit addresses D8 – DFH are not assigned.
The bit addresses EO – E7H are assigned to the Accumulator register.
The bit addresses E8 – EFH are not assigned.
The bit addresses FO – F7H are assigned to the B register.
External Program Memory
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When the the EA’=0 at RESET, the PC (MCU program counter ) starts from 0x0000
and accesses the external addresses from the memory. Memory addresses are between
0x0000 and 0x1FFF.
● When the EA’=1 at RESET, the PC starts from 0x0000 for banks0 and 1 and accesses
the internal addresses and the 0x1000 onwards from the external addresses from the
memory.
External Data Memory
It can be accessed through the indirect
addressing mode used.
Special Function Registers (SFR)
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SFRs are at the directly addressable space special registers.
These can be accessed by their names or by their addresses.
The SFRs have addresses between 80H and FFH.
These addresses are above 80H, since the addresses 00 to 7FH are addresses of RAM
memory inside the 8051.
Not all the address space of 80 to FF is used by the SFR.
The unused locations 80H to FFH are reserved and must not be used by the 8051
programmer.
Special Function Registers (SFR)
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The 8051 microcontroller has 11 SFR
divided in 4 groups:
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Timer/Counter register
Serial data register
Interrupt register
Power control register
Timer/Counter register
● Timer/Counter register:
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8051 microcontroller has 2-16 bit Timer/counter registers called Timer-reg-T0 And Timer/counter Reg-T1.
Each register is 16 bit register divide into lower and higher byte register
These register are used to hold initial no. of count.
All of the 4 register are byte addressable.
Timer control register:
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8051 microcontroller has two 8-bit timer control register i.e. TMOD and TCON register.
■ TMOD Register:
● It is 8-bit register. Its address is 89H.
● It is byte addressable.
● It used to select mode and control operation of time by writing control word.
■ TCON register:
● It is 8-bit register. Its address is 88H.
● It is byte addressable. Its MSB 4-bit are used to control operation of timer/ counter and LSB 4-bit
are used for external interrupt control.
Timer T0 and T1
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8051 has two timers Timer0 (T0) and Timer1 (T1), both are 16-bit wide.
Since 8051 has 8-bit architecture, each of these is accessed by two
separate 8-bit registers
These registers are used to load timer count.
TMOD Register
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TMOD is an 8-bit register used to set timer mode of timer0 and timer1.
Its lower 4 bits are used for Timer0 and the upper 4 bits are used for Timer1
TMOD Register
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Bit 7,3 – GATE:
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0 = Enable Timer/Counter when TR0/TR1 is set.
Bit 6,2 - C/(Counter/Timer): Timer or Counter select bit
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1 = Enable Timer/Counter only when the INT0/INT1 pin is high and TR0/TR1 is set.
1 = Use as Counter
0 = Use as Timer
Bit 5:4 & 1:0 - M1:M0: Timer/Counter mode select bit
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These are Timer/Counter mode select bit as per the below table
M0
M1
Mode
Operations
0
0
13-bit timer mode
13-bit timer/counter, 8-bit of THx & 5-bit of TLx
0
1
16-bit timer mode
16-bit timer/counter, THx cascaded with TLx
1
0
8-bit auto-reload mode
8-bit timer/counter (auto-reload mode), TLx reload with the value held by THx each time
TLx overflow
1
1
Split timer mode
Split the 16-bit timer into two 8-bit timers i.e. THx and TLx like two 8-bit timer
Timer Modes
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Mode 0 (13-bit timer mode)
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Mode 0 is a 13-bit timer mode for which 8-bit of THx and 5-bit of TLx (as Prescaler) are used.
It is mostly used for interfacing possible with old MCS-48 family microcontrollers.
Higher 3-bits of TLx should be written as zero while using timer mode0, or it will affect the result.
Timer Modes
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Mode1 (16-bit timer mode)
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Mode 1 is a 16-bit timer mode used to generate a delay, it uses 8-bit of THx and 8-bit of TLx to
form a total 16-bit register.
Timer Modes
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Mode2 (8-bit auto-reload timer mode)
○ Mode 2 is an 8-bit auto-reload timer mode.
○ In this mode, we have to load the THx-8 bit value only.
○ When the Timer gets started, the THx value gets automatically loaded into the TLx
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and TLx starts counting from that value.
After the value of TLx overflows from the 0xFF to 0x0, the TFx flag gets set and
again value from the THx gets automatically loaded into the TLx register.
That’s why this is called the auto-reload mode.
TCON Register
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TCON is an 8-bit control register and contains a timer and interrupt flags.
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Bit 7 - TF1: Timer1 Overflow Flag
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1 = Timer1 overflow occurred (i.e. Timer1 goes to its max and roll over back to zero)
0 = Timer1 overflow not occurred.
It is cleared through software. In the Timer1 overflow interrupt service routine, this bit will get cleared automatically
while exiting from ISR.
Bit 6 - TR1: Timer1 Run Control Bit
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1 = Timer1 start.
0 = Timer1 stop.
It is set and cleared by software.
TCON Register
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Bit 5 – TF0: Timer0 Overflow Flag
○ 1 = Timer0 overflow occurred (i.e. Timer0 goes to its max and roll over back to zero).
○ 0 = Timer0 overflow not occurred.
○ It is cleared through software. In the Timer0 overflow interrupt service routine, this bit will get
cleared automatically while exiting from ISR.
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Bit 4 – TR0: Timer0 Run Control Bit
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1 = Timer0 start.
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0 = Timer0 stop.
○ It is set and cleared by software.
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Bit 3 - IE1: External Interrupt1 Edge Flag
○ 1 = External interrupt1 occurred.
○ 0 = External interrupt1 Processed.
○ It is set and cleared by hardware.
TCON Register
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Bit 2 - IT1: External Interrupt1 Trigger Type Select Bit
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1 = Interrupt occurs on falling edge at INT1 pin.
0 = Interrupt occur on a low level at the INT1 pin.
Bit 1 – IE0: External Interrupt0 Edge Flag
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1 = External interrupt0 occurred.
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It is set and cleared by hardware.
0 = External interrupt0 Processed.
Bit 0 – IT0: External Interrupt0 Trigger Type Select Bit
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1 = Interrupt occurs on falling edge at INT0 pin.
0 = Interrupt occur on a low level at INT0 pin.
Serial data register
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Serial buffer register (SBUF):
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It is 8-bit register.
It is byte addressable.
Its address is 99H.
It is used to hold data which is to be transferred serially.
Serial control register (SCON):
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It is 8-bit register.
It is bit/byte addressable.
Its address is 98H.
The 8-bit loaded into this register controls the operation of serial communication.
Interrupt register
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8051 μC has 2 8-bit interrupt register.
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Interrupt enable register (IE):
■ It is 8-bit register.
■ It is bit/byte addressable.
■ Its address is A8H.
■ It is used to enable and disable function of interrupt.
Interrupt priority register (IP):
■ It is 8-bit register.
■ It is bit/byte addressable.
■ Its address is B8H.
■ it is used to select low or high level priority of each individual interrupts.
Power control register (PCON)
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It is 8-bit register.
It is byte addressable .
Its address is 87H. Its bits are used to control mode of power saving circuit, either idle
or power down mode and also one bit is used to modify baud rate of serial
communication.
Internal ROM
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Data memory and program code memory both are in different physical memory but
both have the same addresses.
An internal ROM occupied addresses from 0000h to 0FFFh.
PC addresses program codes from 0000h to 0FFFh.
Program addresses higher than 0FFFh that exceed the internal ROM capacity will
cause 8051 architecture to fetch codes bytes from external program memory.
External ROM Interfacing
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Port 0 is used as multiplexed data & address lines. It gives lower order (A7-A0) 8
bit address in initial T cycle & higher order (A8-A15) used as data bus.
8 bit address is latched using external latch & ALE signal from 8051.
Port 2 provides higher order (A15-A8) 8 bit address.
PSEN is used to activate the output enable signal of external ROM/EPROM.
External RAM Interfacing
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Port 0 is used as multiplexed data & address lines.
Address lines are decoded using external latch & ALE signal from 8051 to provide lower order
(A7-A0) address lines.
Port 2 gives higher order address lines.
RD & WR signals from 8051 selects the memory read & memory write operations respectively.
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RD & WR signals:
○ Generally P3.6 & P3.7 pins of port 3 are
used to generate memory read and memory
write signals.
○ Remaining pins of port 3 i.e. P3.0-P3.5 can
be used for other functions.
External memory Interfacing
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A maximum of 64KB of Program Memory (ROM) and Data Memory (RAM) each can be interface with the 8051
Microcontroller.
when interfacing external memory with 8051 Microcontroller is that Port 0 (P0) cannot be used as an IO Port
It will be used for multiplexed address and data bus (A0 – A7 and D0 – D7).
Not always, but Port 2 may be used as higher byte of the address bus.
Interrupts
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When a device needs its service, the device notifies the microcontroller by sending
an interrupt signal.
Once the interrupt is accepted the microcontroller serves the device by executing an
interrupt service routine (ISR).
All the interrupts are under the control of program
Steps in executing an interrupt:
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Microcontroller finishes the execution of current instruction and save the address of the next instruction
(PC) on the stack.
It also saves the current status of all the interrupts internally
It jumps to a fixed location in memory called the IVT that holds the address of the ISR
The microcontroller gets the address of the ISR from IVT and jumps to it
It starts execute the ISR until reaches last instruction of subroutine RETI (Return from the Interrupt)
Upon executing the RETI, microcontroller returns to the place where it was interrupted after it gets PC
address form the stack
Six Interrupts of 8051
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Reset:
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Two interrupts for the timers: (Auto generated by internal operations)
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One for Timer 0 and one for Timer 1
Memory locations 000BH and 001BH in the IVT belongs to Timer 0 and Timer 1 respectively
Two interrupts for external hardware interrupts:
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When the Reset pin is activated, the 8085 jumps to address location 0000.
■ This is power up reset.
Pin numbers 12 (P3.2) and 13 (P3.3) in port 3 are for the external hardware interrupts INT0 and INT1
respectively
These are also referred to as EX1 and EX2
Memory locations 0003H and 0013H in the IVT are assigned to INT0 and INT1 respectively
Serial communication:(Auto generated by internal operations)
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One interrupt for both receive and transfer in serial communication
IVT location is 0023H for this interrupt
Interrupt Priority
Highest to Lowest Priority
External Interrupt 0
INT0
Timer Interrupt 0
TF0
External Interrupt 1
INT1
Timer Interrupt 1
TF1
Serial Communication
RI-TI
Enabling and Disabling the interrupt
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Upon reset all interrupts are disabled
The interrupts must be enabled by software
There is a register IE ( Interrupt Enable) that is responsible for enabling and
disabling the interrupts
Steps to Enable:
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Bit D7 of IE (EA) register must set high to allow the rest of the register to take effect
If EA = 1, interrupts are enabled and will be responded to if their corresponding bits in IE are high
If EA = 0, no interrupt will be responded to, even if the associated bit in the IE register is high
The programmer is able to alter control bits in the IE register, the Interrupt Priority
(IP) register and the Timer Control (TCON) register.
Interrupt Enable (IE) Register
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D7
D6
D5
D4
EA
—-
ET2
IE.7
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
EA : Used to enable or disable the interrupt
Not implemented, reserved for future use
ET2: Enables or disables Timer 2 overflow or capture interrupt (8952)
ES: Enables or disables the serial port interrupt
ET1: Enables or disables Timer 1 overflow interrupt
EX1: Enables or disables external interrupt 1
ET0: Enables or disables Timer 0 overflow interrupt
EX0: Enables or Disables external interrupt 0
ES
D3
D2
ET1
D1
EX1
D0
ET0
EX0
Programmer’s Model
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The CPU registers are used to store the data temporarily.
The information may be data to be processed or address pointing the data to be
fetched.
The majority of registers are 8 bits. The 8-bit registers are shown in the diagram from
MSB (most significant bit) D7 to the LSB (least significant bit) D0.
The most widely used registers of 8051 are A (accumulator), B, R0, R1, R2, R3, R4,
R5, R6, R7, DPTR (data pointer), and PC (program counter).
Interrupt Priority (IP) SFR
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D7
D6
D5
—
—
PT2
D7
D6
D5
D4
D3
D2
D1
D0
D4
PS
D3
D2
PT1
D1
PX1
D0
PT0
PX0
– : Not Implemented
– : Not Implemented
PT2 : Reserved for future use
PS : Priority of serial port interrupt. Set/cleared by program
PT1 : Priority of Timer 1 overflow interrupt. Set/cleared by program
PX1 : Priority of external interrupt 1. Set/cleared by program
PT0 : Priority of Timer 0. overflow interrupt. Set/cleared by program
PX0 : Priority of external interrupt 0. Set/cleared by program
Interrupt Priority
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Register IP bits determine if any interrupt is to have a high or low priority
Bits set to 1 give the accompanying interrupt a high priority
Bits set to 0 give the accompanying interrupt a low priority
Interrupts with a high priority can interrupt another interrupt with a lower priority
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The lower priority interrupt continues after the higher is finished
If two interrupts with the same priority occur at the same time, then they have the
following ranking:
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IE0
TF0
IE1
TF1
Serial RI OR TI
Programmer’s Model
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All these registers are 8 bits except DPTR and the program counter.
The accumulator is used to hold one operand before execution and hold the result after
execution
The program counter points to the address of next instruction to be fetched.
It is a auto increment register. As the size of program counter is 16 bit.
8051 can access the program addresses from 0000H-FFFFH.
When 8051 is powered-up the program counter contents will be 0000H.
This means that it expects the first opcode to be stored at ROM address 0000H.
For this reason in the 8051 system, the first opcode must be burned memory location 0000H
of program ROM since this is where it looks for the first instruction when it is booted.
Programmer’s model
Programmer’s model
● Data Pointer (DPTR – DPL and DPH
○ The Data Pointer is a 16-bit Register and is physically the combination of DPL
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(Data Pointer Low) and DPH (Data Pointer High) SFRs.
The Data Pointer can be used as a single 16-bit register (as DPTR) or two 8-bit
registers (as DPL and DPH).
DPTR doesn’t have a physical Memory Address but the DPL (Lower Byte of
DPTR) and DPH (Higher Byte of DPTR) have separate addresses in the SFR
Memory Space.
DPL = 82H and DPH = 83H.
The DPTR Register is used by the programmer addressing external memory
(Program – ROM or Data – RAM).
Data Pointer (DPTR) – DPL and DPH
Stack Pointer
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SP or Stack Pointer points out to the top of the Stack
It indicates the next data to be accessed.
Stack Pointer can be accessed using PUSH, POP, CALL and RET Instructions.
The Stack Pointer is an 8-bit register and upon reset, the Stack Pointer is initialized with
07H.
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When writing a new data byte into the stack, the SP (Stack Pointer) is automatically
incremented by 1 and the new data is written at an address SP+1.
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When reading data from stack, the data is retrieved from the Address in SP and after that
the SP is decremented by 1 (SP-1).
Stack Pointer
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The stack area in 8051 always can be
implemented in internal data memory.
Here the Stack Pointer (SP) is only 8-bit register,
because the internal RAM area is only in range
00H to 7FH,
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When all register banks are being used, the stack location
will be in range 30H to 7FH.
So in such a case, the SP will be initialized with 2FH.
I/O Port Registers (P0, P1, P2 and P3)
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The 8051 Microcontroller four Ports which can be used as Input and/or Output.
These four ports are P0, P1, P2 and P3.
Each Port has a corresponding register with same names (the Port Registers are also P0, P1, P2
and P3).
The addresses of the Port Registers are as follows: P0 – 80H, P1 – 90H, P2 – A0H and P2 – B0H
Each bit in these SFRs corresponds to one physical Pin in the 8051 Microcontroller.
All these Port Registers are both Bit Addressable and Byte Addressable.
Writing 1 or 0 on a Port Register Bit will reflect as an appropriate voltage (5V and 0V) on the
corresponding Pin.
If a Port Bit is SET (declared as 1), the corresponding Port Pin will be configured as Input and
similarly if a Port Bit is CLEARED (declared as 0), the corresponding Port Pin is configured as
Output.
Upon reset, all the Port Bits are SET (1) and hence, all the Port Pins are configured as Inputs.
Port Registers
Bit Addresses
Port P0
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Port 0 occupies a total of 8 pins
It can be used for input and output
To use the pins of Port 0 as both input and
output ports, each pin must be connected
externally to a 10K Ohm pull up register
This is due to the fact that P0 is an open drain,
unlike P1, P2 and P3
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Open drain is a term used for MOS chips in the same
way that open collector is used in TTL circuits
In any system using 8051 chip, we normally
connect P0 to pull-up resistors
Port 0 as Input
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With resistors connected to P0, in order to make it an input, the port must be
programmed by writing 1 to all the bits
Port 1
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Port 1 occupies a total of 8 pins
It can be used as input or output
In contrast to Port 0, this port does not need any pull up resistors
Upon reset Port 1 is configured as input ot output
Port 2
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Port 1 occupies a total of 8 pins
It can be used as input or output
Like Port 1, this port does not need any pull up resistors
Upon reset Port 2 is configured as input ot output
Port 3
● Port 3 occupies a total of 8 pins, pins 10
through 17
● It can be used as input or output
● Like Port 1 and P2, this port does not need
any pull up resistors
● Although Port 3 is configured as an input port
upon reset, this is not the way it is most
commonly used
● Port 3 has the additional function of providing
some extremely important signals such as
interrupts
PSW Register
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The program status word register (PSW) is an 8-bit register. It is also referred as Flag
register.
Although this register is size of 8-bits, only 6 bits are used by 8051.
Two unused bits are user definable flags. Other 4 bits are called as conditional flags
such as CY (carry), AC (auxiliary carry), P(parity) and OV(overflow).
In this register the bits PSW.3 and PSW.4 are designated as RS0 and RS1 and used to
select the banks. PSW.5 and PSW.1 bits are general purpose status flags and can be
used by the programmer for any purpose.
PSW Register
Operand addressing
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There are 5 types of addressing modes is supported by 8051.
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Register
Immediate
Direct (memory related)
Register Indirect (memory related)
Index register addressing
Register addressing mode
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This addressing mode involves the use of registers to hold the data to be manipulated.
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Examples:
■ MOV A, R0 ; Copy the contents of R0 int A
■ ADD A, R7 ; Add the contents of R7 to contents of A and the result is stored in A
Immediate addressing mode
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In this addressing mode immediate data is specified in instruction as a source
operand.
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Examples:
■ MOV B, #40H ; load 40H into B register
■ MOV DPTR, #2000H ; load 2000H into DPTR
Direct addressing mode
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The on-chip RAM of 8051 is 128 byte, it can be accessed through memory address
from 00H to FF H.
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RAM location 00H-1FH are assigned to register banks and stack
RAM location 20H-2FH is set aside as bit-addressable space to save single bit data.
RAM location 30H-7F is available as place to save bite-sized data.
Although the entire 128 bytes of RAM can be accessed through direct addressing
mode, it is most often used to access RAM location 30H-7FH.
This is due to fact that register banks are accessed through their names.
Direct addressing mode
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Examples:
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MOV R4, 70H ; move the contents of RAM location 70H to R4.
MOV 56H, A ; save the content of A in RAM location 56H
PUSH 05 ; push R5 onto the stack
Register indirect addressing mode
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In this mode the address (of 8 bits) is indirectly specified in the instruction by the
contents of pointer.
This addressing mode so called because the source operand is from the address
specified indirectly by another register in the instruction.
The limitation is that only R0 and R1 register can be used in 8051 for indirect
addressing. SFRs are directly accessible.
Examples
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MOV R1, #55H ; load pointer R1=55H
MOV A, @R1 ; the content of pointer is transferred to A
Index registers addressing
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We need to access external data RAM and external code space of on-chip ROM 16 bit
address must be required.
In this case we have to use DPTR.
This mode is widely used in accessing data elements of look-up table entries in the
program ROM space of 8051.
Examples;
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MOV DPTR, #0200H ; load DPTR with 0200
CLR A ; clear accumulator
MOVC A,@A+DPTR ; Move the content 0200 location into A
Instruction set
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The instruction set of 8051 can be classified into following group.
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Data Transfer Instructions
Arithmetic Instructions
Logic Instructions
Boolean Variable manipulation Instructions
Program flow control (Processor and Machine control) Instructions
Interrupt flow Control instruction
Data Transfer Instruction
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Three types of the data transfer can be done by move instruction.
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First type is transfer within the internal RAM and SFRs,
Second type is transfer using code memory area (CODE) and
The third is using the external data memory X-DATA).
MOV instruction
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A MOV instruction means move (copy) the bits from one source to a destination.
Types:
■ MOV A,Rn
■ MOV Rn,A
■ MOV A, #data
■ MOV Rn, #data
■ MOV Register, addr(direct)
■ MOV Addr(direct), Register
■ MOV Addr(direct),Addr(direct)
■ MOV Addr(direct), #data
■ MOV A,@Ri
■ MOV @Ri,A
■ MOV Addr(direct), @Ri
■ MOV @Ri, Addr(direct)
■ MOV @Ri, #data
■ MOV DPTR, data16
Data Transfer Instruction
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MOVC-type Instruction
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It moves the 8-bit code from one source at the program memory (internal and external) to the register A
destination.
Example:
■ MOVC A, @A+DPTR
■ MOVC A, @A+PC
MOVX-type instruction
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A MOVX instruction means move (copy) the 8-bit data into A and from A using the external data
memory address using DPTR or Ri as the pointer
Example:
■ MOVX A, @DPTR
■ MOVX @DPTR,A
■ MOVX A,@Ri
■ MOVX @Ri, A
Data Transfer Instruction
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PUSH and POP instructions for using the Stack Area employing SP
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PUSH direct
POP direct
XCH-type instructions
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XCH A@Ri
XCH A,Rn
XCH A, direct
XCHD A,@Ri
Arithmetic Instruction
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These instructions include 8 bit addition, subtraction, increment, decrement, multiply and
division instruction.
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Types:
■ ADD A,Rn
■ ADD A, direct
■ ADD A, @Ri
■ ADD A, #data
■ ADDC A, Rn
■ ADDC A, Addr(direct)
■ ADDC A @Ri
■ ADDC A, #data
■ SBBB A,Rn
■ SBBB A, direct
■ SBBB A, @Ri
■ INC Register
and DEC Register
■ INC Addr(direct)
and DEC Addr(direct)
■ INC @Ri
and DEC Register
■ MUL A,B
■ DIV A,B
■ DAA
Logical Instruction
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Does 8-bit AND, OR and XOR instruction.
These instructions have 4 addressing modes such as register, immediate, direct and
indirect.
Example:
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ANL A, Addr(direct) / @Ri/#data
ANL Addr(direct), A / #data
ORL A, Rn/Addr(direct)/@Ri/#data
ORL Addr(direct), A/#data
XRL A, Rn/Addr(direct)/@Ri/#data
XRLS direct, A/#data
Boolean Variable manipulation Instructions
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These are also called as Boolean processing instruction
Example:
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Control Transfer Instruction
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In the main program other sub programs may be called to perform a particular task.
Sub program is called with the help of JUMP and CALL instruction when some
condition met.
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Delay-Cycle (NOP) instruction ( No operation)
Long, Absolute and Short Jump
■ LJMP addr16
■ AJMP addr11
■ SJMP rel
■ JMP @A+DPTR
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Conditional Short Relative Jumps
Examples:
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JNZ rel
JZ rel
JNC rel
JC rel
JB bit, rel
JNB bit,rel
JBC bit, rel
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Decrement and Conditional jump on Zero
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Examples:
■ DJNZ Rn, Rel
■ DJNZ direct, Re
Jump after comparison
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Examples:
■ CJNE A, #data, rel
■ CJNE Rn, #data, rel
■ CJNE A, direct, rel
■ CJNE @Ri, #data, rel
Call to a Routine
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Long, absolute call and return instruction
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Examples:
■ LCALL addr16
■ ACALL addr11
■ RET
Interrupt Control Flow (RETI instruction)
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RETI
Few Programming Examples
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To find the sum of values and store the result in A ( lower byte and in R7 (higher
byte). Assume that RAM locations 40-44 have the following values.
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Program:
MOV R0, #40H
MOV R2, #05H
CLR A ; A=0
MOV R7, A
AGAIN: ADD A, @R0
JNC NEXT
INC R7
NEXT: INC R0
DJNZ R2, AGAIN
HERE: SJMP HERE
; load pointer
; load counter
; clear R7
; add the byte pointer
; if CY=0 it can jump to NEXT label
; increment counter
; increment pointer
; repeat until R2is zero
Few Programming Examples
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Write an ALP to get hex data in the range of 00-FFH from port 1 and convert it to
decimal. Save the digits in R7, R6 and R5, where the least significant digit in R7.
Program:
MOV A, #0FFH
MOV P1, A
MOV A1, P1
MOV B, #0AH
DIV AB
MOV R7, B
MOV B , #0AH ;
DIV AB ;
MOV R6, B
MOV R5, A
HERE: SJMP HERE
; Make an P1 an input port
; Read data from P1
; Move 0AH to register b
; Divide by the contents of A by B
; Save lower digit in R7 register
; Save the next digit
; Save the last digit
Few Programming Examples
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Write an ALP to determine if register A contains the value 99H, if so, make
R1=FFH otherwise make R1=0.
Program:
MOV R1, #00H
; clear R1
CJNE A, #99H, NEXT ; if A is not equal 99H then jump
MOV R1, #0FFH
NEXT …..
; make R1=FFH
Few Programming Examples
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Assume that P1 is an input port connected to a temperature sensor. Write an ALP to read the temperature and test it for
the value 75. According to the rest result, place the temperature value into the registers indicated by the following.
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If T=75 then A=75
If T<75 then R1=T
If T>75 then R2=T
Program:
MOV P1, # 0FFH
MOV A, P1
CJNE A, #75, OVER
SJMP EXIT
OVER: JNC NEXT
MOV R1, A
SJMP EXIT
NEXT: MOV R2, A
EXIT ……
; make P1 an input port
; read P1 port, temperature
; jump if A is not equal 75
; if CY=0, then A>75
; if CY=1, A<75
; Exit