Digital Systems - Lab Manual
Lab 5 - FPGA and Vivado Tutorial
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Objective
This lab is the first lab in the course, and it will guide you through the installation of the Xilinx Vivado, the
design flow using Xilinx Vivado software to create digital circuits using VHDL. A typical design flow consists
of creating a Vivado project, creating device entities (.VHD files), assigning created constraint file (.XDC
file), building the testbench (.VHD file), running the simulations, synthesizing the design, implementing the
design, generating the bitstream, and finally verifying the functionality in the hardware by downloading
the generated bitstream file. You will go through the typical design flow targeting the Artix7 based Arty A7
trainer board[1].
Introduction
Field-programmable gate array (FPGA) is a type of integrated circuit (IC) that can be programmed for
different functionalities after manufacturing. The application of FPGA reduces the time of the design to
market time and provides significant cost advantages in comparison to the traditional IC development
effort and offers the same level of performance in most cases. The FPGA configuration is generally specified
using a programming language called hardware description language (HDL). Today, the FPGA devices could
consist of millions of logic units that can be programmed and configured to implement different logic
functions. Meanwhile, FPGA ICs can be reprogrammed dynamically to meet the onsite requirements on
the digital circuits [2].
The basic structure of an FPGA is composed of the following elements:
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•
•
•
Look-up table (LUT): This element performs logic operations (Inside the LC unit).
Flip-Flop (FF): This register element stores the result of the LUT (Inside the LC unit).
Programmable Interconnect Wires: These elements connect elements in the FPGA.
Input/Output (I/O) pads: These physically available ports get data in and out of the FPGA.
The circuit board you will use in the lab of this class is called “Xilinx Arty A7 FPGA Trainer Board”. The
picture of this trainer board is shown below (picture courtesy of Xilinx Inc., https://www.xilinx.com):
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Some of the on-board components included on this board:
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•
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Internal clock speeds exceeding 450MHz
1 MSPS On-chip ADC
On-chip analog-to-digital converter (XADC)
Programmable over JTAG and Quad-SPI Flash
USB-JTAG Programming circuitry
Powered from USB or any 7V-15V source
10/100 Mbps Ethernet
USB-UART Bridge
4 Switches, 4 buttons, 4 LEDs, 4 RGB LEDs, 1 reset button
4 Pmod connectors
Arduino/ChipKit Shield connector
Lab Procedures
This lab will introduce the software design environment used for the “Xilinx Arty A7-100 FPGA Trainer
Board”, the simulation of the VHDL program, and the FPGA programming process. The whole process
includes the following parts. Please follow the procedures carefully because these procedures are always
needed to implement the designs in future labs and your bus project.
Procedures
Purpose of the Procedure
Part 1. Installation of the Vivado WebPACK software
Install the software package
Part 2. Use Vivado to design a logic circuit in VHDL
Introduction to input the source VHDL code into the project
Part 3. Use Vivado to Perform RTL analysis on the
source file
Perform the RTL analysis on the VHDL code
Part 4. Simulate the Design using the XSim Simulator
Run the behavior simulation without the implementation
(To verify the functions of the VHDL design)
Part 5. Synthesize the Design
Synthesize the design and generate the schematics
Part 6. Implement the Design
Run the implementation process on FPGA based on the
synthesis output files
Part 7. Generate the Bitstream
Generate the final Bitstream output file.
Part 8. Verify functionality on the trainer board (if
the trainer board is available)
Download the Bitstream file to the target circuit board (the
Arty-A7 trainer board).
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Please follow the steps from Part 1 to Part 9 to finish the whole procedure.
Part 1. Installation of the Vivado WebPACK software on your computer
1. If you don’t have Vivado WebPACK software installed on your computer, please download the software
from the Xilinx Website: The version we need to install is 2019.1, and it can be found in the following
Website:
https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivadodesigntools/archive.html
Please notice you MUST choose the version 2019.1 under “Vivado Archive” link to download, and
please don’t install the latest version of the Vivado from this website. Installing other versions will
make the software very huge and not compatible with your lab projects.
Choose the Vivado HLx 2019.1: All OS installer Single-File Download Version to download and
start the installation process. Please notice that you need to register an account with Xilinx to
download the software.
2. The file you downloaded is a zip file, and please download and install 7Zip from here and use it
to unzip the .gz file to .tar file and then unzip .tar file (please notice that you need to unzip the
downloaded file twice) to a folder that will include the installer files. After this step, you would
have a file called xsetup.exe in the unzipped folder.
3. Follow the following steps to install the Vivado software on your computer, please notice that the
software installation process will take a long time and it will take about 30G bytes of storage space on
your hard drive.
Step 1. Start the software installer program xsetup.exe after downloading.
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Step 2. Click Next on the welcome screen.
Note: If you saw the following screen to ask you to get the latest version, please click “Continue” instead
of “Get latest”.
Step 3. Input your Xilinx ID and password (you need to create one if you didn’t do it yet).
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Step 4. Make sure you choose Vivado HL WebPACK to continue.
Step 5. Please make sure you ONLY select “Artix-7” under the Devices group and select the SDK option.
Meanwhile, please uncheck DocNav, System Generator for DSP, and Model Composer options (this is to
reduce the installation time and the disk storage usage of your computer, you can also find the space
requirement of the installation on the bottom left corner of this screen).
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Step 6. Select the default installation directory (C:\Xilinx) to start the installation process.
Step 7. This installation process will download about 10G bytes of data from the internet and could take
more than 1 hour to finish, please make sure the internet connection is stable and the power of your
computer is always connected during the whole process.
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Step 8. After the installation is completed :
A. Go to website: https://github.com/Digilent/vivad o-boards to download repository vivadoboards to a local folder and unzip it, then copy all the contents of subfolder \new\board_files\ to
the installed Xilinx folder(C:\Xilinx\Vivado\2019.1\data\boards), make sure after this copy, all
the board files are under C:\Xilinx\Vivado\2019.1\data\boards\board_files directory as the
following picture shows, and double check if you have a directory named
“C:\Xilinx\Vivado\2019.1\data\boards\board_files\arty-a7-100”. Please notice that this is
essential for the BUS project, you must have it in the right directory.
B. Go to website: https://github.com/Digilent/vivado-library to download repository vivado-library to
the local folder and unzip it, then copy it to the local folder C:\Xilinx.
o Start Vivado software, go to Tools -> Settings -> General -> IP Defaults and add the path of
this folder the local folder. This setting will apply to newly created projects.
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Now the installation and configuration the software Vivado 2019.1 is finished, and you can use this
software to create projects.
Part 2. Use Vivado to design a logic circuit in VHDL.
4. After the software is installed, you are ready to use the Vivado to design the circuit for FPGA.
5. Start Vivado 2019.1 from “Windows -> programs -> Xilinx program groups->Vivado 2019.1” or from the
Desktop shortcut.
6. After that, click “Create Project” OR go to Menu->File->Project->New to follow the “create a new Vivado
project” procedures to create the new project.
7. You need to have a specific directory to save this project, such as the C:\XilinxCode\Lab5 directory used in
this example.
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8. Choose the RTL Project and make sure you check “Do not specify sources at this time” in this step. RTL
stands for register transfer level. This approach intends to create high-level representations of a circuit so
that the lower-level representations and ultimately actual wiring can be achieved. It implies that the VHDL
code is used to describe how data is transformed as it is passed from register to register. The transforming
of the data is performed by the combinational logic that exists between the registers.
9. On the next screen, please choose the FPGA part number “XC7A100TCSG324-1”. That is the FPGA part on
the Arty-A7 board. You can narrow down the part list by filtering the corresponding parts in the dropdown
lists.
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Or you can choose from the list of the Boards tab, please choose Arty A7-100:
10. After the project is created, you can create a VHDL code in the project and test the circuit with the simulator
or the Arty A7 trainer board.
11. By default, the program language is chosen to be Verilog, as we will be using VHDL, please click the Target
Langauge and Simulator Languaage under the Project Summary, and make sure you change them to
VHDL.
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12. Now click Add sources under Project Manager tasks of the Flow Navigator pane (or you can use Alt+A
shortcut), then choose Add or create design sources on the next screen. Lastly, choose Create File, make
sure you choose VHDL as the “file type” and give a name to the file. Then follow the dialog box procedures
to create an empty VHDL file.
13. After you finish the previous step, a new VHDL file under the Design Sources tab of the Project Manager
pane is created. Double click this file to edit the file. Please type the following code into your VHDL code
editor, and make sure you change the entity name (the highlighted part in the code) to your VHDL file’s
name (in this example, it is called Lab5.VHD). Fix any syntax errors if there are any.
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library IEEE; use
IEEE.STD_LOGIC_1164.ALL;
entity Lab5 is
Port (A, B, C, D:in std_logic;
X, Y, Z:out std_logic); end Lab5;
architecture Behavioral of Lab5 is
begin
X
<= (A AND B) OR C;
Y
<= (A AND (NOT B)) OR ((NOT A) AND C);
A OR B OR D; end Behavioral;
Z <=
Figure 1 Sample VHDL Code
14. Till now, you have created the source code for the circuit to be tested. This circuit has 4 inputs (A, B, C, D)
and 3 outputs (X, Y, Z). The block diagram is shown as below.
15. To test this circuit in the future, you need to assign the 4 input pins to 4 switches and 3 output pins to 3
LEDs on the trainer board, this is done by generating a Xilinx Design Constraints (.XDC) file for the project.
A template of the XDC file is already provided with this manual (Arty-A7-100-Master.xdc), and you need
to add it to the project by clicking “Add Sources” (or using ALT+A shortcut), then choose the option “Add
or create constraints”.
16. On the next screen, click “Create File” and give a new file name for this constraint file.
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17. Open this file Lab5_XDC.xdc by double-clicking the “Sources->Constraints->constrs_1->Lab5_XDC.xdc”.
Then copy and paste all the contents of the Arty-A7-100-Master.xdc to the file Lab5_XDC.xdc.
18. Read the comments at the beginning of the .XDC file. Then update the Lab5_XDC.xdc file by doing the
following:
a. Remove the hash (“#”) character of the first FOUR lines in the “##Switches” section, and
assign A, B, C, and D after the “get_ports” curly brackets, respectively. Four switches on
the trainer board will be served as the inputs to the circuit.
b. Remove the hash (“#”) character of the first THREE lines in the “## LEDs” section, and
assign X, Y, and Z after the “get_ports” curly brackets, respectively. Three LEDs on the
trainer board will be served as the outputs of the circuit.
c. After these changes, save the file. The .XDC file should have something like the following
picture, please pay special attention to the highlighted area.
d. Please don’t make any other changes to this file to avoid any mistakes.
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19. At this point, you have assigned the switches SW0 to SW3 on the trainer board as the inputs A to D of your
circuit, and LED0 to LED2 (labeled as LED 4 to 6 on the circuit board) on the trainer board as the outputs X,
Y, and Z of your circuit, respectively.
Part 3. Use Vivado to Perform RTL analysis on the source file
20. Expand the Open Elaborated Design entry under the RTL Analysis tasks of the Flow Navigator pane and
click on Schematic. It will display the synthesized schematic circuit of your VHDL code. As you can see, your
circuit should have 4 inputs and 3 outputs.
Part 4. Simulate the Design using the Vivado Simulator
21. The purpose of the simulation is to verify if the design is correct before it is implemented. In this section,
you will use the Vivado simulator to simulate the design.
22. To simulate the circuit you build in part 3 with VHDL code, you need to have the following components:
a. The original entity (which is the circuit from part 3) in the project, this is called the UUT (unit under
test). – You have already finished this step in part 3.
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b. A testbench VHDL entity, which would specify the inputs to the UUT and prepare for the simulation. A
testbench is a VHDL entity without any input/output ports. It contains both the UUT and the input
stimuli for the simulation. The output signals can be monitored by the simulator after the simulation is
done. – You will need to specify a testbench entity in the next few steps.
Testbench (in VHDL)
Input
Stimuli
UUT
Output
Monitor
23. Similar to the procedure to add the VHDL design file into the project, please go to “File -> Add sources” (or
use Alt+A shortcut), and choose “Add or create simulation sources” this time.
24. On the next screen, please select “Create file” and input the name of the testbench. In this example, the
file name is called Lab5_Sim. On the next a few screens, leave all the selections as default settings, and
finish the creation of the testbench.
25. Now under the “Sources” pane, find the VHDL source file “Lab5_Sim.vhd” and double-click to open it. Copy
and paste the following code into this file and save it. Please read through the comments (the contents
start with “--“, and try to understand the functions of the Test_bench architecture.
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-- the library and package needed for the VHDL code.
library IEEE; use
IEEE.STD_LOGIC_1164.ALL;
entity Lab5_Sim
is
-- As a testbench, it must be an entity without any ports.
end Lab5_Sim;
-- Define the architecture description of the Lab5_Sim testbench.
architecture Test_bench of Lab5_Sim is
-- This section must be inside the architecture and before the keyword "begin".
component Lab5
Port (A, B, C, D:in std_logic;
X, Y, Z:inout
std_logic);
end component; -- declare the entity you want to
test.
signal A, B, C, D, X, Y, Z: std_logic; -- declare the
signals.
begin -- This is the beginning of the description of Test_bench
-- define the UUT as Lab5, which is the entity to be tested. Lab5 is the name of the
entity, it could be different and depend on the entity of your name.
UUT:Lab5
PORT MAP (
A => A,
B => B,
C => C,
D => D,
X => X,
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Y => Y,
Z => Z
);
-- Port map makes the wire connections between the input signals and the UUT.
-- Each process here defines the behavior of an input signal.
SignalA: PROCESS -- The process SignalA to define the behavior of signal A in the
simulation.
begin
A
<='0'; loop
wait for 100 ns;
-- Signal A
flips every 100ns.
A <= NOT A; end loop;
end PROCESS; -- end of this process
SignalB: PROCESS -- This process is to define the behaviour of signal B in the
simulation.
begin
B
<= '0'; loop
wait for 200 ns;
-Signal B flips every 200ns.
B <= NOT B;
end
loop;
end PROCESS;
-- end of this process
SignalC: PROCESS -- This process is to define the behaviour of signal C in the
simulation.
begin
C
<='0'; loop
wait for 400 ns;
-- Signal
C flips every 400ns.
C <= NOT C; end loop;
end PROCESS;
-- end of this process
SignalD: PROCESS -- This process is to define the behaviour of signal D in the
simulation.
begin
D
<='0'; loop
wait for 800 ns;
-Signal D flips every 800ns.
D <= NOT D; end
loop;
end PROCESS;
-- end of this process
end Test_bench; -- end of the architecture of Lab5_Sim
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26. After the testbench VHDL code is created and saved, it will be used to test the UUT (the circuit you build in
part 3). First of all, you need to configure the simulation settings, and right-click the Simulation task under
Flow Navigator pane and choose “Simulation Settings...”.
27. In the simulation settings screen, please make sure the Simulator language is set to VHDL, and the
Simulation top module name is “Lab5_Sim”, which is the same as defined in the testbench. Also, please set
the runtime (which is specified by xsim.simulate.runtime) to be at least 3200ns. This is the time length of
the simulation.
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28. Next, click the “Run Simulation”, and choose “Run Behavioural Simulation” to start the simulation. Please
notice that this process will take some time. You may need to temporarily disable the Antivirus program
on your computer OR put your whole project directory under the “Exception” list in the Antivirus
software to avoid future problems.
29. After the simulation is over, a waveform screen will pop up, in the “Objects” window, you will see a list of
the signals defined in the testbench circuit. Please select all the signals (Shift + mouse click) and choose
“Add to waveforms”.
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30. Click on Run Simulation under the Simulation tasks of the Flow Navigator pane again, after the simulation
is over, a waveform screen will show up, and the results of the simulation will be shown on the waveform
viewing window. You can move the yellow vertical “marker” to observe the values of the inputs/outputs of
the circuits. E.g., at time stamp 0.151825µs of the following screenshot, A=1, B = C = D = 0, the outputs X =
0, Y = 1 and Z = 1.
31. To this step, you have finished the behavioral simulation process, and all the results should be verified
before you download your circuit to the FPGA board.
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Part 5. Synthesize the Design
32. Click on Run Synthesis under the Synthesis tasks of the Flow Navigator pane. The synthesis process will be
run on the Lab5.vhd (and all its hierarchical files if they exist). This process will take some time, and when
the process is completed, a Synthesis Completed dialog box with three options will be displayed.
33. Select the Open Synthesized Design option and click OK as you want to look at the synthesis output before
progressing to the implementation stage.
34. Click on Schematic under the Open Synthesized Design tasks of Synthesis tasks of the Flow Navigator pane
to view the synthesized design in a schematic view.
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Part 6. Implement the Design
35. Click on Run Implementation under the Implementation tasks of the Flow Navigator pane. The
implementation process will be run on the synthesis output files. When the process is completed an
Implementation Completed dialog box with three options will be displayed.
36. Select Open implemented design if you want to look at the implemented design in a Device view tab. You
can also find all the generated netlist under the netlist tab.
Part 7. Generate the Bitstream File
37. The bitstream file is the binary file of your design that is generated to program the FPGA. This file will be
downloaded to the Arty A7 trainer board.
38. Click on the Generate Bitstream entry under the Program and Debug tasks of the Flow Navigator pane.
The bitstream generation process will be run on the implemented design. This process will have Lab5.bit
file generated under impl_1 directory which was generated under the Lab5.runs directory.
39. When the process is completed a Bitstream Generation Completed dialog box will be displayed, and you
can choose “View the reports” to find all the former procedures’ reports.
Part 8. Verify functionality on the trainer board (needs to use Arty A7 trainer board)
40. Please connect the provided Micro-USB cable between the board and your PC. Note that you do not need
to connect the power jack because the board can be powered and configured via USB alone.
41. In Vivado, select the Open Target option and choose Auto Connect, if any. Also, try to click the Program
device to start the program on the FPGA board.
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42. After the program is finished, you can verify your circuit on the Arty A7 board. Verify the functionality by
flipping switches and observing the output on the LEDs.
43. If you need to see the project summary at any time, you can click the menu option Window->Project
Summary to see the summary report of your working project. Refer to the following picture.
44. Congratulations for finishing the first Vivado FPGA programming project! After you finish all these
procedures, close the hardware session by selecting File > Close Hardware Manager and exit the program.
Conclusion
This lab introduces the general procedures to build a Vivado project, prepare the VHDL source code and
testbench entity, simulate the circuit, implement the circuit, and verify functionality on the Arty A7 trainer
board. Please keep in mind that the project needs to prepare at least three input files from the users to
finish a complete design:
1. The VHDL source files for the circuits/entities. (.VHD files)
2. The testbench VHDL files to set up the input signals for the unit under test (UUT) and monitor the
outputs (.VHD files).
3. The Xilinx Design Constraints (.XDC) file to assign the input/output pins to implement and verify
the FPGA design on the Arty A7 trainer board.
In future labs, you will need to follow the similar procedures described in this lab to complete the whole
designs.
Reference:
[1 ] Vivado Tutorial, Xilinx Inc. www.xilinx.com/university
[2] Kleitz, William. Digital Electronics: A Practical Approach with VHDL. Upper Saddle River, NJ: PrenticeHall.
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Lab Report Submission Requirements
Please use the template Word document provided, prepare a report (in PDF or Word document format)
with the following:
1. Install the Vivado software on your computer, and follow the procedures from procedure 1 to 8 to finish
the complete design (if the trainer board is available). Please indicate if you have finished this step in
the report.
2. Based on the timing simulation results in Part 4, fill in the following truth table:
Inputs
Outputs
D
C
B
A
0
0
0
0
Z
Y
X
0
0
0
0
0
0
1
1
1
0
0
0
1
0
1
0
0
0
0
1
1
1
0
1
0
1
0
0
0
1
1
0
1
0
1
1
1
1
0
1
1
0
1
1
1
0
1
1
1
1
0
1
1
0
0
0
1
0
0
1
0
0
1
1
1
0
1
0
1
0
1
0
0
1
0
1
1
1
0
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
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1
1
1
0
1
1
0
1
1
1
1
1
1
1
3. Go to the menu option “Window-> Project Summary” and get the screenshot of the project summary
report, please include this screenshot in your lab report. You can use the Windows Snipping Tool to get
the screenshot easily.
4. Get the screenshots of Simulation (make sure you click “Zoom Fit” button
screenshot. Please include this screenshot in your lab report.
before you get the
5. Get the screenshot of the Schematic under the Implementation tasks of the Project Navigator pane.
Please include this screenshot in your lab report.
6. Please attach your revised .XDC file with the report submission. This file could be found under the
“/Lab5.srcs/constrs_1/new/” folder of your project. It should be a separate file submitted with your
final lab report.
7. Please attach your final bitstream file (.bit file) with the report submission. This file could be found
under the “/Lab5.runs/impl_1/” folder of your project. It should be a separate file submitted with
your final lab report.
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