Design, Manufacturing, and Modelling
Challenges for Very-Large-Scale Integrated
Quantum Processors in Foundry CMOS
Technology
Sorin P. Voinigescu
University of Toronto
STMicroelectronics, Crolles, September 22, 2023
1
Acknowledgments: Graduate Students
l
Shai Bonen, Alireza Zandieh, Sadegh Dadash, Utku Alakusu,
l
Lucy Wu, Mecca Gong, Tony Liu, Greg Cooke, Alex Hsu, Jianan Zhao, Srirup Bagchi
l
Suyash Pati Tripathi, Apurv Bharadwaj, Thomas Jager, Julie McIntosh
l
Yu Duan, Ayse Ozdincer
l
Vivek Dhande, Andrei Olar
Voinigescu
2
Current Research Topics & Collaborations
o
Quantum Processors at 4-12 K (NSERC, Ciena, GF, EU IQubits)
o
Technology scaling characterization (Ciena, STM, GF, NTT)
-
5nm, 3nm FinFET, 22nm FDSOI, 450GHz SiGe BiCMOS,
700/1000 GHz InP HBT
o
250GBaud (>125GHz bandwidth) ADCs, DACs, modulator drivers
and TIAs (NSERC, Ciena, Marvell, fJscaler, NTT)
o
mm-wave radar sensor transceivers (Bosch)
Sorin P. Voinigescu
Research overview
3
Agenda
o
QP Architecture Challenges
o
Cryogenic QP Test Vehicle Characterization
o
Qubit Array Manufacturing Challenges
o
Qubit Array Modelling Challenges
o
Conclusions
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
4
Why Do We Need fRABI >1 GHz and T1,2 >1 ms?
Need isotopic purification
[S. Huang, IEDM 2020]
of Si29
2fRabi✕T1,2 > 106 circuit depth
2q error ~ 10-5 =>
Voinigescu
•
(IQ) phase error < 0.2o
•
SNDR > 50 dB
Cryo mm-wave Characterization, Modelling, Design Methodologies
5
Quantum Processor: 5-200 GHz FDM+Reflectometry
Block diagram by Shai Bonen
As in 5G/radar/fibreoptic
systems
As in 5G/radar transmitter
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
As in 5G/radar receiver
6
Quantum Processor: 5-200 GHz, Small Footprint
Block diagram by Shai Bonen
Voinigescu
As in 5G/radar transmitter arrays
as in fibreoptic receivers
Also needed for photonics QP
Cryo mm-wave Characterization, Modelling, Design Methodologies
7
The SiGe p-MOSFET is The SiGe Hole-Spin Qubit
o
o
𝛥𝑉#$
𝑞
=
𝐶%
𝛥𝑡 =
o
𝑞
𝐼&$
L=18 nm; W = 50 nm
source/drain-to-channel
heterojunction: ΔEV = 35-40 meV
toxe= 1 nm => larger fR than thick
oxide/semiconductor qubits
[S. Bonen et al., EDL 2019]
with Bdc
B= 2.5 Tesla
Bdc
z
|0>
|1>
E2—E1 =4-6 meV>>10kT
[S. Pati Tripathi, et al., JED 2022]
y
x
Voinigescu
𝐵 = 0,0, 𝐵!"
Bac(t)
Cryo mm-wave Characterization, Modelling, Design Methodologies
8
22nm FDSOI DQD with Selective Backgate
Sentaurus simulation at 300 K
[S. Bonen et al., EDL 2019]
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
9
1024 DQD Array+Readout With Selective Backgate
[S. Bonen, PhD proposal 2022]
• Oxide spacers between top gates create
potential barriers
• Need selective back gate between top gate pairs
with <50 nm gate pitch
• Possible only every 5 top gates in 22nm FDSOI
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
10
Reduced-Crosstalk Control-Signal Distribution Scheme
[S.P. Voinigescu, S. Bonen, et al. US patent 2021]
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
11
Passive IQ Modulator Array to Drive Qubit Array
• Control & readout circuits need same
pitch as minimum size transistor
• Process variation in minimum size FET
• Layout crosstalk mitigation needed
Voinigescu
•
Architecture scalable to 200 GHz
•
n-MOSFET passive IQ modulator for
each qubit
•
Reuse of 80GHz radar PLL and tag SSB
modulator
•
No room for inductors
•
Transistor scaling needed < 20 nm pitch
Cryo mm-wave Characterization, Modelling, Design Methodologies
12
Characterization of MOSFET(s) as
QD/SET/SHT (Arrays)
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
13
FDSOI L=18nm, W=50nm SHT Flavours: 2K, B=2.5T
• Vt defined as VGSp1
• Impact of Vt implants
on quantum cap.,
Coulomb peaks
• Vt variation between
identical devices
100’s
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
µm apart
14
SHT and SET Coulomb Peaks @2K in 22nm FDSOI
1x18nmx70nm
Measurements at IMT, EU IQubits project
[S. Pati Tripathi, et al., JED 2022]
Coulomb peaks can be controlled from back gate
Entire transfer characteristics shifted by ~90 mV/V, as at 300 K
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
15
Back Gate Voltage Dependence of Current Peak VGS
not published
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
16
SET Behaviour vs. Backgate Captured by QuantumATK
[V. Dhande, self-study course report 2023]
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
17
5nm FinFET Si(Ge) QD Behaviour at 9-35 K
p-MOSFET
n-MOSFET
[S. Pati Tripathi MASc thesis 2022]
Behaviour present in subthreshold in all FinFETs irrespective of Nf, Nfin
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
18
QuantumATK Simulation of Scaled Nanowire, FinFET
1.8nm
1.175nm
1.28nm
5nm
1.1nm
1.175nm
1.28nm
Voinigescu
5nm
Cryo mm-wave Characterization, Modelling, Design Methodologies
19
QuantumATK Simulation of Scaled Nanowire, FinFET
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
20
Process Variation at 2 K in 512 SHTs in Parallel
512x18nmx50nm
Small variation between
dies at 2 -11 K,
dies # 1, 21, 22
VBG = 0.5 to -4 V
not published
VDS = -1 mV
Different current peak values and shapes
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
21
Repeatability of 512 QDs in 3nm FinFET
• As with the 22nm FDSOI 512 QD Array, even better match between
dies in exponential subthreshold regions at both 300 K and 2 K
• But the Coulomb IDS peak values and their VGS positions vary,
dominated by lowest Vt QD in the 512 QD Array
not published
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
22
The Coupled Quantum Dot Gate Challenge
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
23
1999 Burkard, Loss, DiVincenzo DQD Gate Proposal
QD-to-QD pitch 40-50 nm to match electron/hole spin orbit diameter
Need barrier gate between QDs
Gate pitch ~1/2 of QD pitch => 20-25 nm
Need self-aligned gates even in 3nm FinFET with ~23 nm gate pitch
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
24
Basel U, 4K Hole-Spin Si FinFET Qubit Process
~50 nm QD pitch
~25 nm gate pitch
~15 nm gate length
IQubits goal: 20 nm gate pitch
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
25
Commercial 3nm FinFET Gate/Contact Pitch
Gate Length 10-11 nm
[Chang et al., IEDM 2022]
[Wu et al., IEDM 2022]
Gate Pitch CPP: 45 nm
Metal Contact Pitch: 23 nm
Fin pitch < 30 nm
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
26
Impact of Ungated Channel Regions
•
•
•
Sentaurus TCAD simulations
of GaN HEMT 3dot
structures [by Ayse
Ozdincer]
Difference between the 2
structures is whether Gate 2
overlaps across the adjacent
spacers (right) or not (left).
Simulated at 300 K, with VG1
= VG3 = -2.5V and VG2 = 0V
for both devices.
Barriers under spacers
between gates cannot be
suppressed without gate
overlap, demonstrating that
ungated regions will always
leave barriers in quantum
dot arrays.
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
27
QuantumATK Simulation of Scaled DQD
To investigate:
[V. Dhande, summer research report 2022]
• swap-gate scaling
• control of the inter-dot barrier by selective backgate
Voinigescu
28
Simulated DQD Potential Profile DoS vs. VBG
VG1=VG2 = 200 mV
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
29
Impact of Barrier Gate Spacer Width in DQD
Scaled FDSOI DQD structures with top or bottom barrier gates and different spacer
lengths to the adjacent plunger gates were simulated at 10 Kelvin to guide future FDSOI
process changes to accommodate coupled qubit arrays.
Non-overlapping gates lead to parasitic potential barriers between the coupled QDs
affecting qubit fidelity and introducing non-linearities.
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
30
Impact of Spacer Width on Parasitic Barriers
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
31
Required Process Changes for DQD Arrays
o
Block diffusion and contact between gates to enable coupled QDs
o
Reduce gate pitch to match the spin orbit length of electrons or
holes to allow for strong tunnel coupling in exchange gates,
o
Reduce gate current <10 pA/µm to increase T1 ~ e/IG
o
without increasing short channel effects and VGS beyond 1 V, which would increase
the power consumption of the control electronics
o
Isotopic purification of Si and Ge in the QD array channel
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
32
Agenda
o
QP Architecture Challenges
o
Cryogenic QP Test Vehicle Characterization
o
Qubit Array Manufacturing Challenges
o
Qubit Array Modelling Challenges
o
Conclusions
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
33
On-Die mm-Wave Setup at 2 K With 2.5 Tesla VF
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
34
DC-80 GHz 2-Lane QP Test Vehicle
Bias circuit & technique
verification
QD transfer char.
QD heating study
QD µ-wave absorption
S-param meas.
• lane gain, BW
18nmx50nm p-MOSFETs
as qubits and readout SHTs
Voinigescu
single-spin gate
characterization
Cryo mm-wave Characterization, Modelling, Design Methodologies
35
DC-80 GHz 2-Lane QP Test Vehicle
• lane gain, BW
• switch isolation
• SHT to SHT
coupling
• single-spin gate
characterization
• two-spin gate
[L. Wu MASc. Thesis, 2022]
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
characterization
36
Constant Current-Density Bias Circuit
DQD qubit with readout TIA
[S. Bonen et al., SSE 2022]
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
37
SHT Heating in QP, 2.5T, 2K: Zoom at Peaks 1,2
Pdc = Wtotal*Jbias*0.8V
Pdc = 0 … 36 mW
• Peaks broader as
Jbias increases
• VGS at peak
~constant
[L. Wu, MASc thesis 2022]
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
38
SHT Measurements in QP vs. Temperature
Floating backgate
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
39
QD Capacitance vs. Temperature
𝛥𝑉#$
𝑞
=
𝐶%
𝛥𝑡 =
𝑞
𝐼&$
B= 2.5 Tesla
Floating backgate
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
40
SET-to-SET Readout DC Coupling Experiment
Transfer A, B peaks & valleys
Needed for direct readout circuit design
Measurements at IMT
EU IQubits project
[S. Pati Tripathi, et al., JED 2022]
VDS =1 mV
Floating backgate
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
41
Gyromagnetic Factor Measurements at DC
18nmx70nm p-MOSFET, 6 gate dummies
Measurements at IMT EU IQubits project
• Measurements conducted on two different days
• Probes lifted during B-field sweep, January 2020
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
42
Gyromagnetic Factor vs. Back Gate Voltage: Day1/2
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
43
Gyromagnetic Factor From µ-Wave Absorption
Pin = -50 dBm, B = 0.4 T
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
44
Agenda
o
QP Architecture Challenges
o
Cryogenic QP Test Vehicle Characterization
o
Qubit Array Manufacturing Challenges
o
Qubit Array Modelling Challenges
o
Conclusions
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
45
Investigated Issues
o
Repeatability and yield of Coulomb peaks
o
Gate leakage current
o
Process waivers to block diffusion and contact
formation between gates
o
Selective backgate for DQDs
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
46
Process Variation in 128 QD Array with SHT Readout
[S. Bonen, PhD proposal 2022]
• 3x1dot 128 array: 3 independent
18nmx50nm QDs
• 1dotx1dotx1dot 128 array:
Wf =70nmx50nmx70nm
• 3dot within 128 array
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
47
Layout Detail of 128 QD Array
128x18nmx50nm p/n qubit array with 128x18nmx70nm SHT/SET
readout above and below.
Green marks the active channel area
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
48
QD Process Variation at 2 K by Location in QD Array
not published
128x18nm50nm QD
array with 40 dummy
gates per side
Almost perfect match at 300 K!
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
49
QD Process Variation at 2 K by Location in QD Array
not published
128x18nm50nm p-type QD
array with 40 dummy
gates per side
VBG = 0.5, -2 and -4 V
VDS = -1 mV
Die #1
Similar variation as in n-type QD array
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
50
QD Process Variation at 2 K from die to die
Process variation may also be
due to small antenna diode
affecting integrity of gate
oxide
VBG = 0.5, -2 and -4 V
VDS = -1 mV
Die #22
Different current peak values and shapes
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
51
Test structure Die October 2022 Tapeout (19dot)
PMOS
PMOS Backgate
NMOS
NMOS Backgate
Voinigescu
22FDX QD/QD Array Characterization from
October 2022 Tapeout,
CONFIDENTIAL
52
Test Structures in October 2022 Tapeout
q Single QD (1dot 1x18nmx50nm in QPU Array with 1104
gates) with ~24.5 dB attenuator on gate)
q 512x QD (512x18nmx50nm in QPU Array with 1104 gates)
q QD Array with 4 top gates and selective backgate (4dot
1x18nmx50nm in QPU Array with 1104 gates)
q QD Array with 19 top gates and full backgate (19dot
1x18nmx50nm in QPU Array with 1104 gates)
Voinigescu
22FDX QD/QD Array Characterization from
October 2022 Tapeout,
CONFIDENTIAL
53
QD in 1014 QD Array with 24dB Gate Attenuator
NMOS
PMOS
• Provides a baseline single QD against
which we can compare QD arrays
• Broadband attenuator at the gate
designed to reduce 300K noise below 2K
noise while being co-located on-die to
reduce the noise it generates on its own
• On-chip decoupling capacitance on the
drain (~18 pF) reduces the noise BW
• Table of kT/C voltage noise for 18 pF is
shown at right
• Attenuator bandwidth over 100 GHz
Voinigescu
Temp [K]
Voltage Noise on Drain [μVrms]
300
15.1
2
1.23
0.1
0.275
22FDX QD/QD Array Characterization from
October 2022 Tapeout,
CONFIDENTIAL
54
1x18nmx50nm SLVTN With Attenuator: 4 Dies
T = 300 K
VDS = 800mV
VDS = 1mV
Ig below setup leakage
until VGS > 0.6V at 300K
Voinigescu
The MOSFETs are generally wellmatched over process above
subthreshold, with more noticeable
variation in subthreshold.
22FDX QD/QD Array Characterization from
October 2022 Tapeout,
CONFIDENTIAL
55
1x18nmx50nm SLVTN With Attenuator over Temp.
• Measurement setup noise
floor is ~100 fA
Die #38
• Some peaks buried in noise
• Peaks decrease in current
value than increase vs.
backgate bias voltage
Voinigescu
22FDX QD/QD Array Characterization from
October 2022 Tapeout,
CONFIDENTIAL
T = 2 K, 300 K
56
1x18nmx50nm SLVTP With Attenuator: 4 Dies
T = 300 K
VDS = -800mV
VDS = -1mV
Ig below setup leakage
until VGS < -0.3V to
0.6V at 300K
The MOSFETs are generally wellmatched over process above
subthreshold, with more noticeable
variation in subthreshold.
Some variation in the gate leakage
current between different PMOS.
Voinigescu
22FDX QD/QD Array Characterization from
October 2022 Tapeout,
CONFIDENTIAL
57
1x18nmx50nm SLVTP With Attenuator Over Temp.
• Measurement setup noise floor
Die #38
is ~100 fA.
• Some peaks buried in noise.
• The PMOS peak current values
T = 2 K, 300 K
seem to be monotonically
increasing with backgate
voltage bias, at least more so
compared to NMOS
Voinigescu
22FDX QD/QD Array Characterization from
October 2022 Tapeout,
CONFIDENTIAL
58
[7p]
SLVTP/N 1dot 1x18nmx50nm vs. VBG at 2K, 2 Dies
d
g
Voinigescu
22FDX QD/QD Array Characterization from
October 2022 Tapeout,
CONFIDENTIAL
Repeatability on Two Dies: 300 K vs. 2 K
Mismatch at 2 K
similar to 300 K
IG< 0.5 pA
Vt mismatch different
trends for n/p QDs
p/n QDs
uncorrelated
not published
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
60
Test Structures in October 2022 Tapeout
q Single QD (1dot 1x18nmx50nm in QPU Array with 1104 gates)
with ~24.5 dB attenuator on gate)
q 512x QD (512x18nmx50nm in QPU Array with 1104 gates)
q QD Array with 4 top gates and selective backgate (4dot
1x18nmx50nm in QPU Array with 1104 gates)
q QD Array with 19 top gates and full backgate (19dot
1x18nmx50nm in QPU Array with 1104 gates)
Voinigescu
22FDX QD/QD Array Characterization from
October 2022 Tapeout,
CONFIDENTIAL
61
512x18nmx50nm SLVTN in 1104 Array: 4 Dies, 300K
Matching over process for
512x devices is excellent
T = 300 K
VDS = 800mV
VDS = 1mV
Max Ig of 1x18nmx50nm was
~1pA. For 512x18nmx50nm
we get about 512x that value
Since Ig @ Vg = 0.8V is about 512x the Ig of the 1x device,
the gate current of this device can be scaled by 512 to get
an estimate of the 1dot.
Layout of this device consists of connecting device #1 #512 from the 1024 array with every other gate connected
to make 512x18nmx50nm overall
Voinigescu
22FDX QD/QD Array Characterization from
October 2022 Tapeout,
CONFIDENTIAL
62
512x18nmx50nm SLVTN in 1104 Array Over Temp.
• Measurement setup noise floor
is ~100 fA.
Die #42
• Jump in current at ~1µA is due
to instrument changing its ADC
range.
T = 2 K, 300 K
• Peaks are due to 512
devices in parallel. The QDs
with the lowest Vt will have
the most clearly visible
peaks in subthreshold.
Voinigescu
22FDX QD/QD Array Characterization from
October 2022 Tapeout,
CONFIDENTIAL
63
512x18nmx50nm SLVTP in Middle of 1104 Gate Array:4 Dies
VDS = -800mV
T = 300 K
Matching over process for
512x devices is excellent
VDS = -1mV
Max Ig of 1x18nmx50nm was
~1pA. For 512x18nmx50nm
we get about 512x that value
Since Ig @ Vg = 0.8V is about 512x the Ig of the 1x device,
the gate current of this device can be scaled by 512 to get
an estimate of the 1dot.
Layout of this device consists of connecting device #1 #512 from the 1024 array with every other gate connected
to make 512x18nmx50nm overall
Voinigescu
22FDX QD/QD Array Characterization from
October 2022 Tapeout,
CONFIDENTIAL
64
512x18nmx50nm SLVTP in Middle of 1104 Top Gate Array
• Measurement setup noise
floor is ~100 fA.
• Jump in current at ~1µA is
due to instrument changing
its ADC range
Die #42
T = 2 K, 300 K
• Peaks are due to 512
devices in parallel. The QDs
with the lowest Vt will have
the most clearly visible
peaks in subthreshold
Voinigescu
22FDX QD/QD Array Characterization from
October 2022 Tapeout,
CONFIDENTIAL
65
Process Variation at 2-11 K Across 3 Dies
Small variation
between dies at 2-11 K
dies # 21, 22, 42
Temp. changed during
measurements from 2
to 11 K
Different current peak
values and shapes
512x18nmx50nm in 1104 gate array
Voinigescu
66
Test Structures in October 2022 Tapeout
q Single QD (1dot 1x18nmx50nm in QPU Array with 1104 gates) with
~24.5 dB attenuator on gate)
q 512x QD (512x18nmx50nm in QPU Array with 1104 gates)
q QD Array with 4 top gates and selective backgate (4dot
1x18nmx50nm in QPU Array with 1104 gates)
q QD Array with 19 top gates and full backgate (19dot 1x18nmx50nm
in QPU Array with 1104 gates)
Voinigescu
22FDX QD/QD Array Characterization from
October 2022 Tapeout,
CONFIDENTIAL
67
1x18nmx50nm SLVTN 4dot With 200nm Selective
Backgate Between Gates 2 and 3 (I): 7 Dies
T = 300K
VDS = 1mV
VBG = 0V, 2V, 4V
All gates are swept together
Voinigescu
Process variation may come from
placement of ~200nm selective
backgate relative to QD array and
not just the variation in the array
itself (i.e. it may have the backgate
closer to G1 side or G4 side)
4dot devices have four independent top-gates with
gates 1 and 4 tied together (“gate14”).
BG
22FDX QD/QD Array Characterization from
October 2022 Tapeout,
CONFIDENTIAL
68
1x18nmx50nm SLVTN With 200nm Selective
Backgate Between Gates 2 and 3 (II)
Want to prove that the backgate is selective. In these VDS = 1mV sweeps, “VGS” is either VG1 = VG4, VG2, or VG3 and
the other gates are held at 0.8V. Each curve corresponds to VBG = -0.5V to 4V in 0.5V steps.
Gate 2 and Gate 3
Gate 14 and Gate 3
Gate 14 and Gate 2
Die #39
T = 300 K
The backgate is indeed selective under gates 2 and 3 (and not under gate 1 or 4). The reasoning is that VBG has little
impact in the subthreshold region in the Vg14 sweep, but shows a change in series resistance in triode. There is more
VBG impact in the Vg3 sweep because VBG is impacting Rsource of G3 in addition to changing Vt of G3.
BG
Voinigescu
22FDX QD/QD Array Characterization from
October 2022 Tapeout,
CONFIDENTIAL
69
1x18nmx50nm SLVTN 4dot With 200nm Selective
Backgate Between Gates 2 and 3 (IV)
G2 and G3 are
swept together
Die #39
T=2K
VDS = 50 mV
VBG = 4 V
VG1 = VG4 = 0.8 V
With larger VDS, IDS does show
quantum effects.
Unfortunately, could not
measure this device further due
to probestation issue killing the
device
Voinigescu
22FDX QD/QD Array Characterization from
October 2022 Tapeout,
CONFIDENTIAL
70
Impact of Ungated Channel Regions (I)
•
•
•
Sentaurus simulation of the
4dot slvtn cross-section with
selective backgate.
The conduction band near
the top gate interface is
shown at a bias when all
gates and the selective
backgate are turned on (i.e.
VG1=VG2=VG3=VG4=0.8V,
VBG=4V, VDS=1mV)
The conduction band barriers
in the ungated region are
too high to be overcome at 2
K for transport
measurements at low VDS.
Voinigescu
22FDX QD/QD Array Characterization from
October 2022 Tapeout,
CONFIDENTIAL
71
1x18nmx50nm SLVTP 4dot With 200nm Selective Backgate
Between Gates 2 and 3 (I)
BG
4dot devices have
four independent
top-gates with
gates 1 and 4 tied
Devices need screening at together (“gate14”)
room temperature due to
gate leakage from not
having a large enough ANT
diode. Die 42 is an
example with low leakage,
Die 49 has nulls from gate
leaking into drain.
Voinigescu
22FDX QD/QD Array Characterization from
October 2022 Tapeout,
CONFIDENTIAL
T = 300 K
72
1x18nmx50nm SLVTP 4dot With 200nm Selective Backgate
Between Gates 2 and 3 (II)
T = 4.2 K
Die #42
BG
VBG = -2V, -4V
4dot devices have four
independent top-gates
with gates 1 and 4 tied
together (“gate14”)
VG1 = VG4 = -0.8V
VDS = -0.1V
|IDS| reduced by
gate leakage
Voinigescu
IDS is reduced at cryogenic temperature compared to 300
K. Gate leakage (due to not having large enough ANT
diode on this tapeout) causes noisier IDS at low temperature
despite gate leakage being sufficiently small at 300 K.
Larger ANT diode on future fabrication run should reduce
the gate leakage.
22FDX QD/QD Array Characterization from
October 2022 Tapeout,
CONFIDENTIAL
73
1x18nmx50nm SLVTP 4dot With 200nm Selective
Backgate Between Gates 2 and 3 (III)
The double-QD between G2 and G3 appears to be in a low coupling
regime (despite the VBG = -4V bias), so the capacitance between dots
(C23) can be estimated from the slope of the black line tracing the first
peak (S), the capacitance of each individual QD to its environment
(Ctot), and the equation [Ferry 2009 Transport in Nanostructures]:
𝐶#$#
𝐶!" ≈
𝑆+1
Regular 1dot 1x18nmx50nm SLVTP devices typically have ~32mV
spacing between first 2 peaks (corresponds to Cg = 5aF through
electron charge) and a gate lever arm of ~0.75 (making Ctot ~=
6.675aF). The slope is estimated as 15.8 V/V (VG3 vs VG2), so C23 ~=
Ctot/16.8 = 0.397aF. There is a lot of uncertainty in estimating the
slope since it is near vertical and the VG2/VG3 step size is 2mV/5mV.
Die #42
Voinigescu
Does this value make sense? If we assume C23 can be approximated
as a parallel plate capacitance through the Si0.75Ge0.25 (relative
permittivity of 12.825) between G2 and G3 and we note Wf = 50 nm,
tchannel = 6 nm, distance between G2 & G3 d = 86 nm:
𝜀- 𝜀(,.)/' 𝑊0 𝑡*&+11',
𝐶!",#&'$('#)*+, =
= 0.396𝑎𝐹
𝑑
Theoretical C23 close to the measured C23. In conclusion, we need the
gate-to-gate pitch significantly reduced to enable strong coupling
regime for QDs in QD arrays.
22FDX QD/QD Array Characterization from
October 2022 Tapeout,
CONFIDENTIAL
74
Test Structures in October 2022 Tapeout
q Single QD (1dot 1x18nmx50nm in QPU Array with 1104 gates)
with ~24.5 dB attenuator on gate)
q 512x QD (512x18nmx50nm in QPU Array with 1104 gates)
q QD Array with 4 top gates and selective backgate (4dot
1x18nmx50nm in QPU Array with 1104 gates)
q QD Array with 19 top gates and full backgate (19dot
1x18nmx50nm in QPU Array with 1104 gates)
Voinigescu
22FDX QD/QD Array Characterization from
October 2022 Tapeout,
CONFIDENTIAL
75
1x18nmx50nm SLVTN 19dot
Die 38
Evidence of tunnelling through 19 series QDs
IDS is much smaller than in a single dot
Why 19 top gates? This is
the minimum # of gates
to meet the minimum
area DRC rules for the
silicide-blocking mask
VDS = 1mV
VBG = -0.5V to 4V in 0.5V steps while allowing gate
contacts on both the
north and south sides of
the QPU array.
Voinigescu
22FDX QD/QD Array Characterization from
October 2022 Tapeout,
CONFIDENTIAL
76
1x18nmx50nm SLVTP 19dot vs. VBG over Temperature
Die 38
Strong evidence of tunnelling
through 19 series QDs which
indicates that the 19 dots have
very well-matched energy levels.
IDS is much smaller than in
single dot.
SiGe p-MOSFET channel behaves
better than Si n-MOSFET
channel and gate leakage is
smaller, ~1pA/gate, similar to
that of the single QD with
attenuator test structure.
Voinigescu
22FDX QD/QD Array Characterization from
October 2022 Tapeout,
CONFIDENTIAL
77
Lessons Learned on QPU Array Manufacturing
•
Larger antenna diode required for small MOSFET and QD array (ndot) test structures when
they are connected to pads for probing (i.e. should not waive ANT.RS.GT.1a)
•
Process waivers with SBLK and blocked doping reduce IDS (as expected), make the gate
more susceptible to antenna effect damage. Can addressed with larger antenna diodes
•
Selective backgate appears to be working, although we can only verify the impact of VBG on
transfer characteristics vs. individual gates (we don’t know how close to 200 nm we got)
•
Ungated channel regions in ndot structures make IDS too small to measure with small |VDS|
(< 50mV) at 2 K
•
Measurements of 4dot SLVTP suggest that gate-to-gate pitch needs to be smaller to enable
stronger QD coupling regimes in SLVTP devices
•
If selective backgates cannot be made narrower than 200 nm and placed more frequently
than every 5 gate pitches, and the gate pitch cannot be modified to enable additional top
gates to control barriers, a proper QPU will not be possible in 22FDX
Voinigescu
22FDX QD/QD Array Characterization from
October 2022 Tapeout,
CONFIDENTIAL
78
Next Steps
• The MOSFETs with attenuator have reliably low gate leakage, to
be tested as qubits with B-field in Toronto and Sydney.
• Additional devices can also be measured at 2 K to understand
process variation (die-to-die) of quantum effects and try to
correlate those to 300 K subthreshold behavior.
• Taped out structures in September 2023 with larger antenna
diodes and 4dots with full backgate to confirm our theories on
reducing gate leakage and to enable study of smaller quantum
dot arrays.
Voinigescu
22FDX QD/QD Array Characterization from
October 2022 Tapeout,
CONFIDENTIAL
79
Conclusions
Ø
Ø
Ø
FDSOI & FinFET SHTs/SETs show strong quantum effects in the 2-50
K range well explained and understood by QuantumATK
Large arrays of 512 QDs shunted together have low gate leakage
(<0.5pA/qubit) and are reproduceable across tapeouts
Selective backgate and diffusion blocking demonstrated for DQD
formation, but it is too wide and pitch is coarse
Challenges
l
l
Currently only linear arrays of single qubits and with coupled qubits
between every five top gates possible with control and readout
need finer gate pitch, overlapping gates with 5-6 nm spacers and 2D
tunnel-coupled qubit arrays
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
80
Conclusions (ii)
q
q
q
q
q
q
Process variation in SHTs/SETs due to oxide spacer variation not an
issue in qubit arrays but relevant for SET readout arrays
Gate leakage <0.5 pA with large antenna diode, but >10x
reduction still needed; thicker gate oxide increases SCE and control
voltage, PDC of control circuits
Gate pitch must be <25 nm if top barrier gates are used for DQDs
Alternatively, top gates and selective back gates with <50nm pitch
needed
Testing must be conducted in cryogenic probestation and limits
research progress speed
Wirebonding not a solution for process variation evaluation
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
81
Acknowledgments
l
Dr. N. Cave of GlobalFoundries
l
Dr. P. Schvan of Ciena
l
Dr. Juergen Hasch of Bosch
l
Dr. David Daughton of LakeShore Cryotronics
l
NSERC, OCE, Bosch, Ciena, and EU Horizon2020 IQubits for funding
l
GlobalFoundries for chip donations
l
Keysight, LakeShore Cryotronics for test equipment support
l
CMC and Jaro Pristupa for CAD tools and support
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
82
E-level splitting due to coupling between QDs
AlGaAs/GaAs/AlGaAs double well
Coupling frequency
𝑓' =
2𝛥𝐸
; 2𝛥𝐸 = 1𝑚𝑒𝑉 → 241.47𝐺𝐻𝑧
2𝜋ℏ
[S. Voinigescu, IJE Feb. 1989]
ΔE (or t or J) = coupling energy
ΔE must be > kT
Want electric control of ΔE (barrier) for
Swap or C-NOT gate
𝐸 = 𝐸 + 𝛥𝐸
(+
(
𝐸(− = 𝐸( − 𝛥𝐸
t=1 meV =>T=12 K, fLarmor=240 GHz
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
83
QD coupling energy splitting, T with scaling
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
84
Non-Selective Backgate Not Solution for DQD
VBG=0V
VBG=4V
VBG=4V
[Yu Hao Duan, Capstone project, UofT 2017]
VG1=VG2=0.8V, VDS=0V, VS=VD=0V
Voinigescu
22FDX QD/QD Array Characterization from
October 2022 Tapeout,
CONFIDENTIAL
85
QuantumATK Simulation of DQD Process Limitations
[V. Dhande, summer research report 2023]
Voinigescu
86
Desired 2D Array of 1M Tunnel-Coupled Qubits
1024x1024
qubit core matrix
Control and
readout planes
above and below
same package
Process changes
needed
[S.P. Voinigescu, S. Bonen, et al. US patent 2021]
Voinigescu
Monolithic QPs in FDSOI
87
LETI’s Proposal for 3D stacked >1M Qubit QPs
Top control and bottom readout planes
can be capacitively coupled to middle
qubit array plane
Bias and DAC circuits must be DC
coupled to 2D qubit array
On same die?
Voinigescu
Monolithic QPs in FDSOI
88
Technology Requirements for DQD Gate: UNSW
• Overlap of spacer oxide by barrier gate
• Using self-aligned gate technology
• 1.5 K electron-spin qubit operation
[W. Gilbert et al., Nature 2023]
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
89
INTEL’s Latest Qubit: Replace SiGe/Si/SiGe With Si
[Zwerver et al., Nature 2022]
• 1.5 K electron spin qubit operation
• Gate pitch ~50 nm, Gate length ~30 nm
• No barrier gate overlap of gate-oxide spacer but tall gate may help
• Gate oxide (III) too thick for <1 V control circuits
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
90
LETI’s Proposal at IEDM 2021
•
Gate pitch ~80nm not fine enough
•
Gate overlap of oxide spacer not adequate
•
Gate oxide too thick for <1 V control circuits
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
91
Agenda
o
QP Architecture Challenges
o
Cryogenic QP Test Vehicle Characterization
o
Qubit Array Manufacturing Challenges
o
Qubit Array Modelling Challenges
o
Conclusions
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
92
Simulate Control and Readout Ckts. With Qubit Core
Example 1D array with 20 QDs each
with individual capacitively coupled SHT
either above or below for readout.
Need VerilogA model of qubit array
[S. Bonen, PhD proposal 2022]
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
93
QD Model Added to Design Kit MOSFET Model
18nmx70nm n-MOSFET
-
𝐼) = <
*+,
𝑞" 𝑉&$
𝑘. 𝑇
−Δ𝐹&/ 𝑖
𝑞 𝑉
+ exp
+ exp " &$
𝑘0 𝑇
𝑘0 𝑇
𝐼* (𝑉𝑔𝑠) A 1 − exp
Δ𝐹$/ 𝑖
1 + exp
𝑘0 𝑇
[S. Pati Tripathi et al., ESSDERC 2021, JEDS 2022]
18nmx70nm p-MOSFET
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
94
QD Diamonds: Model vs. Measurements at 6.2 K
[S. Pati Tripathi et al., ESSDERC 2021]
Voinigescu
18nmx70nm p-MOSFET
Cryo mm-wave Characterization, Modelling, Design Methodologies
95
5nm n-FinFET QD Model vs. Meas. at 2 K
[S. Pati Tripathi MASc thesis 2022]
More difficult to model because two QD’s are connected in parallel
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
96
Model Extension With VBG Impact on Vt Only
Impact of BG on the shift in SHT transfer
characteristics preliminarily captured using:
ΔV2 =
t 34 V56
t 𝜖
t 734 − 89𝜖 :;
<=
-4 V
0.5 V
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
97
Impact of Gate-Oxide Spacer Width Variation
Captured by QuantumATK on scaled
device structure
a)
d)
c)
b)
[A. Bharadwaj, MASc thesis 2022]
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
98
QuantumATK Sims of Barrier Height vs. VBG
[V. Dhande, self-study course report 2023]
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
99
Measured ISD at Peak 1,2 vs. Temperature
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
100
QuantumATK Simulation of Scaled FDSOI MOSFET
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
101
Gyromagnetic Factor Measurements at DC (ii)
Probes not
lifted, July 2021
Voinigescu
Cryo mm-wave Characterization, Modelling, Design Methodologies
102