Lecture Notes
EECS 40
Introduction to Microelectronic Circuits
Prof. C. Chang-Hasnain
Spring 2007
EE 40 Course Overview
Important DATES
• EECS 40:
– One of five EECS core courses (with 20, 61A, 61B, and 61C)
• introduces “hardware” side of EECS
• prerequisite for EE105, EE130, EE141, EE150
– Prerequisites: Math 1B, Physics 7B
– Course involves three hours of lecture, one hour of discussion
and three hours of lab work each week.
• Course content:
–
–
–
–
–
Fundamental circuit concepts and analysis techniques
First and second order circuits, impulse and frequency response
Op Amps
Diode and FET: Device and Circuits
Amplification, Logic, Filter
• Text Book
– Electrical Engineering: Principles and Applications”, third edition,
Allan R. Hambley, Pearson Prentice Hall, 2005
– Supplementary Reader
EE40 Fall
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Slide 1
Prof. Chang-Hasnain
• Office hours, Discussion and Lab
Sessions will start on week 2
– Stay with ONE Discussion and Lab session
you registered.
• Midterm and Final Dates:
– Midterms: 6-7:40 pm on 2/21 and
4/11(Location TBD)
– Final: 8-11am on 5/14 (Location TBD)
• Best Final Project Contest
– 5/4 3-5pm Location TBD
– Winner projects will be displayed on second
floor Cory Hall.
EE40 Fall
2006
Grading Policy
Prof. Chang-Hasnain
Grading Policy (Cont’d)
• Weights:
• Weekly HW:
– 12%: 12 HW sets
– 15%: 11 Labs
• 7 structured experiments (7%)
• one 4-week final project (8%)
– 40%: 2 midterm exams
– 33%: Final exam
– Assignment on the web by 5 pm Wednesdays, starting 1/24/07.
– Due 5 pm the following Wednesday in HW box, 240 Cory.
– On the top page, right top corner, write your name (in the form:
Last Name, First Name) with discussion session number.
– Graded homework will be returned one week later in discussion
sessions.
• No late HW or Lab reports accepted
• No make-up exams unless Prof. Chang’s approval is
obtained at least 24 hours before exam time; proofs of
extraneous circumstances are required.
– If you miss one of the midterms, you lose 20 % of the grade.
• Departmental grading policy:
– A typical GPA for courses in the lower division is 2.7. This GPA
would result, for example, from 17% A's, 50% B's, 20% C's, 10%
D's, and 3% F's.
EE40 Fall
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Slide 3
Prof. Chang-Hasnain
• Labs
– Complete the prelab section before going to the lab, or your
points will be taken off.
– Lab reports are supposed to be turned in at the end of each lab,
except for the final project, which is due at the end of the last lab
session.
• It is your responsibility to check with the head GSI from
time to time to make sure all grades are entered
correctly.
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Prof. Chang-Hasnain
Classroom Rules
Chapter 1
• Please come to class on time. There is no
web-cast this semester.
• Turn off cell phones, pagers, radio, CD,
DVD, etc.
• No food.
• No pets.
• Do not come in and out of classroom.
• Lectures will be recorded and webcasted.
• Outline
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Prof. Chang-Hasnain
– Electrical quantities
• Charge, Current, Voltage, Power
– The ideal basic circuit element
– Sign conventions
– Circuit element I-V characteristics
– Construction of a circuit model
– Kirchhoff’s Current Law
– Kirchhoff’s Voltage Law
Electric Charge
– separation of charge
electric force (voltage)
– charges in motion
electric flow (current)
• Macroscopically, most matter is electrically
neutral most of the time.
– Exceptions: clouds in a thunderstorm, people on
carpets in dry weather, plates of a charged capacitor,
etc.
• Microscopically, matter is full of electric charges
– Electric charge exists in discrete quantities, integral
multiples of the electronic charge -1.6 x 10-19
Coulomb
Slide 7
Prof. Chang-Hasnain
Classification of Materials
• Electrical effects are due to
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Slide 6
Prof. Chang-Hasnain
• Solids in which the outermost atomic electrons
are free to move around are metals.
– Metals typically have ~1 “free electron” per atom
– Examples:
• Solids in which all electrons are tightly bound to
atoms are insulators.
– Examples:
• Electrons in semiconductors are not tightly
bound and can be easily “promoted” to a free
state.
– Examples:
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Prof. Chang-Hasnain
Electric Current
Definition: rate of positive charge flow
Symbol: i
Units: Coulombs per second Amperes (A)
Note: Current has polarity.
i = dq/dt
where
q = charge (Coulombs)
t = time (in seconds)
André-Marie Ampère's
1775-1836
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1.
Slide 9
Prof. Chang-Hasnain
Slide 10
Prof. Chang-Hasnain
Electric Current Examples
Current Density
105 positively charged particles (each with charge
1.6×10-19 C) flow to the right (+x direction) every
nanosecond
Definition: rate of positive charge flow per unit area
Symbol: J
Units: A / cm2
Q
105 ×1.6 ×10−19
= 1.6 ×10−5 A
I = =+
−9
t
10
Example 1:
2 cm
2.
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105 electrons flow to the right (+x direction) every
microsecond
Slide 11
C2
10 cm
X
Suppose we force a current of 1 A to flow from C1 to C2:
• Electron flow is in -x direction:
105 ×1.6 ×10−19
Q
I = =−
= −1.6 ×10−5 A
−9
t
10
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1 cm
C1
1C / sec
electrons
= −6.25 × 1018
−19
− 1.6 ×10 C / electron
sec
Prof. Chang-Hasnain
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Slide 12
Prof. Chang-Hasnain
Current Density Example (cont’d)
• Example 2:
Typical dimensions of integrated circuit
components are in the range of 1 µm. What is
the current density in a wire with 1 µm² area
carrying 5 mA?
Electric Potential (Voltage)
• Definition: energy per unit charge
• Symbol: v
• Units: Joules/Coulomb Volts (V)
v = dw/dq
Alessandro Volta
(1745–1827)
where w = energy (in Joules), q = charge (in Coulombs)
Note: Potential is always referenced to some point.
a
b
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Prof. Chang-Hasnain
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Electric Power
Prof. Chang-Hasnain
i
+
v
_
p = dw/dt = (dw/dq)(dq/dt) = vi
• Concept:
As a positive charge q moves through a James Watt
1736 - 1819
drop in voltage v, it loses energy
energy change = qv
rate is proportional to # charges/sec
Slide 15
Slide 14
The Ideal Basic Circuit Element
• Definition: transfer of energy per unit time
• Symbol: p
• Units: Joules per second Watts (W)
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Subscript convention:
vab means the potential at a
minus the potential at b.
vab va - vb
Prof. Chang-Hasnain
Polarity reference for voltage can be
indicated by plus and minus signs
• Reference direction for the current
is indicated by an arrow
Attributes:
• Two terminals (points of connection)
• Mathematically described in terms of current
and/or voltage
• Cannot be subdivided into other elements
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Prof. Chang-Hasnain
A Note about Reference Directions
• A problem like “Find the current” or “Find the
voltage” is always accompanied by a definition
of the direction:
-
i
v
Sign Convention Example
Suppose you have an unlabelled battery and you measure
its voltage with a digital voltmeter (DVM). It will tell you the
magnitude and sign of the voltage.
+
With this circuit, you are
measuring vab.
a
−1.401
• In this case, if the current turns out to be 1 mA
flowing to the left, we would say i = -1 mA.
• In order to perform circuit analysis to determine
the voltages and currents in an electric circuit,
you need to specify reference directions.
• There is no need to guess the reference
direction so that the answers come out positive.
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Prof. Chang-Hasnain
DVM
+
b
a
+
2V
−
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Prof. Chang-Hasnain
Passive sign convention
+
p = vi
vcd
−1 V
b
+
vbd
−
d
+
v
_
Note that the labeling convention has nothing to do with
whether or not v is positive or negative.
Slide 19
p = -vi
i
−
−
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Sign Convention for Power
c
+
Which is the positive battery
terminal?
Note that we have used the “ground” symbol ( ) for the reference
node on the DVM. Often it is labeled “C” for “common.”
Another Example
Find vab, vca, vcb
The DVM indicates −1.401, so
va is lower than vb by 1.401 V.
Prof. Chang-Hasnain
i
i
_
+
v
_
v
+
i
_
v
+
• If p > 0, power is being delivered to the box.
• If p < 0, power is being extracted from the box.
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Prof. Chang-Hasnain
Power
Power Calculation Example
If an element is absorbing power (i.e. if p > 0), positive
charge is flowing from higher potential to lower potential.
Find the power absorbed by each element:
Conservation of energy
total power delivered
equals
total power absorbed
p = vi if the “passive sign convention” is used:
i
i
_
+
v
_
or
Aside: For electronics these are unrealistically
large currents – milliamperes or smaller is more
typical
p (W)
vi (W)
918
- 810
- 12
- 400
- 224
1116
v
+
How can a circuit element absorb power?
By converting electrical energy into heat (resistors in toasters),
light (light bulbs), or acoustic energy (speakers); by storing
energy (charging a battery).
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Prof. Chang-Hasnain
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Circuit Elements
voltage source
current source
resistor
inductor
capacitor
Prof. Chang-Hasnain
Electrical Sources
• 5 ideal basic circuit elements:
–
–
–
–
–
Slide 22
active elements, capable of
generating electric energy
passive elements, incapable of
generating electric energy
• Many practical systems can be modeled with
just sources and resistors
• An electrical source is a device that is capable
of converting non-electric energy to electric
energy and vice versa.
Examples:
– battery: chemical
electric
– dynamo (generator/motor): mechanical
electric
(Ex. gasoline-powered generator, Bonneville dam)
Electrical sources can either deliver or absorb power
• The basic analytical techniques for solving
circuits with inductors and capacitors are
similar to those for resistive circuits
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Prof. Chang-Hasnain
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Prof. Chang-Hasnain
Ideal Voltage Source
Ideal Current Source
• Circuit element that maintains a prescribed
voltage across its terminals, regardless of the
current flowing in those terminals.
• Circuit element that maintains a prescribed
current through its terminals, regardless of the
voltage across those terminals.
– Voltage is known, but current is determined by the
circuit to which the source is connected.
– Current is known, but voltage is determined by the
circuit to which the source is connected.
• The voltage can be either independent or
dependent on a voltage or current elsewhere in
the circuit, and can be constant or time-varying.
• The current can be either independent or
dependent on a voltage or current elsewhere in
the circuit, and can be constant or time-varying.
Device symbols:
Device symbols:
vs +_
independent
vs=µ vx +_
vs=ρ ix +_
voltage-controlled
current-controlled
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Prof. Chang-Hasnain
is
independent
current-controlled
Slide 26
Prof. Chang-Hasnain
R
• Conductance is the reciprocal of resistance.
Symbol: G
Ω
Units: siemens (S) or mhos ( )
Example:
ohms (Ω
Ω)
Consider an 8 Ω resistor. What is its conductance?
• The current flowing in the resistor
is proportional to the voltage
across the resistor:
Georg Simon Ohm
1789-1854
v = i R (Ohm’s Law)
where v = voltage (V), i = current (A), and R = resistance (Ω)
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voltage-controlled
Electrical Conductance
• Resistance: the ratio of voltage drop and
current. The circuit element used to model this
behavior is the resistor.
Units: Volts per Ampere
is=β ix
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Electrical Resistance
Circuit symbol:
is=α vx
Slide 27
Prof. Chang-Hasnain
Werner von Siemens
1816-1892
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Prof. Chang-Hasnain
Short Circuit and Open Circuit
Example: Power Absorbed by a Resistor
• Short circuit
p = vi = ( iR )i = i2R
–R=0
no voltage difference exists
– all points on the wire are at the same
potential.
– Current can flow, as determined by the circuit
• Open circuit
–R=∞
no current flows
– Voltage difference can exist, as determined
by the circuit
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Prof. Chang-Hasnain
p = vi = v ( v/R ) = v2/R
Note that p > 0 always, for a resistor
a resistor
dissipates electric energy
Example:
a) Calculate the voltage vg and current ia.
b) Determine the power dissipated in the 80Ω resistor.
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More Examples
Slide 30
Prof. Chang-Hasnain
Summary
• Are these interconnections permissible?
This circuit connection is
permissible. This is because
the current sources can
sustain any voltage across;
Hence this is permissible.
• Current = rate of charge flow i = dq/dt
• Voltage = energy per unit charge created by
charge separation
• Power = energy per unit time
• Ideal Basic Circuit Elements
– two-terminal component that cannot be sub-divided
– described mathematically in terms of its terminal
voltage and current
– An ideal voltage source maintains a prescribed voltage
regardless of the current in the device.
– An ideal current source maintains a prescribed current
regardless of the voltage across the device.
– A resistor constrains its voltage and current to be
proportional to each other:
v = iR (Ohm’s law)
This circuit connection is
NOT permissible. It violates
the KCL.
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Prof. Chang-Hasnain
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Prof. Chang-Hasnain
Summary (cont’d)
Current vs. Voltage (I-V) Characteristic
• Passive sign convention
– For a passive device, the reference direction
for current through the element is in the
direction of the reference voltage drop across
the element
• Voltage sources, current sources, and
resistors can be described by plotting the
current (i) as a function of the voltage (v)
i
+
v
_
Passive? Active?
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Prof. Chang-Hasnain
I-V Characteristic of Ideal Voltage Source
a i
+
Vab +_ vs
_
i
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i=0
v
i
v
b
Vs>0
Vs<0
1. Plot the I-V characteristic for vs > 0. For what
values of i does the source absorb power? For
what values of i does the source release power?
2. Repeat
vs < 0.power; i>0 absorb power
Vs>0 (1)
i<0for
release
3. What is the I-V characteristic for an ideal wire?
Slide 35
Prof. Chang-Hasnain
I-V Characteristic of Ideal Voltage Source
a i
+
Vab +_ vs
_
b
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Slide 34
Prof. Chang-Hasnain
2. Plot the I-V characteristic for vs < 0. For what
values of i does the source absorb power? For
what values of i does the source release power?
Vs<0
i>0 release power; i<0 absorb power
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Prof. Chang-Hasnain
I-V Characteristic of Ideal Voltage Source
I-V Characteristic of Ideal Current Source
i
a i
+
Vab +_ vs
_
i
i
+
v
_
is
v
b
v
3. What is the I-V characteristic for an ideal wire?
1. Plot the I-V characteristic for is > 0. For what values
of v does the source absorb power? For what
values of v does the source release power?
Do not forget Vab=-Vba
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V>0 absorb power; V<0 release power
Slide 37
Prof. Chang-Hasnain
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Short Circuit and Open Circuit
• Current can flow, as determined by the circuit
R
v
b
1.
• Voltage difference can exist,
as determined by the circuit
Plot the I-V characteristic for R = 1 kΩ
Ω. What is the
slope?
a
+
Vab
_
b
Slide 39
i
i
a
+
v
_
(all points on the wire are at the same potential)
Air (“open circuit”):
• R=∞
no current flows
Prof. Chang-Hasnain
Prof. Chang-Hasnain
I-V Characteristic of Ideal Resistor
Wire (“short circuit”):
• R=0
no voltage difference exists
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Slide 38
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a
R
Vab
R
b
Slide 40
Prof. Chang-Hasnain
More Examples: Correction from last Lec.
• Are these interconnections permissible?
This circuit connection is
permissible. This is because
the current sources can
sustain any voltage across;
Hence this is permissible.
This circuit connection is
NOT permissible. It violates
the KCL.
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Construction of a Circuit Model
• The electrical behavior of each physical
component is of primary interest.
• We need to account for undesired as well
as desired electrical effects.
• Simplifying assumptions should be made
wherever reasonable.
Slide 41
Prof. Chang-Hasnain
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Terminology: Nodes and Branches
Node: A point where two or more circuit elements
are connected
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Prof. Chang-Hasnain
Circuit Nodes and Loops
• A node is a point where two or more circuit
elements are connected.
• A loop is formed by tracing a closed path in a
circuit through selected basic circuit elements
without passing through any intermediate node
more than once
Branch: A path that connects two nodes
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Prof. Chang-Hasnain
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Slide 44
Prof. Chang-Hasnain
Kirchhoff’s Laws
Notation: Node and Branch Voltages
• Kirchhoff’s Current Law (KCL):
– The algebraic sum of all the currents entering
any node in a circuit equals zero.
• Kirchhoff’s Voltage Law (KVL):
– The algebraic sum of all the voltages around
any loop in a circuit equals zero.
• Use one node as the reference (the “common”
or “ground” node) – label it with a symbol
• The voltage drop from node x to the reference
node is called the node voltage vx.
• The voltage across a circuit element is defined
as the difference between the node voltages at
its terminals
– v1 +
Example:
Slide 45
Prof. Chang-Hasnain
Using Kirchhoff’s Current Law (KCL)
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b
+
R2 vb
_
 REFERENCE NODE
Slide 46
Prof. Chang-Hasnain
Formulations of Kirchhoff’s Current Law
(Charge stored in node is zero.)
Consider a node connecting several branches:
Formulation 1:
Sum of currents entering node
= sum of currents leaving node
i2
i3
i1
Formulation 2:
Algebraic sum of currents entering node = 0
i4
• Currents leaving are included with a minus sign.
• Use reference directions to determine whether
currents are “entering” or “leaving” the node –
with no concern about actual current directions
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R1
+
va +_ vs
_
c
Gustav Robert Kirchhoff
1824-1887
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a
Slide 47
Prof. Chang-Hasnain
Formulation 3:
Algebraic sum of currents leaving node = 0
• Currents entering are included with a minus sign.
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Slide 48
Prof. Chang-Hasnain
A Major Implication of KCL
KCL Example
• KCL tells us that all of the elements in a single
branch carry the same current.
• We say these elements are connected in series.
Currents entering the node:
-10 mA
i
Currents leaving the node:
5 mA
15 mA
Current entering node = Current leaving node
i1 = i2
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Prof. Chang-Hasnain
3 formulations of KCL:
1.
2.
3.
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Generalization of KCL
Slide 50
Prof. Chang-Hasnain
Generalized KCL Examples
• The sum of currents entering/leaving a closed
surface is zero. Circuit branches can be inside
this surface, i.e. the surface can enclose more
than one node!
50 mA
5µA
i2
i3
This could be a big
chunk of a circuit,
e.g. a “black box”
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2µA
i
i
i4
i1
Slide 51
Prof. Chang-Hasnain
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Slide 52
Prof. Chang-Hasnain
Using Kirchhoff’s Voltage Law (KVL)
Consider a branch which forms part of a loop:
Formulation 2:
Algebraic sum of voltage drops around loop = 0
+
Moving from + to We add V1
Moving from - to +
We subtract V1
• Use reference polarities to determine whether a
voltage is dropped
• No concern about actual voltage polarities
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Slide 53
Prof. Chang-Hasnain
• Voltage rises are included with a minus sign.
!
"#
Formulation 3:
Algebraic sum of voltage rises around loop = 0
• Voltage drops are included with a minus sign.
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A Major Implication of KVL
Slide 54
Prof. Chang-Hasnain
KVL Example
• KVL tells us that any set of elements which are
connected at both ends carry the same voltage.
• We say these elements are connected in parallel.
Three closed paths:
a
+ v2 −
1
+
va
−
+
vb
_
+
va
_
!
b
+
vb
-
−
loop
–
v2
(Conservation of energy)
Formulation 1:
Sum of voltage drops around loop
= sum of voltage rises around loop
v3
2
+
loop
+
v1
_
Formulations of Kirchhoff’s Voltage Law
c
+
vc
−
3
Path 1:
Applying KVL in the clockwise direction,
starting at the top:
vb – va = 0
vb = va
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Slide 55
Path 2:
Path 3:
Prof. Chang-Hasnain
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Slide 56
Prof. Chang-Hasnain
An Underlying Assumption of KVL
I-V Characteristic of Elements
• No time-varying magnetic flux through the loop
a
+
Vab
_
Otherwise, there would be an induced voltage (Faraday’s Law)
• Note: Antennas are designed to “pick up”
electromagnetic waves; “regular circuits”
often do so undesirably.
B( t )
Avoid these loops!
+
Find the I-V characteristic.
i
R
i
+
_ vs
b
v( t )
v
−
How do we deal with antennas (EECS 117A)?
Include a voltage source as the circuit representation
of the induced voltage or “noise”.
(Use a lumped model rather than a distributed (wave) model.)
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Slide 57
Prof. Chang-Hasnain
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Summary
– Lumped model
• The Current versus voltage characteristics (I-V plot) is
a universal means of describing a circuit element.
• Kirchhoff’s current law (KCL) states that the algebraic
sum of all currents at any node in a circuit equals zero.
– Comes from conservation of charge
• Kirchhoff’s voltage law (KVL) states that the algebraic
sum of all voltages around any closed path in a circuit
equals zero.
– Comes from conservation of potential energy
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Prof. Chang-Hasnain
Chapter 2
• An electrical system can be modeled by an electric circuit
(combination of paths, each containing 1 or more circuit
elements)
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Slide 58
Prof. Chang-Hasnain
• Outline
– Resistors in Series – Voltage Divider
– Conductances in Parallel – Current Divider
– Node-Voltage Analysis
– Mesh-Current Analysis
– Superposition
– Thévenin equivalent circuits
– Norton equivalent circuits
– Maximum Power Transfer
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Slide 60
Prof. Chang-Hasnain
Resistors in Series
Voltage Divider
Consider a circuit with multiple resistors connected in series.
Find their “equivalent resistance”.
R1
VSS
R2
+
−
R1
• KCL tells us that the same
current (I) flows through
every resistor
I
I
VSS
+
−
+
– V1
I = VSS / (R1 + R2 + R3 + R4)
R2
R3
• KVL tells us
+
– V3
R4
R3
R4
Equivalent resistance of resistors in series is the sum
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Slide 61
Prof. Chang-Hasnain
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I
R1
+
−
VSS
R2
R1
+
– V2
VSS
R3
+
−
R4
R2
+
– V2
R3
R4
R5
Prof. Chang-Hasnain
Resistors in Parallel
When can the Voltage Divider Formula be Used?
I
Slide 62
ISS
Consider a circuit with two resistors connected in parallel.
Find their “equivalent resistance”.
x
• KVL tells us that the
same voltage is dropped
I1
I2
across each resistor
R1
R2
Vx = I1 R1 = I2 R2
• KCL tells us
V =
2
R
2
⋅V
SS
R +R +R +R
1 2 3 4
Correct, if nothing else
is connected to nodes
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V
2
R
2
⋅V
SS
R +R +R +R
1 2 3 4
Why? What is V2?
Slide 63
Prof. Chang-Hasnain
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Slide 64
Prof. Chang-Hasnain
General Formula for Parallel Resistors
Current Divider
x
What single resistance Req is equivalent to three resistors in parallel?
I
I
+
+
V
R1
R2
eq
R3
≡
−
V
Req
ISS
I1
I2
R1
R2
Vx = I1 R1 = ISS Req
−
Equivalent conductance of resistors in parallel is the sum
EE40 Fall
2006
Slide 65
Prof. Chang-Hasnain
EE40 Fall
2006
Generalized Current Divider Formula
Consider a current divider circuit with >2 resistors in parallel:
+
R1
V
I3
I2
I1
I
R2
R3
−
I3 =
V=
I
1
1
1
+
+
R1
R2
R3
Slide 66
Prof. Chang-Hasnain
Measuring Voltage
To measure the voltage drop across an element in a
real circuit, insert a voltmeter (digital multimeter in
voltage mode) in parallel with the element.
Voltmeters are characterized by their “voltmeter input
resistance” (Rin). Ideally, this should be very high
(typical value 10 MΩ)
1/R 3
V
=I
R3
1/R 1 + 1/R 2 + 1/R 3
Ideal
Voltmeter
Rin
EE40 Fall
2006
Slide 67
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 68
Prof. Chang-Hasnain
Effect of Voltmeter
circuit with voltmeter inserted
undisturbed circuit
R1
R1
+
_
VSS +
Measuring Current
R2
+
+
VSS _
V2
R2
V2
Rin
–
–
To measure the current flowing through an element in a
real circuit, insert an ammeter (digital multimeter in
current mode) in series with the element.
Ammeters are characterized by their “ammeter input
resistance” (Rin). Ideally, this should be very low
(typical value 1Ω).
Ideal
Ammeter
Compare to R2
R2
R1 + R 2
V2 = VSS
V2′ = VSS
R 2 || Rin
R 2 || Rin + R1
Rin
Example: VSS = 10 V , R 2 = 100 K , R1 = 900 K
V2 = 1V
Rin = 10 M , V2′ = ?
EE40 Fall
2006
Slide 69
Prof. Chang-Hasnain
EE40 Fall
2006
Effect of Ammeter
circuit with ammeter inserted
Imeas
I
V1
Simplify a circuit before applying KCL and/or KVL:
Example: Find I
I
ammeter
R1
R1
R1
Rin
V1 +
_
+
_
R2
R2
7V
+
−
R2
V1
R1 + R 2
Imeas =
Slide 71
R1 = R2 = 3 kΩ
R3 = 6 kΩ
R6
R4 = R5 = 5 kΩ
R6 = 10 kΩ
V1
R1 + R 2 + Rin
Example: V1 = 1 V, R1= R2 = 500 Ω, Rin = 1Ω
1V
I=
= 1mA, I meas = ?
500Ω + 500Ω
EE40 Fall
2006
R3
R4
R5
I=
Prof. Chang-Hasnain
Using Equivalent Resistances
Measurement error due to non-zero input resistance:
undisturbed circuit
Slide 70
Compare to
R2 + R2
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 72
Prof. Chang-Hasnain
Node-Voltage Circuit Analysis Method
Nodal Analysis: Example #1
R
3
R1
1. Choose a reference node (“ground”)
Look for the one with the most connections!
+
-
2. Define unknown node voltages
V1
R2
IS
R4
those which are not fixed by voltage sources
3. Write KCL at each unknown node, expressing
current in terms of the node voltages (using the
I-V relationships of branch elements)
Special cases: floating voltage sources
1. Choose a reference node.
2. Define the node voltages (except reference node and
the one set by the voltage source).
3. Apply KCL at the nodes with unknown voltage.
4. Solve the set of independent equations
N equations for N unknown node voltages
EE40 Fall
2006
Slide 73
4. Solve for unknown node voltages.
Prof. Chang-Hasnain
Nodal Analysis: Example #2
V
R3
1
R2
I1
R4
Slide 74
Prof. Chang-Hasnain
Nodal Analysis w/ “Floating Voltage Source”
A “floating” voltage source is one for which neither side is
connected to the reference node, e.g. VLL in the circuit below:
R1
Va
EE40 Fall
2006
R5
VLL
Va
Vb
- +
V2
I1
Challenges:
Determine number of nodes needed
Deal with different types of sources
R2
R4
I2
Problem: We cannot write KCL at nodes a or b because
there is no way to express the current through the voltage
source in terms of Va-Vb.
Solution: Define a “supernode” – that chunk of the circuit
containing nodes a and b. Express KCL for this supernode.
Incorporate voltage source constraint into KCL equation.
EE40 Fall
2006
Slide 75
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 76
Prof. Chang-Hasnain
Nodal Analysis: Example #3
Formal Circuit Analysis Methods
supernode
VLL
Va
-
MESH ANALYSIS
(“Mesh-Current Method”)
NODAL ANALYSIS
(“Node-Voltage Method”)
Vb
0) Choose a reference node
+
1) Define unknown node voltages
I1
R2
I2
R4
Eq’n 1: KCL at supernode
2) Apply KCL to each unknown
node, expressing current in
terms of the node voltages
=> N equations for
N unknown node voltages
3) Solve for node voltages
=> determine branch currents
1) Select M independent mesh
currents such that at least one
mesh current passes through each
branch*
M = #branches - #nodes + 1
2) Apply KVL to each mesh,
expressing voltages in terms of
mesh currents
=> M equations for
M unknown mesh currents
3) Solve for mesh currents
=> determine node voltages
Substitute property of voltage source:
EE40 Fall
2006
Slide 77
*Simple method for planar circuits
A mesh current is not necessarily identified with a branch current.
Prof. Chang-Hasnain
Mesh Analysis: Example #1
EE40 Fall
2006
Slide 78
Prof. Chang-Hasnain
Mesh Analysis with a Current Source
ia
ib
1. Select M mesh currents.
Problem: We cannot write KVL for meshes a and b
because there is no way to express the voltage drop
across the current source in terms of the mesh currents.
2. Apply KVL to each mesh.
Solution: Define a “supermesh” – a mesh which avoids the
branch containing the current source. Apply KVL for this
supermesh.
3. Solve for mesh currents.
EE40 Fall
2006
Slide 79
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 80
Prof. Chang-Hasnain
Mesh Analysis: Example #2
ia
Mesh Analysis with Dependent Sources
• Exactly analogous to Node Analysis
• Dependent Voltage Source: (1) Formulate
and write KVL mesh eqns. (2) Include and
express dependency constraint in terms of
mesh currents
• Dependent Current Source: (1) Use
supermesh. (2) Include and express
dependency constraint in terms of mesh
currents
ib
Eq’n 1: KVL for supermesh
Eq’n 2: Constraint due to current source:
EE40 Fall
2006
Slide 81
Prof. Chang-Hasnain
EE40 Fall
2006
Circuit w/ Dependent Source Example
Slide 82
Prof. Chang-Hasnain
Superposition
A linear circuit is one constructed only of linear
elements (linear resistors, and linear capacitors and
inductors, linear dependent sources) and
independent sources. Linear
means I-V charcteristic of elements/sources are
straight lines when plotted
Find i2, i1 and io
Principle of Superposition:
•
EE40 Fall
2006
Slide 83
Prof. Chang-Hasnain
In any linear circuit containing multiple
independent sources, the current or voltage at
any point in the network may be calculated as
the algebraic sum of the individual contributions
of each source acting alone.
EE40 Fall
2006
Slide 84
Prof. Chang-Hasnain
Superposition
Source Combinations
• Voltage sources in series can be replaced by an
equivalent voltage source:
Procedure:
1. Determine contribution due to one independent source
•
–
+
–
+
v2
v1+v2
–
+
v1
Set all other sources to 0: Replace independent voltage
source by short circuit, independent current source by open
circuit
2. Repeat for each independent source
3. Sum individual contributions to obtain desired voltage
or current
• Current sources in parallel can be replaced by
an equivalent current source:
i1+i2
i2
EE40 Fall
2006
Slide 85
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 86
Prof. Chang-Hasnain
Superposition Example
Open Circuit and Short Circuit
• Open circuit
i=0 ; Cut off the branch
• Short circuit
v=0 ; replace the element by wire
• Turn off an independent voltage source means
• Find Vo
24 V
– V=0
– Replace by wire
– Short circuit
4V
+–
2Ω
–
+
i1
+
4 Ω Vo
4A
–
• Turn off an independent current source means
– i=0
– Cut off the branch
– open circuit
EE40 Fall
2006
Slide 87
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 88
Prof. Chang-Hasnain
Equivalent Circuit Concept
Thévenin Equivalent Circuit
• A network of voltage sources, current sources,
and resistors can be replaced by an
equivalent circuit which has identical terminal
properties (I-V characteristics) without
affecting the operation of the rest of the circuit.
• Any* linear 2-terminal (1-port) network of indep. voltage
sources, indep. current sources, and linear resistors can
be replaced by an equivalent circuit consisting of an
independent voltage source in series with a resistor
without affecting the operation of the rest of the circuit.
iB
network B
of
sources
and
resistors
+
vA
_
$ %&
' &
RTh
a
+
vB
_
network
of
sources
and
resistors
iA(vA) = iB(vB)
+
iL
vL
RL
VTh
a
–
+
iA
network A
of
sources
and
resistors
–
+
iL
vL
RL
–
b
b
“load” resistor
EE40 Fall
2006
Slide 89
Prof. Chang-Hasnain
EE40 Fall
2006
I-V Characteristic of Thévenin Equivalent
• The I-V characteristic for the series combination of
elements is obtained by adding their voltage drops:
For a given current i, the voltage drop
vab is equal to the sum of the voltages
dropped across the source (VTh)
and across the resistor (iRTh)
RTh
Prof. Chang-Hasnain
Thévenin Equivalent Example
Find the Thevenin equivalent with respect to the terminals a,b:
i
vab = VTh- iR
a
v
i +
–
+
VTh
Slide 90
vab
–
I-V characteristic
of resistor: v = iR
b
I-V characteristic of voltage source: v = VTh
EE40 Fall
2006
Slide 91
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 92
Prof. Chang-Hasnain
RTh Calculation Example #1
Norton Equivalent Circuit
• Any* linear 2-terminal (1-port) network of indep. voltage
sources, indep. current sources, and linear resistors can
be replaced by an equivalent circuit consisting of an
independent current source in parallel with a resistor
without affecting the operation of the rest of the circuit.
(
a
Set all independent sources to 0:
network
of
sources
and
resistors
+
iL
vL
RL
' &
iN
a
RN
–
Slide 93
Prof. Chang-Hasnain
EE40 Fall
2006
For a given voltage vab, the current i is
equal to the sum of the currents in
each of the two branches:
a i
+
iN
RN
–
b
EE40 Fall
2006
RL
b
Slide 94
Prof. Chang-Hasnain
Analogous to calculation of Thevenin Eq. Ckt:
1) Find o.c voltage and s.c. current
i
I-V
characteristic
of current
source: i = -IN
i = IN-Gv
v
vab
vL
Finding IN and RN = RTh
I-V Characteristic of Norton Equivalent
• The I-V characteristic for the parallel combination of
elements is obtained by adding their currents:
iL
–
b
EE40 Fall
2006
+
IN
isc = VTh/RTh
2) Or, find s.c. current and Norton (Thev) resistance
I-V characteristic
of resistor: i=Gv
Slide 95
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 96
Prof. Chang-Hasnain
Finding IN and RN
Maximum Power Transfer Theorem
RTh
a
–
+
vTh
iL
vL
RL
iN
RN
–
+
iL
vL
RL
–
' &
Power absorbed by load resistor:
RTh
VTh
a
+
$ %&
–
+
• We can derive the Norton equivalent circuit from
a Thévenin equivalent circuit simply by making a
source transformation:
+
iL
vL
RL
VTh
p = i RL =
RTh + RL
2
L
b
RN = RTh =
v
voc
; iN = Th = isc
RTh
isc
To find the value of RL for which p is maximum, set
(RTh + RL ) − RL × 2(RTh + RL ) = 0
dp
= VTh2
dRL
(RTh + RL )4
Slide 97
dp
to 0:
dRL
(RTh + RL )2 − RL × 2(RTh + RL ) = 0
)
RTh = RL
EE40 Fall
2006
RL
–
2
b
2
Prof. Chang-Hasnain
&
&
'
EE40 Fall
2006
*
$ %&
Slide 98
"
Prof. Chang-Hasnain
The Wheatstone Bridge
Finding the value of Rx
• Circuit used to precisely measure resistances in
the range from 1 Ω to 1 MΩ, with ±0.1% accuracy
• Adjust R3 until there is no current in the detector
Then, Rx =
R1 and R2 are resistors with known values
R3 is a variable resistor (typically 1 to 11,000Ω)
Rx is the resistor whose value is to be measured
battery
R1
+
V
–
R1
R2
current detector
R3
+
V
–
Rx
R1
R3
Derivation:
R2
i1 i2
i3
R3
R2
ix
Rx
variable resistor
Typically, R2 / R1 can be varied
from 0.001 to 1000 in decimal steps
EE40 Fall
2006
Slide 99
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 100
Prof. Chang-Hasnain
Finding the value of Rx
Identifying Series and Parallel Combinations
• Adjust R3 until there is no current in the detector
Then, Rx =
R2
R1
Some circuits must be analyzed (not amenable to simple inspection)
R1
V
Derivation:
+
+
V
–
i3
R3
R4
Special cases:
R3 = 0 OR R3 = ∞
R5
Rx
R3
Typically, R2 / R1 can be varied
from 0.001 to 1000 in decimal steps
EE40 Fall
2006
R1
Rx
=
R2
Slide 101
Prof. Chang-Hasnain
EE40 Fall
2006
Y-Delta Conversion
a
b
Rb
R1
RbRc
Ra + Rb + Rc
b
a
R3
RaRc
Ra + Rb + Rc
Rab =
Rb
R3 =
c
b
Rbc =
R2
RaRb
R3
Ra + Rb + Rc
Brain Teaser Category: Important for motors and electrical utilities.
Slide 103
Ra
R1
c
R2 =
Rc
a
R2
Ra
c
Prof. Chang-Hasnain
• In order for the Delta interconnection to be equivalent
to the Wye interconnection, the resistance between
corresponding terminal pairs must be the same
b
Rc
a
Slide 102
Delta-to-Wye (Pi-to-Tee) Equivalent Circuits
• These two resistive circuits are equivalent for
voltages and currents external to the Y and ∆
circuits. Internally, the voltages and currents
are different.
EE40 Fall
2006
R2
+
-
i1R3 = i2Rx
ix
R3
R1 =
V
R5
R4
KVL => i3R3 = ixRx and i1R1 = i2R2
R2
i1 i2
I
R3
−
KCL => i1 = i3 and i2 = ix
R1
R2
R1
R3
Prof. Chang-Hasnain
Rca =
Rc (Ra + Rb)
Ra + Rb + Rc
Ra (Rb + Rc)
Ra + Rb + Rc
Rb (Ra + Rc)
Ra + Rb + Rc
= R1 + R2
= R2 + R3
= R1 + R3
c
EE40 Fall
2006
Slide 104
Prof. Chang-Hasnain
Circuit Simplification Example
∆-Y and Y-∆
∆ Conversion Formulas
Delta-to-Wye conversion
Wye-to-Delta conversion
Find the equivalent resistance Rab:
2Ω
Ω
2Ω
Ω
a
R1 =
R2 =
Rc
RbRc
a
Ra + Rb + Rc
b
Rb
RaRc
c
Rb =
Ra + Rb + Rc
RaRb
R1R2 + R2R3 + R3R1
18Ω
Ω
R1R2 + R2R3 + R3R1
R2
Ra + Rb + Rc
Rc =
12Ω
Ω
9Ω
Ω
4Ω
Ω
b
R2
b
b
R1
6Ω
Ω
R1
Ra
a
R3 =
Ra =
a
R1R2 + R2R3 + R3R1
9Ω
Ω
4Ω
Ω
R3
R3
c
EE40 Fall
2006
Slide 105
Prof. Chang-Hasnain
EE40 Fall
2006
• Node-Voltage Method
– Dependent current source:
• treat as independent current source in organizing node eqns
• substitute constraining dependency in terms of defined node voltages.
– Dependent voltage source:
• treat as independent voltage source in organizing node eqns
• Substitute constraining dependency in terms of defined node voltages.
• Mesh Analysis
– Dependent Voltage Source:
• Formulate and write KVL mesh eqns.
• Include and express dependency constraint in terms of mesh currents
– Dependent Current Source:
• Use supermesh.
• Include and express dependency constraint in terms of mesh currents
A dependent source establishes a voltage or current
whose value depends on the value of a voltage or
current at a specified location in the circuit.
(device model, used to model behavior of transistors & amplifiers)
To specify a dependent source, we must identify:
1.
2.
3.
Prof. Chang-Hasnain
the controlling voltage or current
the relationship between the controlling voltage or current
and the supplied voltage or current
the reference direction for the supplied voltage or current
The relationship between the dependent source
and its reference cannot be broken!
–
Slide 107
Prof. Chang-Hasnain
Comments on Dependent Sources
Dependent Sources
EE40 Fall
2006
Slide 106
EE40 Fall
2006
Dependent sources cannot be turned off for various
purposes (e.g. to find the Thévenin resistance, or in
analysis using Superposition).
Slide 108
Prof. Chang-Hasnain
RTh Calculation Example #2
Node-Voltage Method and Dependent Sources
• If a circuit contains dependent sources, what to do?
Find the Thevenin equivalent with respect to the terminals a,b:
Example:
Ix
i∆
+
Vx
-
20 Ω
10 Ω
EE40 Fall
2006
20 Ω
–
+ 5i∆
Slide 109
–
+
2.4 A
80 V
Since there is no independent source and we cannot
arbitrarily turn off the dependence source, we can add a
voltage source Vx across terminals a-b and measure the
current through this terminal Ix . Rth= Vx/ Ix
Prof. Chang-Hasnain
Circuit w/ Dependent Source Example
EE40 Fall
2006
Slide 110
Prof. Chang-Hasnain
Summary of Techniques for Circuit Analysis -1
(Chap 2)
• Resistor network
Find i2, i1 and io
– Parallel resistors
– Series resistors
– Y-delta conversion
– “Add” current source and find voltage (or vice
versa)
• Superposition
– Leave one independent source on at a time
– Sum over all responses
– Voltage off
SC
– Current off
OC
EE40 Fall
2006
Slide 111
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 112
Prof. Chang-Hasnain
Summary of Techniques for Circuit Analysis -2
(Chap 2)
• Node Analysis
Chapter 3
• Outline
– Node voltage is the unknown
– Solve for KCL
– Floating voltage source using super node
– The capacitor
– The inductor
• Mesh Analysis
– Loop current is the unknown
– Solve for KVL
– Current source using super mesh
• Thevenin and Norton Equivalent Circuits
– Solve for OC voltage
– Solve for SC current
EE40 Fall
2006
Slide 113
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 114
Prof. Chang-Hasnain
Capacitor
The Capacitor
Two conductors (a,b) separated by an insulator:
Symbol:
difference in potential = Vab
=> equal & opposite charge Q on conductors
+
or
C
C
(typical range of values: 1 pF to 1 µF; for “supercapacitors” up to a few F!)
where C is the capacitance of the structure,
Current-Voltage relationship:
positive (+) charge is on the conductor at higher potential
dQ
dv
dC
ic =
= C c + vc
dt
dt
dt
Parallel-plate capacitor:
(m2)
• area of the plates = A
• separation between plates = d (m)
• dielectric permittivity of insulator = ε
(F/m)
=> capacitance
EE40 Fall
2006
Aε
d
If C (geometry) is unchanging, iC = C dvC/dt
ic
+
vc
–
Note: Q (vc) must be a continuous function of time
(FF)
Slide 115
Electrolytic (polarized)
capacitor
Units: Farads (Coulombs/Volt)
Q = CVab
C=
C
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 116
Prof. Chang-Hasnain
Voltage in Terms of Current
Stored Energy
CAPACITORS STORE ELECTRIC ENERGY
t
You might think the energy stored on a capacitor is QV =
CV2, which has the dimension of Joules. But during
charging, the average voltage across the capacitor was
only half the final value of V for a linear capacitor.
Q(t ) = ic (t )dt + Q(0)
0
t
t
Q(0) 1
1
ic (t )dt + vc (0)
vc (t ) =
ic (t )dt +
=
C
C0
C0
Thus, energy is 1 QV =
Uses: Capacitors are used to store energy for camera flashbulbs,
in filters that separate various frequency signals, and
they appear as undesired “parasitic” elements in circuits where
they usually degrade circuit performance
EE40 Fall
2006
Slide 117
1
CV 2
2
2
Prof. Chang-Hasnain
A more rigorous derivation
.
Example: A 1 pF capacitance charged to 5 Volts
has ½(5V)2 (1pF) = 12.5 pJ
(A 5F supercapacitor charged to 5
volts stores 63 J; if it discharged at a
constant rate in 1 ms energy is
discharged at a 63 kW rate!)
EE40 Fall
2006
Slide 118
Prof. Chang-Hasnain
Example: Current, Power & Energy for a Capacitor
t
+
vc
–
This derivation holds
independent of the circuit!
v (V)
1
0
t = t Final
v = VFinal
v = VFinal dQ
dt =
v c dQ
w=
v c ⋅ ic dt =
vc
dt
t = t Initial
v = VInitial
v = VInitial
i (µA)
v = VFinal
1
1
w=
Cv c dv c = CVFinal2 − CVInitial2
2
2
v = VInitial
0
EE40 Fall
2006
Slide 119
1
v(t ) =
i (τ )dτ + v(0)
C0
1
2
3
4
5
2
3
4
v(t)
10 µF
t (µs)
vc and q must be continuous
functions of time; however,
ic can be discontinuous.
dv
i =C
dt
1
i(t)
–
+
ic
5
t (µs)
Note: In “steady state”
(dc operation), time
derivatives are zero
C is an open circuit
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 120
Prof. Chang-Hasnain
Capacitors in Series
p (W)
–
+
v(t)
0
+ v1(t) – + v2(t) –
i(t)
1
2
3
4
10 µF
i(t)
t (µs)
5
+
C2
C1
i(t)
Ceq
v(t)=v1(t)+v2(t)
–
p = vi
w (J)
0
t
1
w = pdτ = Cv 2
2
0
1
2
3
4
EE40 Fall
2006
1
1
1
= +
Ceq C1 C2
t (µs)
5
Slide 121
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 122
Capacitive Voltage Divider
Inductor
Q: Suppose the voltage applied across a series combination
of capacitors is changed by ∆v. How will this affect the
voltage across each individual capacitor?
∆Q1=C1∆v1
Q1+∆
∆Q1
C1
v+∆
∆v
+
–
-Q1−∆Q1
Q2+∆
∆Q2
C2
−Q2−∆Q2
∆Q2=C2∆v2 (
EE40 Fall
2006
∆v = ∆v1 + ∆v2
+
v1+∆
∆v1
–
Note that no net charge can
can be introduced to this node.
Therefore, −∆Q1+∆Q2=0
+
v2(t)+∆
∆v2
–
+
! "
C1∆v1 = C2 ∆v2
∆v2 =
C1
∆v
C1 + C2
&
Slide 123
Prof. Chang-Hasnain
Symbol:
L
Units: Henrys (Volts • second / Ampere)
(typical range of values: µH to 10 H)
Current in terms of voltage:
1
vL (t )dt
L
t
1
iL (t ) =
vL (τ )dτ + i (t0 )
L t0
diL =
iL
+
vL
–
Note: iL must be a continuous function of time
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 124
Prof. Chang-Hasnain
Stored Energy
Inductors in Series and Parallel
INDUCTORS STORE MAGNETIC ENERGY
Consider an inductor having an initial current i(t0) = i0
Common
Current
p(t ) = v(t )i(t ) =
t
w(t ) = p(τ )dτ =
t0
Common
Voltage
1
1 2
w(t ) = Li 2 − Li0
2
2
EE40 Fall
2006
Slide 125
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 126
Summary
Capacitor
v cannot change instantaneously
i can change instantaneously
Do not short-circuit a charged
capacitor (-> infinite current!)
1
=
n cap.’s in series:
Ceq
n
i =1
1
Ci
n
n cap.’s in parallel: Ceq =
Ci
i =1
Chapter 4
Inductor
di
1
v = L ; w = Li 2
dt
2
dv
1
i = C ; w = Cv 2
dt
2
• OUTLINE
– First Order Circuits
i cannot change instantaneously
v can change instantaneously
Do not open-circuit an inductor with
current (-> infinite voltage!)
n
n ind.’s in series:
Leq =
Li
• RC and RL Examples
• General Procedure
– RC and RL Circuits with General Sources
• Particular and complementary solutions
• Time constant
– Second Order Circuits
• The differential equation
• Particular and complementary solutions
• The natural frequency and the damping ratio
i =1
1
=
n ind.’s in parallel: L
eq
n
i =1
1
Li
In steady state (not time-varying), In steady state, an inductor
a capacitor behaves like an open behaves like a short circuit.
circuit.
EE40 Fall
2006
Slide 127
Prof. Chang-Hasnain
Prof. Chang-Hasnain
• Reading
– Chapter 4
EE40 Fall
2006
Slide 128
Prof. Chang-Hasnain
First-Order Circuits
Response of a Circuit
• A circuit that contains only sources, resistors
and an inductor is called an RL circuit.
• A circuit that contains only sources, resistors
and a capacitor is called an RC circuit.
• RL and RC circuits are called first-order circuits
because their voltages and currents are
described by first-order differential equations.
R
– Behavior when voltage or current source are suddenly
applied to or removed from the circuit due to switching.
– Temporary behavior
• Steady-state response (aka. forced response)
– Response that persists long after transient has decayed
• Natural response of an RL or RC circuit is
R
i
vs
L
–
+
EE40 Fall
2006
Slide 129
– Behavior (i.e., current and voltage) when stored energy
in the inductor or capacitor is released to the resistive
part of the network (containing no independent
sources).
i
–
+
vs
• Transient response of an RL or RC circuit is
C
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 130
Natural Response Summary
RL Circuit
L
First Order Circuits
RC Circuit
i
+
+
C
R
v R
+
EE40 Fall
2006
•
•
Slide 131
vr(t)
-
R
C
vs(t)
-
–
• Inductor current
cannot change
instantaneously
• In steady state, an
inductor behaves like
a short circuit.
Prof. Chang-Hasnain
iL(t)
ic(t)
+
+
vc(t)
-
is(t)
R
L
vL(t)
-
Capacitor voltage
cannot change
instantaneously
In steady state, a
capacitor behaves like
an open circuit
Prof. Chang-Hasnain
KCL at the node:
KVL around the loop:
vr(t) + vc(t) = vs(t)
RC
t
v(t ) 1
+
v( x)dx = is (t )
R
L −∞
dvc (t )
+ vc (t ) = vs (t )
dt
EE40 Fall
2006
L diL (t )
+ iL (t ) = is (t )
R dt
Slide 132
Prof. Chang-Hasnain
Procedure for Finding Transient Response
1. Identify the variable of interest
•
•
For RL circuits, it is usually the inductor current iL(t)
For RC circuits, it is usually the capacitor voltage vc(t)
Procedure (cont’d)
3. Calculate the final value of the variable
(its value as t
)
•
2. Determine the initial value (at t = t0- and t0+) of
the variable
•
Recall that iL(t) and vc(t) are continuous variables:
iL(t0+) = iL(t0−) and vc(t0+) = vc(t0−)
•
4. Calculate the time constant for the circuit
τ = L/R for an RL circuit, where R is the Thévenin
equivalent resistance “seen” by the inductor
τ = RC for an RC circuit where R is the Thévenin
equivalent resistance “seen” by the capacitor
Assuming that the circuit reached steady state before
t0 , use the fact that an inductor behaves like a short
circuit in steady state or that a capacitor behaves like
an open circuit in steady state
EE40 Fall
2006
Slide 133
Prof. Chang-Hasnain
Again, make use of the fact that an inductor
behaves like a short circuit in steady state (t
)
or that a capacitor behaves like an open circuit in
steady state (t
)
EE40 Fall
2006
Slide 134
Natural Response of an RC Circuit
• Consider the following circuit, for which the switch is
closed for t < 0, and then opened at t = 0:
Vo +
−
Ro
C
t=0
+
v
–
Prof. Chang-Hasnain
Solving for the Voltage (t ≥ 0)
• For t > 0, the circuit reduces to
i
Vo +
−
+
Ro
C
v
R
–
R
• Applying KCL to the RC circuit:
Notation:
0– is used to denote the time just prior to switching
0+ is used to denote the time immediately after switching
• The voltage on the capacitor at t = 0– is Vo
EE40 Fall
2006
Slide 135
• Solution:
Prof. Chang-Hasnain
EE40 Fall
2006
v(t ) = v(0)e−t / RC
Slide 136
Prof. Chang-Hasnain
Solving for the Current (t > 0)
Solving for Power and Energy Delivered (t > 0)
i
+
Ro
Vo +
−
i
C
Vo +
−
v(t ) = Voe−t / RC
R
v
+
Ro
C
–
v(t ) = Vo e − t / RC
R
–
v 2 Vo2 −2 t / RC
=
p=
e
R
R
t
t
Vo2 −2 x / RC
w = p( x )dx =
e
dx
R
0
0
• Note that the current changes abruptly:
i (0− ) = 0
v Vo −t / RC
= e
R R
V
i (0+ ) = o
R
for t > 0, i (t ) =
EE40 Fall
2006
v
1
= CVo2 (1 − e −2 t / RC )
2
Slide 137
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 138
Natural Response of an RL Circuit
• Consider the following circuit, for which the switch is
closed for t < 0, and then opened at t = 0:
Prof. Chang-Hasnain
Solving for the Current (t ≥ 0)
• For t > 0, the circuit reduces to
i
t=0
Io
Ro
i
L
R
0– is used to denote the time just prior to switching
0+ is used to denote the time immediately after switching
• t<0 the entire system is at steady-state; and the inductor
is
like short circuit
• The current flowing in the inductor at t = 0– is Io and V
across is 0.
EE40 Fall
2006
Slide 139
Ro
L
R
Prof. Chang-Hasnain
v
–
v
–
Notation:
Io
+
+
•
•
•
•
Applying KVL to the LR circuit:
v(t)=i(t)R
At t=0+, i=I0,
di (t )
At arbitrary t>0, i=i(t) and v(t ) = -L
• Solution:
EE40 Fall
2006
dt
i (t ) = i (0)e − ( R / L ) t = I0e-(R/L)t
Slide 140
Prof. Chang-Hasnain
Solving for the Voltage (t > 0)
Solving for Power and Energy Delivered (t > 0)
i(t ) = I oe
i (t ) = I o e − ( R / L )t
−( R / L )t
+
+
Io
L
Ro
Io
v
R
Ro
L
v
R
–
–
p = i 2 R = I o2 Re −2 ( R / L ) t
• Note that the voltage changes abruptly:
t
−
v (0 ) = 0
w = p ( x)dx = I o2 Re − 2 ( R / L ) x dx
−( R / L ) t
0
=
v(0 ) = I0R
EE40 Fall
2006
Slide 141
Prof. Chang-Hasnain
1 2
LI o 1 − e − 2 ( R / L )t
2
EE40 Fall
2006
Natural Response Summary
RC Circuit
RL Circuit
i
C
•
Capacitor voltage cannot
change instantaneously
i ( 0 − ) = i (0 + )
v (0 − ) = v (0 + )
i (t ) = i (0)e −t /τ
v(t ) = v(0)e −t /τ
• time constant
EE40 Fall
2006
τ=
L
R
•
Slide 143
Slide 142
Prof. Chang-Hasnain
Digital Signals
We compute with pulses.
v R
–
• Inductor current cannot
change instantaneously
)
We send beautiful pulses in:
+
R
(
voltage
+
0
time constant
τ = RC
Prof. Chang-Hasnain
time
But we receive lousy-looking
pulses at the output:
voltage
for t > 0, v(t ) = iR = I o Re
L
t
time
Capacitor charging effects are responsible!
• Every node in a real circuit has capacitance; it’s the charging
of these capacitances that limits circuit performance (speed)
EE40 Fall
2006
Slide 144
Prof. Chang-Hasnain
Circuit Model for a Logic Gate
Pulse Distortion
R
• Recall (from Lecture 1) that electronic building blocks
referred to as “logic gates” are used to implement
logical functions (NAND, NOR, NOT) in digital ICs
– Any logical function can be implemented using these gates.
+
+
Vin(t)
Vout
C
–
• A logic gate can be modeled as a simple RC circuit:
The input voltage pulse
width must be large
enough; otherwise the
output pulse is distorted.
(We need to wait for the output to
reach a recognizable logic level,
before changing the input again.)
–
R
Pulse width = 0.1RC
Vout
–
switches between “low” (logic 0)
and “high” (logic 1) voltage states
EE40 Fall
2006
0
Slide 145
Prof. Chang-Hasnain
Example
Suppose a voltage pulse of width
5 µs and height 4 V is applied to the
input of this circuit beginning at t = 0:
τ = RC = 2.5 µs
2
Time
3
4
0
5
1
EE40 Fall
2006
2
Time
3
4
5
0
Slide 146
R
Vin
+
Vout
R = 2.5 k
C = 1 nF
C
What is the peak value of Vout?
The output increases for 5 µs, or 2 time constants.
It reaches 1-e-2 or 86% of the final value.
0.86 x 4 V = 3.44 V is the peak value
Slide 147
1
5
10
Time
15
20
25
Prof. Chang-Hasnain
First Order Circuits: Forced Response
• First, Vout will increase exponentially toward 4 V.
• When Vin goes back down, Vout will decrease exponentially
back down to 0 V.
EE40 Fall
2006
Vout
C
Pulse width = 10RC
6
5
4
3
2
1
0
6
5
4
3
2
1
0
Vout
Vin(t) +
−
Pulse width = RC
6
5
4
3
2
1
0
Vout
+
Prof. Chang-Hasnain
+
vr(t)
-
R
C
vs(t)
-
iL(t)
ic(t)
+
+
vc(t)
-
is(t)
R
L
vL(t)
-
KCL at the node:
KVL around the loop:
vr(t) + vc(t) = vs(t)
RC
t
v(t ) 1
+
v( x)dx = is (t )
R
L −∞
dvc (t )
+ vc (t ) = vs (t )
dt
EE40 Fall
2006
L diL (t )
+ iL (t ) = is (t )
R dt
Slide 148
Prof. Chang-Hasnain
Complete Solution
The Time Constant
• Voltages and currents in a 1st order circuit satisfy a
differential equation of the form
x(t ) + τ
dx(t )
= f (t )
dt
• The complementary solution for any 1st
order circuit is
xc (t ) = Ke − t /τ
– f(t) is called the forcing function.
• The complete solution is the sum of particular solution
(forced response) and complementary solution (natural
response).
x(t ) = x p (t ) + xc (t )
• For an RC circuit, τ = RC
• For an RL circuit, τ = L/R
– Particular solution satisfies the forcing function
– Complementary solution is used to satisfy the initial conditions.
– The initial conditions determine the value of K.
x p (t ) + τ
EE40 Fall
2006
dx p (t )
dt
dxc (t )
=0
dt
xc (t ) = Ke − t /τ
xc (t ) + τ
= f (t )
Slide 149
Homogeneous
equation
Prof. Chang-Hasnain
EE40 Fall
2006
What Does Xc(t) Look Like?
xc (t ) = e− t /τ
τ = 10-4
• τ is the amount of time necessary
for an exponential to decay to
36.7% of its initial value.
• -1/τ is the initial slope of an
exponential with an initial value of
1.
EE40 Fall
2006
Slide 151
Prof. Chang-Hasnain
Slide 150
Prof. Chang-Hasnain
The Particular Solution
• The particular solution xp(t) is usually a
weighted sum of f(t) and its first derivative.
• If f(t) is constant, then xp(t) is constant.
• If f(t) is sinusoidal, then xp(t) is sinusoidal.
EE40 Fall
2006
Slide 152
Prof. Chang-Hasnain
The Particular Solution: F(t) Constant
xP (t ) + τ
dx (t )
xP (t ) + τ P = F
dt
Equation holds for all time
and time variations are
independent and thus each
time variation coefficient is
individually zero
( A + Bt ) + τ
EE40 Fall
2006
d ( A sin( wt ) + B cos( wt ))
= FA sin( wt ) + FB cos( wt )
dt
( A − τω B − FA ) sin(ωt ) + ( B + τω A − FB ) cos(ωt ) = 0
Equation holds for all time and
( B + τω A − FB ) = 0
( A − τω B − FA ) = 0
( A + τB − F ) + ( B )t = 0
A= F
=
Slide 153
Prof. Chang-Hasnain
xP (t ) + τ
Guess a solution
xP (t ) = A + Be −αt
Equation holds for all time
and time variations are
independent and thus each
time variation coefficient is
individually zero
( A + Be −αt ) + τ
d ( A + Be −αt )
= F1e −αt + F2
dt
( A + Be −αt ) − ατBe −αt = F1e −αt + F2
( A − F2 ) + ( B − ατ − F1 )e −αt = 0
( A − F2 ) = 0
( B − ατ − F1 ) = 0
Slide 155
2
(τω ) + 1
1
2
(τω ) + 1
2
(τω ) + 1
sin(ωt ) +
(τω ) 2 + 1
cos(ωt )
cos(ωt − θ ); where θ = tan −1 (τω )
Slide 154
Prof. Chang-Hasnain
dxP (t )
= FA sin( wt ) + FB cos( wt )
dt
F + τω F
τω FA − FB
B=−
A= A 2 B
xP (t ) = A sin( wt ) + B cos( wt )
(τω ) 2 + 1
(τω ) + 1
xP (t ) + τ
xC (t ) = Ke
−t
τ
xT (t ) = A sin( wt ) + B cos( wt ) + Ke
Only K is unknown and
is determined by the
initial condition at t =0
−0
τ
τ
= VC (t = 0)
xT (0) = B + K = VC (t = 0)
EE40 Fall
2006
−t
Example: xT(t=0) = VC(t=0)
xT (0) = A sin(0) + B cos(0) + Ke
Prof. Chang-Hasnain
1
The Total Solution: F(t) Sinusoid
A = F2
B = ατ + F1
EE40 Fall
2006
dxP (t )
= F1e −αt + F2
dt
τω
1
EE40 Fall
2006
The Particular Solution: F(t) Exp.
time variations are independent
and thus each time variation
coefficient is individually zero
τω FA − FB
B=−
(τω ) 2 + 1
F + τω F
A= A 2 B
(τω ) + 1
xP (t ) =
( A + τB − F ) = 0
B=0
xP (t ) = A sin( wt ) + B cos( wt )
( A sin( wt ) + B cos( wt )) + τ
d ( A + Bt )
=F
dt
( A + Bt ) + τB = F
( B) = 0
dxP (t )
= FA sin( wt ) + FB cos( wt )
dt
Guess a solution
Guess a solution
xP (t ) = A + Bt
The Particular Solution: F(t) Sinusoid
K = VC (t = 0) − B
Slide 156
Prof. Chang-Hasnain
Example
R
Vs
+
−
C
2nd Order Circuits
t=0
+
vc
–
• Given vc(0-)=1, Vs=2 cos(ωt), ω=200.
• Find i(t), vc(t)=?
EE40 Fall
2006
Slide 157
Prof. Chang-Hasnain
• Any circuit with a single capacitor, a single
inductor, an arbitrary number of sources,
and an arbitrary number of resistors is a
circuit of order 2.
• Any voltage or current in such a circuit is
the solution to a 2nd order differential
equation.
EE40 Fall
2006
A 2nd Order RLC Circuit
Slide 158
The Differential Equation
i (t)
i (t)
+
vs(t)
vs(t)
C
-
R
+
Prof. Chang-Hasnain
+
vc(t)
C
-
• Application: Filters
– A bandpass filter such as the IF amp for
the AM radio.
– A lowpass filter with a sharper cutoff
than can be obtained with an RC circuit.
Slide 159
+ vr(t) -
R
L
EE40 Fall
2006
Prof. Chang-Hasnain
KVL around the loop:
vr(t) + vc(t) + vl(t) = vs(t)
vl(t) +
-
L
t
di (t )
1
= vs (t )
i ( x)dx + L
C −∞
dt
R di (t ) 1
d 2i (t ) 1 dvs (t )
+
i (t ) +
=
L dt
LC
dt 2
L dt
Ri (t ) +
EE40 Fall
2006
Slide 160
Prof. Chang-Hasnain
The Differential Equation
The Particular Solution
The voltage and current in a second order circuit is
the solution to a differential equation of the
following form:
d 2 x(t )
dx(t )
+ 2α
+ ω02 x(t ) = f (t )
2
dt
dt
• The particular solution xp(t) is usually a
weighted sum of f(t) and its first and
second derivatives.
• If f(t) is constant, then xp(t) is constant.
• If f(t) is sinusoidal, then xp(t) is sinusoidal.
x(t ) = x p (t ) + xc (t )
Xp(t) is the particular solution (forced response)
and Xc(t) is the complementary solution (natural
response).
EE40 Fall
2006
Slide 161
Prof. Chang-Hasnain
EE40 Fall
2006
The Complementary Solution
The complementary solution has the following
form:
st
xc (t ) = Ke
K is a constant determined by initial conditions.
s is a constant determined by the coefficients of
the differential equation.
d 2 Ke st
dKe st
+ 2α
+ ω02 Ke st = 0
2
dt
dt
2
st
st
2
0
• To find the complementary solution, we
need to solve the characteristic equation:
s 2 + 2ζω0 s + ω02 = 0
α = ζω0
• The characteristic equation has two rootscall them s1 and s2.
xc (t ) = K1e s1t + K 2 e s2t
st
s1 = −ζω0 + ω0 ζ 2 − 1
s 2 + 2α s + ω02 = 0
Slide 163
Prof. Chang-Hasnain
Characteristic Equation
s Ke + 2α sKe + ω Ke = 0
EE40 Fall
2006
Slide 162
s2 = −ζω0 − ω0 ζ 2 − 1
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 164
Prof. Chang-Hasnain
Damping Ratio and Natural Frequency
• If ζ > 1, s1 and s2 are real and not equal.
s1 = −ζω0 + ω0 ζ 2 − 1
ic (t ) = K 1e
s2 = −ζω0 − ω0 ζ 2 − 1
damping ratio
• The damping ratio determines what type of
solution we will get:
– Exponentially decreasing (ζ >1)
– Exponentially decreasing sinusoid (ζ < 1)
• The natural frequency is ω0
– It determines how fast sinusoids wiggle.
EE40 Fall
2006
Slide 165
Prof. Chang-Hasnain
Underdamped: Complex Roots
• If ζ < 1, s1 and s2 are complex.
• Define the following constants:
+ K 2e
1
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0
-1.00E-06
-0.2
0
-1.00E-06
t
t
EE40 Fall
2006
Slide 166
• If ζ = 1, s1 and s2 are real and equal.
xc (t ) = K1e −ςω0t + K 2te −ςω0t
Note: The
degeneracy of the
roots results in the
extra factor of ‘t’
1
0.8
0.6
i(t)
0.4
0.2
1.00E-05
Prof. Chang-Hasnain
Critically damped: Real Equal Roots
xc (t ) = e −α t ( A1 cos ωd t + A2 sin ωd t )
0
-1.00E-05
-0.2
−ςω 0 −ω 0 ς 2 −1 t
0.2
ω d = ω0 1 − ζ 2
α = ζω0
−ςω 0 +ω 0 ς 2 −1 t
i(t)
α
ω0
i(t)
ζ =
Overdamped : Real Unequal Roots
3.00E-05
-0.4
-0.6
-0.8
-1
t
EE40 Fall
2006
Slide 167
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 168
Prof. Chang-Hasnain
Example
Example
For the example, what are ζ and ω0?
i (t)
+
d 2i (t ) R di (t ) 1
1 dvs (t )
+
+
i (t ) =
2
dt
L dt
LC
L dt
10Ω
d 2 xc (t )
dx (t )
+ 2ζω0 c + ω02 xc (t ) = 0
2
dt
dt
769pF
159µH
• ζ = 0.011
• ω0 = 2π455000
• Is this system over damped, under
damped, or critically damped?
• What will the current look like?
1
0.8
0.6
0.4
i(t)
1
R
R C
, 2ζω0 =
, ζ =
ω =
2 L
LC
L
2
0
0.2
0
-1.00E-05
-0.2
1.00E-05
3.00E-05
-0.4
-0.6
-0.8
-1
t
EE40 Fall
2006
Slide 169
Prof. Chang-Hasnain
EE40 Fall
2006
Slightly Different Example
Linear TimeInvariant
Circuit
i (t)
1
1kΩ
769pF
Steady-State Excitation
(DC Steady-State)
0.6
0.4
0.2
-
0
-1.00E-06
159µH
Linear TimeInvariant
Circuit
t
ζ = 2.2
ω0 = 2π455000
EE40 Fall
2006
Linear TimeInvariant
Circuit
0.8
i(t)
vs(t)
Prof. Chang-Hasnain
Types of Circuit Excitation
• Increase the resistor to 1kΩ
• What are ζ and ω0?
+
Slide 170
OR
Digital
Pulse
Source
Sinusoidal (SingleFrequency) Excitation
AC Steady-State
Slide 171
Prof. Chang-Hasnain
EE40 Fall
2006
Linear TimeInvariant
Circuit
Transient Excitation
Slide 172
Prof. Chang-Hasnain
Representing a Square Wave as a Sum of Sinusoids
Why is Single-Frequency Excitation Important?
EE40 Fall
2006
Slide 173
Prof. Chang-Hasnain
b
signal(V)
Signal
signal(V)
Signal
a
Frequency (Hz)
(a)Square wave with 1-second period. (b) Fundamental component
(dotted) with 1-second period, third-harmonic (solid black) with1/3-second
period, and their sum (blue). (c) Sum of first ten components. (d)
Spectrum with 20 terms.
EE40 Fall
2006
Steady-State Sinusoidal Analysis
• Also known as AC steady-state
• Any steady state voltage or current in a linear circuit with
a sinusoidal source is a sinusoid.
– This is a consequence of the nature of particular solutions for
sinusoidal forcing functions.
• All AC steady state voltages and currents have the same
frequency as the source.
• In order to find a steady state voltage or current, all we
need to know is its magnitude and its phase relative to
the source
– We already know its frequency.
• Usually, an AC steady state voltage or current is given
by the particular solution to a differential equation.
EE40 Fall
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Slide 175
Prof. Chang-Hasnain
T i me (ms)
d
Relative Amplitude
c
Signal (V)
• Some circuits are driven by a single-frequency
sinusoidal source.
• Some circuits are driven by sinusoidal sources
whose frequency changes slowly over time.
• You can express any periodic electrical signal as
a sum of single-frequency sinusoids – so you
can analyze the response of the (linear, timeinvariant) circuit to each individual frequency
component and then sum the responses to get
the total response.
• This is known as Fourier Transform and is
tremendously important to all kinds of engineering
disciplines!
Slide 174
Prof. Chang-Hasnain
Chapter 5
• OUTLINE
– Phasors as notation for Sinusoids
– Arithmetic with Complex Numbers
– Complex impedances
– Circuit analysis using complex impdenaces
– Dervative/Integration as multiplication/division
– Phasor Relationship for Circuit Elements
• Reading
– Chap 5
– Appendix A
EE40 Fall
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Slide 176
Prof. Chang-Hasnain
Example 1: 2nd Order RLC Circuit
t=0
Example 2: 2nd Order RLC Circuit
t=0
+
Vs
-
R
C
L
EE40 Fall
2006
R
+
Vs
-
Slide 177
Prof. Chang-Hasnain
C
EE40 Fall
2006
Slide 178
imaginary
axis
Two terms to be general
Dervatives
(t ) = A sin( wt ) + B cos( wt )
Addition
d ( A sin( wt ) + B cos( wt ))
Guess a solution
xP
( A sin( wt ) + B cos( wt )) + τ
dt
F + τF
A = A2 B
τ +1
τF − F
B = − A2 B
τ +1
Phasors (vectors that rotate in the complex
plane) are a clever alternative.
EE40 Fall
2006
Slide 179
Prof. Chang-Hasnain
j = (−1)
θ
= FA sin( wt ) + FB cos( wt )
( A − τB − FA ) sin( wt ) + ( B + τA − FB ) cos( wt ) = 0
Equation holds for all time
( A − τB − FA ) = 0
and time variations are
( B + τA − FB ) = 0
independent and thus each
time variation coefficient is
individually zero
y
z
dxP (t )
= FA sin( wt ) + FB cos( wt )
dt
Prof. Chang-Hasnain
Complex Numbers (1)
Sinusoidal Sources Create Too Much Algebra
xP (t ) + τ
L
real
axis
x
• Rectangular Coordinates
Z = x + jy
• Polar Coordinates:
Z=z∠θ
• Exponential Form:
jθ
Z = Z e = ze
EE40 Fall
2006
jθ
•
•
•
•
x is the real part
y is the imaginary part
z is the magnitude
θ is the phase
y = z sin θ
x = z cos θ
z = x2 + y2
θ = tan −1
y
x
Z = z (cos θ + j sin θ )
1 = 1e j 0 = 1∠0°
j = 1e
Slide 180
j
π
2
= 1∠90°
Prof. Chang-Hasnain
Arithmetic With Complex Numbers
Complex Numbers (2)
Euler’s Identities
e jθ + e − jθ
cos θ =
2
jθ
e − e − jθ
sin θ =
2j
e jθ = cos θ + j sin θ
e jθ = cos 2 θ + sin 2 θ = 1
• To compute phasor voltages and currents, we
need to be able to perform computation with
complex numbers.
– Addition
– Subtraction
– Multiplication
– Division
• (And later use multiplication by jω to replace
Exponential Form of a complex number
jθ
jθ
Z = Z e = ze = z∠θ
EE40 Fall
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Slide 181
Prof. Chang-Hasnain
– Diffrentiation
– Integration
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2006
Slide 182
Addition
Prof. Chang-Hasnain
Addition
• Addition is most easily performed in
rectangular coordinates:
A = x + jy
B = z + jw
Imaginary
Axis
A+B
A + B = (x + z) + j(y + w)
B
EE40 Fall
2006
Slide 183
Prof. Chang-Hasnain
EE40 Fall
2006
A
Slide 184
Real
Axis
Prof. Chang-Hasnain
Subtraction
Subtraction
• Subtraction is most easily performed in
rectangular coordinates:
A = x + jy
B = z + jw
Imaginary
Axis
A - B = (x - z) + j(y - w)
B
A
Real
Axis
A-B
EE40 Fall
2006
Slide 185
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 186
Multiplication
Multiplication
• Multiplication is most easily performed in
polar coordinates:
A = AM ∠ θ
B = BM ∠ φ
A×B
Slide 187
Imaginary
Axis
B
A × B = (AM × BM) ∠ (θ + φ)
EE40 Fall
2006
Prof. Chang-Hasnain
A
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 188
Real
Axis
Prof. Chang-Hasnain
Division
Division
• Division is most easily performed in polar
coordinates:
A = AM ∠ θ
B = BM ∠ φ
Imaginary
Axis
B
A / B = (AM / BM) ∠ (θ − φ)
A
Real
Axis
A/B
EE40 Fall
2006
Slide 189
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 190
Phasors
Arithmetic Operations of Complex Numbers
• Add and Subtract: it is easiest to do this in rectangular
format
– Add/subtract the real and imaginary parts separately
• Multiply and Divide: it is easiest to do this in
exponential/polar format
– Multiply (divide) the magnitudes
– Add (subtract) the phases
• Assuming a source voltage is a sinusoid timevarying function
v(t) = V cos (ωt + θ)
• We can write:
v(t ) = V cos(ωt + θ ) = V Re e j (ωt +θ ) = Re Ve j (ωt +θ )
Define Phasor as Ve jθ = V ∠θ
Z1 = z1e jθ1 = z1∠θ1 = z1 cos θ1 + jz1 sin θ1
• Similarly, if the function is v(t) = V sin (ωt + θ)
Z 2 = z2 e jθ2 = z2∠θ 2 = z2 cos θ 2 + jz2 sin θ 2
π
Z1 + Z 2 = ( z1 cos θ1 + z2 cos θ 2 ) + j ( z1 sin θ1 + z2 sin θ 2 )
v(t ) = V sin(ωt + θ ) = V cos(ωt + θ − ) = Re Ve
2
Z1 − Z 2 = ( z1 cos θ1 − z2 cos θ 2 ) + j ( z1 sin θ1 − z2 sin θ 2 )
Z1 × Z 2 = ( z1 × z2 )e j (θ1 +θ2 ) = ( z1 × z2 )∠(θ1 + θ 2 )
Phasor = V ∠
Slide 191
π
j (ω t +θ − )
2
( )
θ−
π
2
Z1 / Z 2 = ( z1 / z2 )e j (θ1 −θ2 ) = ( z1 / z2 )∠(θ1 − θ 2 )
EE40 Fall
2006
Prof. Chang-Hasnain
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 192
Prof. Chang-Hasnain
Phasor: Rotating Complex Vector
{
}
(
v(t ) = V cos(ωt + φ ) = Re Ve jφ e jwt = Re V e jωt
Imaginary
Axis
)
Rotates at uniform
angular velocity ωt
V
cos(ω
ωt+φ
φ)
Real
Axis
The head start angle is φ.
EE40 Fall
2006
Slide 193
Prof. Chang-Hasnain
Complex Exponentials
• We represent a real-valued sinusoid as the real
part of a complex exponential after multiplying
by e jω.t
• Complex exponentials
– provide the link between time functions and phasors.
– Allow dervatives and integrals to be replaced by
multiplying or dividing by jω
– make solving for AC steady state simple algebra with
complex numbers.
• Phasors allow us to express current-voltage
relationships for inductors and capacitors much
like we express the current-voltage relationship
for a resistor.
EE40 Fall
2006
Slide 194
I-V Relationship for a Capacitor
v(t)
C
Capacitor Impedance (1)
i(t)
C
+
i(t)
i (t ) = C
-
dv(t )
dt
Prof. Chang-Hasnain
+
v(t
-)
v(t ) = V cos(ωt + θ ) =
i (t ) = C
dv(t )
dt
V j (ωt +θ ) − j (ωt +θ )
+e
e
2
dv(t ) CV d j (ωt +θ ) − j (ωt +θ )
CV
=
+e
=
e
jω e j (ωt +θ ) − e − j (ωt +θ )
2 dt
2
dt
−ωCV j (ωt +θ ) − j (ωt +θ )
π
=
−e
= −ωCV sin(ωt + θ ) = ωCV cos(ωt + θ + )
e
2j
2
V
π
1
π
1
1
V ∠θ
V
=
∠(θ − θ − ) =
Zc = =
∠(− ) = − j
=
π
I
2
2
ωCV
ωC
ωC jωC
I∠ θ +
2
i (t ) = C
Suppose that v(t) is a sinusoid:
v(t) = Re{VM ej(ωt+θ)}
Find i(t).
EE40 Fall
2006
Slide 195
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 196
Prof. Chang-Hasnain
Capacitor Impedance (2)
+
i(t)
C
v(t
-)
Example
v(t) = 120V cos(377t + 30°)
C = 2µF
dv(t )
i (t ) = C
dt
Phasor definition
v(t ) = V cos(ωt + θ ) = Re Ve
j (ωt +θ )
V = V ∠θ
dv(t )
de j (ωt +θ )
i (t ) = C
= Re CV
= Re jωCVe j (ωt +θ )
dt
dt
Zc =
• What is V?
• What is I?
• What is i(t)?
I = I ∠θ
1
V V ∠θ
V
=
=
∠(θ − θ ) =
I I ∠θ
jωCV
jωC
EE40 Fall
2006
Slide 197
Prof. Chang-Hasnain
EE40 Fall
2006
Computing the Current
Slide 198
Inductor Impedance
+
i(t)
EE40 Fall
2006
dt
jω
Slide 199
v(t)
L
Note: The differentiation and integration
operations become algebraic operations
d
dt
Prof. Chang-Hasnain
-
1
jω
v(t ) = L
di (t )
dt
V = jωL I
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 200
Prof. Chang-Hasnain
Example
Phase
i(t) = 1µA cos(2π 9.15 107t + 30°)
L = 1µH
Voltage
7 cos(ωt ) = 7∠0°
π
π
7 sin(ωt ) = 7 cos(ωt − ) = 7∠ −
2
2
8
lead
• What is I?
• What is V?
• What is v(t)?
inductor current
6
Behind
4
2
t
0
-2 0
0.01
0.02
0.03
0.04
0.05
-4
-6
-8
capacitor current
π
π
−7 sin(ωt ) = 7 cos(ωt + ) = 7∠ +
2
2
EE40 Fall
2006
Slide 201
Prof. Chang-Hasnain
EE40 Fall
2006
Phasor Diagrams
Slide 202
Prof. Chang-Hasnain
Impedance
• A phasor diagram is just a graph of
several phasors on the complex plane
(using real and imaginary axes).
• A phasor diagram helps to visualize the
relationships between currents and
voltages.
• Capacitor: I leads V by 90o
• Inductor: V leads I by 90o
• AC steady-state analysis using phasors
allows us to express the relationship
between current and voltage using a
formula that looks likes Ohm’s law:
V=IZ
• Z is called impedance.
EE40 Fall
2006
EE40 Fall
2006
Slide 203
Prof. Chang-Hasnain
Slide 204
Prof. Chang-Hasnain
Some Thoughts on Impedance
Example: Single Loop Circuit
• Impedance depends on the frequency ω.
• Impedance is (often) a complex number.
• Impedance allows us to use the same
solution techniques for AC steady state as
we use for DC steady state.
+
10V ∠ 0°
20kΩ
+
VC
1µF
-
-
f=60 Hz, VC=?
How do we find VC?
First compute impedances for resistor and capacitor:
ZR = R= 20kΩ = 20kΩ ∠ 0°
ZC = 1/j (2πf x 1µF) = 2.65kΩ ∠ -90°
EE40 Fall
2006
Slide 205
Prof. Chang-Hasnain
EE40 Fall
2006
Impedance Example
Slide 206
Prof. Chang-Hasnain
What happens when ω changes?
20kΩ ∠ 0°
+
VC
-
+
10V ∠ 0°
-
+
2.65kΩ ∠ -90°
10V ∠ 0°
+
VC
1µF
-
-
ω = 10
Find VC
Now use the voltage divider to find VC:
VC = 10V ∠0°
20kΩ
2.65kΩ∠ - 90°
2.65kΩ∠ - 90° + 20kΩ∠0°
VC = 1.31V ∠ - 82.4°
EE40 Fall
2006
Slide 207
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 208
Prof. Chang-Hasnain
Steady-State AC Analysis
Circuit Analysis Using Complex Impedances
• Suitable for AC steady state.
• KVL
+
v1 (t ) + v2 (t ) + v3 (t ) = 0
5mA ∠ 0°
V1 cos (ωt + θ1 ) + V2 cos (ωt + θ 2 ) + V3 cos (ωt + θ3 ) = 0
0.1µF
V
1kΩ
-
Re V1e j (ωt +θ1 ) + V2 e j (ωt +θ2 ) + V3e j (ωt +θ3 ) = 0
Find v(t) for ω=2π 3000
Phasor Form KVL
V1e j (θ1 ) + V2e j (θ2 ) + V3e j (θ3 ) = 0
V1 + V2 + V3 = 0
+
I1 + I 2 + I 3 = 0
• Phasor Form KCL
• Use complex impedances for inductors and capacitors and
follow same analysis as in chap 2.
EE40 Fall
2006
Slide 209
Prof. Chang-Hasnain
5mA ∠ 0°
V
-j530kΩ
1kΩ
EE40 Fall
2006
Find the Equivalent Impedance
Slide 210
Prof. Chang-Hasnain
Change the Frequency
+
+
5mA ∠ 0°
5mA ∠ 0°
Zeq
V
0.1µF
V
1kΩ
-
Find v(t) for ω=2π 455000
1000(− j 530 ) 10 ∠0° × 530∠ − 90°
=
1000 − j 530
1132∠ − 27.9°
3
Z eq =
+
-j3.5Ω
Z eq = 468.2Ω∠ − 62.1°
5mA ∠ 0°
V = IZ eq = 5mA∠0° × 468.2Ω∠ − 62.1°
V
1kΩ
-
V = 2.34V∠ − 62.1°
v(t ) = 2.34V cos(2π 3000t − 62.1°)
EE40 Fall
2006
Slide 211
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 212
Prof. Chang-Hasnain
Find an Equivalent Impedance
Series Impedance
+
5mA ∠ 0°
Zeq
Z eq =
V
Z1
-
Z3
Z2
1000(− j 3.5) 10 3 ∠0° × 3.5∠ − 90°
=
1000 − j 3.5
1000∠ − 0.2°
Z eq = 3.5Ω∠ − 89.8°
Zeq
Zeq = Z1 + Z2 + Z3
For example:
V = IZ eq = 5mA∠0° × 3.5Ω∠ − 89.8°
V = 17.5mV∠ − 89.8°
L1
v(t ) = 17.5mV cos(2π 455000t − 89.8°)
C1
L2
Z eq =
Zeq = jω(L1+L2)
EE40 Fall
2006
Slide 213
Prof. Chang-Hasnain
Parallel Impedance
EE40 Fall
2006
Z2
Z3
1
1
+
jωC1 jωC2
Slide 214
Prof. Chang-Hasnain
Steady-State AC Node-Voltage Analysis
+
Z1
C2
Zeq
I0sin(ωt)
VC
I1cos(ωt)
C
R
-
L
1/Zeq = 1/Z1 + 1/Z2 + 1/Z3
For example:
L1
Z eq = jω
EE40 Fall
2006
• Try using Thevinin equivalent circuit.
L2
C1
L1 L2
( L1 + L2 )
Z eq =
Slide 215
C2
• What happens if the sources are at different
frequencies?
1
jω (C1 + C2 )
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 216
Prof. Chang-Hasnain
Resistor I-V relationship
R
vR = iRR ………….VR = IRR where R is the resistance in ohms,
VR = phasor voltage, IR = phasor current
(boldface indicates complex quantity)
v0 (t ) = V0 cos(ωt )
v0 (t ) = V0 cos(ωt )
V 0 = V0 ∠0
V 0 = V0 ∠0
V 0 = V0 ∠0
i0 (t ) =
Inductor I-V relationship
Slide 217
Prof. Chang-Hasnain
+
+
VC
1µF
-
-
i0 (t ) =
I 0 = ωCV0∠90
I0 =
Slide 218
V0
ωL
V0
ωL
sin(ωt )
∠ − 90
Prof. Chang-Hasnain
Root Mean Square (rms) Values
ZTH
20kΩ
V0
∠0
R
EE40 Fall
2006
Thevenin Equivalent
10V ∠ 0°
V0
cos(ωt ) i0 (t ) = −ωCV0 sin(ωt )
R
I0 =
vL = LdiL/dt ...............Phasor voltage VL = phasor current IL/
inductive impedance ZL VL = ILZL
where ZL = jωL, j = (-1)1/2 and boldface
indicates complex quantity
EE40 Fall
2006
L
v0 (t ) = V0 cos(ωt )
Capacitor I-V relationship
iC = CdvC/dt ...............Phasor current IC = phasor voltage VC /
capacitive impedance ZC: IC = VC/ZC
where ZC = 1/jωC , j = (-1)1/2 and boldface
indicates complex quantity
C
• rms valued defined as
T
1 2
v (t )dt
T o
vRMS =
+
VTH
-
T = period
• Assuming a sinusoid gives
f=60 Hz
T
1
2
vm cos 2 (ωt + θ )dt
T o
vRMS =
ZR = R= 20kΩ = 20kΩ ∠ 0°
ZC = 1/j (2πf x 1µF) = 2.65kΩ ∠ -90°
• Using an identity gives
2 T
VTH = VOC = 10V ∠0°
ZTH
EE40 Fall
2006
2.65kΩ∠ - 90°
= 1.31∠ − 82.4
2.65kΩ∠ - 90° + 20kΩ∠0°
20kΩ∠0° ⋅ 2.65kΩ∠ - 90°
= 2.62∠ − 82.4
= Z R || Z C = °
2.65kΩ∠ - 90° + 20kΩ∠0°
Slide 219
Prof. Chang-Hasnain
vRMS =
vm
[1 + cos(2ωt + 2θ )]dt
2T o
• Evaluating at limits gives
2
vRMS =
EE40 Fall
2006
1
1
vm
[T +
sin(2ωT + 2θ ) −
sin(2θ )]
2T
2ω
2w
Slide 220
vRMS =
vm
2
Prof. Chang-Hasnain
Power: Instantaneous and Time-Average
For a Resistor
• The instantaneous power is
p(t ) = v(t )i (t ) =
v(t ) 2
R
ZTH
+
T
T
-
T
v2
1
1 v(t ) 2
1 1
p (t )dt =
dt = [
v(t ) 2 dt ] = rms
R
T 0
T 0 R
R T 0
For an Impedance
v(t )i (t
• The instantaneous power is
• Maximum time average power occurs when
Z LOAD = Z*TH
p(t ) = v(t )i (t )
• This presents a resistive impedance to the source
• The time-average power isT
PAVE =
1
T
T
p(t )dt =
0
• The reactive power at 2ω is
1
*
v(t )i (t )dt = Re{Vrms ⋅ I rms }
T 0
Q = Im{Vrms ⋅ I *rms }
EE40 Fall
2006
ZLOAD
VTH
• The time-average power is
PAVE =
Maximum Average Power Transfer
Slide 221
Z total = ZTH + Z*TH
• Power transferred is
PAVE = Re{VI*} = Re{V
2
PAVE
+ Q 2 = (Vrms ⋅ I rms ) 2
Prof. Chang-Hasnain
EE40 Fall
2006
Chapter 6
V2
V*
} = 12 rms
2R
R
Slide 222
Prof. Chang-Hasnain
Bel and Decibel (dB)
• OUTLINE
– Frequency Response for Characterization
– Asymptotic Frequency Behavior
– Log magnitude vs log frequency plot
– Phase vs log frequency plot
– dB scale
– Transfer function example
• A bel (symbol B) is a unit of measure of ratios of power
levels, i.e. relative power levels.
– The name was coined in the early 20th century in honor of
Alexander Graham Bell, a telecommunications pioneer.
– The bel is a logarithmic measure. The number of bels for a given
ratio of power levels is calculated by taking the logarithm, to the
base 10, of the ratio.
– one bel corresponds to a ratio of 10:1.
– B = log10(P1/P2) where P1 and P2 are power levels.
• The bel is too large for everyday use, so the decibel
(dB), equal to 0.1B, is more commonly used.
– 1dB = 10 log10(P1/P2)
• dB are used to measure
– Electric power, Gain or loss of amplifiers, Insertion loss of filters.
EE40 Fall
2006
Slide 223
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 224
Prof. Chang-Hasnain
Logarithmic Measure for Power
• To express a power in terms of decibels, one starts by
choosing a reference power, Preference, and writing
Power P in decibels = 10 log10(P/Preference)
• Exercise:
– Express a power of 50 mW in decibels relative to 1 watt.
– P (dB) =10 log10 (50 x 10-3) = - 13 dB
• Exercise:
– Express a power of 50 mW in decibels relative to 1 mW.
– P (dB) =10 log10 (50) = 17 dB.
Logarithmic Measures for Voltage or Current
From the expression for power ratios in decibels, we can
readily derive the corresponding expressions for voltage
or current ratios.
Suppose that the voltage V (or current I) appears across
(or flows in) a resistor whose resistance is R. The
corresponding power dissipated, P, is V2/R (or I2R). We
can similarly relate the reference voltage or current to the
reference power, as
Preference = (Vreference)2/R or Preference= (Ireference)2R.
• dBm to express absolute values of power relative to a
milliwatt.
Hence,
– dBm = 10 log10 (power in milliwatts / 1 milliwatt)
– 100 mW = 20 dBm
– 10 mW = 10 dBm
EE40 Fall
2006
Slide 225
Voltage, V in decibels = 20log10(V/Vreference)
Current, I, in decibels = 20log10(I/Ireference)
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 226
Prof. Chang-Hasnain
Logarithmic Measures for Voltage or Current
Logarithmic Measures for Voltage or Current
Note that the voltage and current expressions are just
like the power expression except that they have 20 as
the multiplier instead of 10 because power is
proportional to the square of the voltage or current.
The gain produced by an amplifier or the loss of a filter
is often specified in decibels.
Exercise: How many decibels larger is the voltage of a
9-volt transistor battery than that of a 1.5-volt AA
battery? Let Vreference = 1.5. The ratio in decibels is
The input voltage (current, or power) is taken as the
reference value of voltage (current, or power) in the
decibel defining expression:
Voltage gain in dB = 20 log10(Voutput/Vinput)
Current gain in dB = 20log10(Ioutput/Iinput
Power gain in dB = 10log10(Poutput/Pinput)
20 log10(9/1.5) = 20 log10(6) = 16 dB.
Example: The voltage gain of an amplifier whose input
is 0.2 mV and whose output is 0.5 V is
20log10(0.5/0.2x10-3) = 68 dB.
EE40 Fall
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Slide 227
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 228
Prof. Chang-Hasnain
Frequency Response
Bode Plot
• Plot of magnitude of transfer function vs.
frequency
– Both x and y scale are in log scale
– Y scale in dB
• The shape of the frequency response of the complex
ratio of phasors VOUT/VIN is a convenient means of
classifying a circuit behavior and identifying key
parameters.
• Log Frequency Scale
– Decade
= 10
– Octave
=2
Break point
Ratio of higher to lower frequency
VOUT
VIN
Gain
Break point
VOUT
VIN
Low Pass
Ratio of higher to lower frequency
Gain
High Pass
Frequency
Frequency
FYI: These are log ratio vs log frequency plots
EE40 Fall
2006
Slide 229
Prof. Chang-Hasnain
EE40 Fall
2006
Example Circuit
+
+
+
AVT
+
R1
VT
C
−
TransferFunction =
VOUT
VIN
VOUT
AZ c
=
VIN
Z R + Zc
Prof. Chang-Hasnain
Break Point Values
R2
VIN
Slide 230
VOUT
A = 100
R1 = 100,000 Ohms
• When dealing with resonant circuits it is convenient
to refer to the frequency difference between points at
which the power from the circuit is half that at the
peak of resonance.
• Such frequencies are known as “half-power
frequencies”, and the power output there referred to
the peak power (at the resonant frequency) is
• 10log10(Phalf-power/Presonance) = 10log10(1/2) = -3 dB.
R2 = 1000 Ohms
C = 10 uF
A(1 / jwC )
A
VOUT
=
=
VIN
R2 + 1 / jωC ) (1 + jωR2C )
EE40 Fall
2006
Slide 231
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 232
Prof. Chang-Hasnain
Example: Circuit in Slide #3 Phase
Phase
Magnitude
Example: Circuit in Slide #3 Magnitude
A = 100
R2 = 1000 Ohms
C = 10 uF
1000
A
100 VV
OUT
IN
=
A
(1 + jωR2C )
100
C = 10 uF
1
100
10
100
10
100
1000
0.1
EE40 Fall
2006
Prof. Chang-Hasnain
-45o
100∠0
100∠0
Phase{
} = 0 − 45 = −45
} = Phase{
|1+ j |
2∠45
EE40 Fall
2006
Bode Plot: Label as dB
VOUT
A
=
VIN
(1 + jωR2C )
A
Prof. Chang-Hasnain
• Transfer function is a function of frequency
A = 100
C = 100 uF
– Complex quantity
– Both magnitude and phase are function of
frequency
wp = 1/(R2C) = 100
40
Slide 234
Transfer Function
R2 = 1000 Ohms
60
Radian
Frequency
Actual value is
Radian
Frequency
Slide 233
1000
-90
-180
1
Magnitude in dB
R2 = 1000 Ohms
180
0
Actual value = | 1 + j | =
2
1
A = 100
90
wp = 1/(R2C) = 100
10
VOUT
A
=
VIN
(1 + jωR2C )
Vin
Two Port
filter network
Vout
20
0
1
10
100
1000
-20
H( f ) =
Radian
Frequency
Vout Vout
=
∠ (θ out − θin )
Vin
Vin
H(f) = H ( f )∠θ
Note: Magnitude in dB = 20 log10(VOUT/VIN)
EE40 Fall
2006
Slide 235
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 236
Prof. Chang-Hasnain
Filters
Common Filter Transfer Function vs. Freq
• Circuit designed to retain a certain
frequency range and discard others
H( f )
Low-pass: pass low frequencies and reject high
frequencies
High-pass: pass high frequencies and reject low
frequencies
Band-pass: pass some particular range of
frequencies, reject other frequencies outside
that band
Notch: reject a range of frequencies and pass
all other frequencies
EE40 Fall
2006
Slide 237
Prof. Chang-Hasnain
H( f )
Low Pass
Frequency
H( f )
Frequency
1
1
and f B =
RC
2π RC
H(f) = H ( f )∠θ
H( f ) =
1+
f
fB
2
, θ = − tan
Slide 238
H(f) =
f
fB
EE40 Fall
2006
1+
f
fB
1
H ( fB ) =
= 2−1/ 2
2
H ( fB )
1
= 20(− ) log10 2 = −3 dB
20 log10
H (0)
2
Slide 239
Prof. Chang-Hasnain
(ω RC ) ∠ π − tan −1 ω RC
VR
R
jω RC
=
=
=
(
)
2
V 1 ( jωC ) + R 1 + jω RC
2
1 + (ω RC )
H( f ) =
+
V
-
Frequency
EE40 Fall
2006
Let ωB =
−1
Band Reject
Band Pass
First-Order Highpass Filter
VC
1 ( jωC )
1
1
=
=
=
∠ − tan −1 (ω RC )
2
V 1 ( jωC ) + R 1 + jω RC
1 + (ω RC )
1
Frequency
H( f )
First-Order Lowpass Filter
H(f) =
High Pass
R
,θ =
π
2
− tan −1
f
fB
VR
1
= 2−1/ 2
2
H ( fB )
1
20 log10
= 20(− ) log10 2 = −3 dB
2
H (0)
H ( fB ) =
+
VC
C
f
fB
2
-
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 240
+
V
-
R
+
VC
C
-
Prof. Chang-Hasnain
First-Order Lowpass Filter
H(f) =
1
1
VR
=
=
jω L
V
ωL
+1
1+
R
R
2
∠ − tan −1
First-Order Highpass Filter
ωL
jω L
VL
R
R
H(f) =
=
=
jω L
V
ωL
+1
1+
R
R
ωL
R
R
R
and f B =
L
2π L
H(f) = H ( f )∠θ
Let ωB =
1
H( f ) =
1+
f
fB
2
VR
f
fB
R
+
V
-
H( f ) =
+
-
Prof. Chang-Hasnain
R
C
ωL
R
EE40 Fall
2006
VS
+
–
R
L
High
Pass
HR = R / (R + jωL)
HC = (1/jωC) / (R + 1/jωC)
HL = jωL / (R + jωL)
Slide 243
2
,θ =
π
2
VR
− tan −1
f
fB
Slide 242
+
V
-
R
+
VL
L
-
Prof. Chang-Hasnain
One may wish to specify the change of a quantity
such as the output voltage of a filter when the
frequency changes by a factor of 2 (an octave) or 10
(a decade).
HR = R / (R + 1/jωC)
EE40 Fall
2006
2
− tan −1
Change of Voltage or Current with
A Change of Frequency
Low Pass
Low
Pass
f
fB
f
1+
fB
VL
L
Slide 241
High Pass
+
–
π
R
R
and f B =
L
2π L
H(f) = H ( f )∠θ
First-Order Filter Circuits
VS
∠
Let ωB =
, θ = − tan −1
EE40 Fall
2006
2
Prof. Chang-Hasnain
For example, a single-stage RC low-pass filter has at
frequencies above ω = 1/RC an output that changes
at the rate -20dB per decade.
EE40 Fall
2006
Slide 244
Prof. Chang-Hasnain
High-frequency asymptote of Lowpass filter
Low-frequency asymptote of Highpass filter
The high frequency asymptote of magnitude
Bode plot assumes -20dB/decade slope
As f → 0
As f → ∞
H( f ) =
H( f ) =
20 log10
f
fB
f
fB
1+
−1
f
fB
2
→
f
fB
f →∞
H (10 f B )
= −20dB
H ( fB )
20 log10
H ( fB )
= 20dB
H (0.1 f B )
The low frequency asymptote of magnitude
Bode plot assumes 20dB/decade slope
Slide 245
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 246
Second-Order Filter Circuits
Series Resonance
VIN
+
VOUT
−
Voltage divider
Band Pass
R
VS
+
–
Z = R + 1/jωC + jωL
Low
Pass
C
High
Pass
L
HBP = R / Z
Resonance quality factor
VOUT
ZR
=
VIN
Z L + Z R + ZC
Q=
Substitute branch elements
VOUT
R
=
VIN
jω L + R + 1 / jω C
Band HLP = (1/jωC) / Z
Reject
HHP = jωL / Z
Arrange in resonance form
VOUT
R
=
VIN
R + j (ωL − 1 / ωC )
HBR = HLP + HHP
Slide 247
Prof. Chang-Hasnain
EE40 Fall
2006
ωL
R
Ratio of reactance to resistance
Closely related to number
of round trip cycles before
1/e decay.
Maximum when w2 = 1/(LC)
EE40 Fall
2006
Prof. Chang-Hasnain
+
EE40 Fall
2006
Slide 248
Bandwidth is f0/Q
Prof. Chang-Hasnain
Chapter 14
Parallel Resonance
• OUTLINE
+
IIN
VOUT
– Op-Amp from 2-Port Blocks
– Op-Amp Model and its Idealization
– Negative Feedback for Stability
– Components around Op-Amp define the
Circuit Function
Admittance
VOUT =
Resonance quality factor
IS
YL + YR + YC
Q=
Substitute branch elements
VOUT
IS
=
1
+ 1 + jwC
j ωL
R
Arrange in resonance form
VOUT =
IS
1 + j (ωC − 1 )
ωL
R
R
Ratio of reactance to resistance
Closely related to number
of round trip cycles before
1/e decay.
Maximum = IS/R when w2 = 1/(LC)
EE40 Fall
2006
ωL
• Reading
– Chap 14
Bandwidth is f0/Q
Slide 249
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 250
Prof. Chang-Hasnain
High Quality Dependent Source In an Amplifier
The Operational Amplifier
• The operational amplifier (“op amp”) is a
basic building block used in analog circuits.
– Its behavior is modeled using a dependent source.
– When combined with resistors, capacitors, and
inductors, it can perform various useful functions:
•
•
•
•
•
•
•
•
amplification/scaling of an input signal
sign changing (inversion) of an input signal
addition of multiple input signals
subtraction of one input signal from another
integration (over time) of an input signal
differentiation (with respect to time) of an input signal
analog filtering
nonlinear functions like exponential, log, sqrt, etc
Differential Amplifier
V+
V−
Slide 251
Prof. Chang-Hasnain
Circuit Model in linear region
V0
Ri
+
−
V1
+
−
AV1
+
−
V0
V0 depends only on input (V+ − V-)
See the utility of this: this Model when used correctly
mimics the behavior of an amplifier but omits the
complication of the many many transistors and other
components.
– Isolate input from output; allow cascading
EE40 Fall
2006
+
A
−
V0 = A( V+ − V− )
EE40 Fall
2006
Slide 252
Prof. Chang-Hasnain
Model for Internal Operation
Op Amp Terminals
• A is differential gain or
open loop gain
• Ideal op amp
A→∞
Ri → ∞
Ro = 0
• 3 signal terminals: 2 inputs and 1 output
• IC op amps have 2 additional terminals for DC
power supplies
• Common-mode signal= (v1+v2)/2
• Differential signal = v1-v2
V+
Inverting input v2
-
Non-inverting input v1
+
vcm =
( v1 + v2 )
Prof. Chang-Hasnain
• Circuit Model
EE40 Fall
2006
Slide 254
• Input impedance: R
looking into the input
terminals
• Output impedance:
Impedance in series with
the output terminals
v1
i1
Slide 255
R1
R2
Ro io
i2
_
vo
+
–
−
+
VIN
R2
V0
Ri
VIN
+
V1
+
AV1
−
+
−
V0
Summing Point
Circuit Model
Negative feedback
A(v1–v2)
Hambley Example pp. 644 for Power Steering
We can show that that for A → ∞ and Ri → ∞,
V 0 ≅ V IN ⋅
EE40 Fall
2006
Prof. Chang-Hasnain
+
Ri
v2
A(v1–v2)
A very high-gain differential amplifier can function in an extremely linear
fashion as an operational amplifier by using negative feedback.
R1
– connecting the output port to
the positive input (port 1)
+
–
_
Op-Amp and Use of Feedback
– connecting the output port to
the negative input (port 2)
• Positive feedback
v2
, vd = v1 − v2
vo
i2
Since vo = A(v1 − v2 ) , Acm = 0
Model and Feedback
• Negative feedback
Ro io
Ri
2
vo = Acm vcm + Ad vd
v0 output
Slide 253
v1
+
i1
– Common mode gain = 0
positive power supply
V – negative power supply
EE40 Fall
2006
• Circuit Model
Prof. Chang-Hasnain
EE40 Fall
2006
R1 + R 2
R1
Slide 256
Prof. Chang-Hasnain
Ideal Op-Amp Analysis Technique
Summing-Point Constraint
• Check if under negative feedback
Applies only when Negative Feedback is present in circuit!
– Small vi result in large vo
– Output vo is connected to the inverting input to reduce
vi
– Resulting in vi=0
Assumption 1: The potential between the op-amp input terminals, v(+) –
v(-), equals zero.
Assumption 2: The currents flowing into the op-amp’s two input
terminals both equal zero.
• Summing-point constraint
– v1= v2
– i1 = i2 =0
No Potential Difference
R2
R1
No Currents
• Virtual short circuit
– Not only voltage drop is 0 (which is short circuit), input
current is 0
– This is different from short circuit, hence called
“virtual” short circuit.
EE40 Fall
2006
Slide 257
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 258
Non-Inverting Amplifier
Closed loop gain = Av =
Assumption 1: The potential between the op-amp input terminals, v(+) –
v(-), equals zero.
+
v2
vin +-
2
KCL with currents in only two branches
R1
R2
v
v −v
−
+
VIN
V0
vout
EXAMPLE
VIN appears here
EE40 Fall
2006
in
out
=0
R2
R + R2
vin
= 1
R1
v0
_
Assumption 2: The currents flowing into the op-amp’s two input
terminals both equal zero.
+
Prof. Chang-Hasnain
• Ideal voltage amplifier
Yes Negative Feedback is present in this circuit!
in
V0
EXAMPLE
Ideal Op-Analysis: Non-Inverting Amplifier
R1
−
+
VIN
v1 = v2 = vin , i1 = i2 = 0
RL
R2
vo
vin
Use KCL At Node 2.
i=
R1
(v0 − v2 ) (v2 − 0)
=
R2
R1
A=
vo ( R1 + R2 )
=
vin
R1
Input impedance =
vin
→∞
i
Non-inverting Amplifier
Slide 259
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 260
Prof. Chang-Hasnain
Ideal Op-Amp Analysis: Inverting Amplifier
R2
R1
I2
RL V OUT
-VR
Voltage is VR
VR − VIN VR − VOUT
+
=0
R1
R2
Only two
currents
for KCL
VOUT = VR −
vin +-
R2
(Vin − VR )
R1
Slide 261
v1
Prof. Chang-Hasnain
(vin − v2 ) (vout − v2 )
=
R1
R2
vo = −
R2 vo
R1
RL
Slide 262
2
i4
_
RL
R
i3
R2 = 0
vin
= R1
i
Prof. Chang-Hasnain
R
i5
R
v2 i 2 _
v1 i 1
v0
+
RL • Switch is open
v1 = v2 , i1 = 0 → i3 = 0
R1 → ∞
(vin − v1 )
→ v1 = v2 = vin → i4 = 0 → i5 = 0
R
(v − v )
i 5 = 0 2 → v0 = v2 = vin
R
vo
= 1 , Rin → ∞
A=
vin
i3 =
(v − v ) (v − 0)
i= 0 2 = 2
R2
R1
EE40 Fall
2006
i=
Example 1
vin +-
A=
Use KCL At Node 2.
Input impedance =
EE40 Fall
2006
v0
+
v2
v1 = v2 = 0 , i1 = i2 = 0
+
Voltage Follower
vin +
-
vo
vin
Ideal voltage source – independent of load resistor
Inverting Amplifier with reference voltage
EE40 Fall
2006
Closed loop gain = Av =
• Negative feedback
checked
• Use summing-point
constraint
R2
2
R1 v
i
2 _
v0
Yes Negative Feedback is present in circuit!
VIN
Inverting Amplifier
vo ( R1 + R2 )
R
=
= 1+ 2 = 1
vin
R1
R1
Slide 263
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 264
Prof. Chang-Hasnain
Example 2
2
i4
R
i3
vin +-
i5
R
v2 i 2 _
R
v1 i 1
v1 = v2 = 0 , i1 = 0 → i3 = 0
v0
+
RL
(v − v )
(v − v )
i4 = in 2 = i 5 = − 0 2
R
R
v0 = −vin
A=
EE40 Fall
2006
• Design an analog front end
circuit to an instrument system vin
– Requires to work with 3 full-scale of
input signals (by manual switch): vb
0 ±1, 0 ±10, 0 ±100 V
va
– For each input range, the output
needs to be 0 ±10 V
– The input resistance is 1MΩ
vo
= −1 , Rin = R
2
vin
Slide 265
Prof. Chang-Hasnain
vo = (1 +
v1 =
Ra + Rb
vin Switch at b
Ra + Rb + Rc
v1 =
Ra
vin Switch at a
Ra + Rb + Rc
EE40 Fall
2006
2
v0
RL
R2
R1
Slide 266
Prof. Chang-Hasnain
Summing Amplifier
v1
R1
+
-
R2
) Switch at c
R1
R0
+
-
Ra + Rb
Ra + Rb
R
(1 + 2 ) Switch at b ∴
= 0.1
Ra + Rb + Rc
R1
Ra + Rb + Rc
v2
R2
_
+
-
Av = 0.1 =
a
v2
v1 = vin Switch at c
Rin = Ra + Rb + Rc = 1M Ω
Av = 1 =
b
v1
R2
)v1
R1
Example 2 (cont’d)
Max Av = 10 = (1 +
c
_
• Switch is closed
+
Example 1
Ra
Ra
R
(1 + 2 ) Switch at a ∴
= 0.01
Ra + Rb + Rc
R1
Ra + Rb + Rc
v3
R3
v0
+
∴ Ra = 10k Ω, Rb = 90k Ω, Rc = 900k Ω
R2 = 9 R1
EE40 Fall
2006
Slide 267
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 268
Prof. Chang-Hasnain
Difference Amplifier
Integrator
• Want v = K v dt
o
in
R2
v1
R1
_
+
EE40 Fall
2006
v0
+
+
v2
• What is the difference
between:
R3
R
+
vin
R4
+
Slide 269
Prof. Chang-Hasnain
V0
C
-
-
EE40 Fall
2006
Slide 270
Differentiator
Prof. Chang-Hasnain
Bridge Amplifier
• Want
vx
R0
R0(1+ε)
_
+
vin -
R
C
_
vin +-
EE40 Fall
2006
Slide 271
+
Ra
vx
v0
v0
Ra
+
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 272
Prof. Chang-Hasnain
Application: Digital-to-Analog Conversion
20K
40K
S2
80K
+
-
S1
4-Bit D/A
(Transistors are used
as electronic switches)
EE40 Fall
2006
5K
+
−
S3
8V
10K
−
+
V0
S1 closed if LSB =1
S2
" if next bit = 1
S3
" if " " = 1
S4
" if MSB = 1
Slide 273
MSB
.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
0000
0
2
0001
Prof. Chang-Hasnain
0100
EE40 Fall
2006
8
10
12
14
16
1111
1000
Digital Input
Slide 274
Prof. Chang-Hasnain
Active Filter Example
• Contain few components
• Transfer function that is insensitive to
component tolerance
• Easily adjusted
• Require a small spread of components
values
• Allow a wide range of useful transfer
functions
Slide 275
6
LSB
Active Filter
EE40 Fall
2006
4
Prof. Chang-Hasnain
C
v3
vin
+
-
R
v1
_
S4
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
8
7
6
5
4
3
2
1
0
+
“Weighted-adder D/A converter”
Analog Output (V)
A DAC can be used to convert the digital representation Binary Analog
number output
of an audio signal into an analog voltage that is then
(volts)
used to drive speakers -- so that you can hear it!
0000
0
Characteristic of 4-Bit DAC
R
v2
v0
(k-1)Rf
C
Rf
EE40 Fall
2006
Slide 276
Prof. Chang-Hasnain
Active Filter Solution
Cascaded Active Filter Example
v
v1 = v 2 = o
k
C
R
+
vin -
Let ω B = 1 / RC
v
H (ω ) = o =
vin
ω2
ωB2
1−
+
R
C
k
2
v1
_
vo
k
=
vin 1 − ω 2 R 2 C 2 + jω RC (3 − k )
+
v3
v2
C2
v3’
v0’
R2
(k-1)Rf
v1’
+
Use KC L At Node B
R
2
C2
Rf
ω2
(3 − k ) 2
ωB2
v2’
_
( v3 − v1 )
= jω C v1
R
( vin − v3 )
( v − v1 )
= jω C ( v 3 − v o ) + 3
R
R
Use KC L At Node A
v0
(k2 -1)Rf
Rf
ω = 0, H (ω ) = k DC gain
k
3−k
k
ω >> ω B , H (ω ) =
2
ω = ω B , H (ω ) =
ω
ωB2
ω −2
20 log H (ω ) decays at a rate of 40 dB / decade
EE40 Fall
2006
Slide 277
Prof. Chang-Hasnain
EE40 Fall
2006
Let ωB = 1/ RC , ωB 2 = 1/ R2C2
H (ω ) =
vo
=
vin
k2
1−
ω2
ωB 2 2
2
+
k
ω2
(3 − k2 ) 2
ωB 2 2
1−
ω2
ωB 2
2
+
ω2
(3 − k ) 2
ωB 2
ω = 0, H (ω ) = k2 k DC gain
ω = ωB , H (ω ) =
k2
k
3 − k2 3 − k
ω >> ωB , H (ω ) =
k2 k
ω4
ωB 2 2ωB 2
Prof. Chang-Hasnain
Chapter 10
Cascaded Active Filter Solution
vo
k2
k
=
vin 1 − ω 2 R2 2C2 2 + jω R2C2 (3 − k2 ) 1 − ω 2 R 2C 2 + jω RC (3 − k )
Slide 278
• OUTLINE
–
–
–
–
–
–
–
Diode Current and Equation
Some Interesting Circuit Applications
Load Line Analysis
Solar Cells, Detectors, Zener Diodes
Circuit Analysis with Diodes
Half-wave Rectifier
Clamps and Voltage Doublers using Capacitors
• Reading
ω
−4
– Hambley 10.1-10.8
– Supplementary Notes Chapter 2
20 log H (ω ) decays at a rate of 80dB / decade
EE40 Fall
2006
Slide 279
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 280
Prof. Chang-Hasnain
I-V Characteristics
Diode Physical Behavior and Equation
I
In forward bias (+ on p-side) we
have almost unlimited flow
(very low resistance).
Qualitatively, the I-V
characteristics must look like:
Schematic Device
current increases
rapidly with V
Symbol
N
P
type type
VF
I
− V+
− V+
Quantitative I-V characteristics:
Qualitative I-V characteristics:
I V positive,
easy
conduction
I
In reverse bias (+ on n-side)
almost no current can flow.
Qualitatively, the I-V
characteristics must look like: The current is close
to zero for any
negative bias
I
I = I 0 (e qV kT − 1)
In which kT/q is 0.026V and IO is a
constant depending on diode area.
Typical values: 10-12 to 10-16 A.
Interestingly, the graph of this
equation looks just like the figure to
the left.
V
VF
V negative,
no
conduction
A non-ideality factor n times kT/q is often included.
EE40 Fall
2006
Slide 281
Prof. Chang-Hasnain
EE40 Fall
2006
The equation I = I 0 exp(qV kT − 1)
I-V characteristic of PN junctions
In EECS 105, 130, and other courses you will learn why the I vs. V
relationship for PN junctions is of the form
If we can ignore the small forwardbias voltage drop of a diode, a
simple effective model is the
“perfect rectifier,” whose I-V
characteristic is given below:
10
Current
in mA 8
6
4
where I0 is a constant proportional to junction area and depending
on doping in P and N regions, q = electronic charge = 1.6 × 10 −19 ,
k is Boltzman constant, and T is absolute temperature.
KT q = 0.026V at300°K , a typical value for I0 is 10 −12 − 10 −15 A
We note that in forward bias, I increases exponentially and is in
the µA-mA range for voltages typically in the range of 0.6-0.8V.
In reverse bias, the current is essentially zero.
Prof. Chang-Hasnain
Simple “Perfect Rectifier” Model
is graphed below for I 0 = 10 −15 A
I = I 0 (eqV kT − 1)
Slide 283
Prof. Chang-Hasnain
Diode Ideal (Perfect Rectifier) Model
The pn Junction I vs. V Equation
EE40 Fall
2006
Slide 282
2
Forward
Voltage in V
I
0
-5
0
5
10
The characteristic is described as
a “rectifier” – that is, a device that
permits current to pass in only one
direction. (The hydraulic analog is
a “check value”.) Hence the
symbol:
I
EE40 Fall
2006
− V+
Slide 284
Reverse bias
I ≅ 0, any V < 0
Forward bias
V ≅ 0, any I > 0
V
A perfect rectifier
Prof. Chang-Hasnain
- 0.7+
400
(microamp)
Current
Diode Large-Signal Model (0.7 V Drop)
Rectifier Circuit
Assume the ideal
(perfect rectifier)
model.
I
300
200
100
− V+
0
-5
-3
-1
forward bias (V)
1
The Large-Signal
Diode Model
VS(t)
+
VS(t) +
−
VR(t)
−
I
Improved “Large-Signal Diode” Model:
If we choose not to ignore the small
Forward bias
Reverse bias
forward-bias voltage drop of a
V ≅ 0.7, any I > 0
I ≅ 0, any V < 0
diode, it is a very good
V
approximation to regard the voltage
0.7
drop in forward bias as a constant,
about 0.7V. the “Large signal
model” results.
t
VR(t)
“rectified” version of
input waveform
t
EE40 Fall
2006
Slide 285
Prof. Chang-Hasnain
EE40 Fall
2006
• As the reverse bias voltage increases, the peak electric
field in the depletion region increases. When the electric
field exceeds a critical value (Ecrit ≅ 2x105 V/cm), the
reverse current shows a dramatic increase:
Assume the ideal (perfect rectifier) model.
Vi(t)
+
Vi(t) −
−
C
+
Vi
VC(t)
reverse (leakage) current
−
EE40 Fall
2006
ID (A)
forward current
t
Key Point:
The capacitor charges
due to one way current
behavior of the diode.
Prof. Chang-Hasnain
pn-Junction Reverse Breakdown
Peak Detector Circuit
+
Slide 286
VC(t)
Slide 287
breakdown voltage
VBD
VD (V)
VC
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 288
Prof. Chang-Hasnain
Zener Diode
Load Line Analysis Method
A Zener diode is designed to operate in the breakdown mode.
1. Graph the I-V relationships for the non-linear
element and for the rest of the circuit
2. The operating point of the circuit is found from
the intersection of these two curves.
reverse (leakage) current
breakdown voltage
VBD
ID (A)
forward
current
VD (V)
I
RTh I
VTh/RTh
+
Example:
R
+
vs(t)
– VBD = 15V
t
VTh
+
−
operating point
V
V
–
+
integrated
vo(t) circuit
–
VTh
$
*
,
EE40 Fall
2006
Slide 289
Prof. Chang-Hasnain
EE40 Fall
2006
Solar cell: Example of simple PN junction
Slide 290
Photovoltaic (Solar) Cell
• What is a solar cell?
I D = I S (e qVD
– Device that converts
sunlight into electricity
– In simple configuration, it is a
diode made of PN junction
– Incident light is absorbed by
material
– Creates electron-hole pairs that
transport through the material
through
EE40 Fall
2006
Slide 291
kT
− 1) − I optical
ID (A)
• How does it work?
• Diffusion (concentration gradient)
• Drift (due to electric field)
Prof. Chang-Hasnain
in the dark
VD (V)
with incident light
Operating point
The load line a simple resistor.
PN Junction Diode
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 292
Prof. Chang-Hasnain
I-V characteristics of the device
Example 2: Photodiode
• An intrinsic region is placed
between the p-type and n-type
regions
• I-V characteristics of a PN
junction is given by
I = I S exp(
eV
) −1 − I L
kT
Voc
where Is is the saturation intensity
depending on band gap and doping
of the material and IL is the
photocurrent generated due to light
Isc
Wj ≅ Wi-region, so that most of the
electron-hole pairs are generated
in the depletion region
(Vm, Im)
faster response time
(~10 GHz operation)
ID (A)
• Efficiency is defined as
η=
I m .Vm
FF *Voc * I sc
=
Light Intensity Light Intensity
Isc - Short circuit current
Imp , Vmp- Current and voltage
FF is the Fill Factor
in the dark
Voc - Open circuit voltage
VD (V)
operating point
at maximum power
with incident light
EE40 Fall
2006
Slide 293
Prof. Chang-Hasnain
EE40 Fall
2006
Photodetector Circuit Using Load Line
I
RTh I
+
−
VTh
operating
points under
different light
conditions.
+
V
–
As light shines on the photodiode, carriers
are generated by absorption. These excess V
Th
carriers are swept by the electric field at the
junction creating drift current, which is same
direction as the reverse bias current and
hence negative current. The current is
proportional to light intensity and hence can
provide a direct measurement of light
intensity
photodetector.
As light
intensity
increases.
Why?
Circuit symbol
ID
+
I-V characteristic
VD
–
Slide 295
Switch model
ID
ID (A)
+
VD
–
forward bias
reverse bias
VD (V)
• An ideal diode passes current only in one direction.
• An ideal diode has the following properties:
• when ID > 0, VD = 0
-
.
&
• when VD < 0, ID = 0
.
&
- What happens when Rth is too large?
- Why use Vth?
EE40 Fall
2006
Prof. Chang-Hasnain
Ideal Diode Model of PN Diode
V
VTh/RTh
Slide 294
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 296
.
Prof. Chang-Hasnain
Large-Signal Diode Model
Circuit symbol
ID
+
I-V characteristic
Switch model
ID
+
ID (A)
+
−
VD
–
Diode: Large Signal Model
VDon
VD
forward bias
reverse bias
• Use piece-wise linear model
–
VD (V)
VDon
0 VDon ≅ "1 2
/
RULE 1: When ID > 0, VD = VDon
-
.
&
&
RULE 2: When VD < VDon, ID = 0
.
&
EE40 Fall
2006
!
Slide 297
.
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 298
How to Analyze Circuits with Diodes
A diode has only two states:
• forward biased: ID > 0, VD = 0 V (or 0.7 V)
Diode Logic: AND Gate
• Diodes can be used to perform logic functions:
AND gate
• reverse biased: ID = 0, VD < 0 V (or 0.7 V)
&
.
Procedure:
1. Guess the state(s) of the diode(s)
2. Check to see if KCL and KVL are obeyed.
3. If KCL and KVL are not obeyed, refine your guess
4. Repeat steps 1-3 until KCL and KVL are obeyed.
A
Example:
B
vs(t)
EE40 Fall
2006
+
−
+
vR(t)
–
Prof. Chang-Hasnain
If vs(t) > 0 V, diode is forward biased
(else KVL is disobeyed – try it)
!
)
!
3
Inputs A and B vary between 0
Volts (“low”) and Vcc (“high”)
Between what voltage levels
does C vary?
!
Vcc
RAND
VOUT
5
C
EOC
Slope =1
Shift 0.7V Up
0
If vs(t) < 0 V, diode is reverse biased
(else KVL is disobeyed – try it)
Slide 299
Prof. Chang-Hasnain
0
EE40 Fall
2006
Slide 300
5
VIN
Prof. Chang-Hasnain
Diode Logic: OR Gate
Diode Logic: Incompatibility and Decay
• Diodes can be used to perform logic functions:
• Diode Only Gates are Basically Incompatible:
OR gate
&
Inputs A and B vary between 0
Volts (“low”) and Vcc (“high”)
Between what voltage levels
does C vary?
.
!
#)
!
3
&
!
.
)
!
3
&
!
.
A
!
#)
!
3
!
A
B
5
RAND
C
ROR
EOC
A
B
COR
CAND
B
Slope =1
Shift 0.7V Down
ROR
CAND High want RAND >> ROR
CAND Low want RAND << ROR
0
5
!
Vcc
VOUT
0 0.7V
OR gate
AND gate
VIN
Signal Decays with each stage (Not regenerative)
EE40 Fall
2006
Slide 301
Prof. Chang-Hasnain
Device Isolation using pn Junctions
regions of n-type Si
n
n
n
n
Slide 302
Prof. Chang-Hasnain
Why are pn Junctions Important for ICs?
• The basic building block in digital ICs is the
MOS transistor, whose structure contains
reverse-biased diodes.
n
– pn junctions are important for electrical isolation of
transistors located next to each other at the
surface of a Si wafer.
p-type Si
No current flows if voltages are applied between n-type
regions, because two pn junctions are “back-to-back”
n-region
EE40 Fall
2006
n-region
– The junction capacitance of these diodes can limit
the performance (operating speed) of digital
circuits
p-region
=> n-type regions isolated in p-type substrate and vice versa
EE40 Fall
2006
Slide 303
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 304
Prof. Chang-Hasnain
Power Conversion Circuits
Rectifier Equivalent circuit
• Converting AC to DC
• Potential applications: Charging a battery
R
VI=Vm sin (ωt)
EE40 Fall
2006
V>0.6V, diode = short circuit
Vo=VI-0.6
V<0.6V, diode = open circuit
Vo=0
Vo
Slide 305
Prof. Chang-Hasnain
EE40 Fall
2006
Half-wave Rectifier Circuits
Slide 306
Prof. Chang-Hasnain
Half-Wave Rectifier
• Adding a capacitor: what does it do?
+
Vm sin (ωt)
C
R
V0
Current
charging
up
capacitor
EE40 Fall
2006
Slide 307
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 308
Prof. Chang-Hasnain
Voltage Doubler Circuit
Level Shift Circuit
- VC1 +
+
+
C1
R1
VIN
-
-
+
VIN
VOUT
VOUT
VOUT
-
-
t
R1
Level Shift
VIN
C2
+ VC21 -
C1
VIN
+
+
+
- VC1 +
R2
VOUT
-
-
Peak Detect
t
The final output is the peak to peak voltage of the input.
Once the capacitor is charged by the negative most voltage
the rest of the signal is shifted up by that amount.
EE40 Fall
2006
Slide 309
Prof. Chang-Hasnain
Week 12
• Reading
– Supplementary Notes Chap 3
Slide 311
Prof. Chang-Hasnain
• Solids with “free electrons” – that is electrons not
directly involved in the inter-atomic bonding- are
the familiar metals (Cu, Al, Fe, Au, etc).
• Solids with no free electrons are the familiar
insulators (glass, quartz crystals, ceramics, etc.)
• Silicon is an insulator, but at higher
temperatures some of the bonding electrons can
get free and make it a little conducting – hence
the term “semiconductor”
• Pure silicon is a poor conductor (and a poor
insulator). It has 4 valence electrons, all of
which are needed to bond with nearest
neighbors. No free electrons.
Basic Semiconductor Materials
n and p doping
Bandgap
Gauss’s Law
Poisson Equation
Depletion approximation
Diode I-V characteristics
Lasers and LEDs
Solar Cells
EE40 Fall
2006
Slide 310
Conductors, Insulators and Semiconductors
• OUTLINE
–
–
–
–
–
–
–
–
–
EE40 Fall
2006
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 312
Prof. Chang-Hasnain
The Periodic Table
Electronic Bonds in Silicon
III IV V
2-D picture of perfect crystal of pure silicon; double line is a Si-Si
bond with each line representing an electron
Si ion
(charge
+4 q)
Two electrons in each bond
Actual structure is 3-dimensional tetrahedral- just like carbon
bonding in organic and inorganic materials.
Essentially no free electrons, and no conduction - insulator
EE40 Fall
2006
Slide 313
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 314
Prof. Chang-Hasnain
Doping Silicon with Donors (n-type)
How to get conduction in Si?
Donors donate mobile electrons (and thus “n-type” silicon)
We must either:
1) Chemically modify the Si to produce free carriers (permanent) or
Example: add arsenic (As) to the silicon crystal:
2) Electrically “induce” them by the field effect (switchable)
For the first approach controlled impurities, “dopants”, are added to
Si:
Add group V elements (5 bonding electrons vs four for Si),
such as phosphorus or arsenic
(Extra electrons produce “free electrons” for conduction.)
Mobile electron
donated by As ion
As
or
Add group III elements (3 bonding electrons), such as boron
Immobile (stuck) positively charged arsenic ion after 5th electron left
Deficiency of electrons results in “free holes”
The extra electron with As, “breaks free” and becomes a free
electron for conduction
EE40 Fall
2006
Slide 315
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 316
Prof. Chang-Hasnain
Doping with Acceptors (p-type)
Group III element (boron, typically) is added to the crystal
Immobile (stuck) negative boron ion after accepting electron from neighboring bond
Mobile hole contributed by B ion
and later path
Doping
• Typical doping densities:
1016~1019 cm-3
• Atomic density for Si: 5 x
1022 atoms/cm3
• 1018 cm-3 is 1 in 50,000
– two persons in entire
Berkeley wearing a green
hat
B
• P-n junction effect is like
The “hole” which is a missing bonding electron, breaks free from
the B acceptor and becomes a roaming positive charge, free to
carry current in the semiconductor. It is positively charged.
EE40 Fall
2006
Slide 317
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 318
Prof. Chang-Hasnain
Shockley’s Parking Garage Analogy for Conduction in Si
Shockley’s Parking Garage Analogy for Conduction in Si
Two-story parking garage on a hill:
Two-story parking garage on a hill:
If the lower floor is full and top one is empty, no traffic is
possible. Analog of an insulator. All electrons are
locked up.
EE40 Fall
2006
Slide 319
Prof. Chang-Hasnain
If one car is moved upstairs, it can move AND THE HOLE
ON THE LOWER FLOOR CAN MOVE. Conduction is
possible. Analog to warmed-up semiconductor. Some
electrons get free (and leave “holes” behind).
EE40 Fall
2006
Slide 320
Prof. Chang-Hasnain
Shockley’s Parking Garage Analogy for Conduction in Si
Shockley’s Parking Garage Analogy for Conduction in Si
Two-story parking garage on a hill:
Two-story parking garage on a hill:
If an extra car is “donated” to the upper floor, it can move.
Conduction is possible. Analog to N-type semiconductor.
(An electron donor is added to the crystal, creating free
electrons).
EE40 Fall
2006
Slide 321
Prof. Chang-Hasnain
Summary of n- and p-type silicon
Pure silicon is an insulator. At high temperatures it conducts
weakly.
If we add an impurity with extra electrons (e.g. arsenic,
phosphorus) these extra electrons are set free and we have a
pretty good conductor (n-type silicon).
If a car is removed from the lower floor, it leaves a HOLE
which can move. Conduction is possible. Analog to P-type
semiconductor. (Acceptors are added to the crystal,
“consuming” bonding electrons,creating free holes).
EE40 Fall
2006
EE40 Fall
2006
Slide 323
Prof. Chang-Hasnain
Prof. Chang-Hasnain
Junctions of n- and p-type Regions
p-n junctions form the essential basis of all semiconductor devices.
A silicon chip may have 108 to 109 p-n junctions today.
How do they behave*? What happens to the electrons and holes?
What is the electrical circuit model for such junctions?
n and p regions are brought into contact :
If we add an impurity with a deficit of electrons (e.g. boron) then
bonding electrons are missing (holes), and the resulting holes
can move around … again a pretty good conductor (p-type
silicon)
Now what is really interesting is when we join n-type and p-type
silicon, that is make a pn junction. It has interesting electrical
properties.
Slide 322
aluminum
aluminum
?
wire
n
p
*Note that the textbook has a very good explanation.
EE40 Fall
2006
Slide 324
Prof. Chang-Hasnain
The pn Junction Diode
Schematic diagram
p-type
Depletion Region Approximation
• When the junction is first formed, mobile carriers diffuse
across the junction (due to the concentration gradients)
Circuit symbol
ID
n-type
+
VD
– Holes diffuse from the p side to the n side,
leaving behind negatively charged immobile acceptor
ions
– Electrons diffuse from the n side to the p side,
leaving behind positively charged immobile donor ions
–
,
Physical structure:
(an example)
acceptor ions
ID
+
metal
SiO2
/
VD
0
!
.
4
EE40 Fall
2006
!
"
SiO2
n
• The space charge due to immobile ions in the depletion region
establishes an electric field that opposes carrier diffusion.
metal
Slide 325
+
+
+
+
+
A region depleted of mobile carriers is formed at the junction.
n-type Si
–
–
–
–
–
–
p
p-type Si
donor ions
Prof. Chang-Hasnain
EE40 Fall
2006
Summary: pn-Junction Diode I-V
Slide 326
Prof. Chang-Hasnain
Charge Density Distribution
• Under forward bias, the potential barrier is reduced, so
that carriers flow (by diffusion) across the junction
Charge is stored in the depletion region.
acceptor ions
– Current increases exponentially with increasing forward bias
– The carriers become minority carriers once they cross the
junction; as they diffuse in the quasi-neutral regions, they
recombine with majority carriers (supplied by the metal contacts)
p
donor ions
–
–
–
–
–
+
+
+
+
+
n
“injection” of minority carriers
• Under reverse bias, the potential barrier is increased, so
that negligible carriers flow across the junction
quasi-neutral p region
depletion region
quasi-neutral n region
charge density (C/cm3)
– If a minority carrier enters the depletion region (by thermal
generation or diffusion from the quasi-neutral regions), it will be
swept across the junction by the built-in electric field
ID (A)
“collection” of minority carriers
reverse current
distance
VD (V)
EE40 Fall
2006
Slide 327
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 328
Prof. Chang-Hasnain
Effect of Applied Voltage
p
VD
–
–
–
–
–
+
+
+
+
+
Forward Bias
• As VD increases, the potential barrier to carrier
diffusion across the junction decreases*, and
current increases exponentially.
n
VD > 0
• The quasi-neutral p and n regions have low resistivity,
whereas the depletion region has high resistivity. Thus,
when an external voltage VD is applied across the diode,
almost all of this voltage is dropped across the depletion
region. (Think of a voltage divider circuit.)
• If VD > 0 (forward bias), the potential barrier to carrier
diffusion is reduced by the applied voltage.
• If VD < 0 (reverse bias), the potential barrier to carrier
diffusion is increased by the applied voltage.
EE40 Fall
2006
Slide 329
p
–
–
–
–
–
+
+
+
+
+
$
4
n
'
.
,
!
.
4
!
ID (Amperes)
5
0
"
VD (Volts)
* Hence, the width of the depletion region decreases.
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 330
Prof. Chang-Hasnain
Reverse Bias
Optoelectronic Diodes
• As |VD| increases, the potential barrier to carrier
diffusion across the junction increases*; thus, no
carriers diffuse across the junction.
• Light incident on a pn junction generates electron-hole pairs
VD < 0
p
–
–
–
–
–
+
+
+
+
+
)&
'
,
!
!
!
ID (Amperes)
4
VD (Volts)
* Hence, the width of the depletion region increases.
EE40 Fall
2006
Slide 331
• The carriers that are generated in the quasi-neutral regions
diffuse into the depletion region, together with the carriers
generated in the depletion region, are swept across the
junction by the electric field
&
0
!
6 #
n
• Carriers are generated in the depletion region as well as ndoped and p-doped quasi-neutral regions.
Prof. Chang-Hasnain
"
• This results in an additional component of current flowing in
the diode:
qVD kT
I D = I S (e
− 1) − I optical
where Ioptical is proportional to the intensity of the light
EE40 Fall
2006
Slide 332
Prof. Chang-Hasnain
Example: Photodiode
Planck Constant
• An intrinsic region is placed
between the p-type and n-type
regions
Wj ≅ Wi-region, so that most of the
electron-hole pairs are generated
in the depletion region
faster response time
(~10 GHz operation)
ID (A)
in the dark
VD (V)
operating point
with incident light
EE40 Fall
2006
Slide 333
Prof. Chang-Hasnain
Planck’s constant h = 6.625·10-34 J·s
E=hν=hc/λ
C is speed of light and hν is photon energy
The first type of quantum effect is the quantization of
certain physical quantities.
• Quantization first arose in the mathematical formulae of
Max Planck in 1900. Max Planck was analyzing how the
radiation emitted from a body was related to its
temperature, in other words, he was analyzing the
energy of a wave.
• The energy of a wave could not be infinite, so Planck
used the property of the wave we designate as the
frequency to define energy. Max Planck discovered a
constant that when multiplied by the frequency of any
wave gives the energy of the wave. This constant is
referred to by the letter h in mathematical formulae. It is
a cornerstone of physics.
•
•
•
•
EE40 Fall
2006
Slide 334
Prof. Chang-Hasnain
Chapter 12 MOSFET
Bandgap Versus Lattice Constant
• OUTLINE
–
–
–
–
–
–
–
–
–
–
Si
The MOSFET as a controlled resistor
Pinch-off and current saturation
MOSFET ID vs. VGS characteristic
NMOS and PMOS I-V characteristics
Load-line analysis; Q operating point; Bias circuits
Small-signal equivalent circuits
Common source amplifier
Source follower
Common gate amplifier
Gain
• Reading
– Supplementary Notes Chapter 4
– Hambley: Chapter 12.1-12.5
EE40 Fall
2006
Slide 335
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 336
Prof. Chang-Hasnain
MOSFET Structure
MOSFET Terminals
• The voltage applied to the GATE terminal determines whether
current can flow between the SOURCE & DRAIN terminals.
“Metal”
– For an n-channel MOSFET, the SOURCE is biased at a lower
potential (often 0 V) than the DRAIN
“Oxide”
DEVICE IN CROSS-SECTION
“Semiconductor”
G
“Metal” gate (Al or Si)
D
S
(Electrons flow from SOURCE to DRAIN when VG > VT)
gate
oxide insulator
– For a p-channel MOSFET, the SOURCE is biased at a higher
potential (often the supply voltage VDD) than the DRAIN
n
(Holes flow from SOURCE to DRAIN when VG < VT )
n
P
• The BODY terminal is usually connected to a fixed potential.
– For an n-channel MOSFET, the BODY is connected to 0 V
– For a p-channel MOSFET, the BODY is connected to VDD
• In the absence of gate voltage, no current can flow between S and D.
• Above a certain gate to source voltage Vt (the “threshold”), electrons are
induced at the surface beneath the oxide. (Think of it as a capacitor.)
• These electrons can carry current between S and D if a voltage is applied.
EE40 Fall
2006
Slide 337
Prof. Chang-Hasnain
EE40 Fall
2006
MOSFET
– Upper case for both (e.g. VD) = DC signal (often as bias)
– Lower case for both (e.g. vd) = AC signal (often small signal)
– Lower symbol and upper sub (e.g. vD ) = total signal = VD+vd
• NMOS: Three regions of operation
– VDS and VGS normally positive valus
– VGS<Vt :cut off mode, IDS=0 for any VDS
– VGS>Vt :transistor is turned on
iD = K 2(vGS − Vt )vDS − vDS 2
• VDS< VGS-Vt: Triode Region
2
• VDS> VGS-Vt: Saturation Region iD = K 2(vGS − Vt )
W KP
• Boundary v − V = v
EE40 Fall
2006
t
DS
Slide 339
Prof. Chang-Hasnain
MOSFET
• Symbol and subscript convention
GS
Slide 338
K=
• PMOS: Three regions of operation (interchange
> and < from NMOS)
– VDS and VGS Normally negative values
– VGS>Vt :cut off mode, IDS=0 for any VDS
– VGS<Vt :transistor is turned on
iD = K 2(vGS − Vt )vDS − vDS 2
• VDS> VGS-Vt: Triode Region
• VDS< VGS-Vt: Saturation Region iD = K 2(vGS − Vt ) 2
• Boundary vGS − Vt = vDS
W KP
K=
L 2
L 2
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 340
Prof. Chang-Hasnain
Bias Circuits
MOSFET Operating Regions
• Use load line to find Quiescent operating point.
• Remember no current flow through the gate.
NMOS
Cut-off
Saturation
0
Triode
vDS + Vto
Vto
Fixed-plus Self-Bias CKT
VDD
VDD
vGS
RD
RD
R1
PMOS
VG+vin
Triode
Saturation
vDS + Vto
EE40 Fall
2006
Cut-off
Vto
0
Slide 341
vGS
R2
Prof. Chang-Hasnain
EE40 Fall
2006
MOSFET Circuit
Slide 342
Prof. Chang-Hasnain
Common Source Amplifier
• First look at DC case to find Q point
VDD
– Use load line technique
– All capacitors are open circuit
– From Q-point, get gm and rd for small signal
AC model
RD
C
– DC source is AC ground (because there is no
AC signal variation).
– All capacitors are short circuit (unless
otherwise specified).
Slide 343
Prof. Chang-Hasnain
C
R1
• AC Small signal analysis
EE40 Fall
2006
RS
+
v(t)
-
EE40 Fall
2006
+
vin
-
RL
VG
R2
Slide 344
RS
+
vo
-
C
Prof. Chang-Hasnain
Step 1: find Q point
VG = VDD
R2
R1 + R2
Load line
VDD
VGS = VG − I D RS
VDD = I D ( RD + RS ) + VDS
RD
C
R1
C
+
vin
-
+
v(t)
-
VG
R2
VDS
RL
+
vo
-
C
RS
From load lines, we get ID
EE40 Fall
2006
Slide 345
Prof. Chang-Hasnain
EE40 Fall
2006
and hence gm and rd
Slide 346
Small Signal Model
Prof. Chang-Hasnain
Source Follower
VDD
RR
vo = L D (− g m vgs )
RL + RD
v
RR
Av = o = − g m L D
vin
RL + RD
Rin =
EE40 Fall
2006
R1
For output impedance Rout:
1. Turn off all independent
sources.
2. Take away load
impedance RL
vg = vin , vs = 0 → vgs = vin
C
+
v(t)
-
vin = 0, vgs = 0, g m vgs = 0
vin
RR
= 1 2
iin R1 + R2
Rout =
Slide 347
+
vin
-
VG
R2
C
RS
RL
+
vo
-
rd RD
rd + RD
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 348
Prof. Chang-Hasnain
Step 1: find Q point
VG = VDD
R2
R1 + R2
Load line
VDD
VGS = VG − I D RS
VDD = I D RS + VDS
R1
C
+
vin
-
+
v(t)
-
VG
R2
C
RS
RL
+
vo
-
From load lines, we get ID
EE40 Fall
2006
Slide 349
Prof. Chang-Hasnain
EE40 Fall
2006
Small Signal Model
and hence gm and rd
Slide 350
Prof. Chang-Hasnain
Common Gate Amplifier
VDD
RD
RL′ =
rd −1 + RS −1 + RL −1
vo = g m vgs RL′
For output impedance Rout:
1. Turn off all independent sources.
2. Take away RL
3. Add Vx and find ix
vin = vgs (1 + g m RL′ )
vx = vs , vg = 0, vgs = −vx
v
g m RL′
Av = o =
vin 1 + g m RL′
rR
v
Rs′ = d s , ix = x − g m (−vx ) = vx Rs′−1 + g m
rd + Rs
Rs′
vgs = vin − vo
Rin =
EE40 Fall
2006
C
1
vin
RR
= 1 2
iin R1 + R2
(
Rout =
Slide 351
RL
VG
+
v(t)
-
)
+
vo
-
+ C
vin
RS
-
1
-VSS
g m + rd −1 + Rs −1
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 352
Prof. Chang-Hasnain
Step 1: find Q point
Load line
VDD
VGS = 0 − I D RS + VSS
VDD + VSS = I D ( RD + RS ) + VDS
RD
C
RL
VG
+
v(t)
-
+
vo
-
The only difference in all three circuits are
the intercepts at the axes.
Again from load lines, we get ID and
hence gm and rd
+ C
vin
RS
-VSS
EE40 Fall
2006
Slide 353
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 354
Prof. Chang-Hasnain
Week 15
Small Signal Model
• OUTLINE
RL′ =
1
RL −1 + RD −1
vgs = −vin
vo = − g m vgs RL′
Av =
vo
= g m RL′
vin
iin = −( g m vgs +
Rin =
EE40 Fall
2006
vgs
Rs
)
For output impedance Rout:
1. Turn off all independent sources.
2. Take away RL
3. Add Vx and find ix
RRs
R′ =
R + Rs
v
ix = x + g m vgs
RD
vgs = − g m vgs R′ , but g m R′ ≠ 1∴ vgs = 0
vin
1
=
iin g m + Rs −1
– Need for Input Controlled Pull-Up
– CMOS Inverter Analysis
– CMOS Voltage Transfer Characteristic
– Combinatorial logic circuits
– Logic
– Binary representations
– Combinatorial logic circuits
• Reading
– Chap 7-7.5
– Supplementary Notes Chapter 4
Rout = RD
Slide 355
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 356
Prof. Chang-Hasnain
Digital Circuits – Introduction
• Analog: signal amplitude is continuous with time.
• Digital: signal amplitude is represented by a restricted
set of discrete numbers.
– Binary: only two values are allowed to represent the signal: High
or low (i.e. logic 1 or 0).
• Digital word:
Analog vs. Digital Signals
• Most (but not all) observables are analog
think of analog vs. digital watches
but the most convenient way to represent & transmit
information electronically is to use digital signals
think of telephony
– Each binary digit is called a bit
– A series of bits form a word
• Byte is a word consisting of 8-bits
• Advantages of digital signal
– Digital signal is more resilient to noise
differentiate high (1) and low (0)
Analog-to-digital (A/D) & digital-to-analog (D/A)
conversion is essential (and nothing new)
think of a piano keyboard
can more easily
• Transmission
– Parallel transmission over a bus containing n wires.
• Faster but short distance (internal to a computer or chip)
– Serial transmission (transmit bits sequentially)
• Longer distance
EE40 Fall
2006
Slide 357
Prof. Chang-Hasnain
EE40 Fall
2006
Analog Signal Example: Microphone Voltage
Voltage with normal piano key stroke
Prof. Chang-Hasnain
Digital Signal Representations
Voltage with soft pedal applied
50 microvolt 440 Hz signal
25 microvolt 440 Hz signal
60
V in microvolts
V in microvolts
Slide 358
40
20
0
-20 0 1 2 3 4 5 6 7 8 9 10 11 12
-40
We generally have to agree on some sort of “code”, and
the dynamic range of the signal in order to know the form
and the number of binary digits (“bits”) required.
60
40
20
0
-20 0 1 2
3 4 5 6 7
8 9 10 11 12
-40
-60
Binary numbers can be used to represent any quantity.
Example 1: Voltage signal with maximum value 2 Volts
-60
t in milliseconds
t in milliseconds
• Binary two (10) could represent a 2 Volt signal.
V in microvolts
50 microvolt 220 Hz signal
• To encode the signal to an accuracy of 1 part in 64
(1.5% precision), 6 binary digits (“bits”) are needed
60
40
20
0
-20 0
1
2
3
4
5
6
7
8
9 10 11 12
Analog signal representing piano key A,
below middle C (220 Hz)
-40
-60
Example 2: Sine wave signal of known frequency and
maximum amplitude 50 µV; 1 µV “resolution” needed.
t in milliseconds
EE40 Fall
2006
Slide 359
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 360
Prof. Chang-Hasnain
Decimal Numbers: Base 10
Numbers: positional notation
Digits: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
• Number Base B
Example:
3271 = (3x103) + (2x102) + (7x101) + (1x100)
• Number representation:
This is a four-digit number. The left hand
most number (3 in this example) is often
referred as the most significant number
and the right most the least significant
number (1 in this example).
EE40 Fall
2006
Slide 361
Prof. Chang-Hasnain
B symbols per digit:
–Base 10 (Decimal):
–Base 2 (Binary):
0, 1, 2, 3, 4, 5, 6, 7, 8, 9
0, 1
–d31d30 ... d1d0 is a 32 digit number
–value = d31 × B31 + d30 × B30 + ... + d1 × B1 + d0 × B0
• Binary:
0,1 (In binary digits called “bits”)
= 1×24 + 1×23 + 0×22 + 1×21 + 0×20
= 16 + 8 + 2
= 26
–Here 5 digit binary # turns into a 2 digit decimal #
11010
EE40 Fall
2006
Slide 362
Prof. Chang-Hasnain
Hexadecimal Numbers: Base 16
Digital Signal Representations
• Hexadecimal:
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F
Binary numbers can be used to represent any quantity.
–Normal digits + 6 more from the alphabet
• Conversion: Binary⇔
⇔Hex
–1 hex digit represents 16 decimal values
–4 binary digits represent 16 decimal values
1 hex digit replaces 4 binary digits
We generally have to agree on some sort of “code”, and
the dynamic range of the signal in order to know the form
and the number of binary digits (“bits”) required.
Example 1: Voltage signal with maximum value 2 V and
minimum of 0 V.
• Binary two (10) could represent a 2 Volt signal.
• To encode the signal to an accuracy of 1 part in 64
(1.5% precision), 6 binary digits (“bits”) are needed
Example 2: Sine wave signal of known frequency and
maximum amplitude 50 µV; 1 µV “resolution” needed.
EE40 Fall
2006
Slide 363
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 364
Prof. Chang-Hasnain
Resolution
Decimal-Binary Conversion
• The size of the smallest element that can
be separated from neighboring elements.
The term is used to describe imaging
systems, the frequency separation
achieved by spectrometers, and so on.
• Decimal to Binary
– Repeated Division By 2
• Consider the number 2671.
– Subtraction – if you know your 2N values by
heart.
• Binary to Decimal conversion
1100012 = 1x25 +1x24 +0x23 +0x22 + 0x21 + 1x20
= 3210 + 1610 + 110
= 4910
= 4x101 + 9x100
EE40 Fall
2006
Slide 365
Prof. Chang-Hasnain
EE40 Fall
2006
Example 2 (continued)
EE40 Fall
2006
Digital representation:
Binary number
000001
000010
000011
000100
000101
8
001000
16
010000
32
100000
50
110010
63
111111
Slide 367
Prof. Chang-Hasnain
Binary Representation
Possible digital representation for the sine wave signal:
Analog representation:
Amplitude in µV
1
2
3
4
5
Slide 366
• N bit can represent 2N values: typically
from 0 to 2N-1
– 3-bit word can represent 8 values: e.g. 0, 1, 2,
3, 4, 5, 6, 7
• Conversion
– Integer to binary
– Fraction to binary (13.510=1101.12 and
0.39210=0.0110012)
• Octal and hexadecimal
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 368
Prof. Chang-Hasnain
Boolean algebras
• Algebraic structures
• Logic gates
– Combine several logic variable inputs to
produce a logic variable output
• Memory
– Memoryless: output at a given instant
depends the input values of that instant.
– Momory: output depends on previous and
present input values.
EE40 Fall
2006
Slide 369
Prof. Chang-Hasnain
– "capture the essence" of the logical operations AND,
OR and NOT
– corresponding set for theoretic operations
intersection, union and complement
– named after George Boole, an English mathematician
at University College Cork, who first defined them as
part of a system of logic in the mid 19th century.
– Boolean algebra was an attempt to use algebraic
techniques to deal with expressions in the
propositional calculus.
– Today, Boolean algebras find many applications in
electronic design. They were first applied to switching
by Claude Shannon in the 20th century.
EE40 Fall
2006
Slide 370
Prof. Chang-Hasnain
Boolean Algebra
Boolean algebras
• The operators of Boolean algebra may be
represented in various ways. Often they are
simply written as AND, OR and NOT.
• In describing circuits, NAND (NOT AND), NOR
(NOT OR) and XOR (eXclusive OR) may also be
used.
• Mathematicians often use + for OR and · for
AND (since in some ways those operations are
analogous to addition and multiplication in other
algebraic structures) and represent NOT by a
line drawn above the expression being negated.
• NOT operation (inverter)
• AND operation
A A=0
A+ A =1
A A= A
A 1= A
A 0=0
• OR operation
A B=B A
( A B) C = A ( B C )
A+ A = A
A +1 = 1
A+0 = A
A+ B = B + A
( A + B) + C = A + ( B + C )
EE40 Fall
2006
Slide 371
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 372
Prof. Chang-Hasnain
Graphic Representation
Graphic Representation
A A=0
A
A
A+ A =1
A
Slide 373
AB B
A ⊕ B = AB + AB = ( A + B ) ( A + B ) = A B + A + B
Full square = complete set =1
Yellow part = NOT(A) =A
White circle = A
EE40 Fall
2006
A+ B
Exclusive OR=yellow and blue part –
intersection/overlap part
=exactly when only one of the input is true
Prof. Chang-Hasnain
EE40 Fall
2006
Boolean Algebra
Slide 374
Prof. Chang-Hasnain
Examples
• Distributive Property
F = A•B•C + A•B•C + (C+D)•(D+E)
A (B + C) = A B + A C
( A + B) C = ( A + B) ( A + C )
• De Morgan’s laws
A+ B = A B
A B = A+ B
• An excellent web site to visit
– http://en.wikipedia.org/wiki/Boolean_algebra
F = C•(A+D+E) + D•E
EE40 Fall
2006
Slide 375
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 376
Prof. Chang-Hasnain
Logic Functions, Symbols, & Notation
NAME
“NOT”
“OR”
“AND”
SYMBOL
A
NOTATION
F
A
B
A
B
F
EE40 Fall
2006
TRUTH
TABLE
F = A+B
A B
0 0
0 1
1 0
1 1
F
0
1
1
1
F = A•B
A B
0 0
0 1
1 0
1 1
F
0
0
0
1
Slide 377
“NOR”
A F
0 1
1 0
F=A
F
Logic Functions, Symbols, & Notation 2
Prof. Chang-Hasnain
A
B
“NAND”
A
B
“XOR”
A
B
(exclusive OR)
EE40 Fall
2006
F
F
F
F = A+B
A B
0 0
0 1
1 0
1 1
F
1
0
0
0
F = A•B
A B
0 0
0 1
1 0
1 1
F
1
1
1
0
F=A+B
A B
0 0
0 1
1 0
1 1
F
0
1
1
0
Slide 378
Prof. Chang-Hasnain
Logic Functions, Symbols, & Notation
Circuit Realization
A ⊕ B = AB + AB = ( A + B) ( A + B) = A B + A + B
NAME
SYMBOL
NOTATION
A
A
B
AB
“NOT”
A
“OR”
A
B
“AND”
A
B
F
F=A
A F
0 1
1 0
A⊕ B
B
AB
EE40 Fall
2006
TRUTH
TABLE
Slide 379
Prof. Chang-Hasnain
EE40 Fall
2006
F
F
Slide 380
F = A+B
A B
0 0
0 1
1 0
1 1
F
0
1
1
1
F = A•B
A B
0 0
0 1
1 0
1 1
F
0
0
0
1
Prof. Chang-Hasnain
Logic Functions, Symbols, & Notation 2
“NOR”
A
B
“NAND”
A
B
“XOR”
A
B
(exclusive OR)
EE40 Fall
2006
F
F
F
Fan in/Fan out
F = A+B
A B
0 0
0 1
1 0
1 1
F
1
0
0
0
F = A•B
A B
0 0
0 1
1 0
1 1
F
1
1
1
0
F=A+B
A B
0 0
0 1
1 0
1 1
F
0
1
1
0
Slide 381
Prof. Chang-Hasnain
• Complex digital operations are formed with a
variety of gates interconnected to yield the
desired logic function.
• Sometimes a number of inputs are connected to
one gate input and output of a gate may be
connected to a number of gates.
• Fan-in: the maximum number of logic gates that
can be connected at the input of a gate without
altering its performance.
• Fan-out: the maximum number of logic gates
that can be connected to the output of a gate
without altering its performance.
• Typical fan-in and fan-out numbers are 3.
EE40 Fall
2006
Vout
VDD
Ideal Transfer Characteristics
RPULL UP
Vout
IOUT
VIN
V/2
V
Prof. Chang-Hasnain
Terminology for a Logic Circuit
Inverter = NOT Gate
Vin
Slide 382
Vin
Output
Pull-Down
(NMOS)
VDD = Power supply voltage (D is from
Drain) we do not draw the symbol.
Pull-Up Network = Set of devices used to
carry current from the power supply to
the output node to charge the output
node to the power supply voltage.
Pull-Down Network = Set of devices used to
carry current from the output node to ground to
discharge the output node to ground.
VOUT
IOUT = Current for the device under study.
VTD = Threshold Voltage value of VIN at which the
Pull-Down (NMOS transistor) begins to conduct.
VOUT-SAT-D = Value of VOUT beyond which the current IOUT-D
saturates at the (drain) current saturation value IOUT-SAT-D.
EE40 Fall
2006
Slide 383
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 384
Prof. Chang-Hasnain
Thevenin Model For Pull-Up Device
Load Line For Pull-Up Device
IOUT vs. VOUT
For the Pull-Up Resistor and VDD
VDD
IOUT(µA)
100
RPULL UP
IOUT vs. VOUT is constrained to be on this line
by the circuit external to the three-terminal
device
Output
IOUT
VTHEVENIN = VDD
60
IOUT SHORT CIRCUIT = (VDD/RPULL UP)
Thevenin
Example:
VDD = 5V and RPULL UP = 100kΩ looking
this way
VTHEVENIN = 5V
IOUT SHORT CIRCUIT = 50 µA
INORTON
VOUT
VTHEVENIN
20
0
EE40 Fall
2006
Slide 385
Prof. Chang-Hasnain
NMOS Resistor Pull-Up
VDD
Circuit:
iD
A
iD
+
+
vIN
–
• Large values of RD are required in order to
vIN = VDD
–
VT
VDD
vIN
Large resistors are needed, but these take
up a lot of space.
VDD/RD
• One solution is to replace the resistor with an
NMOSFET that is always on.
7
EE40 Fall
2006
VOUT(V)
vDS = vOUT
0
0
5
Prof. Chang-Hasnain
– achieve a low value of VOL
– keep power consumption low
VDD
F
3
Slide 386
Disadvantages of NMOS Logic Gates
Voltage-Transfer Characteristic
vOUT
RD
EE40 Fall
2006
vGS = vin ≤ VT
Slide 387
VDD
vDS
!
8
A F
0 1
1 0
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 388
Prof. Chang-Hasnain
The CMOS Inverter: Intuitive Perspective
CMOS Inverter Voltage Transfer Characteristic
SWITCH MODELS
CIRCUIT
VDD
VDD
VDD
(
<
VDD
S
G
Rp
VOUT
VOUT
VOL = 0 V
D
A
VOH = VDD
VIN = VDD
VIN = 0 V
Slide 389
Prof. Chang-Hasnain
CMOS Inverter Load-Line Analysis
V
VIN = VDD + VGSp
IDn=-IDp
!
VOUT
VIN
D
VOUT = VDD + VDSp
7 2
GS
p =V
IN -V
DD
+
7
VIN
–
D
S
E
0
EE40 Fall
2006
VIN
VDD
Slide 390
Prof. Chang-Hasnain
CMOS Inverter Load-Line Analysis: Region A
VDD
V
VIN ≤ VTn
–
VDSp=VOUT-VDD
+
B
(
<
0
0
EE40 Fall
2006
D
(
<
Rn
S
9: /;$
S
G
C
G
VOUT
G
VDD
(
<
D
VIN
(
<
VOUT
GS
p =V
IN -V
DD
IDn=-IDp
+
VOUT
VIN
IDn=-IDp
–
VDD
–
VDSp=VOUT-VDD
+
VOUT
IDn=-IDp
!
0
EE40 Fall
2006
0
VDD
7,
7
Slide 391
VOUT=VDSn
0
VDD
0
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 392
VOUT=VDSn
Prof. Chang-Hasnain
CMOS Inverter Load-Line Analysis: Region B
V
VDD/2 > VIN > VTn
GS
p =V
IN -V
DD
IDn=-IDp
–
VDD
0
EE40 Fall
2006
–
+
VIN
IDn=-IDp
VOUT=VDSn
VIN
0
V
GS
p =V
IN -V
DD
VIN
VDD
0
Prof. Chang-Hasnain
+
+
VOUT
EE40 Fall
2006
–
Slide 394
–
VDD
–
VDSp=VOUT-VDD
+
VOUT
IDn=-IDp
VOUT=VDSn
Prof. Chang-Hasnain
Features of CMOS Digital Circuits
CMOS Inverter Load-Line Analysis: Region E
IDn=-IDp
GS
p =V
IN -V
DD
IDn=-IDp
Slide 393
VIN > VDD – |VTp|
V
VDD – |VTp| > VIN > VDD/2
VDSp=VOUT-VDD
+
0
VDD
CMOS Inverter Load-Line Analysis: Region D
VDD
–
VDSp=VOUT-VDD
+
VOUT
IDn=-IDp
• The output is always connected to VDD or GND
in steady state
→ Full logic swing; large noise margins
→ Logic levels are not dependent upon the relative
sizes of the devices (“ratioless”)
• There is no direct path between VDD and GND
in steady state
→ no static power dissipation
0
VDD
0
EE40 Fall
2006
Slide 395
VOUT=VDSn
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 396
Prof. Chang-Hasnain
The CMOS Inverter: Current Flow during Switching
(
<
VOUT
VDD
(
<
VDD
i
vIN
(
<
B
A
D
vOUT
S
i:
E
0
(
<
S
tsc
(
<
0
VIN
VDD
0
EE40 Fall
2006
VT
0
Ipeak
D
G
VOUT
D
G
S
G
VDD-VT
vIN:
D
D
i
VIN
VDD
VDD
i
C
S
G
Power Dissipation due to Direct-Path Current
Slide 397
Prof. Chang-Hasnain
Energy consumed per switching period:
EE40 Fall
2006
time
Edp = t scVDD I peak
Slide 398
NMOS NAND Gate
Prof. Chang-Hasnain
NMOS NOR Gate
• Output is low only if both inputs are high
• Output is low if either input is high
VDD
VDD
RD
RD
F
F
A
A
B
Truth Table
A B
0 0
0 1
1 0
1 1
B
EE40 Fall
2006
Slide 399
Truth Table
A B
0 0
0 1
1 0
1 1
F
1
1
1
0
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 400
F
1
0
0
0
Prof. Chang-Hasnain
N-Channel MOSFET Operation
P-Channel MOSFET Operation
An NMOSFET is a closed switch when the input is high
A PMOSFET is a closed switch when the input is low
A
A
A
B
A
B
B
B
Y
X
Y
X
Y
X
Y = X if A and B
Y = X if A and B
= (A + B)
Y = X if A or B
NMOSFETs pass a “strong” 0 but a “weak” 1
EE40 Fall
2006
Slide 401
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 402
VDD
A
EE40 Fall
2006
A1
A2
AN
Pull-up
network
A1
A2
AN
Pull-down
network
F
1
1
1
0
F
A
PMOSFETs only
F(A1, A2, …, AN)
Slide 403
A B
0 0
0 1
1 0
1 1
B
VDD
input signals
Prof. Chang-Hasnain
CMOS NAND Gate
In CMOS logic gates, NMOSFETs are used to connect
the output to GND, whereas PMOSFETs are used to
connect the output to VDD.
– An NMOSFET functions as a pull-down device when it
is turned on (gate voltage = VDD)
– A PMOSFET functions as a pull-up device when it is
turned on (gate voltage = GND)
Y = X if A or B
= (AB)
PMOSFETs pass a “strong” 1 but a “weak” 0
Pull-Down and Pull-Up Devices
•
Y
X
B
NMOSFETs only
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 404
Prof. Chang-Hasnain
CMOS NOR Gate
VDD
CMOS Pass Gate
A B
0 0
0 1
1 0
1 1
A
F
1
0
0
0
A
Y
X
B
Y = X if A
F
B
EE40 Fall
2006
A
A
Slide 405
Prof. Chang-Hasnain
EE40 Fall
2006
Slide 406
Prof. Chang-Hasnain