EE200: Digital Logic Design
Assignment 8
Deadline: Friday, 22nd May 2020
1. Email snapshot of your Verilog files for processor and testbench, the vpp and vcd files to Mr. Hamza Naeem
(m.hamza_naeem@outlook.com)
2. Plagiarism will result in negative marks.
We designed a processor in the class. You are required to write Verilog code for that processor and test
bench. Your test program should implement an example program code which should go through all
instructions at least once. For example, one possible code could be
A = B & (C*(D+E))
Where A, B, C, D and E are any values stored in data memory. If you write machine code for this
expression, you will have to go through all instructions at least once. Choose a similar expression (you
are not allowed to use this expression, choose your own) that tests all instructions. Write that
expression in comments at top of your top-level file.