September 17th, 2023
The American University in Cairo
School of Sciences and Engineering
Mechanical Engineering Department
MENG 4778 (Fall 2023)
Microcontrollers and Mechatronics Systems
Laboratory 1
In this experiment, you will learn the basis of Logic gates, Boolean algebra, and the
rules for the manipulation of logical expressions. You will use the logic gates and the
Boolean algebra to solve problems of combinatorial logic circuits along with few
applications. In addition, Student will have introductory assignment on how to use
Proteus software in designing Logic circuits.
Logic Gates
AND Gate
In this experiment the truth table of AND gate will be verified.
The AND gate requires that all inputs must be high (True) to yield a high (True) output.
An AND gate is composed of two or more inputs.
AND Gate Symbol
Top View of a TTL 74LS family 74LS08 Quad 2-input AND Gate IC Package
The logical expression of AND function is,
C  A B
AUC_MENG 4778 Fall 2023
Prof. Maki Habib
Page 1
September 17th, 2023
AND Gate Truth Table:
INPUTS
A
B
LOW (0)
LOW (0)
LOW (0)
HIGH (1)
HIGH (1)
LOW (0)
HIGH (1)
OUTPUT
AB
HIGH (1)
PROCEDURE:
1. Insert 7408, Quad (four in one package) 2-input AND gate IC into the Logic Lab
breadboard.
2. Sketch and then wire the inputs/output of one AND gate following the pin
configuration in the data sheet of the IC.
3. Verify the truth table of AND Gate by having all possible input combinations.
OR Gate
In this experiment the basic OR gate truth table will be verified.
The OR gate requires that one or more inputs must be HIGH to yield a
HIGH output. An OR gate is composed of two or more inputs.
OR Gate Symbol:
Top View of a TTL 74LS family 74LS32 Quad 2-input OR Gate IC Package
AUC_MENG 4778 Fall 2023
Prof. Maki Habib
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September 17th, 2023
The logical expression of OR function is,
C  A B
OR Gate Truth Table:
INPUTS
A
B
LOW (0)
LOW (0)
LOW (0)
HIGH (1)
HIGH (1)
LOW (0)
HIGH (1)
HIGH (1)
OUTPUT
A B
PROCEDURE:
1. Insert 7432, Quad (four in one package) 2-input OR gate IC into the Logic Lab
breadboard.
2. Sketch and then wire the inputs/output of one OR gate following the pin
configuration in the data sheet.
3. Verify the truth table of OR Gate by having all possible input combinations.
NOT Gate (Inverter)
In the logic implementation it is often necessary to obtain the inversion
(opposite state) of a signal or function.
A NOT Gate (inverter) provides an output signal of opposite state
from that of the input. A NOT gate is a single input gate.
NOT Gate symbol:
AUC_MENG 4778 Fall 2023
Prof. Maki Habib
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September 17th, 2023
Top View of a TTL 74LS family 74LS04 Hex Inverter IC Package
The circle (bubble) denotes inversion of output function.
The logical expression of NOT function is,
CA
NOT Gate Truth Table:
INPUT
OUTPUT
A
A
LOW (0)
HIGH (1)
PROCEDURE:
1. Insert a 7404 Inverter (NOT) Hex Inverter (six in one package) IC into the Logic
Lab bread board.
2. Sketch and then wire the input/output of one NOT gate following the pin
configuration in the data sheet.
3. Verify the truth table of NOT Gate by having all possible combination of the
inputs.
AUC_MENG 4778 Fall 2023
Prof. Maki Habib
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September 17th, 2023
NAND Gate
AND followed by INVERTER Gate
The NAND gate is an inverted (negated) AND function. Each LOW output of the AND
function is made HIGH and each HIGH output is made LOW. The output is LOW if and
only if all inputs are HIGH. The inverted AND is called NOT-AND and is abbreviated
NAND. Symbolically the NAND gate is represented by the AND symbol followed by a
small circle indicating an inversion of the output. A NAND gate is composed of two or
more inputs.
The NAND gate is one of the universal building blocks of digital logic. It may be used to
implement any logic function without the need for any other type of gates.
NAND Gate Symbol:
C  A B
Top View of a TTL 74LS family 74LS00 Quad 2-input NAND Gate IC Package
NAND Gate Truth Table:
INPUTS
OUTPUT
A
B
LOW (0)
LOW (0)
LOW (0)
HIGH (1)
HIGH (1)
LOW (0)
HIGH (1)
HIGH (1)
AUC_MENG 4778 Fall 2023
Prof. Maki Habib
A B
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September 17th, 2023
PROCEDURE:
1. Insert a 7400 Quad 2-inputs NAND gate IC into the logic Lab breadboard.
2. Sketch and then wire the inputs/output of one NAND gate following the pin
configuration in the data sheet.
3. Verify the truth table of NAND Gate by having all possible input combinations.
NOR Gate
OR followed by INVERTER Gate
The NOR gate (NOT-OR) is the equivalent of an inverted OR function and will yield a
LOW output if either of the inputs is HIGH.
Symbolically, the NOR is represented by the OR gate symbol followed by a small circle
indicating an inversion of the output. A NOR gate is composed of two or more inputs.
NOR Gate Symbol
Top View of a TTL 74LS family 74LS02 Quad 2-input NOR Gate IC Package
NOR Gate Truth Table:
INPUTS
OUTPUT
A
B
LOW (0)
LOW (0)
LOW (0)
HIGH (1)
HIGH (1)
LOW (0)
HIGH (1)
HIGH (1)
AUC_MENG 4778 Fall 2023
Prof. Maki Habib
A B
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September 17th, 2023
The NOR gate like the NAND gate is a universal building block of digital logic because
either may be used to implement any logic function.
PROCEDURE:
1. Insert a 7402 Quad 2-input NOR gate IC into the logic Lab breadboard.
2. Sketch and then wire the inputs/output of one NOR gate following the pin
configuration in the data sheet.
3. Verify the truth table of NOR Gate by having all possible input combinations.
Exclusive-OR Gate (XOR)
These gates are usually formed from the combination of the other logic gates already
discussed. The Exclusive-OR is an "inequality" function and the output is HIGH (1)
when the inputs are not equal to each other. The XOR gate may be depicted as (A  B)
symbolically where the circled OR operator  indicates the Exclusive-OR function.
XOR Gate symbol:
Vcc
14
13
12
11
10
9
8
1
2
3
4
5
6
7
Ground
C  AB  A B  C  A  B
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Prof. Maki Habib
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September 17th, 2023
XOR Gate Truth Table:
INPUTS
OUTPUT
A
B
LOW (0)
LOW (0)
LOW (0)
HIGH (1)
HIGH (1)
LOW (0)
HIGH (1)
HIGH (1)
A B
Write the primitive logical expression for the output of the ExOR gate.
The XOR gate function is stated as:
The output will yield a HIGH if one and only one input is HIGH. If more than one input
is HIGH or all inputs are LOW, the output is always LOW (HIGH output only if the
inputs are different).
PROCEDURE:
1. Insert a 7486 Quad 2-inputs ExOR gate IC into the logic Lab breadboard.
2. Sketch and then wire the inputs/output of one ExOR gate following the pin
configuration in the data sheet.
3. Verify the truth table of ExOR Gate by having all possible input combinations.
4. Finally, implement the ExOR output function using the primitive gates AND,
NOT and OR.
Exclusive-NOR Gate (XNOR)
Exclusive-NOR is an "equality" function and the output is HIGH (1) when the inputs are
equal to each other.
XNOR Gate symbol:
AUC_MENG 4778 Fall 2023
Prof. Maki Habib
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September 17th, 2023
INPUT
A
B
0
0
0
1
1
0
1
1
XOR
XNOR
OUTPUT OUTPUT
PROCEDURE:
1. Insert a 7486 Quad 2-inputs ExOR gate IC and 7404 Inverter (NOT) Hex Inverter
(six in one package) IC into the logic Lab breadboard.
2. Sketch and then wire the inputs/output of one ExOR gate and one Not gate
following the pin configuration in the data sheet.
3. Verify the truth table of XNOR Gate by having all possible input combinations.
Problems for the Report:
1. Write the NOR equivalent circuit of the following logic expression without
simplifying the function,
ABC  A B D  C ( B  D  A )  CB
2. Write the truth table and the equivalent logic circuit of the following logic
expression without simplification the function,
( A B  D )  C  DBC  ( B  BC )  D
3. Design a logic circuit that will implement Temperature Control System
With the following Inputs:
High Temperature (1 if the temperature is above 30°C, 0 otherwise),
LowTemp (1 if the temperature is below 15°C, 0 otherwise)
Rain (1 if it's raining, 0 otherwise)
WindowOpen (1 if the window is open, 0 otherwise)
Output: ActivateHeater: Turns on if LowTemp is 1 and WindowOpen
is 0. Turns off otherwise.
Start with the necessary truth tables and then use the necessary Karnaugh Maps to
get the minimized solution. Implement and test the design using Proteus.
4. Design a logic circuit that will implement Security System for a Vault
AUC_MENG 4778 Fall 2023
Prof. Maki Habib
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September 17th, 2023
With the following Inputs:
MotionDetected (1 if motion is detected inside the vault, 0 otherwise)
DoorOpen (1 if the vault door is open, 0 otherwise)
SecurityBreach (1 if an unauthorized access attempt is made, 0 otherwise)
NightTime (1 between 9 PM to 6 AM, 0 otherwise)
Output:
ActivateAlarm: Turns on if MotionDetected is 1 and DoorOpen is 0, or if
SecurityBreach is 1 during NightTime.
Start with the necessary truth tables and then use the necessary Karnaugh Maps
to get the minimized solution. Implement and test the design using Proteus.
5. Derive the minimized logic expression and draw its logic circuit for the
following list of Minterms and sketch the corresponding logic circuit.
f ( x1 , x2 , x3 , x4 )   (1,4,6,7,89,13,14)  d (0,2,5)
Develop a Boolean expression for the solution of this problem using a
Karnaugh map. Implement and test the design on Proteus.
TTL "subfamilies":
TTL chips require a fairly narrow range of supply voltage -- 5 volts, +/- 0.5V.
For TTL circuits, a logic "1" is usually defined as a signal (Input/Output} of about 2.0
V/2.4 V, while logic "0" is about 0.8 V/0.4 V above ground; any signal between those
values is undefined. Also, note that all unused inputs should be tied to ground.
AUC_MENG 4778 Fall 2023
Prof. Maki Habib
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September 17th, 2023
Bipolar TTL logic comes in many flavors (usually numbered in the "74XX" format,
occasionally in "54XX" format) including 74LS/ALS types. These all require 1000s of
times more power than TTL-compatible CMOS logic (like the 74HCT type, see below).
Note that the 74HCT* ICs have the same logic thresholds as other TTL chips, allowing
them used in a mixed circuits of TTL and HCT logic.
74LXX -- low-power TTL (1/10 the speed, 1/10 the power of "regular" TTL)
74HXX -- high-speed TTL (twice as fast, twice as much power)
74SXX -- Schottky TTL (for high-frequency uses)
74LSXX -- combination of low-power & Schottky, same speed as regular TTL,
but at 1/5 the power consumption
74ASXX = advance Schottky TTL logic
74ALSXX = advance low-power Schottky TTL logic
CMOS -- Complimentary Metal Oxide Silicon
CMOS ICs use much less power than TTL, plus they are fairly forgiving of "slop" in
input voltage -- they're happy with anything between 3 (some, like 1381s, go lower) and
12 volts. CMOS, though, is much more susceptible to damage from static electricity (so
get that grounding strap out!).
AUC_MENG 4778 Fall 2023
Prof. Maki Habib
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September 17th, 2023
CMOS comes in two flavors, with corresponding numbering schemes: "CD40XX" metal
gate CMOS, and "74CXX" silicon gate CMOS (note that this second subfamily borrows
its numbering scheme from TTL ICs).
Metal gate CMOS (CD40XX)has a rated working voltage of 3 - 15 V but can be used
down to 2V.
Silicon gate CMOS (74CXX) logic has a working voltage range of 2 - 6V but can be
used to less than 1V. For microwatt power applications you want to use the lowest
possible voltage.
AC / ACT stands for Advanced CMOS Logic (ACL for short). HC / HCT stands for
High-speed CMOS Logic (HCL).
The AC and ACT subfamilies are faster than the HC and HCT subfamilies, and draw
some more power in some circuits. All chips in the AC* subfamily have lower output
resistance than HC* and can sink and source 24 mA at logic levels and up 70 mA (typ)
per gate for motor loads. As a result AC* gates can handle more than twice the current of
HC* gates (50 - 70 mA vs. 24 mA). Note, though, that while most HC* chips have a 25
mA limit, the HC* driver chips such as the 74HC240 and the 74HC245 (i.e., buffers) can
handle 35 mA per device, and a maximum of 75 mA per chip.
Example
7400
Quad 2-Input NAND
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Prof. Maki Habib
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September 17th, 2023
Pin Arrangement
Electrical Characteristics
Input Output N
-
Propagation Delay
ALS
AS
Unit
LS ALS
F
S AS
HC HCT
1000
1000
[max]
H->L
22
15
11
8
6
L->H
15
15
8
8
5.3
All High
inputs Low
4.5 4.5
5
LS
40
20
20
20
20
1.6
0.4
0.1
0.1
0.6
All High 0.4
outputs Low 16
23
24
nS
3.5
23
24
nS
Input Characteristics
ALS
ALS
F
S
1000
N
N
4
3.5
AS
AS
1000
Unit
50
20
20
uA
2
0.5
0.5
mA
Output Characteristics
ALS
AS
LS ALS
F
S AS
HC HCT Unit
1000
1000
0.4
0.4
2.6
1
1
2
48
4
4
mA
8
8
24
20
20
20
48
4
4
mA
http://upgrade.kongju.ac.kr/data/
You can check the electrical characteristics for other ICs.
AUC_MENG 4778 Fall 2023
Prof. Maki Habib
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