2016 24th Iranian Conference on Electrical Engineering (ICEE)
A Low-Power Current-Reuse Resistive-Feedback
LNA in 90nm CMOS
Parya Khoshroo
Mohammad Elmi
Hossein Miare Naimi
Babol Noshirvani University of Technology
Shahid Beheshti University
Babol Noshirvani University of Technology
Babol, Iran
Tehran, Iran
Babol, Iran
Email: Khoshroo.Parya@Gmail.com
Email: M.Elmi@Mail.SBU.ac.ir
Email: H-Miare@NIT.ac.ir
Abstract—In this paper, an inductorless wideband low noise
amplifier is presented which can cover various wireless standards. The amplifier benefits from techniques such as resistive
feedback to achieve input impedance matching, Miller capacitance to compensate frequency bandwidth, and current-reuse
transconductance-boosting to reduce power consumption. The
required equations for the input impedance matching, gain, and
noise figure are presented. Simulation results in 90nm CMOS
technology show that the amplifier has a frequency bandwidth of
400MHz-10GHz with a voltage gain of 22.2dB and a noise figure
of 1.86-2.42dB. The total power consumption of the amplifier is
approximately equal to 16.6mW.
VDD
I NTRODUCTION
VDD
MP1
Vin
C’
MN2
C’
Cb1
MP2
Cz2
RC2
VDD
Vout
MP3
RO2
Vb
MN3
MP4
Cb2
MN4
RO1
Cz1
MN1
RC1
Rf1
Keywords—low noise amplifier ; inductorless; resistive feedback
I.
Rf2
Fig. 1.
General structure of the proposed inductorless low noise amplifier.
Modern wireless communication systems should cover various standards that would require the multi-standard receiver
structures [1-4]. Using specific low noise amplifier (LNA) for
each standard leads to higher power consumption and larger
area occupation that would not be cost-effective [1-5]. In
such structures, if each amplifier uses low-Q inductors, this
results in large chip area [5]. For these reasons, multi-band
multi-standard LNAs which are inductorless can be a proper
alternative. Although the absence of inductors might result in
an increase in the noise figure value (NF) or improper input
impedance matching, using some structures such as resistive
feedback LNA can maintain NF at reasonable values. It should
be noted that many types of these structures that have been
proposed before have some problems such as high IIP3 [1,2,5],
using two voltage supplies [3], high NF value [4], and high
power dissipation [2,3,5].
Each current-reuse inverter uses the gm-boosted technique
which can increase transconductance of the stage with the
same power dissipation. Each inverter has been followed by
a common gate stage. The DC current that is supplied by the
transistor MP1, has been divided equally between transistors
MN2 and MP3. Also, DC voltages of different nodes have
been selected in such a way that results in a gate-drain
voltage of zero (VGD=0) and a drain-source voltage of VDD/4
(VDS=VDD/4) for all of the transistors. Therefore, by using
multiplying feature, MP1 width is exactly equal to twice width
of MP2 (and MP3). Also, MN1 width is exactly equal to twice
width of MN2 (and MN3). Note that the N-type transistors in
this structure are triple-well and their bulk has been connected
to their sources. Additionally, the width of transistors MN3
and MP3 are exactly equal to twice width of transistors MN4
and MP4, respectively.
In this paper a low-noise low-power inductorless amplifier
with 10GHz 3dB-bandwidth is presented. Simulation results
in 90nm CMOS technology are provided. Section II describes
the proposed circuit in details. Required equations of the noise
figure, gain and input impedance matching are presented in
Section III. Simulation results are presented in Section IV.
Finally, Section V, concludes the paper.
The next common gate stages improve the linearity of the
structure, and also increase the voltage gain. These transistors
are biased by the DC voltage of VDD/2. Two feedback resistances, RF1 and RF2, provide the input impedance matching,
and supply the bias voltage of input inverters. These feedback
resistors ensure the stability, as well. Therefore, bias voltages
of MN1 and MP2 are equal to VDD/4 and bias voltages of
MN2 and MP1 are equal to 3VDD/4. To isolate the output
voltage from two feedback resistances and to use Miller
frequency compensation technique, two current-reuse voltage
buffers are used, and are separated by the capacitor Cb2 in AC
mode.
II.
P ROPOSED C IRCUIT S TRUCTURE
Fig. 1 shows the proposed circuit structure of the multistandard low noise amplifier. The input stage includes two
current-reuse inverters that have been stocked on each other
and are separated in AC mode by the capacitor Cb1 to form
two parallel paths.
c
978-1-4673-8789-7/16/$31.00 2016
IEEE
To increase the 3dB-bandwidth of the frequency response,
two Miller capacitances with two voltage buffers are used. The
917
2016 24th Iranian Conference on Electrical Engineering (ICEE)
2.2V
950ȍ
2.2V
m=4
2.2V
m=2
50ȍ
m=2
Vs
m=4
544ȍ
15fF
2.2V
m=2
4kȍ
4kȍ
m=2
NMOS=6.8μm/100nm
PMOS=20μm/100nm
500ȍ
Vout
500ȍ
m=1
m=1
15fF
544ȍ
950ȍ
Fig. 2.
Implementation of proposed inductorless LNA.
capacitances Cz1 and Cz2 produce a zero in the frequency
response and improve the bandwidth, in case locations of the
zero and poles are chosen carefully. The output resistances,
RO1 and RO2, are implemented to fix and achieve the desired
voltage gain. If a resistive load bank put at the output, the
variable gain amplifier can be obtained. In this case, increasing
in voltage gain leads to better NF values and worse IIP3 values
and decreasing in voltage gain leads to the worse NF values
and better IIP3 values.
Recently some receivers have been reported that their input
LNA requires high gain and its output stage does not seen any
active mixer [6]. In other architectures a voltage buffer stage
should be added to achieve the output impedance matching due
to existing an active mixer in the next stage. Implementation
of proposed LNA circuit is shown in Fig. 2, and the simulation
results in 90nm CMOS technology have been analyzed in the
schematic level.
III.
PARAMETERS C ALCULATION
A. Input impedance matching
If we neglect the effects of two small capacitors Cz1 and
Cz2 at the intermediate frequencies and also assume that the
capacitors Cb1 and Cb2 are completely short circuit, a voltagecurrent feedback (shunt-shunt) is obtained. Note that, here we
assume that the output point is MN4 source and MP4 source,
only to calculate the input impedance matching.
Considering the above assumptions, two equal feedback
resistance operate in parallel, so we have:
Rif =
RS RF 1 RF 2
Ri
=
1 + af
1 + af
(1)
2
RF
(2)
f =−
Also, considering that the upper stage and the lower stage are
completely equal, it can be shown:
vo a = = − (RS (RF /2)) (Ro /2) ×
(3)
ii
(ron /4) (rop /2)
(4gmn + 2gmp )
((ron /4) (rop /2)) + 2g1mn
(ron /2) (rop /4)
+ (2gmn + 4gmp )
((ron /2) (rop /4)) + 2g1mp
gmp (RC2 RF )
×
1 + gmp (1 + ηp ) (RC2 RF )
gmn (RC1 RF )
+
1 + gmn (1 + ηn ) (RC1 RF )
Where RO=RO1=RO2, η = gmb4 /gm4 and a is the ratio
of the output voltage to the input current in the feed-forward
path, and f is the feedback factor. So to achieve the input
impedance matching, we should have:
RS
RS (RF /2)
=
2
1 + af
(4)
By substituting Eq. 2 and Eq. 3 in Eq. 4, suitable RF
can be achieved. In the proposed structure RF1 and RF2 are
approximately equal to 950 Ω.
B. Voltage gain
Considering feedback loop, it can be written:
vo
a
Aif =
=
ii
1 + af
(5)
So the voltage gain of the circuit is equal to:
Avf =
vo
Aif
=
vi
RS
(6)
918
2016 24th Iranian Conference on Electrical Engineering (ICEE)
Voltage Gain
So the overall voltage gain of LNA with input matching
assumption is equal to:
Vout
=
Av =
VG1,2
22.5
22.2
(7)
gmp (RC2 RF )
1+gmp (1+ηp )(RC2 RF )
+
dB
2Avf
gmn (RC1 RF )
1+gmn (1+ηn )(RC1 RF )
21.9
21.6
21.3
21
0
Simulation results shows a voltage gain of 22.2dB at
intermediate frequencies which verifies Eq. 7.
Fig. 3.
C. Noise figure
The main sources of the noise contributions include input
resistance and the input transistors. At the intermediate frequencies Cb1 and Cb2 will be short circuit, and two inverters
are separated. Neglecting some noise sources that have little
effect and assuming input matching condition, equivalent noise
voltage at the output can be obtained as follow:
8
9
10
7
8
9
10
7
8
9
10
4
5
6
7
Frequency (GHz)
8
9
10
Amplifier Voltage gain.
2.1
1.9
1.7
1.5
0
Fig. 4.
1
2
3
4
5
6
Frequency (GHz)
Amplifier noise figure.
S11
0
-5
dB
-10
-15
-20
-25
0
Fig. 5.
1
2
3
4
5
6
Frequency (GHz)
Input impedance matching.
S IMULATION R ESULTS
IIP3
5
2.5
dBm
The proposed LNA is simulated in 90nm CMOS technology. As expected, due to using resistive feedback structure,
LNA has satisfied the required stability parameters. Fig. 3
presents the amplifier voltage gain. As it is evident from the
figure, the 3dB-bandwidth is more than 10GHz. Fig. 4 shows
the amplifier NF. At the whole frequency range of 0.4-10GHz,
the NF is less than 2.42dB. In the best case minimum NF
is equal to 1.86dB. As illustrated in Fig. 4 input impedance
matching is achieved at the whole frequency range of 400MHz
to 10GHz, so that the S11 parameter is less than -10dB at all
frequencies. The IIP3 diagram is shown in Figure 6. As it is
expected, the IIP3 value at high frequencies is reduced, but it
is better than -6dBm at all frequencies.
4
5
6
7
Frequency (GHz)
2.3
So NF is closely related to the voltage gain and can be
expressed as:
2
Vn,out
1
NF =
(9)
1
4kT RS 4 A2v
IV.
3
NF
mp
According to the simulation results noise figure is 1.86dB
at the intermediate frequencies.
2
2.5
dB
R2
1
Ro
+ 4kT o ×
(8)
≈ A2v 4kT RS + +4kT
4
2
4
⎧
2
⎨
((ron /4) (rop /2))
(4g γ + 2gmp γp )
1
⎩ mn n
2gmn + ((ron /4) (rop /2))
2
((ron /2) (rop /4))
+ (2gmn γn + 4gmp γp )
1
2gmp + ((ron /2) (rop /4))
2
γ
1
+
2gmn 2g1mn + ((ron /4) (rop /2))
2 ⎫
⎬
γ
1
+
2gmn 2g1 + ((ron /2) (rop /4)) ⎭
2
Vn,out
1
0
-2.5
-5
-7.5
0
Fig. 6.
1
2
3
Amplifier IIP3.
919
2016 24th Iranian Conference on Electrical Engineering (ICEE)
Table I provides a comparison between performances of the
amplifiers that have been previously reported with this work.
TABLE I.
Technology
BW (GHz)
Power (mW)
Gain (dB)
NF (dB)
IIP3 (dBm)
S11 (dB)
inductor
VDD
P ERFORMANCES COMPARISON .
This Work*
90nm
0.4-10
16.6
22.2
1.86-2.42
3
@1GHz
<-10
no
[1]**
90nm
0.5-8.2
42
25
1.9-2.6
-13
@4GHz
<-8
no
[2]**
90nm
0.5-7
42
24.5
2-2.7
-6
@1GHz
<-9.5
no
2.2
2.7
2.7
[3]**
65nm
0.1-4
12
24
1.79-2.8
-5.5
@1GHz
<-10
no
1.2
2.2
[4]**
135nm
2-9.6
19
11
3.6-4.8
-7.2
@6GHz
<-8.3
no
[5]**
90nm
0.5-7.2
42
25.2
1.8-2.5
-7
@1GHz
<-9
no
1.5
2.7
*In schematic level **Measurement
V.
C ONCLUSION
An inductorless current-reuse low noise amplifier using
different techniques such as transconductance-boosting at the
first stage, Miller frequency compensation, and resistive feedback for a 50ohm input impedance matching is presented. The
voltage gain, noise figure and impedance matching equations
have been approved. The proposed LNA has been simulated in
90nm CMOS technology in schematic level. Simulation results
show the total power consumption of 16.6mW, and the voltage
gain of 22.2dB in 10GHz 3dB-bandwidth. The noise figure is
less than 2.42dB at the whole frequency range and is 1.86dB
in the best case.
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