TUTORIAL
Using Integrated Logic Analyzer (ILA) and Virtual
Input/Output (VIO)
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This tutorial covers using the Integrated Logic Analyzer (ILA) and Virtual Input/Output (VIO) cores to debug and monitor your
VHDL design in the Xilinx Vivado IDE.
In many cases, designers are in need to perform on-chip verification. That is, gaining access to an internal signal's behavior in their
FPGA design for verification purposes.
One option is to bring these signals to the FPGA pins and connect them to LEDs to see their behavior visually. This option is easy,
fast, and works well for simple cases, but it is not flexible, scalable, or realistic.
Another option is to have an external logic analyzer with advanced features that can display and depict these signals' behavior, but
it requires external and relatively expensive equipment.
The Integrated Logic Analyzer (ILA) is an alternative that combines the advantages of both previous options. It is easy, fast, flexible,
and has many advanced features that help designers quickly view and check the chosen signals' behavior.
Overview
This article contains multiple screenshots from the Vivado GUI. Click the images to make them larger!
Use the sidebar to navigate the outline for this tutorial, or scroll down and click the pop-up navigation button in the top-right
corner if you are using a mobile device.
ILAandVIO
The ILA and VIO are free customizable IPs from Xilinx. The ILA IP helps you easily probe internal signals inside your FPGA and bring
them out into a simulation-like environment to monitor them and verify their behavior.
Unlike ILA, the VIO IP allows you to virtually drive internal signals inside your FPGA to stimulate or control your design, like driving
the RESET signal.
• Xilinx Intellectual ProP-fil!Y.: Integrated Logic Analyzer (ILA)
• Xilinx Intellectual ProP-erzy.: Virtual lnP-ut/OutP-Ut (VIO)
Requirements
1. A Xilinx FPGA board
2. The Vivado Design Suite
3. Basic VHDL knowledge
I'm using the Kintex-7 FPGA KC705 Evaluation Kit but the methods shown in this tutorial should work on any modern Xilinx FPGA
board.
Download the example project
You can download the example project and VHDL code using the form below. It should work in Vivado version 2020.2 or newer.
Extract the Zip and open the ila_tutorial.xpr file in Vivado to view the example design, or read the rest of this article to learn to
create it from scratch.
Create a project with Vivado
Start by opening Vivado. In Vivado's welcome screen, click the Create Project button.
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Add sources
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You can also add and create sources later.
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Add the constraint file top.xdc from the design folder. Check Copy constraints files into project and click on Next to continue.
Note:this constraint file is specific to the KC705 board. You need to change the elk pin and the led pin according to your board.
And also, the -period of your board clock.
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ENTITY INSTANTIATION --
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Creating the VIO core for RESET
Now that you understand the design example, we will create a VIO to control the input port reset. That will give us the ability to
manipulate (toggle) the reset from Vivado IDE so we can manually control when to start/stop the counters.
Click on IP Catalog, then search for VIC, then double-click on VIC (Virtual Input/Output).
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First, we change the name to vio_reset.
Second, we only need an output port for the reset, so we put O in the input probe count box, and we put 1 in the output probe
count box.
After Vivado finishes synthesizing the VIO, we need to add it to our design by declaring a component for it and instantiating it in the
counter_top.vhdl file as below.
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-- Declare vio_reset
COMPONENT vio_reset
PORT(
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END COMPONENT;
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flatten_hierarchy to None.
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Change the layout to debug by clicking on Layout and then Debug.
Inserting debugging probe flow
Our synthesized design now contains the vio_reset instance, and it is time to specify the signals that we want to probe. There are
three ways to do that:
1. Insertion from VHDL file
2. Insertion from the Netlist
3. Insertion from xdc/tcl file
We will use the first two methods and leave the third for a later tutorial.
Insertion from VHDL file
This method is the easiest and fastest way to insert a probe, especially when it's a composite type (array or record). But it requires
adding code to the design files, VHDL code that's redundant in the real product.
We can insert a probe in the VHDL design file by:
1. Declaring a special attribute called MARK_DEBUG
2. Attach the signal that we want to probe with this attribute
3. And activate it by giving it the value "true" as below:
1
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We can see from the synthesized design that the signal count in both counter_ 1_inst and counter_2_inst are listed under
Unassigned Debug Nets and marked with a bug icon in both the Netlist and the Schematic.
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This insertion method is also easy, but it requires that you first synthesize the design and then manually click on each signal to mark
it for debugging. It could be exhausting if the design is large and you want to monitor many signals.
We will probe the output port trigger in both counters using the Netlist. We can do this either from the Netlist window or the
Schematic by locating the signal net and then right-click on it and choose Mark Debug.
From the Netlist window, find trigger under counter_ 1_inst
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FORE
a
Creating the ILA debug core
Now it is time to create the ILA debug core. We need to create a probe for each signal that we want to analyze. The easiest way is to
take advantage ofVivado wizard Set Up Debug.
Click on Set Up Debug and then click on Next.
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Sources
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IP Catalog
Nels(124)
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lll.xEd1!0\I
> (I] counter_1_in
1. Choosln11 nets and connecting ttiem to debu11 cores.
> [I] counter_2_in
2. Associating a clockdomaln with eadl ofttie nets chosen for debug.
3. Choosing additonal features on the debug cores like Data Depth. Advanced Tri1111er roode and Capture
Contra!
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Ri!port Clack/nleradian
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Vivado will list all the debug signals and capture the clock domain for you automatically. Here we see that our four signals are listed.
You can remove the signals that you are not interested in or add extra signals, but we will use all of them.
Note:we don't have to use all the signals that we have marked as Debug.
Click on Next.
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Set.Up D�ug
Nets to Debug
w
Toe riets belowwlll be debugged with IL.A. cores. To add nets dlck"find Nets to Add". You cari also select rietsiri the Nellist or other windows. then drag them to the list or dick Add Selected Netsw.
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..,, .!I a counter_2_!nst/courit (4)
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dlUBUF_BUFG
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_f • counlj2J
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S• counlj3J
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clk_lBUF_BUFG
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cik_lBUF _BUFG
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.[Iii c:ounlj3J
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S Ill counter 1 inst/trigger
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fa•
* counter_1_lristlcounl(4)
Flnd Nets to �dd ..
Nets to debug: 10
� l■•iM■I �"� �
Now we configure the ILA by choosing the FIFO depth and checking Capture control. We can leave the FIFO at 1024 as it is enough
depth for our example.
Click on Next.
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SYNTHESIZED DESIGN' - synth_ 1 lxc7s100fgga576-2
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Re1JortClock.lnteraction
Debug Cores
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Debug Nets
IMPORTANT: It is very important to save the constraint in this stage so it can be added to the design. Otherwise, we risk losing our
ILA core.
Click the Save icon or hit Ctrl+S.
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Save the constraintslorthe currentdesi11n
Name the file ila_core and click OK.
Data andTrigger
..,
DataandTrigger v
1 - □ �
Note:the clock connected to ILA and Debug_hub must be a free-running clock.
Now, the ILA is completed and saved. We need to rerun the synthesis so the ILA can be added to the synthesized design.
Click Run Synthesis and then on OK.
When Vivado finishes running the synthesis, click on Open Synthesized Design and then on Schematic.
We can see now that Vivado has added the ILA and Debug_Hub to our design and has connected the debug signals to the ILA
probes.
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SYNTHESIZED DESIGN - synth.J I xc7k325tffg900-2
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Project Summary
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x counter_top.\lhdl
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8 Cells
21/0 Ports
124 Nets
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Now we are ready to implement our design and generate the bitstream so we can test our design.
Click on Run Implementation and then on OK.
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Ill Generate Blt�eam
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eskloplila_tutorial/ila_tutor1al
Evaluation Plallorm[xc7s1DO!gga576-2)
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Constraints
X
• «Delault Launch Directory>
QQenerate scriptsonly
Reports
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Launch giredory·
Net l'roperties
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SynlllesisCofll}lete
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Failed Routes
LVT
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231
BRAM
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00
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DSP
0
start
2/21121,8:32AM
morn, 11:59 PM
Elapsed
00:01:0-4
oo:oi:Jo
Runstrate1n
V"rvadoSynthe
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VNadoSynlhei
After Vivado finish running the implementation, click on Generate Bitstream and then on OK.
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"' SIMULATION
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> Open E laborated Desi11r1
Utlrar!es
CofllJi!e On
Launch _11iredory:
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Select an otlJE<dto see prop
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> Open l"lllemenled Design
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LOIi
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.., PROGR AM AND DEBUG
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@J.aunch runsonlocalhost
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Launch the selected synthesis or il'T"Cllemenla�on runs and <;lenerate
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v SYNTHESIS
J 1n Generate Bllstream
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['_ lla_core.xdc(targel)
Hierarchy
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> e-■• co1mter_toprrtO(counter_lop.�hdl} (JJ
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Project Summary
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Sources
-----
DefaultLayout
synth_desir;inCo"l)letel
THS
0.000
TPWS
0.000
Total Power
0.099
FailedRoutes
0
LUT
10
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1471 2419
102
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0.5
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Start
2121/21,8:32AM
2121'21. 9:31 AIA
2fl0f21, 9:59 PIA
Elapsed
00:01:04
00:08:25
00'.01:30
RunStrate
V-JYadoSy
VIYado Im
VNadoSy
Generate a prograrrrring file after i�lerrenla�an
After Vivado finishes generating the bitstream, click on Open Hardware Manager and then on Open Target, and finally on Auto
connect.
file
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IP Sources
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bigger_..2_0BUF
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Name
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SYNTHESIZED DESIGN syntt1_1 I xc7k.701fbg484-2
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x
? - a�
PratleType
Data ancfTrl!Jger v
Data and Tr19ger v
Data andTrtgqer v
Data and Trt11ger v
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Next, we need to program the FPGA with the bit file (*.bit) and the debug probe file (*.ltx). Vivado automatically finds them for you.
Click on Program Device and then on Program.
file
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HARDWARE MANAGER localhosVxilirur_td/DigilenV210203337626A
0 There a1e no debug cores. Prog1am de...ice Refresh device
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x Messagn
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:
11
Serial 1/0 links
II
)rial/i\a_tutorial/ila_tutorial.runs/impl_t/counter_top.bli
0 Enable end of startup check
□
□
0
.� ....................................... .
General
Prope,lies
,., IMPLEMENTATION
tD Generate Bitstream
Bitstreamflle:
Name:
X
Debug probes file: oriaVila_tutofiaVila_tutorial.runs/impl_ 1/coumer_top.ltx
(I
,., SYNTHESIS
Program Device
Select II bitstream programming file and download it to your hardware device.
You can optionally select a debug probes file that corresponds to the debug
cores contained in the bitstream progr11mming file.
Hardw•re Device Properties
> Open Elaborated Design
,., PROGRAM ANO DEBUG
-
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Hrial 1/0 Saons
7 - □ [:;
II
: INFO: [Labtool:!!tcl 4.4-466] Opening hw target loc:alhost:3121/xilinx tc:t/Digi.lent/210203ll7626A
: open_hw_target.: Time (s): c:pu • 00:00--;-07 ; elap:sed • 00:00:07 . He;;;.,ry (MB): peak• 2416.469 ; 9ain • 1408.211
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Configuring the ILA triggers
After programming the device, we can see that Vivado's GUI layout has changed, and a new hw_ila_1 dashboard has opened,
containing several windows.
We will minimize some windows that we don't need so we can work comfortably.
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From the dashboard options, check hw_vio_1 and uncheck Capture Setup.
Also, close the hw_vios tab because when we checked hw_vio_1, it has been added to the Trigger setup window.
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Now, we need to add the reset button to the VIO so we can control the reset.
Click on hw_vio_ 1 and then add reset as shown in the picture below.
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We can see that hw_vio_ 1 now contains the reset probe.
Change the value of the reset in vio_reset to 1 if it's not 1.
Now, we will add the triggers that we will use. A change of value on a trigger signal will cause the ILA to start recording the probed
signals.
Let us say that we want to trigger (start recording) on the rising edge of the output port trigger of counter_ 1_inst. To do that,
follow these steps:
1. Go to the Trigger Setup - hw_ila_1 window
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2. Click on the+ icon to add a new trigger and choose counter_1_inst/trigger and click on OK.
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3. We can see that the trigger has been added, and now we need to set up the condition. Click on the Value box and choose R(O
to 1 transition). Click on the Operator box and choose == (equal)
We will also change the trigger position to 32, meaning that it will record 32 samples before the trigger event in addition to what
comes after.
Now, the trigger is set up and ready to be armed.
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Now, we move to the waveform window to add the signals that we want to view. First, let's maximize the inner window to gain a
better view.
Second, we need to add some missing signals to the probe. Vivado usually adds all the assigned signals automatically, but in this
case, it didn't.
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Now, we change the radix of the count signal to Unsigned as it is easier to follow.
Right-click on the count signal name and then choose radix and then Unsigned.
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Running the ILA and VIO
Now, we have finished configuring and customizing the ILA, and we are ready to run it.
ILA has two running modes: Immediate and trigger.
Immediate mode
Immediate mode triggers the ILA immediately and starts recording the samples directly until the FIFO is full.
Click on the Run trigger immediate button.
We can now see the recorded samples in the waveform window. We see that both count signals are 0, and both trigger signals are
low ·o· because the reset is active.
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Trigger mode requires that we set up a condition for at least one trigger and arm it. The ILA will keep waiting for the armed trigger's
condition to become true, and then it will start recording the samples directly until the FIFO is full.
We have already added the trigger and set it up to R(O to 1 transition).
Running ILA with one trigger
Change reset back to 1 from vio_reset.
file
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Click on the window Status hw_ila_ 1. We see that the core status is Idle as there are no triggers armed. Click on the Run trigger
button, and that will arm the trigger.
We see now that the core status changed to waiting for trigger. As the reset is high, there is no activity on our trigger signal (port
trigger of counter_1_inst), and I LA is waiting.
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Now, let us change the reset to O so that the counters start working.
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We see now the ILA has got triggered and has recorded the samples, and the core status changed back to Idle.
We see the red vertical line (marker) on the rising edge of our trigger signal {port trigger of counter_ 1_inst), and it is in position 32.
We also can verify that the signal count is behaving correctly and the signal counter_ 1_instltriggeris high for four clock cycles
between 12 and 15 (the output is delayed by one clock cycle).
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If we zoom out a little bit, we can also verify the behavior of count and trigger signals for counter_2_inst.
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Running ILA with multiple triggers
We can use a combination of triggers for complex or advanced conditions. To capture several disjoint time frames in the same
waveform, we can use multiple triggers that fire repeatedly.
For example, let's say we want to trigger when the count signal from counter_ 1_inst is equal to 9 (count== 9) and when the count
signal from counter_2_inst is greater than 2 (count> 2). To do that and split the FIFO into four time windows, follow these steps:
1. Change reset back to 1 from vio_reset
2. Remove the previous trigger probe:
file
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3. Add both count signals as triggers:
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7. Click on the Run trigger button, and that will arm the trigger. Notice that in the window Status hw_ila_1, the capture status is
now window 1 of 4 because we have four windows.
Change reset back to O from vio_reset.
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Maximize the waveform window. We see now that we have four windows and a trigger associated with each window. Notice that
these windows are independent and not continuous.
The ILA waits for the trigger event to happen, and when it does, the ILA uses the first window to record 256 samples. It then
immediately waits for the next trigger until all the windows are full.
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Mestages
Running ILA with Auto re-trigger mode
ILA has a nice feature called Auto re-trigger that will automatically arm the trigger after it gets triggered. It is useful when
monitoring events that occur seldom and you want to run a test overnight. Or you can use it when the trigger happens so often and
fast that you cannot arm the trigger manually to capture the samples repeatedly.
Let us assume that the output port trigger of counter_2_inst gets asserted every 3 hours, and you want to record the data each
time it happens. To use the Auto trigger, follow these steps:
1. Change reset back to 1 from vio_reset
2. Remove the previous trigger probe
3. Add trigger_2_0BUFsignal as trigger:
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Refresh rate: 500
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4. Configure the trigger to the condition to equal(==} and falling edge F(1-to-0 transition}
5. Configure the number of windows to 1 and FIFO depth to 1024, and position to 32:
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F(l-to-0 transition)
B (both transitions)
I Serial 1/0 Links I Serial 1/0Scans I
6. Click on Auto re-trigger button:
Port
_�I probe 3(0]
N (oo transitions)
Refresh rate : 500
Debug Probe Value: trigger_2_OBUF
+ - <>,
Comparator Us.age
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7. Finally, change reset back to O from vio_reset:
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We can see now that the waveform window is getting refreshed and updated as the trigger happen. It is fast, but the behavior is
noticeable.
Click on Stop trigger and toggle Auto re-trigger.
Running ILA with Capture mode
Another feature of ILA is the Capture mode. In some cases, you are not interested in recording all the data but rather capture a
specific sample. Capture mode helps you filter out data and record only the samples you are interested in.
Let's say we are only interested in sampling when the output port trigger of counter_ 1_inst is '1' AND the output port trigger of
counter_2_inst is 'O'.
To use Capture mode to achieve this, follow these steps:
1. Change reset back to 1 from vio_reset
2. Remove the previous trigger probe
3. From the dashboard, Uncheck Trigger Setup and check Capture Setup. Notice that a Capture Setup window will appear.
From the Settings - hw_ila_ 1 window, Change Capture mode to BASIC, the window to 1, the FIFO depth to 1024, and position to
1:
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4. Add trigger_2_0BUF, and counter_1_inst/triggerfrom the Capture Setup window:
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Mes�ges
Debug Probe Value: counter_ l_instftrigger
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5. Configure counter_1_inst/triggerto the condition equal (==) and 1 (logical one):
+
button to add probet
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[1 • 1024]
X(don'tcare)
R(O-to-1 transition)
[0 -1023]
F(1-to-Otransition)
General Settings
Refresh rate:
) Td Console
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v r X-(d-o-,,-ca-,.-, -�1 probe2(0]
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probe3!0J
v j O(logical zero)
B (both transitions)
N (no transitions)
500
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6. Configure trigger_2_0BUFto the condition equal(==) and O (logical zero):
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500
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Serial 1/0 Scans ]
7. Change the Capture Condition to Global AND:
Port
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Set Capture Condition to 'GlobalNOR'
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probe3[0]
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Refresh rate:
500
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Set capture condition to Gtoba1 ANO, OR.NAND orNOR function
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8. Click on the Run trigger button and then change resetto O from vio_reset:
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As we can see from the image below, the waveform has only recorded data when counter_ 1_inst's count signal is 13, 14, 15, or 0.
Any other counts are filtered out because counter_ 1_inst/triggeris high on these counts only.
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Conclusion
In this tutorial, we learned about ILA and VIO and different use-cases for them. ILA and VIO are excellent options for on-chip
debugging. They are free, easy to use, flexible, scalable, and simple yet offer advanced features. The use of multiple triggers and
Capture mode helps you achieve a complex debugging scheme.
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