Lect 15
Programmable Logic
CS221: Digital Design
Dr. A. Sahu
Dept of Comp. Sc. & Engg.
Indian Institute of Technology Guwahati
1
Outline
• Programmable Logic
• PAL,
PAL PLA
PLA,
• Memory
–ROM, PROM, EPROM, EEPROM
–SRAM
SRAM : Memory Cell
• CPLD, CLB, FPGA
• FPGA/ASIC Design Flow
• HDL Programming : Verilog HDL
2
Programmable
Logic Devices
Programmable Via Control :
Adder/Substractor
/
• C= B‐A=B+(‐A)=B+ (Ab+1), Ab is complement of A
• D is control bit: D=0/1 operation is add/sub
A
Result
B
ALU
Operation
4
Programmable Via Select: ALU
• Arithmetic and Logic Unit
• Add/Sub/OR/AND/Shift…
R=0
A
R>0
Co
R
B
Control: What to do ?
if
if
if
if
if
if
if
if
Control=0 R =A +B
Control=1 R =A ‐ B
Control=2 R =NOT A
Control=3 R =A AND B
Control=4 R =A OR B
Control=5 R =A XOR B
Control=6 R = (A<B)?0:A
Control=7 R =A SHFT B
5
Programmable
Logic Devices
Programmable Logic Organization
• Pre‐fabricated building block of many AND/OR
gates (or NOR, NAND)
• "Personalized" by making or breaking
connections among the gates
Inputs
Dense Array of
AND gates
Product
terms
Dense Array of
OR Gates
Outputs
Programmable Array Block Diagram for Sum of Products Form
Basic Programmable Logic
Organizations
• Depending on which of the AND/OR logic
arrays is programmable, we have three basic
organizations
ORGANIZATION
AND ARRAY
OR ARRAY
PAL
PROG.
FIXED
PROM
FIXED
PROG.
PLA
PROG.
PROG.
PLA Logic Implementation
Key to Success: Shared Product Terms
Example: Equations
F0 = A + B’ C’
F1 = A C ‘ + A B
F2 = B ‘C’ + A B
F3 = B ‘C + A
Personality Matrix
Product Inputs Outputs
t erm A B C F0 F 1 F 2
AB 1 1 ‐ 0 1 1
B’ C ‐ 0 1 0 0 0
A C’ 1 ‐ 0 0 1 0
B’ C’ ‐ 0 0 1 0 1
A
1 ‐ ‐ 1 0 0
Input Side:
1 = asserted in term
0 = negated in term
‐ = does not participate
Output Side:
1 = term connected to output
0 = no connection to output
F3
0
1 Reuse
of
0
0 terms
1
PLA Logic Implementation
Example
l Continued
i
d ‐ Unprogrammed
d device
d i
A
B
C
All possible connections are available
b f
before
programming
i
F0
F1
F2
F3
PLA Logic Implementation
Example Continued ‐ Programmed part
A
B
C
Unwanted connections are "blown"
AB
B’C
AC’’
B’C’
A
Note: some array structures
work by making connections
rather than breaking them
F0
F1
F2
F3
PLA Logic Implementation
Alternative representation
Un‐programmed device
Sh t h d notation
Short‐hand
t ti
so we don't
d 't have
h
t
to
draw all the wires!
X at junction indicates a connection
PLA Logic Implementation
Notation for implementing
F0 = A B + A’ B’
F1 = CD
CD’ + C
C’D
D
A
B
C
Programmed device
D
AB
A’B’
CD’
C’D
AB+A’B’
CD’+C’D
PLA Logic Implementation
Multiple functions of A, B, C : List of all product terms
A B C
Design Example
Programmed device
ABC
A
B
C
A’
B’
C’
A’B’C’
A’B’C
A’BC’
AB’C’
ABC’
A’BC
AB’C
F1 = A B C
F2 = A + B + C
F3 = (A B C)
C)’
F4 = (A + B + C)’
F5 = A ⊕ B ⊕ C
F6 = (A ⊕ B ⊕ C)’
F1 F2 F3 F4 F5 F6
PLA Logic Implementation
Another Example: Magnitude Comparator
AB
A
AB
A
CD
00
00
1
01
0
11
0
10
0
CD
00
00
0
01
1
11
1
10
1
01
0
1
0
0
01
1
0
1
1
11
0
0
1
0
11
1
1
0
1
10
0
0
0
1
10
1
1
1
0
C
D
C
B
K‐map for NE
B
K‐map for EQ
AB
A
AB
A
CD
00
00
0
01
0
11
0
10
0
CD
00
00
0
01
1
11
1
10
1
01
1
0
0
0
01
0
0
1
1
11
1
1
0
1
11
0
0
0
0
10
1
1
0
0
10
0
0
1
0
C
B
K‐map for L T
D
D
C
B
K‐map for GT
D
PLA Logic Imp: Magnitude Comparator
A
B
C
D
A’B’C’D’
A’BC’D
A
BC D
ABCD
AB’CD’
AC’
A’C
B’D
BD
A’B’D
B’CD
ABC
B’C’D’
EQ
NE
LT
GT
PALs and PLAs
What is difference between Programmable Array Logic (PAL) and
Programmable Logic Array (PLA)?
PAL concept — implemented by Monolithic Memories
AND array is programmable, OR array is fixed at fabrication
A given column of the
OR array has access to
only a subset of the
possible product terms
PLA concept — Both AND and OR arrays are programmable
PALs and PLAs
• Of the two organizations the PLA is the most
flexible
– One PLA can implement a huge range of logic
functions
– BUT many pins; large package, higher cost
• PALs are more restricted / you trade number
of OR terms vs number of outputs
– Many device variations needed
– Each device is cheaper than a PLA
Read‐Only Memory
ROM
ROM
• Decoder : Produces minterms
• Ors : Produce SOP’s
A
B
C
D
S3
S2
S1
4:16
4
16
dec
S0
Enb
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A‘B’C’D’
A ‘B’C’D
A‘B’CD’
A
B CD
A‘B’CD
A‘BC’D’
A‘BC’D
A‘BCD’
A
BCD
A‘ BCD
A B’C’D’
A B’C’D
AB’CD’
A
B CD
A B’CD
A B C’D’
A B C’D
AB
A
B C D’
AB C D
F1
F2
F3
ROM
• A decoder
• A set of programmable OR’s
A
B
C
D7
D6
D5
D4
A2 D3
D2
A1 D1
A0 D0
X
X
X
X
X
X
F3
21
X
F2
X
X
X
F1
F0
ROM vs. PLA/PAL
Inputs
Fixed
AND array
(d
(decoder)
d )
Programmable
Connections
Programmable
OR array
Outputs
(a) Programmable read-only memory (PROM)
Inputs
Programmable Programmable
AND array
Connections
Fixed
OR array
Outputs
(b) Programmable array logic (PAL) device
Inputs
Programmable Programmable
AND array
Connections
Programmable
Connections
Programmable
OR array
(c) Programmable logic array (PLA) device
22
Outputs
General Logic Implementation
k
• Given a 2 xn ROM, we can implement
ANY combinational
bi ti
l circuit
i it with
ith att mostt k
inputs and at most n outputs.
• Why?
k
k
– k‐to‐2
k to 2 decoder will generate all 2 possible
minterms
– Each
h off the
h OR gates must implement
l
a
∑m()
– Each ∑m() can be programmed
23
Example
• Find a ROM‐based circuit
implementation for:
– f(a,b,c) = a’b’ + abc
– g(a,b,c)
( b ) = a’b’c’
’b’ ’ + ab
b + bc
b
– h(a,b,c) = a’b’ + c
• Solution:
– Express f(), g(), and h() in ∑m() format (use
truth tables)
– Program the ROM based on the 3 ∑m()
∑m()’ss
24
Example
• There are 3 inputs and 3 outputs, thus we need a
8x3 ROM block.
f = ∑m(0, 1, 7), g = ∑m(0, 3, 6, 7), h = ∑m(0, 1, 3, 5, 7)
a
b
c
3-to-8
decoder
0
1
2
3
4
5
6
7
f
25
g
h
ROM as a Memory
• Read Only Memories (ROM) or Programmable
Read Only Memories (PROM) have:
– N input lines,
– M output lines
lines, and
– 2N decoded minterms.
• Can be viewed as a memory with the inputs as
addresses of data (output values),
– hence ROM or PROM names!
26
Memories
• Volatile: Random Access Memory (RAM)
– SRAM "static"
– DRAM "dynamic"
• Non
Non‐Volatile:
Volatile: Read Only Memory (ROM):
– Mask ROM "mask programmable"
– EPROM "electrically
electrically programmable"
programmable
– EEPROM “electrically erasable electrically
p g
programmable"
– FLASH memory ‐ similar to EEPROM with
programmer integrated on chip
27
ROM as Memory
Read Example: For input (A2,A1,A0) = 011, output is
(F0,F1,F2,F3 ) = 0010.
•What are functions F3, F2 , F1 and F0 in terms of (A2, A1, A0)?
•
8x4 ROM
Address
D0
D1
D2
D3
A2 D4
D5
A1 D6
A0 D7
A
B
C
X
X
X
0
1
1
0
1
X
1
0
0
0
0
2
1
0
0
1
A[2:0] 3
0
0
1
0
F[3:0]
4
0
0
0
0
4
5
1
0
0
0
6
0
0
1
1
7
0
1
0
0
X
X
X
X
X
F0
28
X
F1
F2
3
F3
A[2:0] =A2A1A0 F[3:0]=F3F2F1F0
Design by ROM: Example
• BCD to 7 Segment Display
l Controller
ll
29
ABCD
a
b c
d e f
g
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
0111
1
0
1
1
0
1
1
1
1
1
X
X
X
X
X
X
1
1
1
1
1
0
0
1
1
1
X
X
X
X
X
X
1
0
1
1
0
1
1
0
1
0
X
X
X
X
X
X
0
0
1
1
1
1
1
0
1
1
X
X
X
X
X
X
1
1
0
1
1
1
1
1
1
1
X
X
X
X
X
X
1
0
1
0
0
0
1
0
1
0
X
X
X
X
X
X
1
0
0
0
1
1
1
0
1
1
X
X
X
X
X
X
a
f
b
e
c
d
g
Memory Unit
Read/Write
Address
Data to
Read/Write
M
A
R
D
e
c
o
d
e
r
Data
Memory Unit
n bits
Memory cell
0
1
2
3
4
bit 1
Address decoder
Me
emory add
dress regisster
bit 0
2n‐1
bit n ‐ 1
0
1
2
m‐1
Memory data register
m bits
Memory Cell
Select
R
Input
R/W’
S
D
Output
S
RW’
D O/p
0
X
X 0
1
1
X D
1
0
In 0
32
Memory
Data Inputs
W0
Addr
2x4
Dec
ode
r
BC
BC
BC
BC
BC
BC
BC
BC
BC
BC
BC
BC
BC
BC
BC
BC
W1
W2
W3
Enable
R/W’
R/W
33
Data Outputs