Digital System Design Distance Learning Letter Installing Xilinx Simulation Libraries iPLAT – Competence team for Innovative Platforms for Mixed-Hardware/Software Systems MA23 Project 18-06 Version: 0.1 Author: P. Rössler Copyright Notice This document or parts of it (text, photos, graphics and artwork) are copyrighted and not intended to be published to the broad public, e.g., over the internet. Any redistribution, publishing or broadcast with permission only. Violation may be prosecuted by law. Dieses Dokument bzw. Teile davon (Text, Photos, Graphiken und Artwork) sind urheberrechtlich geschützt und nicht für die breite Veröffentlichung, beispielsweise über das Internet, vorgesehen. Jegliche weitere Veröffentlichung nur mit Genehmigung. Zuwiderhandlungen können gerichtlich verfolgt werden. 2 Introduction This Distance Learning Letter describes how to install simulation libraries for technology dependent resources (PLLs, memories …) contained in Xilinx FPGAs. These simulation libraries will be used in various exercises during the Digital System Design lecture. It is assumed that the following tools are already installed: • ModelSim-Intel FPGA Starter Edition, Release 10.5b • Xilinx Vivado 2016.1 HL WebPack Most things will probably apply to other releases of the ModelSim and Xilinx Vivado software. The installation procedure is described for a PC running Windows 7, 64-bit. However, installation works similar on a Linux machine. Compile Xilinx Simulation Libraries First, you need to create a directory that will hold the compiled simulation libraries. If you have installed the ModelSim-Intel simulator to c:/intelFPGA/16.1/modelsim_ase create the following sub-directory called “xilinx” c:/intelFPGA/16.1/modelsim_ase/xilinx Next, start Xilinx Vivado and select “Tools > Compile Simulation Libraries” from the menu bar, as shown in Figure 1. In the “Compile Simulation Libraries” dialogue, specify the options as shown in Figure 2: • Simulator: The simulator that is used to compile libraries for (which is ModelSim in our case) • Family: The FPGA family to compile libraries for (“Artix-7”, since the Basys3 board which is used in the lecture contains an Artix-7 FPGA device) • Compiled library location: Directory for saving the compiled simulation libraries • Simulator executable path: The directory to locate the simulator executable • Compile 32-bit libraries: Use this option to generate 32-bit executable models 3 Figure 1: Start Xilinx Vivado to Compile the Simulation Libraries Figure 2: Compile Simulation Libraries Dialogue Once you click the “Compile” button, the simulation libraries will be compiled (Figure 3) which usually takes a few minutes of time. 4 Figure 3: Compilation of the Simulation Libraries is in Progress Once the window shown in Figure 3 disappears, the compilation of the simulation libraries is finished. You can find the compiled libraries in the selected directory afterwards (Figure 4). Figure 4: Compiled Xilinx Simulation Libraries Modify the “modelsim.ini” File In order to instruct ModelSim to automatically load the Xilinx simulation libraries during startup, open the “modelsim.ini” file located in c:/intelFPGA/16.1/modelsim_ase/modelsim.ini with a text editor and add the following lines to this file (see also Figure 5): 5 ; Xilinx Simulation Libraries unisim = $MODEL_TECH/../xilinx/unisim unimacro = $MODEL_TECH/../xilinx/unimacro unifast = $MODEL_TECH/../xilinx/unifast secureip = $MODEL_TECH/../xilinx/secureip unisims_ver = $MODEL_TECH/../xilinx/unisims_ver unimacro_ver = $MODEL_TECH/../xilinx/unimacro_ver unifast_ver = $MODEL_TECH/../xilinx/unifast_ver simprims_ver = $MODEL_TECH/../xilinx/simprims_ver Figure 5: Modified “modelsim.ini” File If you launch ModelSim afterwards you should now see the Xilinx technology libraries in the “Library” window, see Figure 6. 6 Figure 6: ModelSim with Mapped Xilinx Technology Libraries The Xilinx simulation libraries are now ready to be used in subsequent exercises during the Digital System Design lecture. Version Version 0.1, 2017-01-27 Initial release of this document If you find errors or inconsistencies, please report them to the supervisors of this lecture via email. Thank you! 7