DCP.vhd
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Tue Jun 22 00:05:03 2021
-------------------------------------------------------------------------------------------- Possible solution of Practice Lab (June 11th 2021) - Programmable duty cycle
-- Starting from considerations about timing of interested signals, base timing unit
-- can be suitably chosen as 50ns. So clock period was chosen 50ns, compatible with
-- adopted Spartan3 FPGA (speed grade: -4)
-- In order to express values of duty cycle of 40% 60% 80% and 0%, it is possible to
-- make an engineering choice to express all that values by having a first internal
-- periodicity of 5 clock cycle (20% granularity).
-- Since we must implement it in the first part of output prog2dc, occupying 10% of the
-- total output time; a total of 50 clock cycles will be able to implement the overall
-- requested periodicity.
-- This solution was designed without using any counter, so some ready vector were prepared
-- and by using rotation and shifting only, it was possible to generate the wanted outputs
-- In particular VHDL code was subdivided in three main part:
-- a process dealing with the boost input (in_pro);
-- a process looking after the generation of outputs (out_pro);
-- a concurrent part delaing with the controlling signal and enable implementation
-----------------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Port definition
entity DCP is
Port ( clk, boost, enable : in STD_LOGIC;
prog2dc, boost_flag : out STD_LOGIC);
end DCP;
architecture Behavioral of DCP is
signal regc: std_logic_vector (49 downto 0) :="00011000110001100011000110001100000000000000000000";
signal reg80pc: std_logic_vector (4 downto 0):= "01111";
-- signal related to 80% duty cycle
signal reg60pc: std_logic_vector (4 downto 0):= "00111";
-- signal related to 60% duty cycle
signal reg_boost: std_logic_vector(19 downto 0):= "01010101010101010101"; --register use for boost_flag
signal boost_check: std_logic_vector (5 downto 0):= (others => 'Z'); --register for boost input sampling
signal flagH, flagL: std_logic:='0';
-- couple of signal to pick up a
signal pulse: std_logic:='Z';
-- change of impulse pulse
begin
in_pro: process (clk)
-- 1st process: dealing with input sampling
begin
if rising_edge (clk) then
boost_check <= boost_check (4 downto 0) & boost; --input shift into the boost_check register
end if;
-- boost_check made by 6 bit, because it allows to read up to 200ns plus guard band
end process;
-- of 50 nsec before and after the measured pulse
out_proc: process (clk)
begin
if rising_edge (clk) then
-- 2nd process: generating internal register related to outputs
if pulse = '1' then
-- pulse is calculated in the concurrent part (will be 1 when a positve pulse occurs)
reg_boost <= reg_boost (18 downto 0) & 'Z'; --shift for boost_flag output (see concurrent part)
regc <= regc (48 downto 0) & regc(49); -- regc rotations needed for prog2dc output
if flagH = '0' then
-- flagH will be triggered when a boost variation occurs
regc <= reg80pc & "000110001100011000110001100000000000000000000";
reg_boost <= "01010101010101010101";
flagH <='1'; flagL <='0';
end if;
elsif pulse = '0' then
reg_boost <= reg_boost (18 downto 0) & 'Z';
regc <= regc (48 downto 0) & regc(49);
if flagL = '0' then
regc <= reg60pc & "000110001100011000110001100000000000000000000";
reg_boost <= "01010101010101010101";
flagL <='1'; flagH <= '0';
end if;
end if;
end if;
end process;
--concurrent parts: This will generate signal pulse related to what has been sampled on boost_check vector
pulse <= '1' when (boost_check(3 downto 0) = "0110" or boost_check(4 downto 0) = "01110") else
'0' when (boost_check = "100001" or boost_check (4 downto 0) = "10001" or boost_check(3 downto 0) = "1001" or boost_check(2
downto 0) ="101");
-- Control has been implemented on the rightmost part in order to start immediately with boost_flag signal
prog2dc <= regc(49) when enable ='1' and (pulse = '1' or pulse ='0') else 'Z';
boost_flag <= reg_boost(19) when (pulse = '1' or pulse ='0') else '-';
end Behavioral;
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