5
4
3
2
1
D
D
Mockingbird-N/V 14/15_TGL &
Hellcat 14/15/17_TGL Schematic
C
C
2020-08-01
REV : A00
B
A
B
DY : None Installed
UMA: Unified Memory Architecture
OPS: Optimal Playable Settings
https://realschematic.com
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Cover Page
Size
Document Number
A4
MOCKINGBIRD_TGL
Date: Saturday, August 01, 2020
5
4
3
2
Sheet
1
of
1
Rev
A00
105
A
5
4
3
2
1
Mockingbird N/V/HellCat TGL Block Diagram
GPU
VRAM(GDDR5) *2
NVIDIA
N17S-G3/G5
GDDR5
2GB
81,82
DDR4
PCIE Gen3x2
SODIMM
Channel A
76-80
12
eDP x4 (14/15 eDP x2)
14"/15"/17" LCD
Intel CPU
Touch Panel
D
DDR4
SODIMM
Channel B
D
I2C
55
13
Tiger Lake U
1 PCIE4.0 * 4 Lanes
USB2.0 x1
CCD/DMIC
(HD Camera)
Re-Timer
DMIC
TCSS
Option2
55
73
For MKB
2CH SPEAKER
(2CH 2W/4ohm)
29
Audio Codec
REALTEK
ALC3204
DMIC
DP 1.4/USB3.0
BURNSIDE-BRIDGE
For Hellcat
USB3.1 Type C
Option1
TGL PCH-LP
27
HDA
PD Controller
I2C
CYPRESS
CYPD6127
12 PCIe*3.0 Lanes
2 SATA Lanes
CC1/CC2
72
USB2.0
USB2.0
IO Board
73
4 USB3.1 Gen1/Gen2 Lanes
Universal Jack
10 USB2.0/1.1 Lanes
Finger Print
with Power Button
HDMI
CNVI 2.0
USB2.0
57
(Remove SD/EMMC)
C
For MKB-V
HDMI 1.4b
High Definition Audio
LAN 10/100/1000
RJ45 Conn
PCIE 4.0 x4
M.2 NGFF/NvMe
63
SSD
SATA/PCIEx4
M.2 NGFF/NvMe
63
SSD
PCIE
C
Realtek RTL8111H
USB 3.1 Gen1
Re-driver
USB3.0
For Hellcat
For MKB-V
MKB-N
For MKB-V
MKB-N
PCIE/USB2.0
USB3.0
PARADE
PS8713BT
USB3.0
Port2
61
USB3.0
CardReader
SD 3.0
SD Card
USB3.0 Port1
USB2.0
USB2.0
Realtek
RTS5144
Micro SD Card
Sensor BD on
Panel side
LID SENSOR
S-5712ACDL1
MGR SENSOR
Free Fall Gsensor
Gyro+G
ST
LIS2MDL
HGDEDM013A
35
MB SIDE
For Hellcat
ST LNG2DMTR
Accelerometer
E-compass
INT
For Hellcat
NGFF WLAN
CNVi
USB2.0
ST
LSM6DS3
ST LIS2DW12
For Hellcat
70
Free Fall Gsensor
For Mockingbird
70
KBC
I2C
Flash ROM
SPI
8+16 MB
B
TPM 91
eSPI debug port
I2C
B
25
For MKB-V
Touch PAD
eSPI Bus
65
68
INT
Batt Conn
KBC
Charger
SMBUS
ISL9538C
DC Jack
PS2
MICROCHIP
MEC1515H-D0-I
Thermal
NUVOTON
NCT7718W
Fan Control
PWM
SMBUS
FAN
26
24
26
Keyboard
65
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
https://realschematic.com
Title
Date:
5
Block Diagram
Size
Document Number
Custom
4
3
2
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
2
A00
of
105
5
4
3
2
1
D
D
20191121
Follow Nakia
1D05V_VCCSTG
R301 1
2 1KR2F-3-GP
Follow upsell
change R311 from 100k to 51
20191217
Follow PDG change to 100
EAR_N_TEST_NCTF
1D05V_VCCSTG_TERM
R311 1
R308 1
1D05V_VCCSTG_TERM
2 1KR2F-3-GP
PROCHOT#_CPU
R304 1
2 1KR2F-3-GP
THERMTRIP#_CPU
R307 1
2 1KR2F-3-GP
CPU_CATERR
R302 1
1D05V_VCCST
DY
CPU_POPI_RCOMP
[24]
PECI_CPU
[15]
DBG_PMODE
[22,24,44,46,72]
[24,65]
R305 1
XDP_PREQ#
XDP
XDP_TDI
XDP_TMS
4
3
SRN51J-GP
R310 1
2 49D9R2F-GP
XDP
2 51R2J-2-GP
RN304
PCH_OPI_RCOMP
R306 1
XDP_TRST#
2 49D9R2F-GP
1
2
DY
C
4
3
SRN51J-GP
PROCHOT#_CPU
TOUCHPAD_INTR#
[79]
CPU1U
21 OF 21
GPU_EVENT#
PROCHOT#_CPU
R303 1
2 499R2F-2-GP
DB42: TOUCH_PANEL_DET#
DF8: TOUCH_PANEL_PD#
TOUCHPAD_INTR#
[55]
XDP_TDO_CPU
2 51R2J-2-GP
RN302
1
2
XDP_TCLK
C
2 100R2J-2-GP
M7
BK9
E2
M5
CPU_POPI_RCOMP
PCH_OPI_RCOMP
CT39
CB9
CW12
CM39
DBG_PMODE
1
TOUCH_PANEL_PD#
CPU_CATERR
PECI_CPU
PROCHOT#_CPU_R
THERMTRIP#_CPU
R315
2
0R0402-PAD-7-NP-GP
TOUCH_PAD_INTR#
TOUCH_PANEL_PD#
DF4
DB42
DB41
DF8
DU5
DF31
DV32
DW32
B
DJ27
CATERR#
PECI
PROCHOT#
THRMTRIP#
PROC_TRST#
PROC_TMS
PROC_TDO
PROC_TDI
PROC_TCK
PROC_POPIRCOMP
PCH_OPIRCOMP
TP#CW12
TP#CM39
DBG_PMODE
GPP_B4/CPU_GP3
GPP_B3/CPU_GP2
GPP_E7/CPU_GP1
GPP_E3/CPU_GP0
PCH_JTAGX
PCH_TMS
PCH_TDO
PCH_TDI
PCH_TCK
PCH_TRST#
PROC_PREQ#
PROC_PRDY#
EAR_N/EAR_N_TEST_NCTF
GPP_H2
GPP_H1
GPP_H0
GPP_F7
GPP_F9
GPP_F10
K4
B9
D12
A12
B6
D8
A9
E12
B12
A7
H4
C11
D11
G1
DT15
DR15
DT14
XDP_TRST#
XDP_TMS
XDP_TDO_CPU
XDP_TDI
XDP_TCLK
1
1
1
1
1
PCH_TCK
1
XDP_PREQ#
XDP_PRDY#
1
1
TP309
TP310
TP311
TP312
TP313
XDP
TP314
TP303
TP302
EAR_N_TEST_NCTF
GPP_F7
GC6_EVENT#
GPP_F10
1
1
R316
TP315
TP316
1
B
GPU_EVENT#
2
0R0402-PAD-7-NP-GP
GPP_H19/TIME_SYNC0
TGL-U-1-GP-U2
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A3
Date:
5
4
3
2
CPU (THML/JTAG)
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
3
of
A00
105
5
4
3
2
1
eDP
[55]
[55]
[55]
[55]
[55]
[55]
[55]
[55]
[55]
[55]
[55]
[24]
[55]
[55]
D
eDP_TX_CPU_N0
eDP_TX_CPU_P0
eDP_TX_CPU_N1
eDP_TX_CPU_P1
eDP_TX_CPU_N2
eDP_TX_CPU_P2
eDP_TX_CPU_N3
eDP_TX_CPU_P3
eDP_AUX_CPU_N
eDP_AUX_CPU_P
EDP_HPD
L_BKLT_EN
eDP_VDD_EN
L_BKLT_CTRL
D
CPU1A
eDP_TX_CPU_P3
eDP_TX_CPU_N3
eDP_TX_CPU_P2
eDP_TX_CPU_N2
eDP_TX_CPU_P1
eDP_TX_CPU_N1
eDP_TX_CPU_P0
eDP_TX_CPU_N0
HDMI
[57]
[57]
[57]
[57]
[57]
[57]
[57]
[57]
[57]
[57]
HDMI_DDI_TX_P3
HDMI_DDI_TX_N3
HDMI_DDI_TX_P0
HDMI_DDI_TX_N0
HDMI_DDI_TX_P1
HDMI_DDI_TX_N1
HDMI_DDI_TX_P2
HDMI_DDI_TX_N2
eDP
eDP_AUX_CPU_P
eDP_AUX_CPU_N
TP401
CPU_DPB_CTRL_CLK
CPU_DPB_CTRL_DATA
[57]
1GPP_E23
EDP_HPD
DR5
HDMI_DDI_TX_P3
HDMI_DDI_TX_N3
HDMI_DDI_TX_P0
HDMI_DDI_TX_N0
HDMI_DDI_TX_P1
HDMI_DDI_TX_N1
HDMI_DDI_TX_P2
HDMI_DDI_TX_N2
T12
T11
Y11
Y9
T9
P9
V11
V9
TBT
C
[71]
[71]
[71]
[71]
[71]
[71]
[71]
[71]
[71]
[15,71]
[71]
[71]
USB1_TCSS_TX_N0
USB1_TCSS_TX_P0
USB1_TCSS_TX_N1
USB1_TCSS_TX_P1
USB1_TCSS_RX_N0
USB1_TCSS_RX_P0
USB1_TCSS_RX_N1
USB1_TCSS_RX_P1
HDMI
AB9
AD9
TBT_LSX0_TXD
TBT_LSX0_RXD
USB1_TCSS_AUX_P
USB1_TCSS_AUX_N
DM29
DK27
CPU_DISP_HPDB
DG43
KB_DET#
DN4: WWAN_GPO_PEREST#
DT6: WWAN_CARD_PWR_OFF#
DG47: 3.3V_CAM_EN
DF6: TBT_LSX1_TXD
DN23: SENSOR_DB_DET#
DD6: TBT_LSX1_RXD
DK23: CPU_DDP4_CTRL_CLK
DN21: CPU_DDP4_CTRL_DATA
DF47: CPU_DISP_HPD2
DH52: USB_OC1#
DK45: CPU_DISP_HPD4
[15]
GPP_E21
[15]
GPP_D12
[15]
GPP_D10
[65]
KB_DET#
DU8
DV8
GPP_E21
DF6
DD6
GPP_D10
DN23
DM23
GPP_D12
DK23
DN21
CPU_DISP_HPD1_R
DF43
DF45
DF47
20191211
follow vendor request
R403 1
CPU_DISP_HPD1_R
USB3.2 Type-A Port2 (IO)
[66]
USB_OC1# DH52
SOC_OC_FAULT DK45
eDP_VDD_EN
L_BKLT_EN
L_BKLT_CTRL
eDP
DG47
DJ47
TBT_LSX0_TXD
TBT_LSX0_RXD
SOC_OC_FAULT
Other
B
CPU_DPB_CTRL_CLK
CPU_DPB_CTRL_DATA
20191211
for TBT
TBT
[72]
AJ2
AJ1
DN4
DT6
eDP
CPU_DISP_HPDB
AC2
AC1
AD2
AD1
AF1
AF2
AG2
AG1
DM8
DN8
DG10
1 OF 21
DDIA_TXP3
DDIA_TXN3
DDIA_TXP2
DDIA_TXN2
DDIA_TXP1
DDIA_TXN1
DDIA_TXP0
DDIA_TXN0
TCP0_TXRX_P1
TCP0_TXRX_N1
TCP0_TXRX_P0
TCP0_TXRX_N0
TCP0_TX_P1
TCP0_TX_N1
TCP0_TX_P0
TCP0_TX_N0
TCP0_AUX_P
TCP0_AUX_N
DDIA_AUX_P
DDIA_AUX_N
TCP1_TXRX_P1
TCP1_TXRX_N1
TCP1_TXRX_P0
TCP1_TXRX_N0
TCP1_TX_P1
TCP1_TX_N1
TCP1_TX_P0
TCP1_TX_N0
TCP1_AUX_P
TCP1_AUX_N
GPP_E22/DDPA_CTRLCLK/DNX_FORCE_RELOAD
GPP_E23/DDPA_CTRLDATA
GPP_E14/DDSP_HPDA/DISP_MISCA
DDIB_TXP3
DDIB_TXN3
DDIB_TXP2
DDIB_TXN2
DDIB_TXP1
DDIB_TXN1
DDIB_TXP0
DDIB_TXN0
TCP2_TXRX_P1
TCP2_TXRX_N1
TCP2_TXRX_P0
TCP2_TXRX_N0
TCP2_TX_P1
TCP2_TX_N1
TCP2_TX_P0
TCP2_TX_N0
TCP2_AUX_P
TCP2_AUX_N
DDIB_AUX_P
DDIB_AUX_N
GPP_H16/DDPB_CTRLCLK/PCIE_LNK_DOWN
GPP_H17/DDPB_CTRLDATA
GPP_A18/DDSP_HPDB/DISP_MISCB/I2S4_RXD
TCP3_TXRX_P1
TCP3_TXRX_N1
TCP3_TXRX_P0
TCP3_TXRX_N0
TCP3_TX_P1
TCP3_TX_N1
TCP3_TX_P0
TCP3_TX_N0
TCP3_AUX_P
TCP3_AUX_N
GPP_A21/DDPC_CTRLCLK/I2S5_TXD
GPP_A22/DDPC_CTRLDATA/I2S5_RXD
GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD
GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD
GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD
GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD
GPP_D9/ISH_SPI_CS#/DDP3_CTRLCLK/TBT_LSX2_TXD/GSPI2_CS0#
GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/TBT_LSX2_RXD/GSPI2_CLK
TC_RCOMP_P
TC_RCOMP_N
GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/TBT_LSX3_TXD/GSPI2_MISO
GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/TBT_LSX3_RXD/GSPI2_MOSI
GPP_A17/DISP_MISCC/I2S4_TXD
GPP_A19/DDSP_HPD1/DISP_MISC1/I2S5_SCLK
GPP_A20/DDSP_HPD2/DISP_MISC2/I2S5_SFRM
DSI_DE_TE_2
DDI_RCOMP
DISP_UTILS/DSI_DE_TE_1
AY2
AY1
BB1
BB2
AM5
AM7
AT7
AT5
AP7
AP5
20191211
for TBT
USB1_TCSS_RX_P1
USB1_TCSS_RX_N1
USB1_TCSS_RX_P0
USB1_TCSS_RX_N0
USB1_TCSS_TX_P1
USB1_TCSS_TX_N1
USB1_TCSS_TX_P0
USB1_TCSS_TX_N0
USB1_TCSS_AUX_P
USB1_TCSS_AUX_N
TBT
AT2
AT1
AU1
AU2
AD5
AD7
AH7
AH5
AF7
AF5
BF1
BF2
BE2
BE1
BD7
BD5
AY5
AY7
BB5
BB7
C
BK1
BK2
BJ2
BJ1
BM7
BM5
BH5
BH7
BK5
BK7
AN2
AN1
TCSS_RCOMP_P
TCSS_RCOMP_N
R402 1
2 150R2F-1-GP
DISP_RCOMP
R401 1
2 150R2F-1-GP
M8
AB1
B
CE4
GPP_A14/USB_OC1#/DDSP_HPD3/I2S3_RXD/DISP_MISC3/DMIC_CLK_B1
GPP_A15/USB_OC2#/DDSP_HPD4/DISP_MISC4/I2S4_SCLK
EDP_VDDEN
EDP_BKLTEN
EDP_BKLTCTL
2
DY
TGL-U-1-GP-U2
100KR2J-1-GP
USB_OC1#
20191129
layout Request
3D3V_S0
RN402
2
1
3
4
Add RTC Gen 9 reset circuit_20170814
leakage issue 20191224
CPU_DPB_CTRL_CLK
CPU_DPB_CTRL_DATA
Follow Internal review
3D3V_S5_VCCPRIM
3D3V_S5_VCCPRIM
2 10KR2J-3-GP KB_DET#
1
R419 1
1
SRN2K2J-1-GP
R405
R406
RTC_RST10KR2J-3-GP
2
Q401
1
2
CPU_DISP_HPD1_P 3
Note:ZZ.27002.F7C01
3D3V_S5_VCCPRIM 20191211
Remove R422
USB_OC1#
2
R421 1
10KR2J-3-GP
20191224
Follow Internal review
CPU_DISP_HPD1_R
6
5
4
2N7002KDW -1-GP
https://realschematic.com
<Core Design>
2
RTC_RST10KR2J-3-GP
A
Wistron Corporation
75.27002.F7C
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2nd = 075.27002.0E7C
RTC_RST3rd = 075.67002.007C
4th = 075.07002.0A7C
Title
Size
A3
Date:
5
4
3
A
2
CPU (DDI/EDP/TBT/TPC/)
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
4
of
A00
105
5
4
3
Channel A
2
1
DDR4 ball type: Non-Interleaved Type
CPU1C
M_A_CLK#0
[12]
M_A_CLK0
[12]
M_A_CKE0
[12]
M_A_CKE1
[12]
M_A_DIMA_ODT0
[12]
M_A_DIMA_ODT1
[12]
[12]
M_A_CS#0
[12]
M_A_BA0
[12]
M_A_BA1
[12]
M_A_BG0
[12]
M_A_BG1
M_A_ACT_N
[12]
[12]
C
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
M_A_PARITY
M_A_ALERT_N
M_A_CLK1 [12]
M_A_CLK#1 [12]
M_A_CS#1
[12]
Channel B
M_B_DQS_DN0
M_B_DQS_DN1
M_B_DQS_DN2
M_B_DQS_DN3
M_B_DQS_DN4
M_B_DQS_DN5
M_B_DQS_DN6
M_B_DQS_DN7
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
M_B_DQS_DP0
M_B_DQS_DP1
M_B_DQS_DP2
M_B_DQS_DP3
M_B_DQS_DP4
M_B_DQS_DP5
M_B_DQS_DP6
M_B_DQS_DP7
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
M_B_CLK#0
[13]
[13]
M_B_CLK0
[13]
[13]
M_B_CKE1
[13]
M_B_CKE0
[13]
M_B_CS#0
[13]
M_B_BA0
[13]
M_B_BA1
[13]
M_B_BG0
[13]
M_B_BG1
M_B_DIMB_ODT0
M_B_DIMB_ODT1
[13]
M_B_ACT_N
[13]
M_B_PARITY
[13]
M_B_ALERT_N
M_B_CLK1 [13]
M_B_CLK#1 [13]
A
M_B_CS#1
[13]
DDR0_CS1/DDR1_CA1/DDR1_CA1/DDR1_CA5
DDR0_CS0/NC/DDR1_CS1/DDR1_CA4
NC/DDR0_CA0/DDR0_CA0/DDR0_CA6
NC/DDR0_CA1/DDR0_CA1/DDR0_CA5
NC/DDR2_CS0/DDR2_CA2/DDR2_CA2
NC/DDR3_CA5/DDR3_CA6/DDR3_CA0
NC/DDR3_CA4/DDR3_CA5/DDR3_CA1
NC/DDR3_CA3/DDR3_CA4/DDR3_CS1
NC/DDR3_CA2/DDR3_CA3/DDR3_CS0
DDR3_DQSP_1/DDR0_DQSP_7/DDR1_DQSP_3
DDR3_DQSN_1/DDR0_DQSN_7/DDR1_DQSN_3
DDR3_DQSP_0/DDR0_DQSP_6/DDR1_DQSP_2
DDR3_DQSN_0/DDR0_DQSN_6/DDR1_DQSN_2
DDR2_DQSP_1/DDR0_DQSP_5/DDR0_DQSP_3
DDR2_DQSN_1/DDR0_DQSN_5/DDR0_DQSN_3
DDR2_DQSP_0/DDR0_DQSP_4/DDR0_DQSP_2
DDR2_DQSN_0/DDR0_DQSN_4/DDR0_DQSN_2
DDR1_DQSP_1/DDR0_DQSP_3/DDR1_DQSP_1
DDR1_DQSN_1/DDR0_DQSN_3/DDR1_DQSN_1
DDR1_DQSP_0/DDR0_DQSP_2/DDR1_DQSP_0
DDR1_DQSN_0/DDR0_DQSN_2/DDR1_DQSN_0
DDR0_DQSP_1/DDR0_DQSP_1/DDR0_DQSP_1
DDR0_DQSN_1/DDR0_DQSN_1/DDR0_DQSN_1
DDR0_DQSP_0/DDR0_DQSP_0/DDR0_DQSP_0
DDR0_DQSN_0/DDR0_DQSN_0/DDR0_DQSN_0
DDR0_ODT1/DDR1_CA0/DDR1_CA0/DDR1_CA6
DDR1_ODT0/DDR1_CS0/DDR1_CA2/DDR1_CA2
DDR0_MA16/DDR1_CA4/DDR1_CA5/DDR1_CA1
DDR0_MA15/DDR1_CA3/DDR1_CA4/DDR1_CS1
DDR0_MA14/DDR1_CA2/DDR1_CA3/DDR1_CS0
DDR0_MA13/DDR1_CS1/DDR1_CS0/DDR1_CA3
DDR0_MA12/DDR2_CA1/DDR2_CA1/DDR2_CA5
DDR0_MA11/NC/DDR2_CS1/DDR2_CA4
DDR0_MA10/DDR3_CA1/DDR3_CA1/DDR3_CA5
DDR0_MA9/DDR2_CA0/DDR2_CA0/DDR2_CA6
DDR0_MA8/DDR0_CA2/DDR0_CA3/DDR0_CS0
DDR0_MA7/DDR0_CA4/DDR0_CA5/DDR0_CA1
DDR0_MA6/DDR0_CA3/DDR0_CA4/DDR0_CS1
DDR0_MA5/DDR0_CA5/DDR0_CA6/DDR0_CA0
DDR0_MA4/DDR0_CS0/DDR0_CA2/DDR0_CA2
DDR0_MA3/DDR0_CS1/DDR0_CS0/DDR0_CA3
DDR0_MA2/DDR3_CS0/DDR3_CA2/DDR3_CA2
DDR0_MA1/NC/DDR0_CS1/DDR0_CA4
DDR0_MA0/NC/DDR3_CS1/DDR3_CA4
DDR0_BG1/DDR2_CA2/DDR2_CA3/DDR2_CS0
DDR0_BG0/DDR2_CA3/DDR2_CA4/DDR2_CS1
DDR0_BA1/DDR1_CA5/DDR1_CA6/DDR1_CA0
DDR0_BA0/DDR3_CA0/DDR3_CA0/DDR3_CA6
DDR0_ACT#/DDR2_CS1/DDR2_CS0/DDR2_CA3
DDR0_PAR/DDR3_CS1/DDR3_CS0/DDR3_CA3
DDR0_ALERT#
DDR0_VREF_CA
DDR_VTT_CTL
DRAM_RESET#
DDR_RCOMP
M_A_CLK0
M_A_CLK#0
BT45
BT47
BN51
BN53
CD45
CD47
CA51
CA53
BU52
BL50
M_A_CKE1
M_A_CKE0
CF42
CF47
M_A_CS#1
M_A_CS#0
CE53
CE50
BL53
BP47
BP42
BP45
BP44
BB44
BD44
BK44
BH44
BA51
BA50
BG51
BG50
CK44
CM44
CT44
CV44
CK51
CK50
CR51
CR50
M_A_DQS_DP7
M_A_DQS_DN7
M_A_DQS_DP6
M_A_DQS_DN6
M_A_DQS_DP5
M_A_DQS_DN5
M_A_DQS_DP4
M_A_DQS_DN4
M_A_DQS_DP3
M_A_DQS_DN3
M_A_DQS_DP2
M_A_DQS_DN2
M_A_DQS_DP1
M_A_DQS_DN1
M_A_DQS_DP0
M_A_DQS_DN0
CF44
CF45
M_A_DIMA_ODT1
M_A_DIMA_ODT0
CB47
CB44
CB45
CF41
BU53
BT51
BV42
BU50
BY53
CA50
BY52
BY50
CD51
CD53
BV47
CE52
BV41
M_A_A16
M_A_A15
M_A_A14
M_A_A13
M_A_A12
M_A_A11
M_A_A10
M_A_A9
M_A_A8
M_A_A7
M_A_A6
M_A_A5
M_A_A4
M_A_A3
M_A_A2
M_A_A1
M_A_A0
BN50
BL52
M_A_BG1
M_A_BG0
CB42
BV44
AL53
AL52 DDR4_DQ0_7/DDR1_DQ0_7/DDR0_DQ4_7
AL50 DDR4_DQ0_6/DDR1_DQ0_6/DDR0_DQ4_6
AL49 DDR4_DQ0_5/DDR1_DQ0_5/DDR0_DQ4_5
AP53 DDR4_DQ0_4/DDR1_DQ0_4/DDR0_DQ4_4
AP52 DDR4_DQ0_3/DDR1_DQ0_3/DDR0_DQ4_3
AP50 DDR4_DQ0_2/DDR1_DQ0_2/DDR0_DQ4_2
AP49 DDR4_DQ0_1/DDR1_DQ0_1/DDR0_DQ4_1
AF53 DDR4_DQ0_0/DDR1_DQ0_0/DDR0_DQ4_0
AF52 DDR4_DQ1_7/DDR1_DQ1_7/DDR0_DQ5_7
AF50 DDR4_DQ1_6/DDR1_DQ1_6/DDR0_DQ5_6
AF49 DDR4_DQ1_5/DDR1_DQ1_5/DDR0_DQ5_5
AH53 DDR4_DQ1_4/DDR1_DQ1_4/DDR0_DQ5_4
AH52 DDR4_DQ1_3/DDR1_DQ1_3/DDR0_DQ5_3
AH50 DDR4_DQ1_2/DDR1_DQ1_2/DDR0_DQ5_2
AH49 DDR4_DQ1_1/DDR1_DQ1_1/DDR0_DQ5_1
AR41 DDR4_DQ1_0/DDR1_DQ1_0/DDR0_DQ5_0
AV42 DDR5_DQ0_7/DDR1_DQ2_7/DDR1_DQ4_7
AR42 DDR5_DQ0_6/DDR1_DQ2_6/DDR1_DQ4_6
AV41 DDR5_DQ0_5/DDR1_DQ2_5/DDR1_DQ4_5
AR45 DDR5_DQ0_4/DDR1_DQ2_4/DDR1_DQ4_4
AV45 DDR5_DQ0_3/DDR1_DQ2_3/DDR1_DQ4_3
AR47 DDR5_DQ0_2/DDR1_DQ2_2/DDR1_DQ4_2
AV47 DDR5_DQ0_1/DDR1_DQ2_1/DDR1_DQ4_1
AJ41 DDR5_DQ0_0/DDR1_DQ2_0/DDR1_DQ4_0
AJ42 DDR5_DQ1_7/DDR1_DQ3_7/DDR1_DQ5_7
AL41 DDR5_DQ1_6/DDR1_DQ3_6/DDR1_DQ5_6
AL42 DDR5_DQ1_5/DDR1_DQ3_5/DDR1_DQ5_5
AJ45 DDR5_DQ1_4/DDR1_DQ3_4/DDR1_DQ5_4
AJ47 DDR5_DQ1_3/DDR1_DQ3_3/DDR1_DQ5_3
AL45 DDR5_DQ1_2/DDR1_DQ3_2/DDR1_DQ5_2
AL47 DDR5_DQ1_1/DDR1_DQ3_1/DDR1_DQ5_1
A43 DDR5_DQ1_0/DDR1_DQ3_0/DDR1_DQ5_0
B43 DDR6_DQ0_7/DDR1_DQ4_7/DDR0_DQ6_7
D43 DDR6_DQ0_6/DDR1_DQ4_6/DDR0_DQ6_6
E44 DDR6_DQ0_5/DDR1_DQ4_5/DDR0_DQ6_5
A46 DDR6_DQ0_4/DDR1_DQ4_4/DDR0_DQ6_4
B46 DDR6_DQ0_3/DDR1_DQ4_3/DDR0_DQ6_3
D46 DDR6_DQ0_2/DDR1_DQ4_2/DDR0_DQ6_2
E47 DDR6_DQ0_1/DDR1_DQ4_1/DDR0_DQ6_1
E38 DDR6_DQ0_0/DDR1_DQ4_0/DDR0_DQ6_0
D38 DDR6_DQ1_7/DDR1_DQ5_7/DDR0_DQ7_7
B38 DDR6_DQ1_6/DDR1_DQ5_6/DDR0_DQ7_6
A38 DDR6_DQ1_5/DDR1_DQ5_5/DDR0_DQ7_5
E41 DDR6_DQ1_4/DDR1_DQ5_4/DDR0_DQ7_4
D40 DDR6_DQ1_3/DDR1_DQ5_3/DDR0_DQ7_3
B40 DDR6_DQ1_2/DDR1_DQ5_2/DDR0_DQ7_2
A40 DDR6_DQ1_1/DDR1_DQ5_1/DDR0_DQ7_1
G42 DDR6_DQ1_0/DDR1_DQ5_0/DDR0_DQ7_0
G41 DDR7_DQ0_7/DDR1_DQ6_7/DDR1_DQ6_7
J41 DDR7_DQ0_6/DDR1_DQ6_6/DDR1_DQ6_6
J42 DDR7_DQ0_5/DDR1_DQ6_5/DDR1_DQ6_5
G45 DDR7_DQ0_4/DDR1_DQ6_4/DDR1_DQ6_4
J45 DDR7_DQ0_3/DDR1_DQ6_3/DDR1_DQ6_3
G47 DDR7_DQ0_2/DDR1_DQ6_2/DDR1_DQ6_2
J47 DDR7_DQ0_1/DDR1_DQ6_1/DDR1_DQ6_1
G38 DDR7_DQ0_0/DDR1_DQ6_0/DDR1_DQ6_0
G36 DDR7_DQ1_7/DDR1_DQ7_7/DDR1_DQ7_7
H36 DDR7_DQ1_6/DDR1_DQ7_6/DDR1_DQ7_6
H38 DDR7_DQ1_5/DDR1_DQ7_5/DDR1_DQ7_5
N36 DDR7_DQ1_4/DDR1_DQ7_4/DDR1_DQ7_4
L36 DDR7_DQ1_3/DDR1_DQ7_3/DDR1_DQ7_3
DDR7_DQ1_2/DDR1_DQ7_2/DDR1_DQ7_2
L38 TGL-U-1-GP-U2
N38 DDR7_DQ1_1/DDR1_DQ7_1/DDR1_DQ7_1
DDR7_DQ1_0/DDR1_DQ7_0/DDR1_DQ7_0
NC/DDR7_CKE0/DDR7_WCK_P/DDR7_WCK_P
NC/DDR7_CKE1/DDR7_WCK_N/DDR7_WCK_N
NC/DDR6_CKE0/DDR6_WCK_P/DDR6_WCK_P
NC/DDR6_CKE1/DDR6_WCK_N/DDR6_WCK_N
NC/DDR5_CKE0/DDR5_WCK_P/DDR5_WCK_P
NC/DDR5_CKE1/DDR5_WCK_N/DDR5_WCK_N
NC/DDR4_CKE0/DDR4_WCK_P/DDR4_WCK_P
NC/DDR4_CKE1/DDR4_WCK_N/DDR4_WCK_N
DDR1_CKE1/DDR6_CA4/DDR6_CA5/DDR6_CA1
DDR1_CKE0/DDR6_CA5/DDR6_CA6/DDR6_CA0
DDR1_CS1/DDR5_CA1/DDR5_CA1/DDR5_CA5
DDR1_CS0/NC/DDR5_CS1/DDR5_CA4
NC/DDR7_CA5/DDR7_CA6/DDR7_CA0
NC/DDR7_CA4/DDR7_CA5/DDR7_CA1
NC/DDR7_CA3/DDR7_CA4/DDR7_CS1
NC/DDR7_CA2/DDR7_CA3/DDR7_CS0
NC/DDR6_CS0/DDR6_CA2/DDR6_CA2
NC/DDR4_CA1/DDR4_CA1/DDR4_CA5
NC/DDR4_CA0/DDR4_CA0/DDR4_CA6
DDR7_DQSP_1/DDR1_DQSP_7/DDR1_DQSP_7
DDR7_DQSN_1/DDR1_DQSN_7/DDR1_DQSN_7
DDR7_DQSP_0/DDR1_DQSP_6/DDR1_DQSP_6
DDR7_DQSN_0/DDR1_DQSN_6/DDR1_DQSN_6
DDR6_DQSP_1/DDR1_DQSP_5/DDR0_DQSP_7
DDR6_DQSN_1/DDR1_DQSN_5/DDR0_DQSN_7
DDR6_DQSP_0/DDR1_DQSP_4/DDR0_DQSP_6
DDR6_DQSN_0/DDR1_DQSN_4/DDR0_DQSN_6
DDR5_DQSP_1/DDR1_DQSP_3/DDR1_DQSP_5
DDR5_DQSN_1/DDR1_DQSN_3/DDR1_DQSN_5
DDR5_DQSP_0/DDR1_DQSP_2/DDR1_DQSP_4
DDR5_DQSN_0/DDR1_DQSN_2/DDR1_DQSN_4
DDR4_DQSP_1/DDR1_DQSP_1/DDR0_DQSP_5
DDR4_DQSN_1/DDR1_DQSN_1/DDR0_DQSN_5
DDR4_DQSP_0/DDR1_DQSP_0/DDR0_DQSP_4
DDR4_DQSN_0/DDR1_DQSN_0/DDR0_DQSN_4
DDR1_ODT1/DDR5_CA0/DDR5_CA0/DDR5_CA6
DDR1_ODT0/DDR5_CS0/DDR5_CA2/DDR5_CA2
DDR1_MA16/DDR5_CA4/DDR5_CA5/DDR5_CA1
DDR1_MA15/DDR5_CA3/DDR5_CA4/DDR5_CS1
DDR1_MA14/DDR5_CA2/DDR5_CA3/DDR5_CS0
DDR1_MA13/DDR5_CS1/DDR5_CS0/DDR5_CA3
DDR1_MA12/DDR6_CA1/DDR6_CA1/DDR6_CA5
DDR1_MA11/NC/DDR6_CS1/DDR6_CA4
DDR1_MA10/DDR7_CA1/DDR7_CA1/DDR7_CA5
DDR1_MA9/DDR6_CA0/DDR6_CA0/DDR6_CA6
DDR1_MA8/DDR4_CA2/DDR4_CA3/DDR4_CS0
DDR1_MA7/DDR4_CA4/DDR4_CA5/DDR4_CA1
DDR1_MA6/DDR4_CA3/DDR4_CA4/DDR4_CS1
DDR1_MA5/DDR4_CA5/DDR4_CA6/DDR4_CA0
DDR1_MA4/DDR4_CS0/DDR4_CA2/DDR4_CA2
DDR1_MA3/DDR4_CS1/DDR4_CS0/DDR4_CA3
DDR1_MA2/DDR7_CS0/DDR7_CA2/DDR7_CA2
DDR1_MA1/NC/DDR4_CS1/DDR4_CA4
DDR1_MA0/NC/DDR7_CS1/DDR7_CA4
DDR1_BG1/DDR6_CA2/DDR6_CA3/DDR6_CS0
DDR1_BG0/DDR6_CA3/DDR6_CA4/DDR6_CS1
DDR1_BA1/DDR5_CA5/DDR5_CA6/DDR5_CA0
DDR1_BA0/DDR7_CA0/DDR7_CA0/DDR7_CA6
M_A_BA1
M_A_BA0
BT53
M_A_ACT_N
DDR1_ACT#/DDR6_CS1/DDR6_CS0/DDR6_CA3
BV45
M_A_PARITY
DDR1_PAR/DDR7_CS1/DDR7_CS0/DDR7_CA3
AU50
AU49
M_A_ALERT_N
V_SM_VREF_CNTA
E52
DV47
C49
VTT_CNTL_CPU
SM_DRAMRST#_CPU
SM_RCOMP
R502
DDR1_ALERT#
DDR1_VREF_CA
1
M_B_CLK1
M_B_CLK#1
R41
R42
M52
M53
AC42
AC41
Y52
Y53
M_B_CLK0
M_B_CLK#0
R47
R45
K51
K53
AC47
AC45
W51
W53
D
P52
J50
M_B_CKE1
M_B_CKE0
AE42
AE47
M_B_CS#1
M_B_CS#0
N42
N45
N44
N47
J53
AC50
AC53
K36
K38
G44
J44
D39
C39
C45
D45
AJ44
AL44
AV44
AR44
AG51
AG50
AN51
AN50
M_B_DQS_DP7
M_B_DQS_DN7
M_B_DQS_DP6
M_B_DQS_DN6
M_B_DQS_DP5
M_B_DQS_DN5
M_B_DQS_DP4
M_B_DQS_DN4
M_B_DQS_DP3
M_B_DQS_DN3
M_B_DQS_DP2
M_B_DQS_DN2
M_B_DQS_DP1
M_B_DQS_DN1
M_B_DQS_DP0
M_B_DQS_DN0
AE44
AE45
M_B_DIMB_ODT1
M_B_DIMB_ODT0
AA47
AA44
AA45
AE41
P53
N51
U42
P50
U53
W50
U52
U50
AA51
AA53
U47
AC52
U41
M_B_A16
M_B_A15
M_B_A14
M_B_A13
M_B_A12
M_B_A11
M_B_A10
M_B_A9
M_B_A8
M_B_A7
M_B_A6
M_B_A5
M_B_A4
M_B_A3
M_B_A2
M_B_A1
M_B_A0
K50
J52
M_B_BG1
M_B_BG0
AA42
U44
M_B_BA1
M_B_BA0
N53
M_B_ACT_N
U45
M_B_PARITY
AU53
AU52
M_B_ALERT_N
V_SM_VREF_CNTB
C
2 100R2F-L1-GP-U
B
3D3V_S5
1D2V_S3
3D3V_S0
R508
10KR2J-3-GP
Q501
VTT_CNTL_CPU
G
Q502_G
D
R510
470R2F-GP
SM_DRAMRST#_CPU
R520
10KR2J-3-GP
Q502
2N7002K-2-GP
G
S
D
VTT_CNTL
DY
S
PJA138KA-GP
084.00138.0A31
1 R511 2 DDR4_DRAMRST#
0R0402-PAD-7-NP-GP
Notice:ZZ.2N702.J3101
2nd = 084.01012.0031
84.2N702.J31
2ND = 084.27002.0N31
3rd = 084.27002.0L31
4th = 084.07002.0C31
C501
SCD1U16V2KX-3DLGP
M_B_DQS_DP0
M_B_DQS_DP1
M_B_DQS_DP2
M_B_DQS_DP3
M_B_DQS_DP4
M_B_DQS_DP5
M_B_DQS_DP6
M_B_DQS_DP7
M_B_DQS_DN0
M_B_DQS_DN1
M_B_DQS_DN2
M_B_DQS_DN3
M_B_DQS_DN4
M_B_DQS_DN5
M_B_DQS_DN6
M_B_DQS_DN7
DDR0_CKE1/DDR2_CA4/DDR2_CA5/DDR2_CA1
DDR0_CKE0/DDR2_CA5/DDR2_CA6/DDR2_CA0
M_A_CLK1
M_A_CLK#1
1
B
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
[13]
NC/DDR3_CKE0/DDR3_WCK_P/DDR3_WCK_P
NC/DDR3_CKE1/DDR3_WCK_N/DDR3_WCK_N
NC/DDR2_CKE0/DDR2_WCK_P/DDR2_WCK_P
NC/DDR2_CKE1/DDR2_WCK_N/DDR2_WCK_N
NC/DDR1_CKE0/DDR1_WCK_P/DDR1_WCK_P
NC/DDR1_CKE1/DDR1_WCK_N/DDR1_WCK_N
NC/DDR0_CKE0/DDR0_WCK_P/DDR0_WCK_P
NC/DDR0_CKE1/DDR0_WCK_N/DDR0_WCK_N
BT42
BT41
BP52
BP53
CD42
CD41
CC52
CC53
1
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_A16
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ15
M_B_DQ14
M_B_DQ12
M_B_DQ13
M_B_DQ10
M_B_DQ11
M_B_DQ22
M_B_DQ17
M_B_DQ21
M_B_DQ19
M_B_DQ18
M_B_DQ16
M_B_DQ20
M_B_DQ23
M_B_DQ30
M_B_DQ27
M_B_DQ29
M_B_DQ31
M_B_DQ25
M_B_DQ28
M_B_DQ24
M_B_DQ26
M_B_DQ35
M_B_DQ38
M_B_DQ36
M_B_DQ37
M_B_DQ34
M_B_DQ39
M_B_DQ32
M_B_DQ33
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ47
M_B_DQ44
M_B_DQ45
M_B_DQ43
M_B_DQ46
M_B_DQ52
M_B_DQ51
M_B_DQ55
M_B_DQ49
M_B_DQ54
M_B_DQ48
M_B_DQ50
M_B_DQ53
M_B_DQ63
M_B_DQ62
M_B_DQ57
M_B_DQ56
M_B_DQ58
M_B_DQ59
M_B_DQ61
M_B_DQ60
M_B_DQ7
M_B_DQ6
M_B_DQ5
M_B_DQ4
M_B_DQ3
M_B_DQ2
M_B_DQ1
M_B_DQ0
M_B_DQ15
M_B_DQ14
M_B_DQ13
M_B_DQ12
M_B_DQ11
M_B_DQ10
M_B_DQ9
M_B_DQ8
M_B_DQ23
M_B_DQ22
M_B_DQ21
M_B_DQ20
M_B_DQ19
M_B_DQ18
M_B_DQ17
M_B_DQ16
M_B_DQ31
M_B_DQ30
M_B_DQ29
M_B_DQ28
M_B_DQ27
M_B_DQ26
M_B_DQ25
M_B_DQ24
M_B_DQ39
M_B_DQ38
M_B_DQ37
M_B_DQ36
M_B_DQ35
M_B_DQ34
M_B_DQ33
M_B_DQ32
M_B_DQ47
M_B_DQ46
M_B_DQ45
M_B_DQ44
M_B_DQ43
M_B_DQ42
M_B_DQ41
M_B_DQ40
M_B_DQ55
M_B_DQ54
M_B_DQ53
M_B_DQ52
M_B_DQ51
M_B_DQ50
M_B_DQ49
M_B_DQ48
M_B_DQ63
M_B_DQ62
M_B_DQ61
M_B_DQ60
M_B_DQ59
M_B_DQ58
M_B_DQ57
M_B_DQ56
DDR4/LP4/LP5/LP5 CMD Flip
DDR0_CLK_P1/DDR3_CLK_P/DDR3_CLK_P/DDR3_CLK_P
DDR0_CLK_N1/DDR3_CLK_N/DDR3_CLK_N/DDR3_CLK_N
NC/DDR2_CLK_P/DDR2_CLK_P/DDR2_CLK_P
NC/DDR2_CLK_N/DDR2_CLK_N/DDR2_CLK_N
NC/DDR1_CLK_P/DDR1_CLK_P/DDR1_CLK_P
NC/DDR1_CLK_N/DDR1_CLK_N/DDR1_CLK_N
DDR0_CLK_P0/DDR0_CLK_P/DDR0_CLK_P/DDR0_CLK_P
DDR0_CLK_N0/DDR0_CLK_N/DDR0_CLK_N/DDR0_CLK_N
DDR4/LP4/LP5/LP5 CMD
Flip
DDR1_CLK_P1/DDR7_CLK_P/DDR7_CLK_P/DDR7_CLK_P
DDR1_CLK_N1/DDR7_CLK_N/DDR7_CLK_N/DDR7_CLK_N
NC/DDR6_CLK_P/DDR6_CLK_P/DDR6_CLK_P
NC/DDR6_CLK_N/DDR6_CLK_N/DDR6_CLK_N
NC/DDR5_CLK_P/DDR5_CLK_P/DDR5_CLK_P
NC/DDR5_CLK_N/DDR5_CLK_N/DDR5_CLK_N
DDR1_CLK_P0/DDR4_CLK_P/DDR4_CLKP/DDR4_CLK_P
DDR1_CLK_N0/DDR4_CLK_N/DDR4_CLK_N/DDR4_CLK_N
1
[12]
M_A_DQS_DN0
M_A_DQS_DN1
M_A_DQS_DN2
M_A_DQS_DN3
M_A_DQS_DN4
M_A_DQS_DN5
M_A_DQS_DN6
M_A_DQS_DN7
LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL)
CP53
CP52 DDR0_DQ0_7/DDR0_DQ0_7/DDR0_DQ0_7
CP50 DDR0_DQ0_6/DDR0_DQ0_6/DDR0_DQ0_6
CP49 DDR0_DQ0_5/DDR0_DQ0_5/DDR0_DQ0_5
CU53 DDR0_DQ0_4/DDR0_DQ0_4/DDR0_DQ0_4
CU52 DDR0_DQ0_3/DDR0_DQ0_3/DDR0_DQ0_3
CU50 DDR0_DQ0_2/DDR0_DQ0_2/DDR0_DQ0_2
CU49 DDR0_DQ0_1/DDR0_DQ0_1/DDR0_DQ0_1
CH53 DDR0_DQ0_0/DDR0_DQ0_0/DDR0_DQ0_0
CH52 DDR0_DQ1_7/DDR0_DQ1_7/DDR0_DQ1_7
CH50 DDR0_DQ1_6/DDR0_DQ1_6/DDR0_DQ1_6
CH49 DDR0_DQ1_5/DDR0_DQ1_5/DDR0_DQ1_5
CL53 DDR0_DQ1_4/DDR0_DQ1_4/DDR0_DQ1_4
CL52 DDR0_DQ1_3/DDR0_DQ1_3/DDR0_DQ1_3
CL50 DDR0_DQ1_2/DDR0_DQ1_2/DDR0_DQ1_2
CL49 DDR0_DQ1_1/DDR0_DQ1_1/DDR0_DQ1_1
CT47 DDR0_DQ1_0/DDR0_DQ1_0/DDR0_DQ1_0
CV47 DDR1_DQ0_7/DDR0_DQ2_7/DDR1_DQ0_7
CT45 DDR1_DQ0_6/DDR0_DQ2_6/DDR1_DQ0_6
CV45 DDR1_DQ0_5/DDR0_DQ2_5/DDR1_DQ0_5
CT42 DDR1_DQ0_4/DDR0_DQ2_4/DDR1_DQ0_4
CV42 DDR1_DQ0_3/DDR0_DQ2_3/DDR1_DQ0_3
CT41 DDR1_DQ0_2/DDR0_DQ2_2/DDR1_DQ0_2
CV41 DDR1_DQ0_1/DDR0_DQ2_1/DDR1_DQ0_1
CK47 DDR1_DQ0_0/DDR0_DQ2_0/DDR1_DQ0_0
CM47 DDR1_DQ1_7/DDR0_DQ3_7/DDR1_DQ1_7
CK45 DDR1_DQ1_6/DDR0_DQ3_6/DDR1_DQ1_6
CM45 DDR1_DQ1_5/DDR0_DQ3_5/DDR1_DQ1_5
CK42 DDR1_DQ1_4/DDR0_DQ3_4/DDR1_DQ1_4
CM42 DDR1_DQ1_3/DDR0_DQ3_3/DDR1_DQ1_3
CM41 DDR1_DQ1_2/DDR0_DQ3_2/DDR1_DQ1_2
CK41 DDR1_DQ1_1/DDR0_DQ3_1/DDR1_DQ1_1
BF53 DDR1_DQ1_0/DDR0_DQ3_0/DDR1_DQ1_0
BF52 DDR2_DQ0_7/DDR0_DQ4_7/DDR0_DQ2_7
BF50 DDR2_DQ0_6/DDR0_DQ4_6/DDR0_DQ2_6
BF49 DDR2_DQ0_5/DDR0_DQ4_5/DDR0_DQ2_5
BH53 DDR2_DQ0_4/DDR0_DQ4_4/DDR0_DQ2_4
BH52 DDR2_DQ0_3/DDR0_DQ4_3/DDR0_DQ2_3
BH50 DDR2_DQ0_2/DDR0_DQ4_2/DDR0_DQ2_2
BH49 DDR2_DQ0_1/DDR0_DQ4_1/DDR0_DQ2_1
AY53 DDR2_DQ0_0/DDR0_DQ4_0/DDR0_DQ2_0
AY52 DDR2_DQ1_7/DDR0_DQ5_7/DDR0_DQ3_7
AY50 DDR2_DQ1_6/DDR0_DQ5_6/DDR0_DQ3_6
AY49 DDR2_DQ1_5/DDR0_DQ5_5/DDR0_DQ3_5
BC53 DDR2_DQ1_4/DDR0_DQ5_4/DDR0_DQ3_4
BC52 DDR2_DQ1_3/DDR0_DQ5_3/DDR0_DQ3_3
BC50 DDR2_DQ1_2/DDR0_DQ5_2/DDR0_DQ3_2
BC49 DDR2_DQ1_1/DDR0_DQ5_1/DDR0_DQ3_1
BK47 DDR2_DQ1_0/DDR0_DQ5_0/DDR0_DQ3_0
BK45 DDR3_DQ0_7/DDR0_DQ6_7/DDR1_DQ2_7
BH47 DDR3_DQ0_6/DDR0_DQ6_6/DDR1_DQ2_6
BH45 DDR3_DQ0_5/DDR0_DQ6_5/DDR1_DQ2_5
BH42 DDR3_DQ0_4/DDR0_DQ6_4/DDR1_DQ2_4
BK42 DDR3_DQ0_3/DDR0_DQ6_3/DDR1_DQ2_3
BK41 DDR3_DQ0_2/DDR0_DQ6_2/DDR1_DQ2_2
BH41 DDR3_DQ0_1/DDR0_DQ6_1/DDR1_DQ2_1
BD47 DDR3_DQ0_0/DDR0_DQ6_0/DDR1_DQ2_0
BB47 DDR3_DQ1_7/DDR0_DQ7_7/DDR1_DQ3_7
BD45 DDR3_DQ1_6/DDR0_DQ7_6/DDR1_DQ3_6
BB45 DDR3_DQ1_5/DDR0_DQ7_5/DDR1_DQ3_5
BB42 DDR3_DQ1_4/DDR0_DQ7_4/DDR1_DQ3_4
BB41 DDR3_DQ1_3/DDR0_DQ7_3/DDR1_DQ3_3
DDR3_DQ1_2/DDR0_DQ7_2/DDR1_DQ3_2
BD42 TGL-U-1-GP-U2
BD41 DDR3_DQ1_1/DDR0_DQ7_1/DDR1_DQ3_1
DDR3_DQ1_0/DDR0_DQ7_0/DDR1_DQ3_0
LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL)
2
M_A_DQS_DN0
M_A_DQS_DN1
M_A_DQS_DN2
M_A_DQS_DN3
M_A_DQS_DN4
M_A_DQS_DN5
M_A_DQS_DN6
M_A_DQS_DN7
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
M_A_DQ7
M_A_DQ6
M_A_DQ5
M_A_DQ4
M_A_DQ3
M_A_DQ2
M_A_DQ1
M_A_DQ0
M_A_DQ15
M_A_DQ14
M_A_DQ13
M_A_DQ12
M_A_DQ11
M_A_DQ10
M_A_DQ9
M_A_DQ8
M_A_DQ23
M_A_DQ22
M_A_DQ21
M_A_DQ20
M_A_DQ19
M_A_DQ18
M_A_DQ17
M_A_DQ16
M_A_DQ31
M_A_DQ30
M_A_DQ29
M_A_DQ28
M_A_DQ27
M_A_DQ26
M_A_DQ25
M_A_DQ24
M_A_DQ39
M_A_DQ38
M_A_DQ37
M_A_DQ36
M_A_DQ35
M_A_DQ34
M_A_DQ33
M_A_DQ32
M_A_DQ47
M_A_DQ46
M_A_DQ45
M_A_DQ44
M_A_DQ43
M_A_DQ42
M_A_DQ41
M_A_DQ40
M_A_DQ55
M_A_DQ54
M_A_DQ53
M_A_DQ52
M_A_DQ51
M_A_DQ50
M_A_DQ49
M_A_DQ48
M_A_DQ63
M_A_DQ62
M_A_DQ61
M_A_DQ60
M_A_DQ59
M_A_DQ58
M_A_DQ57
M_A_DQ56
3 OF 21
2 OF 21
2
M_A_DQS_DP0
M_A_DQS_DP1
M_A_DQS_DP2
M_A_DQS_DP3
M_A_DQS_DP4
M_A_DQS_DP5
M_A_DQS_DP6
M_A_DQS_DP7
CPU1B
1
M_A_DQS_DP0
M_A_DQS_DP1
M_A_DQS_DP2
M_A_DQS_DP3
M_A_DQS_DP4
M_A_DQS_DP5
M_A_DQS_DP6
M_A_DQS_DP7
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
2
D
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
2
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_A16
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
[12]
V_SM_VREF_CNTA
[13]
V_SM_VREF_CNTB
[51]
Title
VTT_CNTL
https://realschematic.com
[12,13]
DDR4_DRAMRST#
Size
A2
Date:
5
4
3
2
CPU (DDR)
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
5
of
A00
105
5
4
3
CPU1T
2
1
20 OF 21
1D05V_VCCIO_OUT
RN603
D
CFG14
1
2
BPM_N0
BPM_N1
4
3
CFG11
CFG10
CFG9
SRN10KJ-5-GP
RN602
1
2
BPM_N2
BPM_N3
4
3
CFG7
XDP
SRN10KJ-5-GP
CFG4
CFG3
CFG2
CFG1
T15
V17
U15
K11
K12
K9
T17
K7
H7
K8
H9
E6
H5
E9
D9
E7
CFG_RCOMP B5
CFG_RCOMP
R605 1
2 49D9R2F-GP
U17
H11
607872 Ver0.9 page350 Required
TP601
1
BPM_N3
BPM_N2
BPM_N1
BPM_N0
Y1
M4
AB4
Y2
A3
B3
R601 1
C
2 2K2R2F-GP
TCP_MBIAS_RCOMP
AR2
AL10
AM12
AH12
AJ10
AR1
BN10
BM12
DD13
DF13
CFG15
CFG14
CFG13
CFG12
CFG11
CFG10
CFG9
CFG8
CFG7
CFG6
CFG5
CFG4
CFG3
CFG2
CFG1
CFG0
RSVD_TP#A51
RSVD_TP#B51
RSVD_TP#C1
RSVD_TP#D2
RSVD_TP#CP39
RSVD_TP#CU40
RSVD#AK9
RSVD#AH9
RSVD#DW6
RSVD#DV6
RSVD_TP#DV4
RSVD_TP#DW3
CFG_RCOMP
RSVD_TP#DU1
RSVD_TP#DT2
CFG17
CFG16
RSVD_TP#DW2
RSVD_TP#DV2
BPM#_3
BPM#_2
BPM#_1
BPM#_0
RSVD_TP#E1
RSVD_TP#F1
RSVD#A3
RSVD#B3
RSVD#AB2
RSVD_TP#DR1
RSVD_TP#DR2
RSVD_TP#AR2
RSVD_TP#AL10
RSVD_TP#AM12
RSVD_TP#AH12
RSVD_TP#AJ10
RSVD_TP#AR1
RSVD_TP#DR53
RSVD_TP#DW5
VSS
TP#DW52
TP#DV53
RSVD#W34
RSVD#V35
RSVD#BN10
RSVD#BM12
RSVD#DD13
RSVD#DF13
SKTOCC#
1D05V_VCCIO_OUT
R617
1
DY
20191112 modify
Follow Nakia
20200304
Follow Nakia DY R621
1KR2J-1-GP
2
CFG14
R618 1
2 1KR2J-1-GP CFG11
R619 1
2 1KR2J-1-GP CFG10
R620 1
2 1KR2J-1-GP CFG9
R621 1
R625 1
DY
A51
B51
TP_RSVD_A51
TP_RSVD_B51
1
1
TP607
TP608
C1
D2
TP_RSVD_C1
TP_RSVD_D2
1
1
TP609
TP610
TP_RSVD_DW 3
1
TP606
DW2
DV2
TP_RSVD_DW 2
TP_RSVD_DV2
1
1
TP604
TP605
E1
F1
TP_RSVD_E1
TP_RSVD_F1
1
1
TP611
TP612
D
607872 Ver0.9 page350 recommend
CP39
CU40
AK9
AH9
DW6
DV6
DV4
DW3
DU1
DT2
AB2
DR1
DR2
C
DR53
DW5
DV51
DW52
DV53
W34
V35
TP_RSVD_DW 52 1
TP_RSVD_DV53 1
TP602
TP603
D52
TGL-U-1-GP-U2
607872 Ver0.9 page350 Required
2 1KR2J-1-GP CFG7
2 1KR2J-1-GP CFG3
B
B
R626 1
2 1KR2J-1-GP CFG2
R627 1
2 1KR2J-1-GP CFG1
CFG14
R606 1
CFG4
R607 1
CFG7
R608 1
DY
2 1KR2J-1-GP
2 1KR2J-1-GP
DY
2 1KR2J-1-GP
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A3
Date:
5
4
3
2
CPU (CFG/IST)
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
6
of
A00
105
VSSCORE_SENSE
[46]
SVID_ALERT#_CPU
[46]
SVID_CLK_CPU
[46]
SVID_DATA_CPU
A
https://realschematic.com
1V_CPU_CORE
A24
A26
A29
A30
A33
A35
AY39
B24
B26
B29
B30
B33
B35
BA10
BA40
BB39
BB9
BC10
BC40
BD39
BD9
BE10
BE40
BF9
BG10
BG40
BH12
BH39
BH9
BJ10
BJ40
BK39
BL10
BL40
BM39
BN40
BP12
BP39
BR10
BR40
BT12
BT39
BU10
BU40
BV12
BY12
CA10
CB12
D24
D26
D29
D30
D33
D35
E24
E26
E27
E29
E30
E32
E33
G2
G24
G26
G30
1V_CPU_CORE
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN_SENSE
VSSIN_SENSE
VIDSOUT
VIDSCK
VIDALERT#
R703 1
20191112 modify
Follow Nakia
20200311(DVT1)
R701 change to 56R follow INTEL PDG
2 100R2F-L1-GP-U SVID_DATA_CPU
R701 1
256R2F-1-GP
1D05V_VCCST
G32
H24
H26
H30
H32
J1
J2
K1
K2
K24
K26
K30
K32
L24
L26
L30
L32
N24
N26
N30
N32
P24
P26
P28
P30
P32
T21
T23
T25
T27
T31
U23
U27
U29
U31
U33
V23
V25
V27
V29
V31
V33
W22
W24
W28
W32
SVID_ALERT#_CPU
DY
C702
DY
C701
Layout Note:
1. Place close to CPU within 2"
2. VCC_SENSE/ VSS_SENSE
impedance=50 ohm
3. Length match<25mil
1V_CPU_CORE
R704
R705
C
1
1
2 100R2F-L1-GP-U
2 100R2F-L1-GP-U
VCCCORE_SENSE
VSSCORE_SENSE
B
R38
R37
VCCCORE_SENSE
VSSCORE_SENSE
M12
M11
P12
SVID_DATA_CPU
SVID_CLK_CPU
SVID_ALERT#_CPU_R
1 R706
2
0R0402-PAD-7-NP-GP
SVID_ALERT#_CPU
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
TGL-U-1-GP-U2
CPU (VCCIN/VID)
Size
A4
Document Number
Rev
MOCKINGBIRD_TGL
Date: Saturday, August 01, 2020
5
4
D
Close to CPU
SCD1U25V2KX-1-DL-GP
B
Layout note:
3.Length matchin 25mil, and close SOC in 2inch "
13 OF 21
SCD1U25V2KX-1-DL-GP
C
CPU1M
1
1
[46]
2
2
VCCCORE_SENSE
3
1
D
[46]
4
2
5
3
2
Sheet
7
of
1
A00
105
A
5
4
3
2
1
Main Func = CPU
AA39
AB40
AC39
AD40
AD51
AD52
AE39
AF40
AG39
AH40
AJ39
AK40
AK51
AK52
AL39
AM40
AN39
AP40
AR39
AT52
AU40
AW40
AW51
AW52
BD51
BD52
BK51
BK52
BV51
BV52
CA40
CC40
CC49
CC50
CE40
CG40
CH39
CJ40
CL40
CN40
CP47
CR40
D50
E51
F49
T51
T52
C
C803
2
C804
SC1U10V2KX-1DLGP
2
DY
SC1U10V2KX-1DLGP
B
1
1
1D05V_VCCSTG_OUT_R
C803 close to pin AN10, AM9
C804 close to pin AF12, AD12
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VCCSTG_OUT
VCCSTG
VCCSTG
VCCSTG_OUT
VCCSTG_OUT
VCCSTG_OUT
VCCION_OUT
VCCSTG_OUT_LGC
VCCST
VCCST
VCCST
VCCSTG
VCCSTG
VCCSTG
AF9
AF12
AD12
AN10
AM9
AG10
output
input
1D05V_VCCSTG_OUT_R
1
1D05V_VCCIO_OUT
M9
1D05V_VCCSTG_TERM
BP2
BP1
BP4
R801 2
0R0603-PAD-7-NP-GP
1D05V_VCCSTG_OUT_R
V15
BT2
BT1
BT4
D
1D05V_VCCSTG_OUT
output
output
1D05V_VCCST
(1200mA)
1D05V_VCCSTG
(300mA)
C
1D05V_VCCSTG
1D05V_VCCST
C802
SC1U10V2KX-1DLGP
1
1200mA
C801
SC1U10V2KX-1DLGP
2
1D2V_S3
1
D
15 OF 21
2
CPU1O
B
TGL-U-1-GP-U2
<Core Design>
Wistron Corporation
Lack of VCCPLL_OC / VCC1P8A / VCCPLL
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
CPU (VDDQ/VCC/VCCST/VCCSTG)
Size
A4
Document Number
Rev
MOCKINGBIRD_TGL
Date: Saturday, August 01, 2020
5
4
3
2
Sheet
8
of
1
A00
105
A
5
4
3
2
1
D
D
CPU1S
C
1
1
TP901
TP902
607872 Ver0.9 page350 Optional
20191112 modify
Follow Nakia DY R902
PCH_IST_TP1 DT52
PCH_IST_TP0 DU53
DF50
DF49
1D8V_ES1_ONLY
R902
1
ES1 2
0R2J-2-GP
CY30
CY15
1D8V_S5_ES1_CY15
D4
20190430_Byron
607872 Ver0.9 page350 recommend
TP903
TP904
1
1
IST_TP1
IST_TP0
A6
A4
RSVD#DF52
PCH_IST_TP1
PCH_IST_TP0
RSVD#DF50
RSVD#DF49
RSVD_TP#CY30
RSVD_TP#CY15
RSVD_TP#D4
IST_TP1
IST_TP0
RSVD#C53
RSVD#T35
RSVD#E53
RSVD#CF39
RSVD#U35
RSVD#F53
RSVD#B53
RSVD#AP9
RSVD#A52
RSVD_TP#BF12
RSVD_TP#V21
RSVD_TP#W20
RSVD_TP#U37
RSVD_TP#CD39
RSVD_TP#U21
RSVD#CB39
RSVD_TP#BB12
RSVD_TP#W37
RSVD_TP#AY12
RSVD_TP#W38
RSVD_TP#U38
RSVD_TP#CY28
C53
T35
E53
CF39
U35
F53
B53
AP9
A52
BF12
V21
W20
U37
CD39
U21
CB39
BB12
W37
AY12
W38
U38
CY28
1D05V_S5_OUT
CPU1D
1
DF52
20190430_Byron
RSVD#DF53
C
24D9R2F-L-GP
DP_COMP
DV24
DW47
DW49
A48
20191112 modify
Follow Nakia DY R903
1D8V_S5_ES1_CY28
4 OF 21
R901
ES1
2
DF53
19 OF 21
R903
1
ES1 2
RSVD#DV24
RSVD#DW47
RSVD#DW49
RSVD#A48
1D8V_ES1_ONLY
0R2J-2-GP
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
CPU (RSVD)
Size
A4
Document Number
Rev
MOCKINGBIRD_TGL
Date: Saturday, August 01, 2020
5
4
3
2
Sheet
9
of
1
A00
105
A
5
4
3
2
1
Main Func = CPU
1
PC1023
SC22U6D3V3MX-1-DL-GP
SC10U6D3V3MX-DL-GP
PC1035
SC10U6D3V3MX-DL-GP
DY
D
PC1036
SC10U6D3V3MX-DL-GP
DY
PC1022
SC22U6D3V3MX-1-DL-GP
10uF *4pcs
1D8V_CPU_AUX
PC1028
SC10U6D3V3MX-DL-GP
1
1
2
2
DY
C
PC1029
SC10U6D3V3MX-DL-GP
DY
PC1025
SC22U6D3V3MX-1-DL-GP
2
1
PC1021
SC22U6D3V3MX-1-DL-GP
2
1
2
2
PC1020
SC22U6D3V3MX-1-DL-GP
SC10U6D3V3MX-DL-GP
DY
DY
PC1019
SC22U6D3V3MX-1-DL-GP
PC1027
1
SC10U6D3V3MX-DL-GP
2
1
2
PC1026
1
1
PC1024
SC22U6D3V3MX-1-DL-GP
2
1
PC1018
SC22U6D3V3MX-1-DL-GP
2
1
PC1017
SC22U6D3V3MX-1-DL-GP
2
PC1016
SC22U6D3V3MX-1-DL-GP
2
1
1
1
PC1034
2
1
2
DY
2
1
PC1015
SC22U6D3V3MX-1-DL-GP
2
1
PC1014
SC22U6D3V3MX-1-DL-GP
2
2
PC1013
SC22U6D3V3MX-1-DL-GP
C
1
SC10U6D3V3MX-DL-GP
DY
2
1
1
PC1012
SC22U6D3V3MX-1-DL-GP
2
2
2
PC1011
SC22U6D3V3MX-1-DL-GP
PC1033
22uF *12pcs
1D8V_CPU_AUX
1
1
1
1
2
PC1010
SC22U6D3V3MX-1-DL-GP
SC10U6D3V3MX-DL-GP
DY
DY
PC1009
SC22U6D3V3MX-1-DL-GP
PC1032
2
1
1
SC10U6D3V3MX-DL-GP
1
2
2
1
PC1008
SC22U6D3V3MX-1-DL-GP
2
PC1007
SC22U6D3V3MX-1-DL-GP
2
2
1
1
1
2
PC1006
SC22U6D3V3MX-1-DL-GP
PC1031
2
1
PC1004
SC22U6D3V3MX-1-DL-GP
D
PC1005
SC22U6D3V3MX-1-DL-GP
10uF *6pcs
1V_CPU_CORE
PC1003
SC22U6D3V3MX-1-DL-GP
2
2
PC1002
SC22U6D3V3MX-1-DL-GP
1
1
1
2
PC1001
SC22U6D3V3MX-1-DL-GP
2
22uF *12pcs
1V_CPU_CORE
B
B
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A2
Date:
5
4
3
2
CPU (CORE Power Cap1)
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
10
of
A00
105
5
4
3
2
1
Main Func = CPU
1
C1107
SC1U10V2KX-1DLGP
2
1
C1106
SC1U10V2KX-1DLGP
2
1
C1105
SC1U10V2KX-1DLGP
2
1
C1104
SC1U10V2KX-1DLGP
2
C1103
SC1U10V2KX-1DLGP
2
2
C1102
SC1U10V2KX-1DLGP
1
1
1D2V_S3
C1128
SC12P50V2JN-DL-GP
1
C1130
SC4D7P50V2BN-2-GP
C1131
SC4D7P50V2BN-2-GP
2
2
C1129
SC4D7P50V2BN-2-GP
1
1
C1124
SC12P50V2JN-DL-GP
2
1
2
1
C1113
SC10U6D3V2MX-6-GP
2
2
DY
DY
Decoupling capacitors of 12 pF (0402) and 2.2 pF (0402)
are required to suppress the broadband noise at RF frequency
C1117
SC22U6D3V3MX-1-DL-GP
2
2
C1123
SC12P50V2JN-DL-GP
1
1
DY
1
2
C1112
SC10U6D3V2MX-6-GP
1
2
C1111
SC10U6D3V2MX-6-GP
C1116
SC22U6D3V3MX-1-DL-GP
2
C1110
SC10U6D3V3MX-DL-GP
2
1
1
2
C1109
SC10U6D3V3MX-DL-GP
1
D
1
D
C
1
C
C1118
SC22U6D3V3MX-1-DL-GP
2
DY
1D8V_S5
1
DY
2
1
2
1
2
2
2
DY
C1134
SC10U6D3V3MX-DL-GP
B
C1133
SC10U6D3V3MX-DL-GP
1
C1132
C1121
C1122
SC1U10V2KX-1DLGP DY SC1U10V2KX-1DLGP
SC10U6D3V3MX-DL-GP
1
1D05V_VCCST
B
1
11/5 Tery Don
add 1D8V_S5 decoupling cap. follow Shuri
2
C1126
C1127
SC1U10V2KX-1DLGP DY SC1U10V2KX-1DLGP
2
1
1D05V_VCCSTG
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A3
Date:
5
4
3
2
CPU (Power Cap2)
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
11
of
A00
105
4
149
157
162
165
M_A_DIMA_ODT0
M_A_DIMA_ODT1
155
161
SA0_CHA_DIM0
SA1_CHA_DIM0
SA2_CHA_DIM0
256
260
166
254
253
DDR4_DRAMRST#
M_A_ACT_N
M_A_ALERT_N
TS#_DIMM0_1
108
114
116
134
M_A_PARITY
143
M_VREF_CA_DIMMA
164
2
240R2F-1-GP
CKE0
CKE1
CS0#
CS1#
C0/CS2#/NC
C1/CS3#/NC
ODT0
ODT1
SA0
SA1
SA2
SDA
SCL
RESET#
ACT#
ALERT#
EVENT#/NF
PARITY
VREFCA
M_A_DQ[48:55]
M_A_DQ[40:47]
DM0#/DBI0#
DM1#/DBI#
DM2#/DBI2#
DM3#/DBI3#
DM4#/DBI4#
DM5#/DBI5#
DM6#/DBI6#
DM7#/DBI7#
DM8#/DBI#/NC
M_A_DQ[32:39]
1
2
5
6
9
10
14
15
18
19
22
23
26
27
30
31
35
36
39
40
43
44
47
48
51
52
56
57
60
61
64
65
68
69
72
73
77
78
81
82
85
86
89
90
93
94
98
M_A_DQS_DN7
M_A_DQS_DP7
M_A_DQS_DN6
M_A_DQS_DP6
M_A_DQS_DN5
M_A_DQS_DP5
M_A_DQS_DN4
M_A_DQS_DP4
M_A_DQS_DN1
M_A_DQS_DP1
M_A_DQS_DN0
M_A_DQS_DP0
M_A_DQS_DN3
M_A_DQS_DP3
M_A_DQS_DN2
M_A_DQS_DP2
11
13
32
34
53
55
74
76
177
179
198
200
219
221
240
242
95
97
1D2V_S3
12
33
54
75
178
199
220
241
96
DDR4-260P-78-GP-U
M_A_DQ[8:15]
062.10011.M001
1D2V_S3
111
112
117
118
123
124
129
130
135
136
141
142
147
148
153
154
159
160
163
M_A_DQ[0:7]
M_A_DQ[24:31]
DM1D
4 OF 4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
2 OF 4
DQS0_C
DQS0_T
DQS1_C
DQS1_T
DQS2_C
DQS2_T
DQS3_C
DQS3_T
DQS4_C
DQS4_T
DQS5_C
DQS5_T
DQS6_C
DQS6_T
DQS7_C
DQS7_T
DQS8_C
DQS8_T
M_A_DQ[16:23]
3D3V_S0
DM1C
3 OF 4
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDSPD
255
2D5V_S3
VPP
VPP
VTT
261
262
NP1
NP2
257
259
C1228
258
0D6V_S0
DY
C1201
1
M_A_CS#0
M_A_CS#1
CK0_T
CK0_C
CK1_T/NF
CK1_C/NF
DM1B
2
109
110
CB0/NC
CB1/NC
CB2/NC
CB3/NC
CB4/NC
CB5/NC
CB6/NC
CB7/NC
10/15 Modify DIM1 DQ/DQS tuning. follow CRB
M_A_DQ[56:63]
1
M_A_CKE0
M_A_CKE1
BA0
BA1
BG0
BG1
M_A_DQ63
M_A_DQ58
M_A_DQ56
M_A_DQ59
M_A_DQ60
M_A_DQ62
M_A_DQ61
M_A_DQ57
M_A_DQ51
M_A_DQ53
M_A_DQ49
M_A_DQ54
M_A_DQ48
M_A_DQ52
M_A_DQ55
M_A_DQ50
M_A_DQ45
M_A_DQ47
M_A_DQ41
M_A_DQ40
M_A_DQ44
M_A_DQ46
M_A_DQ42
M_A_DQ43
M_A_DQ36
M_A_DQ38
M_A_DQ33
M_A_DQ35
M_A_DQ39
M_A_DQ37
M_A_DQ34
M_A_DQ32
M_A_DQ11
M_A_DQ10
M_A_DQ14
M_A_DQ8
M_A_DQ12
M_A_DQ9
M_A_DQ15
M_A_DQ13
M_A_DQ5
M_A_DQ7
M_A_DQ0
M_A_DQ2
M_A_DQ6
M_A_DQ4
M_A_DQ3
M_A_DQ1
M_A_DQ31
M_A_DQ24
M_A_DQ26
M_A_DQ30
M_A_DQ27
M_A_DQ29
M_A_DQ25
M_A_DQ28
M_A_DQ17
M_A_DQ23
M_A_DQ20
M_A_DQ18
M_A_DQ21
M_A_DQ19
M_A_DQ22
M_A_DQ16
DY
261
262
SC2D2U10V3KX-1DLGP-U
DDR4-260P-78-GP-U
062.10011.M001
C
DDR4-260P-78-GP-U
062.10011.M001
0D6V_S0
0D6V_S0
C1226
C1223
2
SC1U10V2KX-1DLGP
2
1
2
1
1
2
2
1
1
2
2
1
1
C1210
DY
SC10U6D3V3MX-DL-GP
2
C1206
DY
SC10U6D3V3MX-DL-GP
2
C1205
SC10U6D3V3MX-DL-GP
2
C1204
SC10U6D3V3MX-DL-GP
SA0_CHA_DIM0
C1203
SC10U6D3V3MX-DL-GP
2 10KR2J-3-GP
C1209
DY
SC10U6D3V3MX-DL-GP
DY
2 R1205 1
0R0402-PAD-7-NP-GP
SC10U6D3V3MX-DL-GP
R1204 1
C1202
C1227
SC4D7U6D3V3KX-DLGP
C1208
DY
SC10U6D3V3MX-DL-GP
3D3V_S0
SC4D7U6D3V3KX-DLGP
DY
1
C1225
2
1
1D2V_S3
1
062.10011.M001
2nd = 062.10011.M021
3rd = 062.10011.M003
SC1U10V2KX-1DLGP
C1229
1
DDR4-260P-78-GP-U
1
1
D
NP1
NP2
0D6V_S0
2
99
102
103
106
107
167
168
171
172
175
176
180
181
184
185
188
189
192
193
196
197
201
202
205
206
209
210
213
214
217
218
222
223
226
227
230
231
234
235
238
239
243
244
247
248
251
252
2
DY
137
139
138
140
PCH_SMBDATA
PCH_SMBCLK
1D2V_S3
1
R1215
M_A_CLK0
M_A_CLK#0
M_A_CLK1
M_A_CLK#1
SCD1U16V2KX-3DLGP
2D5V_S3
DY
2 10KR2J-3-GP
DY
1
C1212
C1207
2
1
C1231
2
EC1203
1
1
DY
2
2
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
2
2
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
2
2
SC1U10V2KX-1DLGP
SA2_CHA_DIM0
DY
2
EC1202
1
C1221
2
C1220
1
1
C1219
DY
SC1U10V2KX-1DLGP
DY
1
1
1
1
C1218
R1212 1
0R0402-PAD-7-NP-GP
B
SC1U10V2KX-1DLGP
2
C1217
SC4D7U6D3V3KX-DLGP
3D3V_S0
C1216
SC4D7U6D3V3KX-DLGP
83.05725.0A0
R1211 1
DY
2
2 10KR2J-3-GP
SC1U10V2KX-1DLGP
DY
2 R1210 1
0R0402-PAD-7-NP-GP
C1215
2
1
R1208 1
ED1217
AZ5725-01FDR7G-GP
C1214
SCD1U25V2KX-1-DL-GP
DY
SA1_CHA_DIM0
1
3D3V_S0
DDR4_DRAMRST#
SC2D2U6D3V2MX-DL-GP
B
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
150
145
115
113
92
91
101
105
88
87
100
104
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_A_BA0
M_A_BA1
M_A_BG0
M_A_BG1
8
7
20
21
4
3
16
17
28
29
41
42
24
25
38
37
50
49
62
63
46
45
58
59
70
71
83
84
66
67
79
80
174
173
187
186
170
169
183
182
195
194
207
208
191
190
203
204
216
215
228
229
211
212
224
225
237
236
249
250
232
233
245
246
SCD1U16V2KX-3DLGP
C
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
2
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_A16
M_A_DQS_DP0
M_A_DQS_DP1
M_A_DQS_DP2
M_A_DQS_DP3
M_A_DQS_DP4
M_A_DQS_DP5
M_A_DQS_DP6
M_A_DQS_DP7
1
1 OF 4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
WE#/A14
CAS#/A15
RAS#/A16
2
M_A_DQS_DP0
M_A_DQS_DP1
M_A_DQS_DP2
M_A_DQS_DP3
M_A_DQS_DP4
M_A_DQS_DP5
M_A_DQS_DP6
M_A_DQS_DP7
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
144
133
132
131
128
126
127
122
125
121
146
120
119
158
151
156
152
1
D
M_A_DQS_DN0
M_A_DQS_DN1
M_A_DQS_DN2
M_A_DQS_DN3
M_A_DQS_DN4
M_A_DQS_DN5
M_A_DQS_DN6
M_A_DQS_DN7
DM1A
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_A16
2
SC1U10V2KX-1DLGP
M_A_DQS_DN0
M_A_DQS_DN1
M_A_DQS_DN2
M_A_DQS_DN3
M_A_DQS_DN4
M_A_DQS_DN5
M_A_DQS_DN6
M_A_DQS_DN7
3
2
5
Main Func = MEMORY
M_A_CLK0 [5]
M_A_CLK#0 [5]
M_A_CLK1 [5]
M_A_CLK#1 [5]
[5]
[5]
M_A_CS#0
M_A_CS#1
[5]
[5]
1
2
RN1201
SRN1KJ-7-GP
[5]
[5]
4
3
R1206
M_VREF_CA_DIMMA 1
2R2F-GP
V_SM_VREF_CNTA
2
C1222
SCD022U16V2KX-3DLGP
2
M_A_DIMA_ODT0
M_A_DIMA_ODT1
1D2V_S3
1
M_A_CKE0
M_A_CKE1
1
PCH_SMBDATA [13,18]
PCH_SMBCLK [13,18]
+V_VREF_PATH1
R1209
24D9R2F-L-GP
2
DDR4_DRAMRST#
[5,13]
M_A_ACT_N [5]
M_A_ALERT_N [5]
M_A_PARITY
[5]
M_A_BA0 [5]
M_A_BA1 [5]
M_A_BG0 [5]
M_A_BG1 [5]
A
V_SM_VREF_CNTA
[5]
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A2
Date:
5
4
3
2
DDR3-SODIMM1
MOCKINGBIRD_TGL
Document Number
Saturday, August 01, 2020
Sheet
1
12
Rev
A00
of
105
3
M_B_DQ[16:23]
D
1
1
2
0D6V_S0
0D6V_S0
0D6V_S0
2D5V_S3
2 10KR2J-3-GP
SA0_CHB_DIM0
C1303
83.05725.0A0
3D3V_S0
R1306 1
2
2 10KR2J-3-GP
DY
SA1_CHB_DIM0
C1304
DY
C1305 C1306
C1307
DY
C1308
C1309
DY
1
DY
R1303 1
0R0402-PAD-7-NP-GP
C1310
2
2
DY
1
1
2
C1327
2
C1326
1
1
C1311
C1325
C1313
SC1U10V2KX-1DLGP
2
SC10U6D3V3MX-DL-GP
R1302 1
C1324
2
3D3V_S0
SC1U10V2KX-1DLGP
2
1
1D2V_S3
1
062.10011.M004
SC4D7U6D3V3KX-DLGP
2
99
102
103
106
107
167
168
171
172
175
176
180
181
184
185
188
189
192
193
196
197
201
202
205
206
209
210
213
214
217
218
222
223
226
227
230
231
234
235
238
239
243
244
247
248
251
252
C
SC1U10V2KX-1DLGP
2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
062.10011.M004
SC4D7U6D3V3KX-DLGP
ED1302
AZ5725-01FDR7G-GP
4 OF 4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DDR4-260P-82-GP-U
SC4D7U6D3V3KX-DLGP
DDR4_DRAMRST#
062.10011.M004
2nd = 062.10011.M020
3rd = 062.10011.M007
1D2V_S3
12
33
54
75
178
199
220
241
96
DM2D
DDR4-260P-82-GP-U
DDR4-260P-82-GP-U
C1301
DM0#/DBI0#
DM1#/DBI#
DM2#/DBI2#
DM3#/DBI3#
DM4#/DBI4#
DM5#/DBI5#
DM6#/DBI6#
DM7#/DBI7#
DM8#/DBI#/NC
1
VREFCA
M_B_DQ[24:31]
M_B_DQS_DN5
M_B_DQS_DP5
M_B_DQS_DN4
M_B_DQS_DP4
M_B_DQS_DN7
M_B_DQS_DP7
M_B_DQS_DN6
M_B_DQS_DP6
M_B_DQS_DN1
M_B_DQS_DP1
M_B_DQS_DN0
M_B_DQS_DP0
M_B_DQS_DN3
M_B_DQS_DP3
M_B_DQS_DN2
M_B_DQS_DP2
2
PARITY
M_B_DQ[0:7]
11
13
32
34
53
55
74
76
177
179
198
200
219
221
240
242
95
97
2
164
M_B_DQ[8:15]
SC10U6D3V3MX-DL-GP
143
2 OF 4
DQS0_C
DQS0_T
DQS1_C
DQS1_T
DQS2_C
DQS2_T
DQS3_C
DQS3_T
DQS4_C
DQS4_T
DQS5_C
DQS5_T
DQS6_C
DQS6_T
DQS7_C
DQS7_T
DQS8_C
DQS8_T
1
M_B_PARITY
M_VREF_CA_DIMMB
DM2B
SC10U6D3V3MX-DL-GP
2
DY 240R2F-1-GP
1
1 R1312
RESET#
ACT#
ALERT#
EVENT#/NF
NP1
NP2
1
SDA
SCL
DY
062.10011.M004
1 R1307
V_SM_VREF_CNTB
2
SA2_CHB_DIM0
2
1
C1322
2
1
1
C1321
DY
2
1
2
1
2
1
2
1
2
1
C1320
DY
DY
EC1303
B
C1323
SCD022U16V2KX-3DLGP
1
2
2R2F-GP
2 10KR2J-3-GP
2
2
M_VREF_CA_DIMMB 1
SRN1KJ-7-GP
DY
R1311 1
0R0402-PAD-7-NP-GP
C1319
SC1U10V2KX-1DLGP
2
R1305
C1318
SC1U10V2KX-1DLGP
4
3
C1317
SC1U10V2KX-1DLGP
RN1301
C1316
SC1U10V2KX-1DLGP
R1310 1
1
2
C1315
SC1U10V2KX-1DLGP
DY
1D2V_S3
SC2D2U6D3V2MX-DL-GP
1
0R2J-2-GP
3D3V_S0
SC1U10V2KX-1DLGP
A
M_B_DQS_DP0
M_B_DQS_DP1
M_B_DQS_DP2
M_B_DQS_DP3
M_B_DQS_DP4
M_B_DQS_DP5
M_B_DQS_DP6
M_B_DQS_DP7
SA0
SA1
SA2
261
262
C1328
DDR4-260P-82-GP-U
SC1U10V2KX-1DLGP
M_B_DQS_DN0
M_B_DQS_DN1
M_B_DQS_DN2
M_B_DQS_DN3
M_B_DQS_DN4
M_B_DQS_DN5
M_B_DQS_DN6
M_B_DQS_DN7
254
253
DDR4_DRAMRST# 108
M_B_ACT_N
114
M_B_ALERT_N
116
TS#_DIMM1_1 134
1D2V_S3
DY
256
260
166
PCH_SMBDATA
PCH_SMBCLK
NP1
NP2
DY
C1329
1
2
5
6
9
10
14
15
18
19
22
23
26
27
30
31
35
36
39
40
43
44
47
48
51
52
56
57
60
61
64
65
68
69
72
73
77
78
81
82
85
86
89
90
93
94
98
M_B_DQ[48:55]
SC1U10V2KX-1DLGP
+V_VREF_PATH2
R1309
24D9R2F-L-GP
2
B
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
SA0_CHB_DIM0
SA1_CHB_DIM0
SA2_CHB_DIM0
SCD1U16V2KX-3DLGP
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ15
M_B_DQ14
M_B_DQ12
M_B_DQ13
M_B_DQ10
M_B_DQ11
M_B_DQ22
M_B_DQ17
M_B_DQ21
M_B_DQ19
M_B_DQ18
M_B_DQ16
M_B_DQ20
M_B_DQ23
M_B_DQ30
M_B_DQ27
M_B_DQ29
M_B_DQ31
M_B_DQ25
M_B_DQ28
M_B_DQ24
M_B_DQ26
M_B_DQ35
M_B_DQ38
M_B_DQ36
M_B_DQ37
M_B_DQ34
M_B_DQ39
M_B_DQ32
M_B_DQ33
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ47
M_B_DQ44
M_B_DQ45
M_B_DQ43
M_B_DQ46
M_B_DQ52
M_B_DQ51
M_B_DQ55
M_B_DQ49
M_B_DQ54
M_B_DQ48
M_B_DQ50
M_B_DQ53
M_B_DQ63
M_B_DQ62
M_B_DQ57
M_B_DQ56
M_B_DQ58
M_B_DQ59
M_B_DQ61
M_B_DQ60
[5]
ODT0
ODT1
261
262
0D6V_S0
258
2
[5]
155
161
1
C
M_B_DIMB_ODT0
M_B_DIMB_ODT1
CS0#
CS1#
C0/CS2#/NC
C1/CS3#/NC
VTT
257
259
2
M_B_PARITY
CKE0
CKE1
149
157
162
165
2D5V_S3
VPP
VPP
SC10U6D3V3MX-DL-GP
[5,12,13]
[5]
[5]
V_SM_VREF_CNTB
109
110
255
1
PCH_SMBDATA [12,18]
PCH_SMBCLK [12,18]
DDR4_DRAMRST#
M_B_ACT_N
M_B_ALERT_N
M_B_CKE0
M_B_CKE1
M_B_CS#0
M_B_CS#1
VDDSPD
SC10U6D3V3MX-DL-GP
[5]
[5]
CK0_T
CK0_C
CK1_T/NF
CK1_C/NF
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
1
M_B_DIMB_ODT0
M_B_DIMB_ODT1
137
139
138
140
M_B_DQ[56:63]
3 OF 4
2
[5]
[5]
M_B_CLK0
M_B_CLK#0
M_B_CLK1
M_B_CLK#1
M_B_DQ[32:39]
2
M_B_CS#0
M_B_CS#1
[5]
[5]
1
M_B_CKE0
M_B_CKE1
111
112
117
118
123
124
129
130
135
136
141
142
147
148
153
154
159
160
163
M_B_DQ[40:47]
DM2C
SC10U6D3V3MX-DL-GP
2
M_B_CLK0 [5]
M_B_CLK#0 [5]
M_B_CLK1 [5]
M_B_CLK#1 [5]
CB0/NC
CB1/NC
CB2/NC
CB3/NC
CB4/NC
CB5/NC
CB6/NC
CB7/NC
1D2V_S3
1
92
91
101
105
88
87
100
104
M_B_DQ42
M_B_DQ47
M_B_DQ45
M_B_DQ43
M_B_DQ41
M_B_DQ40
M_B_DQ46
M_B_DQ44
M_B_DQ34
M_B_DQ36
M_B_DQ32
M_B_DQ37
M_B_DQ35
M_B_DQ33
M_B_DQ38
M_B_DQ39
M_B_DQ58
M_B_DQ62
M_B_DQ60
M_B_DQ57
M_B_DQ59
M_B_DQ61
M_B_DQ63
M_B_DQ56
M_B_DQ54
M_B_DQ49
M_B_DQ52
M_B_DQ50
M_B_DQ55
M_B_DQ51
M_B_DQ53
M_B_DQ48
M_B_DQ8
M_B_DQ14
M_B_DQ10
M_B_DQ12
M_B_DQ15
M_B_DQ13
M_B_DQ9
M_B_DQ11
M_B_DQ7
M_B_DQ6
M_B_DQ2
M_B_DQ3
M_B_DQ0
M_B_DQ5
M_B_DQ1
M_B_DQ4
M_B_DQ30
M_B_DQ26
M_B_DQ29
M_B_DQ25
M_B_DQ27
M_B_DQ31
M_B_DQ28
M_B_DQ24
M_B_DQ21
M_B_DQ17
M_B_DQ16
M_B_DQ20
M_B_DQ19
M_B_DQ23
M_B_DQ18
M_B_DQ22
SC10U6D3V3MX-DL-GP
M_B_BA0 [5]
M_B_BA1 [5]
M_B_BG0 [5]
M_B_BG1 [5]
BA0
BA1
BG0
BG1
8
7
20
21
4
3
16
17
28
29
41
42
24
25
38
37
50
49
62
63
46
45
58
59
70
71
83
84
66
67
79
80
174
173
187
186
170
169
183
182
195
194
207
208
191
190
203
204
216
215
228
229
211
212
224
225
237
236
249
250
232
233
245
246
1
150
145
115
113
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
3D3V_S0
10/15 Modify DIM2 DQ/DQS tuning. follow CRB
1 OF 4
2
M_B_BA0
M_B_BA1
M_B_BG0
M_B_BG1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
WE#/A14
CAS#/A15
RAS#/A16
SCD1U16V2KX-3DLGP
D
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
144
133
132
131
128
126
127
122
125
121
146
120
119
158
151
156
152
1
SC2D2U10V3KX-1DLGP-U
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_A16
DM2A
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_A16
2
2
4
SC10U6D3V3MX-DL-GP
5
Main Func = MEMORY
M_B_DQS_DN0
M_B_DQS_DN1
M_B_DQS_DN2
M_B_DQS_DN3
M_B_DQS_DN4
M_B_DQS_DN5
M_B_DQS_DN6
M_B_DQS_DN7
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
M_B_DQS_DP0
M_B_DQS_DP1
M_B_DQS_DP2
M_B_DQS_DP3
M_B_DQS_DP4
M_B_DQS_DP5
M_B_DQS_DP6
M_B_DQS_DP7
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A2
Date:
5
4
3
2
DDR3-SODIMM1
MOCKINGBIRD_TGL
Document Number
Saturday, August 01, 2020
Sheet
1
13
Rev
A00
of
105
5
4
3
2
1
D
D
C
C
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
DDR (RSVD) (DDR4-CHA1)
Size
A4
Document Number
Rev
MOCKINGBIRD_TGL
Date: Saturday, August 01, 2020
5
4
3
2
Sheet
14
of
1
A00
105
A
5
4
2
1
R1523
2
1
2
2
sky 0329
20KR2J-L2-GP
R1528
R1526
100KR2J-1-GP
4K7R2J-2-GP
GPP_D12
R1525
20KR2J-L2-GP
1
2
1D05V_S5_OUT
1
3D3V_S5
SPI_HOLD_ROM
Close to U2501
DY
R1527
100KR2J-1-GP
GPP_E11
=20K PU=
20191211
Always stuff
Follow Nakia
1D8V_S5
1KR2F-3-GP
DBG_PMODE
R1529
1D8V_S5
1
R1524
sky 0329
20KR2J-L2-GP
=NO INTERNAL=
R1531
20KR2J-L2-GP
GPP_E10
2
sky 0329
4K7R2J-2-GP
GPP_D10
GPP_E10
A0
DY
2
R1522
3D3V_S5
1
1
2
4K7R2J-2-GP
GPP_E21
=NO INTERNAL=
4K7R2J-2-GP
1
R1520
DY
2
20KR2J-L2-GP
1
sky 0329
R1521
2
DY
4K7R2J-2-GP
TBT_LSX0_RXD
3D3V_S5
TBT LSX VCCIO conf.#3
D12
2
R1519
=NO INTERNAL=
1
D10
1
1
3D3V_S5
2
1
2
1
2
TBT LSX VCCIO conf.#2
=NO INTERNAL=
D
DY
E
L
B
A
N
E
I
V
N
C
D
E
T
A
R
G
E
T
N
I
R1518
DY
Schematic
E21
R1516
E
L
B
A
S
I
D
I
V
N
C
D
E
T
A
R
G
E
T
N
I
3D3V_S5
TBT LSX VCCIO conf.#1
S
E
R
UN
SE
AD
EI
MR
YR
TE
IV
RO
UT
C
EO
SN
=NO INTERNAL=
N
E
D
I
R
R
E
V
O
E19
e
l
b
a
n
E
TBT LSX VCCIO conf.#0
T
C
E
R
I
D
M
O)
T
RL
FU
KA
CF
OE
LD
C(
ZL
HA
MT
4S
.Y
8R
3C
e
l
b
a
s
i
D
GPIO
e
l
b
a
n
E
e
l
b
a
n
E
=default=
Low
e
l
b
a
s
i
D
High
4K7R2J-2-GP
ME_UNLOCK 1 R1515 2HDA_SDO
0R0402-PAD-7-NP-GP
2
4K7R2J-2-GP
1
1
2
1
4K7R2J-2-GP
CNV_RGI_DT
DY
4K7R2J-2-GP
)
L
A
T
RS
EY
DR
IC
VZ
IH
DM
M4
O.
R8
F3
KM
CO
OR
LF
CD
E
ZV
HI
MR
2E
.
9D
1(
GPP_E11
DY
DY
e
l
b
a
n
E
[18]
20K5R2F-GP
Close to U2501
R1512
e
l
b
a
s
i
D
GPP_E10
20200221(DVT1)
Change to 4.7k follow CRB
e
l
b
a
s
i
D
I
P
S
E
[18]
DY
SPI_WP_ROM
R1514
20191112 modify
Follow Nakia using 1.8V GPPR
1
GPP_E21
DY
GPP_E6
Close to U2501
R1511
=NO INTERNAL=
1D8V_S5
R1507
100KR2J-1-GP
R1509
R1530
20KR2J-L2-GP
GPP_E11
DY
2
[4]
SPI_SI_ROM
R1502
2
1
GPP_D12
2
[4]
1
SML0_ALERT#
Schematic
R1506
100KR2J-1-GP
1
DBG_PMODE
1D8V_GPPR_S5
100KR2J-1-GP
2
GPP_D10
[3]
BOOT_HALT
=20K PD=
* PH as VCCPGPPR
1
TBT_LSX0_RXD
[4]
4K7R2J-2-GP
ME_UNLOCK (GPP_R2) CNVI debug MODES (GPP_F2)
=NO INTERNAL=
3D3V_SPI
R1504
R1503
4K7R2J-2-GP
DY
D
SPI_WP
=20K PD=
2
HDA_SDO
R1501
GPP_B23
=NO INTERNAL=
3D3V_S5
2
GPP_E6
[19]
2
[18]
GPP_E6
=NO INTERNAL=
3D3V_S5
1
SML0_ALERT#
SPI_SI
=20K PD=
2
CNV_RGI_DT
[18]
GPP_C5
3D3V_S5
1
[21]
GPIO
2
SPI_HOLD_ROM
1
SPI_WP_ROM
[18,24,25]
2
[18,24,25]
[4,71]
3
SPI_SI_ROM
1
[18,24,25,91]
20190515_neal
1KR2F-3-GP
C
C
D
E
L
B
A
S
I
D
E
D
O)
MT
TL
SU
EA
TF
XE
FD
D(
e
l
b
a
s
i
D
V
3
.
3
V
3
.
3
V
3
.
3
V
3
.
3
High
D
E
L
B
A
N
E
E
D
O
M
T
S
E
T
X
F
D
e
l
b
a
n
E
V
8
.
1
V
8
.
1
V
8
.
1
V
8
.
1
Low
Original Ref.
GPP_C5
TBT LSX #1
SPI_SI
GPP_E6
GPP_B23
TBT LSX #2
TBT LSX #3
A0
SPI_WP
ME_UNLOCK
GPP_E10
M.2 CNVI MODES
TBT LSX #0
GPP_E11
B
B
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A2
Date:
5
4
3
2
CPU (STRAP)
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
15
of
A00
105
5
4
3
2
1
GPU
[76]
[76]
[76]
[76]
GFX_PCIE_TX_P0
GFX_PCIE_TX_N0
GFX_PCIE_RX_P0
GFX_PCIE_RX_N0
[76]
[76]
[76]
[76]
GFX_PCIE_TX_P1
GFX_PCIE_TX_N1
GFX_PCIE_RX_P1
GFX_PCIE_RX_N1
[63]
[63]
[63]
[63]
SSD_PCIE_TX_P0
SSD_PCIE_TX_N0
SSD_PCIE_RX_P0
SSD_PCIE_RX_N0
[63]
[63]
[63]
[63]
SSD_PCIE_TX_P1
SSD_PCIE_TX_N1
SSD_PCIE_RX_P1
SSD_PCIE_RX_N1
[63]
[63]
[63]
[63]
SSD_PCIE_TX_P2
SSD_PCIE_TX_N2
SSD_PCIE_RX_P2
SSD_PCIE_RX_N2
[63]
[63]
[63]
[63]
SSD_PCIE_TX_P3
SSD_PCIE_TX_N3
SSD_PCIE_RX_P3
SSD_PCIE_RX_N3
M.2 SSD1
D
CPU1I
[63]
[63]
[63]
[63]
C
SSD2
SSD_PCIE_TX_P9
SSD_PCIE_TX_N9
SSD_PCIE_RX_N9
SSD_PCIE_RX_P9
[63]
[63]
[63]
[63]
SSD_PCIE_TX_P10
SSD_PCIE_TX_N10
SSD_PCIE_RX_P10
SSD_PCIE_RX_N10
[63]
[63]
[63]
[63]
SSD_PCIE_TX_P11
SSD_PCIE_TX_N11
SSD_PCIE_RX_P11
SSD_PCIE_RX_N11
[63]
[63]
[63]
[63]
SSD_PCIE_TX_P12
SSD_PCIE_TX_N12
SSD_PCIE_RX_P12
SSD_PCIE_RX_N12
LAN
LAN_PCIE_TX_P
LAN_PCIE_TX_N
LAN_PCIE_RX_P
LAN_PCIE_RX_N
USB1_USB30_RX_N
USB1_USB30_RX_P
USB1_USB30_TX_N
USB1_USB30_TX_P
[35]
[35]
BV7
BV8
CG2
CG1
SSD_PCIE_TX_P9
SSD_PCIE_TX_N9
SSD_PCIE_RX_P9
SSD_PCIE_RX_N9
BY7
BY8
CG5
CG4
LAN_PCIE_TX_C_P CB8
LAN_PCIE_TX_C_N CB7
CK5
CK4
WLAN_PCIE_TX_P
WLAN_PCIE_TX_N
WLAN_PCIE_RX_P
WLAN_PCIE_RX_N
CD9
CD8
CK1
CK2
1
1
2 SCD22U10V1KX-1-GP
OPS
2 SCD22U10V1KX-1-GP
OPS
GFX_PCIE_TX_C_P1
GFX_PCIE_TX_C_N1
GFX_PCIE_RX_P1
GFX_PCIE_RX_N1
CG8
CG7
CL4
CL3
GFX_PCIE_TX_P0
GFX_PCIE_TX_N0
C1607
C1608
1
1
2 SCD22U10V1KX-1-GP
OPS
2 SCD22U10V1KX-1-GP
OPS
GFX_PCIE_TX_C_P0
GFX_PCIE_TX_C_N0
GFX_PCIE_RX_P0
GFX_PCIE_RX_N0
CJ8
CJ7
CN2
CN1
20191211
For TBT solution
CR8
CR7
CN5
CN4
USB1_USB20_P
USB1_USB20_N
[35]
CU8
CU7
CT2
CT1
USB_OC0#
USB2
USB3.2 Type-A Port2 (IO)
[66]
[66]
[66]
[66]
SSD_PCIE_TX_P10
SSD_PCIE_TX_N10
SSD_PCIE_RX_P10
SSD_PCIE_RX_N10
C1605
C1606
USB3.2 Type-A Port1 (MB)
[35]
[35]
[35]
[35]
BT9
BV9
CF4
CF3
GFX_PCIE_TX_P1
GFX_PCIE_TX_N1
GPU
USB1
SSD_PCIE_TX_P11
SSD_PCIE_TX_N11
SSD_PCIE_RX_P11
SSD_PCIE_RX_N11
C1614 1LAN 2 SCD1U16V2KX-3DLGP
C1613 1LAN 2 SCD1U16V2KX-3DLGP
WLAN
[63] M2_DEVSLP1
[63] M2_PEDET1
BT7
BT8
CE2
CE1
USB2_USB30_RX_N
USB2_USB30_RX_P
USB2_USB30_TX_N
USB2_USB30_TX_P
[66]
[66]
USB2_USB20_P
USB2_USB20_N
USB2_IO
USB2_USB30_TX_P
USB2_USB30_TX_N
USB2_USB30_RX_P
USB2_USB30_RX_N
CW8
CW7
CU3
CT4
USB1_MB
USB1_USB30_TX_P
USB1_USB30_TX_N
USB1_USB30_RX_P
USB1_USB30_RX_N
DA8
DA7
CV2
CV1
PCIE12_TXP/SATA1_TXP
PCIE12_TXN/SATA1_TXN
PCIE12_RXP/SATA1_RXP
PCIE12_RXN/SATA1_RXN
USB2P_10
USB2N_10
USB2P_9
USB2N_9
PCIE11_TXP/SATA0_TXP
PCIE11_TXN/SATA0_TXN
PCIE11_RXP/SATA0_RXP
PCIE11_RXN/SATA0_RXN
USB2P_8
USB2N_8
USB2P_7
USB2N_7
PCIE10_TXP
PCIE10_TXN
PCIE10_RXP
PCIE10_RXN
USB2P_6
USB2N_6
PCIE9_TXP
PCIE9_TXN
PCIE9_RXP
PCIE9_RXN
USB2P_5
USB2N_5
USB2P_4
USB2N_4
PCIE8_TXP
PCIE8_TXN
PCIE8_RXP
PCIE8_RXN
USB2P_3
USB2N_3
USB2P_2
USB2N_2
PCIE7_TXP
PCIE7_TXN
PCIE7_RXP
PCIE7_RXN
USB2P_1
USB2N_1
PCIE6_TXP
PCIE6_TXN
PCIE6_RXP
PCIE6_RXN
GPP_E0/SATAXPCIE0/SATAGP0
GPP_A12/SATAXPCIE1/SATAGP1/I2S3_SFRM
GPP_E9/USB_OC0#
GPP_A16/USB_OC3#/I2S4_SFRM
PCIE5_TXP
PCIE5_TXN
PCIE5_RXP
PCIE5_RXN
GPP_E5/DEVSLP1
GPP_E4/DEVSLP0
GPP_H15/M2_SKT2_CFG3
GPP_H14/M2_SKT2_CFG2
GPP_H13/M2_SKT2_CFG1
GPP_H12/M2_SKT2_CFG0
PCIE4_TXP/USB31_4_TXP
PCIE4_TXN/USB31_4_TXN
PCIE4_RXP/USB31_4_RXP
PCIE4_RXN/USB31_4_RXN
PCIE_RCOMP_P
PCIE_RCOMP_N
PCIE3_TXP/USB31_3_TXP
PCIE3_TXN/USB31_3_TXN
PCIE3_RXP/USB31_3_RXP
PCIE3_RXN/USB31_3_RXN
USB_VBUSSENSE
USB_ID
USB2_COMP
PCIE2_TXP/USB31_2_TXP
PCIE2_TXN/USB31_2_TXN
PCIE2_RXP/USB31_2_RXP
PCIE2_RXN/USB31_2_RXN
RSVD_BSCAN
BT_USB20_P
BT_USB20_N
BT
DD1
DD2
CARD1_USB20_P
CARD1_USB20_N
Card Reader
DA1
DA2
CCD_USB20_P
CCD_USB20_N
Camera
DA12
DA11
FP1_USB20_P
FP1_USB20_N
Finger Print
DB4
DB3
USB4_USB20_P
USB4_USB20_N
TBT
DA5
DA4
USB2_USB20_P
USB2_USB20_N
USB2_IO
DC11
DC9
USB1_USB20_P
USB1_USB20_N
USB1_MB
DP4
DF41
M2_PEDET1
DD8
DJ45
USB_OC0#
USB_OC3#
DN6
DG8
M2_DEVSLP1
CV4
CY3
DD5
DD4
CW9
DA9
DC8
DC7
20191211
Follow Nakia
C
3D3V_S5_VCCPRIM
R1605
R1607
1
1
2 10KR2J-3-GP
2 10KR2J-3-GP
DN29
DK29
DT31
DR32
20191223
For customer request
20191211
DUAL_BOOT_EVENT#
For TBT solution
WLAN_RF_DIS#
PCH_TBT_PERST#
TBT_FORCE_PWR
DV9
DT9
PCIE_RCOMP_P
PCIE_RCOMP_N
R1601
1
2 100R2F-L1-GP-U
DC12
DF1
DE1
USB_VBUSSENSE
USB_ID
USB2_COMP
R1602
R1604
R1603
1
1
1
2 10KR2F-2-GP
2 10KR2F-2-GP
2 113R2F-GP
20191224
Follow Internal review
USB3.2 Type-A Port1 (MB)
20191211
Remove R1607
20191220
Follow Intel check list
20191224
For Customer and BIOS require
3D3V_S5_VCCPRIM
1
M.2 SSD2
SSD_PCIE_TX_P12
SSD_PCIE_TX_N12
SSD_PCIE_RX_P12
SSD_PCIE_RX_N12
9 OF 21
Dual Boot
R1608
100KR2J-1-GP
2
D
DUAL_BOOT_EVENT#
E3
PCIE1_TXP/USB31_1_TXP
PCIE1_TXN/USB31_1_TXN
PCIE1_RXP/USB31_1_RXP
PCIE1_RXN/USB31_1_RXN
TGL-U-1-GP-U2
Card Reader
[66]
[66]
CARD1_USB20_P
CARD1_USB20_N
B
CPU1H
Camera
[55]
[55]
CCD_USB20_P
CCD_USB20_N
Finger Print
[66]
[66]
SSD1
FP1_USB20_N
FP1_USB20_P
TpyeC
[72]
[72]
[71,72]
SSD_PCIE_TX_P3
SSD_PCIE_TX_N3
SSD_PCIE_RX_P3
SSD_PCIE_RX_N3
P5
P7
N1
N2
SSD_PCIE_TX_P2
SSD_PCIE_TX_N2
SSD_PCIE_RX_P2
SSD_PCIE_RX_N2
T5
T7
R1
R2
B
8 OF 21
PCIE4_TX_P3
PCIE4_TX_N3
PCIE4_RX_P3
PCIE4_RX_N3
PCIE4_TX_P1
PCIE4_TX_N1
PCIE4_RX_P1
PCIE4_RX_N1
PCIE4_TX_P2
PCIE4_TX_N2
PCIE4_RX_P2
PCIE4_RX_N2
PCIE4_TX_P0
PCIE4_TX_N0
PCIE4_RX_P0
PCIE4_RX_N0
USB4_USB20_P
USB4_USB20_N
PCIE4_RCOMP_P
PCIE4_RCOMP_N
V5
V7
T1
T2
SSD_PCIE_TX_P1
SSD_PCIE_TX_N1
SSD_PCIE_RX_P1
SSD_PCIE_RX_N1
Y5
Y7
V1
V2
SSD_PCIE_TX_P0
SSD_PCIE_TX_N0
SSD_PCIE_RX_P0
SSD_PCIE_RX_N0
Y12
V12
PCIE4_RCOMP_P
PCIE4_RCOMP_N
SSD1
R1606
1
2 2K2R2F-GP
TBT_FORCE_PWR
PD
[17,71]
PCH_TBT_PERST#
BT
[61]
[61]
BT_USB20_P
BT_USB20_N
WLAN
[61]
A
[61]
[61]
[61]
[61]
WLAN_RF_DIS#
WLAN_PCIE_RX_N
WLAN_PCIE_RX_P
WLAN_PCIE_TX_N
WLAN_PCIE_TX_P
A
LAN
<Core Design>
[66]
[66]
[66]
[66]
LAN_PCIE_RX_N
LAN_PCIE_RX_P
LAN_PCIE_TX_N
LAN_PCIE_TX_P
[24]
DUAL_BOOT_EVENT#
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A2
Date:
5
4
3
2
CPU (PCIE/SATA/USB)
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
16
of
A00
105
3
2
PCH_PLTRST#
[51,66]
SIO_SLP_S4#
DM43: SIO_SLP_S5#
DR41: SIO_SLP_A#
DT44: SIO_SLP_WLAN#
TP1707
[25,45]
3V_5V_PWRGD
[24]
SIO_PWRBTN#
TP1709
20191112 modify 20191119 modify
Follow Nakia
Follow EC GPIO review
20191203 modify
Follow Nakia
PCH_DPWROK
R1723
20191206 modify
For High limit
ALL_SYS_PWRGD D1704 K
D
[24,26]
IMVP_VR_ON
[24,40]
PCH_RSMRST#
ALL_SYS_PWRGD
[24]
SYS_PWROK
[40]
SIO_SLP_SUS#
DV49
1
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_S3#
SIO_SLP_A#
DM43
DJ41
DJ43
DR41
DT44
1
SIO_SLP_S0#
DD42
DN39
PM_RSMRST#
SYS_RESET#
PCH_PLTRST#
NON-G3
1
RB520S30-GP
RTC_INTRUDER# DM37
SPI_VCC_SEL
DT49
1 R1745 2
0R0402-PAD-7-NP-GP
1 R1746 2
0R0402-PAD-7-NP-GP
IMVP_VR_ON
DM35
DD10
DD41
DSW_PWROK_R DK35
SYS_PWROK
DF10
PCH_PWROK
DN35
2 0R2J-2-GP
DYA
PWR_IMVP_PWRGD
[17,24,40,44,46]
SIO_SLP_SUS#
1
TP1705
SLP_SUS#
PROCPWRGD
GPD3/PWRBTN#
GPD0/BATLOW#
GPD1/ACPRESENT
GPD10/SLP_S5#
GPD5/SLP_S4#
GPD4/SLP_S3#
GPD6/SLP_A#
GPD9/SPL_WLAN#
GPP_B11/PMCALERT#
GPP_H18/CPU_C10_GATE#
GPP_H3/SX_EXIT_HOLDOFF#
GPP_B12/SLP_S0#
SLP_LAN#
WAKE#
RSMRST#
SYS_RESET#
GPP_B13/PLTRST#
GPD2/LAN_WAKE#
GPD11/LANPHYPC/DSWLDO_MON
GPD7
DSW_PWROK
SYS_PWROK
PCH_PWROK
VCCSTPWRGOOD_TCSS
VCCST_PWRGD
VCCST_OVERRIDE
INTRUDER#
SPIVCCIOSEL
GPP_F20/EXT_PWR_GATE#
GPP_F21/EXT_PWR_GATE2#
BM9
DK41
DN41
DK43
TP_VCORE_PWRGD
SIO_PWRBTN#
PCH_BATLOW#
AC_PRESENT
1
CW40
DN27
DG31
TBT_PD_ALERT#
CPU_C10_GATE#
TPM_PRSNT#
1
DK39
PCH_PCIE_WAKE#
DM41
DT41
LAN_WAKE#
DN43
PCH_TBT_PERST#_GPD7
follow 612304 Ver0.9
TP1702
3D3V_S5
20191211
For TBT solution
TP1703
CE5
BP8
BP9
VCCSTPWRGOOD_TCSS
VCCST_PWRGD_R
VCCST_OVERRIDE_R
DR12
DW12
EXT_PWR_GATE#
EXT_PWR_GATE2#
VCCST_OVERRIDE
2
0R0402-PAD-7-NP-GP
VCCST_OVERRIDE
2
0R0402-PAD-7-NP-GP
R1731 1
R1728 1
Q1702
2
PM_RSMRST#
5
1MR2F-GP
1
ALL_SYS_PWRGD
2
3D3V_S5
1
[72]
TBT_PD_ALERT#
ALL_SYS_PWRGD 2
[24]
[16,71]
5
A
GND
Y
R1702
R1724
1
DY
DY
2
2
2
2
R1744
100KR2J-1-GP
20200413(DVT2)
Change R1713 to 100K follow intel SPEC
AC_PRESENT
PCH_BATLOW#
EXT_PWR_GATE#
EXT_PWR_GATE2#
100KR2J-1-GP
10KR2J-3-GP
100KR2J-1-GP
100KR2J-1-GP
20191112 modify
need confirm
LAN_WAKE#
2 10KR2J-3-GP
R1706
4K7R2J-2-GP
DY
VCCST_OVERRIDE
PCH_PWROK
SYS_PWROK
DSW_PWROK_R
R1730
R1732
R1733
R1734
1
1
1
1
C
2
2
2
2
100KR2J-1-GP
100KR2J-1-GP
100KR2J-1-GP
100KR2J-1-GP
20191220
Follow Intel design
20191217
Follow Nakia N7
From EC Control
3V_5V_PWRGD
1KR2F-3-GP
VCCST_PWRGD_RR
4
1
1
1
1
R1703
1
2
60D4R2F-GP
R1750
VCCST_PWRGD_R
1
DSW_PWROK_R
2 68KR2F-GP
C1750
SCD1U10V2KX-4DLGP
DY
2
3
NC#1 VCC
1D05V_VCCST
1
U1704
2
1
PWR_IMVP_PWRGD
2
[44,46]
SCD1U16V2KX-3DLGP
C1702
R1713
R1715
R1740
R1741
SPI_VCC_SEL
R1714
1MR2F-GP
SYS_RESET# 20191225
Follow Intel check list
20200304
Change SYS_RESET# PU to 3D3V_S5_VCCPRIM
2 10KR2J-3-GP
1
Volatge Level 1V
LAN_WAKE#
C1701
20191224
Follow Internal review
4K7R2J-2-GP
RTC_INTRUDER#
C
[24]
2
2
75.27002.F7C
AC_IN#
1
3D3V_S5_VCCPRIM
R1705
DY
2N7002KDW-1-GP
PCH_DPWROK
R1704
4
1
3
PCH_PLTRST#
3D3V_S5_VCCPRIM
R1701
SCD1U16V2KX-3DLGP
[17,24,40,44,46]
TPM
PCH_PCIE_WAKE#
2 1KR2F-3-GP
3D3V_S5_VCCPRIM
2
PM_RSMRST#_M
RTC_AUX_S5
1
2
2nd = 083.52030.008F
83.R2003.A8MAC_PRESENT
6
1
R1727
SPI SELECT STRAP
LOW → 3.3V
HIGH → 1.8V
2
CPU_C10_GATE#
[44]
Note:ZZ.27002.F7C01
3D3V_AUX_S5
AC_IN#
1
PM_RSMRST#
R1737 1
100KR2J-1-GP
[24]
R1743
100KR2J-1-GP
20191111 follow Nakia
SPI SELECT STRAP
Cap LOW → 3.3V
Cap DY → 1.8V
1
D1701
RB520S30-GP
A
K
1
[40]
D
PCH_TBT_PERST#
2 0R2J-2-GP
DY
3D3V_S5
VCCST_OVERRIDE
[64]
TPM_PRSNT#
20200224(DVT1)
Reserve 0 ohm to GPD7
1
TGL-U-1-GP-U2
[40]
R1742
100KR2J-1-GP
fwTPM
R1748
20191219
Follow Nakia
20200330(DVT2)
Follow CY20 change to 3.3V_S5
2
SIO_SLP_S3#
1
[40,55,81]
1
20191217
Follow Intel Requirement
20191220
Follow vendor suggest
1
[61,63,66,71,76,91]
12 OF 21
2
CPU1L
2
4
1
5
EC_PCH_SPI_EN
74LVC1G07GW-GP
3D3V_AUX_S5
R1707
1
DY
73.01G07.0HG
2nd = 073.7SZ07.000G
3rd = 73.01G07.AHG
PCH_TBT_PERST#
1
11.11 Follow Nakia
20191112 modify
20191211
Remove R1725, R1726
2 100KR2J-1-GP
R1708
3D3V_S5
SCD1U16V2KX-3DLGP
C1714
3
PM_RSMRST#
R1709
1
3V_5V_POK#
5
2
3V_5V_POK_C
R1710
1
6
1
4
Note:ZZ.27002.F7C01
2
Q1701
10KR2J-3-GP
1
DY
2
2
PCH_RSMRST#
2 1KR2J-1-GP
3V_5V_PWRGD
0R0402-PAD-7-NP-GP
PCH_RSMRST#
PCH_DPWROK
3D3V_S5_R
R1711
1
1
1
2
PCH_RSMRST#_U
PCH_DPWROK_R
3D3V_S5_U
2
100KR2J-1-GP
1
2
3
4
VDD
PCH_RSMRST#
PCH_DPWPOK
DSW_PWROK
K
PCH_DPWROK
RB520S30-GP
DSW_PWROK A
D1703
DYK
B
DSW_PWROK_R
5
C1712
74LVC1G08GW-1-GP
73.01G08.L04
2nd = 073.7SZ08.000G
3rd = 73.01G08.IHG
4th = 73.7SZ08.DAH
R1776
1
0R1J-GP
2
DY
DY
1 R1751
DSW_PWROK
6
DY
Q1703_2_3
2
DY
1 100KR2J-1-GP
2
1
3D3V_S5
PCH_RSMRST#
R1736
DY 10KR2F-2-GP
2N7002KDW-1-GP
75.27002.F7C
DSW_PWROK
DSW_PWROK
U1702
1
2
3
B
VCC
A
Y
5
4
PM_RSMRST#
GND
74LVC1G08GW-1-GP
R1739
DY1MR2F-GP
2
20191220
Follow Intel design
0R0402-PAD-7-NP-GP
73.01G08.L04
2nd = 073.7SZ08.000G
3rd = 73.01G08.IHG
4th = 73.7SZ08.DAH
PCH_DPWROK
20191213
Follow HC ICL for G3 sharing
RB520S30-GP
A
4
GND
R1735
3
1
Y
4
1
A
3
3V_5V_PWRGD
1 R1772
2
0R0201-PAD-GP
EC_PCH_SPI_EN
1 R1774
2
0R0201-PAD-GP
SC_191206_add RN1701 R1771 R1772 R1773 R1774 R1775
SC_191209_delete RN1701 and add U1703
SC_191211 add C1714
2
2
A
83.R2003.A8M
2nd = 083.52030.008F
VCC
2
5
SCD1U16V2KX-3DLGP
3D3V_S5_R
DY
SCD1U16V2KX-3DLGP
D1702
C1713
3V_5V_PWRGD_U
EC_PCH_SPI_EN_R
3D3V_S5
Q1703
B
Note:ZZ.27002.F7C01
1
3D3V_S5_R
100KR2J-1-GP
3D3V_S5
U1710
1
1
3D3V_S5_PCH_R
8
7
6
5
074.43789.M001
2
20191121
Follow ICL G3 Rework
1 R1738 2
390KR2F-GP
2
R1721 1
2
3D3V_S5_VCCPRIM
3V_5V_PWRGD
NC#7
EC_PCH_SPI_EN
GND
SLG4E43789VTR-1-GP
Power on sequence for G3 sharing
3D3V_S5
20191223
20191213
Change Part number
Follow HC ICL for G3 sharing
U1703
R17730R0201-PAD-GP
R17750R0201-PAD-GP
R1771 0R0201-PAD-GP
2N7002KDW-1-GP
B
2
2
1
A
83.R2003.A8M
2nd = 083.52030.008F
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Date:
5
CPU (PMU)
Size
Document Number
Custom
4
3
2
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
17
of
A00
105
5
4
3
2
1
SPI ROM
[24,25,91]
[15,24,25]
[15,24,25]
[24,25,91]
5,24,25,91]
[24,25]
[24,25]
[91]
3D3V_S0
SPI_CLK_ROM
SPI_HOLD_ROM
SPI_WP_ROM
SPI_SO_ROM
SPI_SI_ROM
SPI_CS_ROM_N0
SPI_CS_ROM_N1
SPI_CS_ROM_N2
[17,64]
3D3V_S5
1 R1821
RN1803
SPK_ID
1
2
ESPI_IO0
ESPI_IO1
ESPI_IO2
ESPI_IO3
[24,68]
[24,68]
[24,68]
ESPI_CS#
ESPI_RESET#
ESPI_CLK
3D3V_S5
RN1807
SPI_CLK_ROM
SPI_HOLD_ROM
SPI_WP_ROM
SPI_SO_ROM
SPI_SI_ROM
SPI_CS_ROM_N1
SPI_CS_ROM_N0
R1826
R1827
R1828
R1829
R1830
R1831
R1832
SPK_ID
1
1
1
1
1
1
1
CPU1E
2
2
2
2
2
2
2
0R0402-PAD-7-NP-GP
0R0402-PAD-7-NP-GP
0R0402-PAD-7-NP-GP
0R0402-PAD-7-NP-GP
0R0402-PAD-7-NP-GP
0R0402-PAD-7-NP-GP
0R0402-PAD-7-NP-GP
DJ37
DG35
DJ39
DJ33
DJ35
DF35
DG37
DF39
GPP_E11
DJ6
DN5
DR9
DM6
DK6
DK8
DV11
DW9
DT8
GC6_FB_EN
1 R1842 2
0R0402-PAD-7-NP-GP
GC6_FB_EN_MCP
SPK_ID
HOST_SD_WP#
SSD2_CLK_CPU_P
SSD2_CLK_CPU_N
SSD2_CLKREQ_CPU_N
DGPU_HOLD_RST# R1843 1
OPS
DN15
DK13
DM13
DN13
DJ15
DK15
DN10
DV14
2 10KR2J-3-GP
DH3
DH4
DF2
GPU
[76]
[76]
[76]
5 OF 21
SPI0_CLK
SPI0_IO3
SPI0_IO2
SPI0_MISO
SPI0_MOSI
SPI0_CS1#
SPI0_CS0#
SPI0_CS2#
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_B23/SML1ALERT#/PCHHOT#/GSPI1_CS1#
GPP_E11/SPI1_CLK/THC0_SPI1_CLK
GPP_E2/SPI1_IO3/THC0_SPI1_IO3
GPP_E1/SPI1_IO2/THC0_SPI1_IO2
GPP_E12/SPI1_MISO_IO1/THC0_SPI1_IO1
GPP_E13/SPI1_MOSI_IO0/THC0_SPI1_IO0
GPP_E10/SPI1_CS#/THC0_SPI1_CS#
GPP_E8/SPI1_CS1#/SATA_LED#
GPP_E17/THC0_SPI1_INT#
GPP_E6/THC0_SPI1_RST#
GPP_A5/ESPI_CLK
GPP_A3/ESPI_IO3/SUSACK#
GPP_A2/ESPI_IO2/SUSWARN#_SUSPWRDNACK
GPP_A1/ESPI_IO1
GPP_A0/ESPI_IO0
GPP_A4/ESPI_CS#
GPP_A6/ESPI_RESET#
SATA_LED#
DK21
DM19
DN19
CPU_SMB_SCL
CPU_SMB_SDA
CPU_SMB_ALERT#
DK19
DM17
DN17
SML0_SMBCLK
SML0_SMBDATA
SML0_ALERT#
DK17
DJ17
CY50
SML1_SMBCLK
SML1_SMBDATA
SML1_ALERT#
DN53
DJ53
DH50
DP50
DP52
DK52
DL50
PCH_ESPI_CLK
PCH_ESPI_IO3
PCH_ESPI_IO2
PCH_ESPI_IO1
PCH_ESPI_IO0
PCH_ESPI_CS#
PCH_ESPI_RESET#
R1802
1
2
10KR2J-3-GP
RN1801
1
2
20191217
Follow HC TGL 13
SO-DIMM
GPU_THM_SMBCLK
GPU_THM_SMBDAT
4
3
SML1_SMBCLK
SML1_SMBDATA
D
SRN1KJ-7-GP
BB
1D8V_S5
PD
GPP_F11/THC1_SPI2_CLK
GPP_F15/GSXSRESET#/THC1_SPI2_IO3
GPP_F14/GSXDIN/THC1_SPI2_IO2
GPP_F13/GSXSLOAD/THC1_SPI2_IO1
GPP_F12/GSXDOUT/THC1_SPI2_IO0
GPP_F16/GSXCLK/THC1_SPI2_CS#
GPP_F18/THC1_SPI2_INT#
GPP_F17/THC1_SPI2_RST#
4
3
SRN1KJ-7-GP
GPP_B23 Strap pin can't pull High
Follow Bacchus
ESPI_CLK
2 33R2F-3-GP
R1804 1
ESPI_IO3
2 15R2F-2-GP
R1808 1
ESPI_IO2
2 15R2F-2-GP
R1807 1
ESPI_IO1
2 15R2F-2-GP
R1806 1
ESPI_IO0
2 15R2F-2-GP
R1805 1
ESPI_CS#
2
0R0402-PAD-7-NP-GP
R1809 1
1
2
0R0402-PAD-7-NP-GP ESPI_RESET#
R1810
2 75KR2F-GP
R1814 1
to EC,debug14pin
R1823
CPU_SMB_ALERT#
1
DY 2
10KR2J-3-GP
R1824
1
2
20191225
10KR2J-3-GP
Reserve for debug
R1825
1 DY 2 SML1_ALERT#
10KR2J-3-GP
3D3V_S0
RN1808
1
2
20191211
Follow Intel CRB use 1%
4
3
SRN1KJ-7-GP
CPU_SMB_SDA
Q1802
6
5
CL_CLK
CL_DATA
CL_RST#
4
Note:ZZ.27002.F7C01
[63]
[63]
[63]
SPI_CLK_R_CPU
SPI_HOLD_R_CPU
SPI_WP_R_CPU
SPI_SO_R_CPU
SPI_SI_R_CPU
SPI_CS_CPU_N1
SPI_CS_CPU_N0
SPI_CS_ROM_N2
GPP_E10
SATA_LED#
DGPU_HOLD_RST#
GPP_E6
M.2 SSD
[63] SSD_CLK_CPU_N
[63] SSD_CLK_CPU_P
[63] SSD_CLKREQ_CPU_N
[64] SATA_LED#
1
2
3D3V_S0
20191211
Follow Intel TGL PDG
20200512
Follow Intel TGL PDG
Audio
[29]
CPU_SMB_SCL
CPU_SMB_SDA
SRN1KJ-7-GP
PM_RSMRST#
[24,68]
[24,68]
[24,68]
[24,68]
4
3
10KR2J-3-GP
EC
D
2
1
3
2N7002KDW-1-GP
GFX_CLK_CPU_N
GFX_CLK_CPU_P
CLK_PCIE_PEG_REQ#
CPU1K
CPU_SMB_SCL
11 OF 21
PCH_SMBDATA
2
PCH_SMBCLK
75.27002.F7C
3D3V_S0
[76] DGPU_HOLD_RST#
[79,86] GC6_FB_EN
RN1805
SMBUS
PCH_SMBCLK
PCH_SMBDATA
OTHER
HOST_SD_WP#
[24,61] SUSCLK
R1819
1
SSD1
SSD_CLK_CPU_P
SSD_CLK_CPU_N
CL7
CL8
LAN
LAN_CLK_CPU_P
LAN_CLK_CPU_N
CB4
CB5
WLAN
WLAN_CLK_CPU_P
WLAN_CLK_CPU_N
BY4
BY3
GPU
GFX_CLK_CPU_P
GFX_CLK_CPU_N
CN7
CN8
XCLK_BIASREF
2 60D4R2F-GP
TGL-U-1-GP-U2
DJ5
XTAL_OUT
XTAL_IN
CLKOUT_PCIE_P3
CLKOUT_PCIE_N3
GPD8/SUSCLK
CLKOUT_PCIE_P2
CLKOUT_PCIE_N2
RTCX2
RTCX1
CLKOUT_PCIE_P1
CLKOUT_PCIE_N1
RTCRST#
SRTCRST#
DM1
DL1
XTL_38D4M_X2_CPU
XTL_38D4M_X1_CPU
DW41
SUSCLK
DT47
DR47
XTL_32K_X2_CPU
XTL_32K_X1_CPU
DN37
DK37
RTC_RST#
SRTC_RST#
20200302(DVT1)
Add R1844 R1845 for EMC protect
R1844
10R2J-2-GP 2
1
2
R1845
R1801
RN1802
SRN20KJ-1-GP
4
3
SRTC_RST#
RTC_RST#
3
1
4
2
1
2
C1804
SC1U10V2KX-1DLGP
Layout: Place at the open door area.
XTAL-38D4MHZ-35-GP
082.30040.0221
2nd = 082.30040.0251
3rd = 082.30040.0231
20200324(DVT2)
X1802 change to common
20200413(DVT2)
BOM use 082.30040.0251 main
082.30040.0221 2nd
1
C1806
2
1
B
2
082.30003.0191
2nd = 082.30003.0301
2
C1801
G1801
1
SC1U10V2KX-1DLGP
C1803
2
1
2 10MR2J-L-GP
1
2
X1801
XTAL-32D768KHZ-88-GP
2 200KR2F-L-GP
C1805
SC10P50V2JN-4DLGP
WLAN_CLK_CPU_P
WLAN_CLK_CPU_N
CLK_PCIE_WLAN_REQ#
USBC1_AUX_N_BIAS
CLK_PCIE_SD_REQ#
CLK_PCIE_LAN_REQ#
MEM_SMBCLK
MEM_SMBDATA
SMLB_ALERT#
1
X1802
SC10P50V2JN-4DLGP
DV14:
DT24:
DT30:
DK21:
DM19:
DN19:
WLAN
1
R1820
SC15P50V2JN-DL-GP
LAN_CLK_CPU_N
LAN_CLK_CPU_P
CLK_PCIE_LAN_REQ#
R1811
C1802
SC15P50V2JN-DL-GP
DW9: DGPU_HOLD_RST#
DK13: SPK_ID
DM13: AUD_PWR_EN
DN13: HOST_SD_WP#
DJ15: WWAN_DB_DET#
DK15: USBC1_AUX_P_BIAS
1
2 SSD_CLKREQ_CPU_N
10KR2J-3-GP
0R2J-2-GP
XCLK_BIASREF
XTL_32K_X1_CPU
TS_SPI_CLK
TS_SPI_IO3
TS_SPI_IO2
TS_SPI_SO
TS_SPI_SI
TS_SPI_CS#
C
SRN10KJ-6-GP
XTL_38D4M_X2
XTL_38D4M_X1
CLKOUT_PCIE_P0
CLKOUT_PCIE_N0
2
DJ6:
DN5:
DR9:
DM6:
DK6:
DK8:
8 CLK_PCIE_LAN_REQ#
7 CLK_PCIE_PEG_REQ#
6 CLK_PCIE_WLAN_REQ#
5 SSD2_CLKREQ_CPU_N
RTC_AUX_S5
XTL_38D4M_X2
1
GPP_E11
SSD_CLKREQ_CPU_N
CLK_PCIE_LAN_REQ#
CLK_PCIE_WLAN_REQ#
CLK_PCIE_PEG_REQ#
XTL_38D4M_X1
2
GPP_E10
[15]
1
2
3
4
SSD2_CLKREQ_CPU_N
GAP-OPEN
[15]
DU14
DF23
DG25
DT24
DT30
DV30
DW30
XTL_32K_X2_CPU
B
[24,26,79]
[24,26,79]
CLKOUT_PCIE_P4
CLKOUT_PCIE_N4
GPP_E6
LAN
[61]
[61]
[61]
CLKOUT_PCIE_P5
CLKOUT_PCIE_N5
SML0_ALERT#
[15]
[66]
[66]
[66]
GPP_F19/SRCCLKREQ6#
GPP_H11/SRCCLKREQ5#
GPP_H10/SRCCLKREQ4#
GPP_D8/SRCCLKREQ3#
GPP_D7/SRCCLKREQ2#
GPP_D6/SRCCLKREQ1#
GPP_D5/SRCCLKREQ0#
TGL-U-1-GP-U2
HW STRAP
[15]
CB2
CB1
BW4
BW5
20191028 Mao Lee (EVT1)
For PCIE4.0 need use #3 or #0
[72] SML1_SMBCLK
[72] SML1_SMBDATA
[71] SML0_SMBCLK
[71] SML0_SMBDATA
[66]
SSD2_CLK_CPU_P
SSD2_CLK_CPU_N
1
[12,13]
[12,13]
SSD2
CLKOUT_PCIE_P6
CLKOUT_PCIE_N6
1
2
BW1
BW2
C
GPU_THM_SMBCLK
GPU_THM_SMBDAT
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A2
Date:
5
4
3
2
CPU (SPI/LPC/SMBS/XTAL/CLK)
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
18
of
A00
105
5
4
3
2
1
Audio
[27] HDA_SYNC_CODEC
[27] HDA_BITCLK_CODEC
[27] HDA_SDOUT_CODEC
[27] HDA_SDIN0_CPU
[15] HDA_SDO
[55]
[55]
20191112 modify
Follow Nakia
1D8V_S5
3D3V_S0
DMIC_PCH_CLK_Q
DMIC_PCH_DATA_Q
1
R1949
2 1KR1J-GP
RTC_DET#
R1907
1
GPU
[24,85]
SNDW_RCOMP
R1903
1
2 200R2F-L-GP
DY
2
FFS_INT2
10KR2J-3-GP
DGPU_PWROK
D
D
DGPU_PWR_EN
Colse to R1904
RTC_DET#
DMIC_PCH_CLK_R
DMIC_PCH_DATA_R
2 10R2J-2-GP-U HDA_BCLK
2 10R2J-2-GP-U HDA_SYNC
2 10R2J-2-GP-U HDA_SDO
HDA_SDI0
2
0R0402-PAD-7-NP-GP
2 1KR1J-GP
1
1
1
1
1
R1916 1
R1917 1
2 0R0201-PAD-GP
2 0R0201-PAD-GP
BT
BT_RADIO_DIS#
DV41: HDA_RST#
DW15: CAM_MIC_CBL_DET#
DN31: TBT_DET#
3D3V_S5_VCCPRIM
1
GPP_S0/SNDW0_CLK
GPP_S1/SNDW0_DATA
Description
Setting
Mapping
1D8V_S5_VCCPRIM
DG41
DT38
DV38
DW38
DGPU_PWROK
BOARD_ID1
BOARD_ID2
RTC_DET#
DN31
DM31
TBT_DET#
DK33
DK31
VRAM_ID1
VRAM_ID2
DW35
DV35
PROJECT_ID2
PROJECT_ID3
DT32
DR35
PROJECT_ID0
PROJECT_ID1
TBT_DET#
no TBT
0
Have TBT
TBT function detected
R1906
10KR2J-3-GP
20191211
For TBT solution
1
NO TBT
TBT_DET#
R1919
10KR2J-3-GP
Have TBT
R1921
R1923
Vostro
10KR1J-GP
1
2
10KR1J-GP
PROJECT_ID2
PROJECT_ID[3:2]
Mapping
11
Inspiron
10
Vostro
01
Latitude
Reseved
Project Type
10KR1J-GP
PROJECT_ID1
C
PROJECT_ID0
R1925
00
R1927
HC 14/MKB N V
HC 15/HC 17
10KR1J-GP
Setting
R1926
HC 15/HC 17
1
10KR1J-GP
R1924
HC 14/MKB N V
2
2
10KR1J-GP
Description
1D8V_S5_VCCPRIM
10KR1J-GP
2
1
1
1
1
2
R1922
ID
PROJECT_ID[1:0]
1D8V_S5_VCCPRIM
Inspiron/Latitude
Latitude
10KR1J-GP
PROJECT_ID[1:0]
N/A
11
3000 Series
10
5000 Series(HC 14/MKB N V)
01
7000 Series(HC 15/HC 17)
Project Series
20200424(DVT1)
R1944 change to 0 ohm
00
N/A
5
1 R1944 2
0R0402-PAD-7-NP-GP
M74VHC1GT50DFT1G-GP
DMIC_PCH_CLK_Q
4
1D8V_S5_VCCPRIM
DY
U1902_2
2
1
1
R1910
DY
2
10KR1J-GP
20191112 modify
Follow Nakia
20191126
For High Limit
10KR1J-GP
BOARD_ID2
Description
ID
BOARD_ID1
TGL-U-1-GP-U2
R1909
R1911
10KR1J-GP
Setting
Mapping
11
N/A
10
Board ID[2:1]
0R1J-GP
2
1D8V_S5
R1908
DY
2
2
2
2
U1902_4 1
R1948
1D8V_S5_VCCPRIM
CY20 Board ID Mapping table
C1902
SC27P50V2JN-2-GP
2nd = 073.74134.0A0G
C1901
DY
R1945
SCD1U16V2KX-3DLGP
DY1KR1F-GP
1
1
1
73.1GT50.00H
1
DMIC_PCH_CLK_R 1 R1943 2
0R0402-PAD-7-NP-GP
R1920
PROJECT_ID3
3D3V_S5
0R1J-GP
1D8V_S5_VCCPRIM
Inspiron/Vostro
U1901_4
2
20191126
For High Limit
PROJECT_ID[3:2]
1D8V_S5_VCCPRIM
U1901
1
2
3
ID
DW15
DW24
10KR2J-3-GP
R1942
DY
GPP_S2/SNDW1_CLK/DMIC_CLK_B0
GPP_S3/SNDW1_DATA/DMIC_CLK_B1
SNDW_RCOMP
2
OPS
2
U1901_2 1
GPP_S4/SNDW2_CLK/DMIC_CLK_A1
GPP_S5/SNDW2_DATA/DMIC_DATA1
GPP_A13/PMC_I2C_SCL/I2S3_TXD/DMIC_CLK_B0
R1941
2DGPU_PWR_EN
20191129
Follow ICL
20200212
no need level shift
20200331
ADD LEVEL SHIFT to Verify
20200416(DVT2)
Follow MKB AMD solution
20200508(DVT2)
Follow Nakia add DATA's Solution
C
DF33
GPP_S6/SNDW3_CLK/DMIC_CLK_A0
GPP_S7/SNDW3_DATA/DMIC_DATA0
GPP_A9/I2S2_TXD/MODEM_CLKREQ/CRF_XTAL_CLKREQ/DMIC_CLK_A1
GPP_A11/PMC_I2C_SDA/I2S3_SCLK
1
DY
10KR2J-3-GP
For SITP
DH49
GPP_A23/I2S1_SCLK
GPP_R7/I2S1_SFRM
GPP_R6/I2S1_TXD
GPP_R5/HDA_SDI1/I2S1_RXD
1
1
DL49
DL52
BT_RADIO_DIS#
GPP_F8/I2S_MCLK2_INOUT
GPP_D19/I2S_MCLK1
GPP_R4/HDA_RST#
GPP_A7/I2S2_SCLK/DMIC_CLK_A0
GPP_A8/I2S2_SFRM/CNV_RF_RESET#/DMIC_DATA_0
GPP_A10/I2S2_RXD/DMIC_DATA1
2
R1928
ME_FWP_SW
DV41
DL53
DG51
DG50
DGPU_PWR_EN
SNDW_RCOMP
ME
[98]
DMIC_PCH_CLK
DMIC_PCH_DATA
FFS_INT2
GPP_R0/HDA_BCLK/I2S0_SCLK
GPP_R1/HDA_SYNC/I2S0_SFRM
GPP_R2/HDA_SDO/I2S0_TXD
GPP_R3/HDA_SDI0/I2S0_RXD
2
[61]
DR38
DU37
DT37
DV37
1
R1904
R1901
R1905
R1918
R1902
2
RTC
[25]
SC10P50V2JN-4DLGP
HDA_BITCLK_CODEC
HDA_SYNC_CODEC
HDA_SDOUT_CODEC
HDA_SDIN0_CPU
ME_FWP_SW
1
DY2
2
1
EC1901
FFS_INT2
1
G SENSOR
[70]
CPU1G
7 OF 21
2
[86]
N/A
Board SKU ID
10KR1J-GP
01
TGL-UP4
00
TGL-UP3
U1902
1 R1946 2
4
0R0402-PAD-7-NP-GP
M74VHC1GT50DFT1G-GP
DMIC_PCH_DATA_Q
0R0402-PAD-7-NP-GP
1D8V_S5_VCCPRIM
20191112 modify
Follow Nakia
20191126
R1912
For High Limit
1
UMA
1D8V_S5_VCCPRIM
CY20 VRAM ID Mapping table
B
R1914
ID
Description
VRAM_ID[2:1]
dGPU VRAM size
4GB VRAM/UMA
Setting
Mapping
10KR1J-GP
2
2
2
2GB VRAM/4GB VRAM
10KR1J-GP
10KR1J-GP
11
VRAM_ID1
1
VRAM_ID2
R1913
R1915
2GB VRAM
2
1
2nd = 073.74134.0A0G
C1904
SCD1U16V2KX-3DLGP
2
2
2
2
C1903
SC27P50V2JN-2-GP
DY
R1950
DY1KR1F-GP
R1947
73.1GT50.00H
1
1
B
1
1
DMIC_PCH_DATA_R
1
2
3
1
5
10KR1J-GP
UMA Board
10
N/A
01
DIS Board with 4GB VRAM
00
DIS Board with 2GB VRAM
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A2
Date:
5
4
3
2
CPU (HAD/I2S/SD/DMIC)
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
19
of
A00
105
5
4
3
2
20200304
KB_LED_BL_DET , GPP_C10 -> GPP_D16
Internal review , follow Nakia
Follow GPIO table
CPU1F
TOUCH PAD/E3
[65,66]
[65,66]
PCH_I2C1_SCL_TP
PCH_I2C1_SDA_TP
3D3V_S0
SPKR
R2058
1
FFS_INT1
DY
2
FFS_INT1
SENSOR_I2C_SDA
SENSOR_I2C_SCL
TP2010
GSEN2_INT1_C
GSEN_INT1_C
3D3V_S0
1
[70]
[55]
AUDIO
SPKR
2
[27]
R2057
100KR2J-1-GP
TOUCH_PANEL_DET#
20191211
follow Upsell
20191212
Follow CY20
PCH to Touch Screen
SDA/SCL/INT Pull UP on PD side(page72)
OTHER
TABLE_MODE#
[24]
NB_MODE#
CY49
CY53
CY52
DA50
DV21
DT21
DR21
DW21
PCH to Touch Pad/E3
TOUCH_PANEL_DET#
DV19
DT19
DR18
DU19
UART_2_CTXD_DRXD
UART_2_CRXD_DTXD
TOUCH_PANEL_INTR#
DJ21
DG23
DJ19
DF21
I2C0_SCL_TS
I2C0_SDA_TS
DV18
DW18
PCH_I2C1_SCL_TP
PCH_I2C1_SDA_TP
DJ23
DT18
SDA/SCL/INT Pull UP on TP side(page65)
DJ29
DJ31
TPM_SPI_IRQ#
DBC_PANEL_EN
DF29
DG29
DF25
DF27
GPP_B16/GSPI0_CLK
GPP_B18/GSPI0_MOSI
GPP_B17/GSPI0_MISO
GPP_B14/SPKR/TIME_SYNC1/GSPI0_CS1#
GPP_B15/GSPI0_CS0#
GPP_D14/ISH_UART0_TXD
GPP_D13/ISH_UART0_RXD
GPP_D16/ISH_UART0_CTS#
GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/IMGCLKOUT5
GPP_B6/ISH_I2C0_SCL
GPP_B5/ISH_I2C0_SDA
GPP_B20/GSPI1_CLK
GPP_B22/GSPI1_MOSI
GPP_B21/GSPI1_MISO
GPP_B19/GSPI1_CS0#
GPP_B8/ISH_I2C1_SCL
GPP_B7/ISH_I2C1_SDA
GPP_C9/UART0_TXD
GPP_C8/UART0_RXD
GPP_C11/UART0_CTS#
GPP_C10/UART0_RTS#
GPP_B10/I2C5_SCL/ISH_I2C2_SCL
GPP_B9/I2C5_SDA/ISH_I2C2_SDA
GPP_E16/ISH_GP7
GPP_E15/ISH_GP6
GPP_D18/ISH_GP5
GPP_D17/ISH_GP4
GPP_D3/ISH_GP3/BK3/SBK3
GPP_D2/ISH_GP2/BK2/SBK2
GPP_D1/ISH_GP1/BK1/SBK1
GPP_D0/ISH_GP0/BK0/SBK0
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C21/UART2_TXD
GPP_C20/UART2_RXD
GPP_C23/UART2_CTS#
GPP_C22/UART2_RTS#
GPP_RCOMP
GPP_T3/I2C7_SCL
GPP_T2/I2C7_SDA
GPP_C17/I2C0_SCL
GPP_C16/I2C0_SDA
GPP_U5/GSPI3_CLK
GPP_U4/GSPI3_CS0#
GPP_C19/I2C1_SCL
GPP_C18/I2C1_SDA
DR27
DW27
DV25 KB_LED_BL_DET
DT25
DB45
DB44
CY39
DB47
ISH_I2C0_ACC_SCL
ISH_I2C0_ACC_SDA
Accelerometer sensor
DR51
0R0402-PAD-7-NP-GP
SENSOR_I2C_SCL
2
SENSOR_I2C_SDA
2
0R0402-PAD-7-NP-GP
R2052 1
R2051 1
ISH
20200113 DVT1
Follow Customer CY20 change from I2C2 to I2C5
PCH to BB
DD47 TBT_I2C_SCL
DD44 TBT_I2C_SDA
DJ8
DR7
DR24
DU25
DV31
DU31
DT27
DV27
20191125
Follow Upsell
20200504
Change to 0402 size
LID_CL_SIO_TAB#
ISH_LID_CL#_NB
ISH_NB_MODE
D
SDA/SCL Pull UP on BB side(page71)
20191210
Follow CY20
20191125
Follow CY20
R2054 1
R2056 1
0R0402-PAD-7-NP-GP LID_CL_SIO#
2
2 100KR2J-1-GP
0R0402-PAD-7-NP-GP
TABLE_MODE#
2
GSEN2_INT1_C
2
0R0402-PAD-7-NP-GP
GSEN_INT1_C
2 0R2J-2-GP
2IN1
ISH_TABLE_MODE#
ISH_ACC2_INT#
ISH_ACC1_INT#
R2053 1
R2037 1
R2039 1
2IN1
GPP_RCOMP
R2021
1
Gyro+G
2 200R2F-L-GP
DN33
DT35
DG17
DG19
GPP_H5/I2C2_SCL
GPP_H4/I2C2_SDA
GPP_H7/I2C3_SCL
GPP_H6/I2C3_SDA
GPP_H9/I2C4_SCL/CNV_MFUART2_TXD
GPP_H8/I2C4_SDA/CNV_MFUART2_RXD
TBT_I2C_SCL
TBT_I2C_SDA
eDP
DBC_PANEL_EN
LID
[24,66] LID_CL_SIO#
[24,66] LID_CL_SIO_TAB#
[68] UART_2_CTXD_DRXD
[68] UART_2_CRXD_DTXD
TOUCH
[55]
[55]
I2C0_SDA_TS
I2C0_SCL_TS
[55]
TOUCH_PANEL_DET#
[55]
TOUCH_PANEL_INTR#
3D3V_S5
Q2001
1
ISH_NB_MODE
2
BATT_WHITE_LED#
3
Note:ZZ.27002.F7C01
DA51: NRB_BIT
DC49: VGA_DB_DET#
CY49: TPM_PIRQ#
CY53: GC6_THM_DIS#_PCH
CY52: PCH_3.3V_TS_EN
DA50: HDD_FALL_INT
DV21: SBIOS_TX
DR21: USBC0_AUX_N_BIAS
DW21: USBC0_AUX_P_BIAS
DV19: DGPU_MACO_EN
DT19: SIO_EXT_WAKE#
DR18: PCH_HDD_EN
DU19: LCD_CBL_DET#
DG23: cTPM_PRSNT#
DJ19: TOUCH_PANEL_INTR#
DF21: TOUCH_I2C_DET#
DV18: I2C0_SCL_TS
DW18: I2C0_SDA_TS
DF29: DBC_PANEL_EN
DG29: LOM_CABLE_DETECT#
DF25: CNV_COEX1
DF27: CNV_COEX2
DR27: STYLUS_PWR_OCP#
DW27: CAM_SHUTTER#
DT25: IO_DB_DET#
CY39: ISH_I2C1_ALS_SCL
DB47: ISH_I2C1_ALS_SDA
DD47: ISH_I2C2_SCL
DD44: ISH_I2C2_SDA
DJ8: ISH_P_SENSOR_INT#
DV31: ISH_ALS_INT#
C
[55]
2
1
TGL-U-1-GP-U2
PD
[71]
[71]
3
4
6
NB_MODE#
5
MASK_SATA_LED#
4
SATA_LED#_D
C
2
[91]
TPM_SPI_IRQ#
GC6_THM_DIS#_PCH
FFS_INT1
KB_LED_BL_DET
[24]
1
20191224
1: Non Touch Panel
0: Touch Panel
KEYBOARD
[65]
RN2005
ISH_I2C0_ACC_SCL
ISH_I2C0_ACC_SDA
6 OF 21
2IN1
R2050
10KR2J-3-GP
1
D
DC53
DA51
DC49
DC50
DC52
20200420(DVT2)
Follow ICL reserved 3.3V PH
10KR2J-3-GP
[55,70]
[55,70]
3D3V_S0
SRN2K2J-1-GP
G SENSOR
[70]
1
20191129
layout design
2N7002KDW-1-GP
NB_MODE#
75.27002.F7C
DG17: ZPODD_PWR_EN#
DG19: ZPODD_DA#
B
B
[24,64]
[64]
[24,64]
MASK_SATA_LED#
SATA_LED#_D
BATT_WHITE_LED#
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A2
Date:
5
4
3
2
CPU (UART/I2C/ISH)
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
20
of
A00
105
5
4
3
2
1
Main Func = PCH
CPU1J
D
[61]
[61]
[61]
[61]
[61]
[61]
[61]
[61]
[61]
[61]
[61]
[61]
CNV_W R_DN0
CNV_W R_DP0
CNV_W R_DN1
CNV_W R_DP1
CNV_W R_CLKN
CNV_W R_CLKP
CNV_W T_DN0
CNV_W T_DP0
CNV_W T_DN1
CNV_W T_DP1
CNV_W T_CLKN
CNV_W T_CLKP
[61]
[15]
[61]
CNV_BRI_RSP
CNV_RGI_DT
CNV_RGI_DT_R
[61]
[61]
CNV_BRI_DT_R
CNV_RGI_RSP
D22
B22
E22
D20
A20
B20
B18
A18
D18
E18
C16
D16
D15
E15
A15
B15
L18
N18
L20
N20
G20
H20
[61]
CNV_RF_RESET#
[61]
CLKREQ_CNV
H16
G16
G18
H18
L16
N16
G14
H14
L14
N14
C
R2103
1
2 150R2F-1-GP
CSI_RCOMP
1
GPP_D4
TP2101
TPAD14-OP-GP
K14
DK25
DM25
DN25
DJ25
DR30
10 OF 21
CSI_F_DP1
CSI_F_DN1
CSI_F_DP0
CSI_F_DN0
CSI_F_CLK_P
CSI_F_CLK_N
CNVI_WT_D1P
CNVI_WT_D1N
CNVI_WT_D0P
CNVI_WT_D0N
CNVI_WT_CLKP
CNVI_WT_CLKN
CSI_E_DP1/CSI_F_DP2
CSI_E_DN1/CSI_F_DN2
CSI_E_DP0/CSI_F_DP3
CSI_E_DN0/CSI_F_DN3
CSI_E_CLK_P
CSI_E_CLK_N
CNVI_WR_D1P
CNVI_WR_D1N
CNVI_WR_D0P
CNVI_WR_D0N
CNVI_WR_CLKP
CNVI_WR_CLKN
CSI_C_DP2
CSI_C_DN2
CSI_C_DP3
CSI_C_DN3
CNVI_WT_RCOMP
GPP_F3/CNV_RGI_RSP/UART0_CTS#
GPP_F2/CNV_RGI_DT/UART0_TXD
GPP_F1/CNV_BRI_RSP/UART0_RXD
GPP_F0/CNV_BRI_DT/UART0_RTS#
CSI_C_DP1
CSI_C_DN1
CSI_C_DP0
CSI_C_DN0
CSI_C_CLK_P
CSI_C_CLK_N
GPP_F5/MODEM_CLKREQ/CRF_XTAL_CLKREQ
GPP_F6/CNV_PA_BLANKING
GPP_F4/CNV_RF_RESET#
DK47
DM47
DN49
DR49
DN45
DN47
CNV_W T_DP1
CNV_W T_DN1
CNV_W T_DP0
CNV_W T_DN0
CNV_W T_CLKP
CNV_W T_CLKN
DU43
DV43
DR44
DT43
DV44
DW44
CNV_W R_DP1
CNV_W R_DN1
CNV_W R_DP0
CNV_W R_DN0
CNV_W R_CLKP
CNV_W R_CLKN
D
DN51
CNV_W T_RCOMP
DJ13
DG13
DF15
DF17
CNV_RGI_RSP
CNV_RGI_DT
CNV_BRI_RSP
CNV_BRI_DT
DJ10
DV15
DK10
CLKREQ_CNV
R2102
1
2 150R2F-1-GP
2 R2110 1
0R0402-PAD-7-NP-GP
2 R2109 1
0R0402-PAD-7-NP-GP
CNV_RGI_DT_R
CNV_BRI_DT_R
CNV_RF_RESET#
CSI_B_DP1
CSI_B_DN1
CSI_B_DP0
CSI_B_DN0
CSI_B_CLK_P
CSI_B_CLK_N
C
CSI_B_DP2
CSI_B_DN2
CSI_B_DP3
CSI_B_DN3
CSI_RCOMP
GPP_H23/IMGCLKOUT4
GPP_H22/IMGCLKOUT3
GPP_H21/IMGCLKOUT2
GPP_H20/IMGCLKOUT1
GPP_D4/IMGCLKOUT_0/BK4/SBK4
TGL-U-1-GP-U2
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A3
Date:
5
4
3
2
CPU (CSI/EMMC/CNVi)
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
21
of
A00
105
5
4
3
CPU1N
3,24,44,46,72]
PROCHOT#_CPU
[40]
V1P05_CTRL_R
[40]
VNN_CTRL_R
PH/PL 100R at VR side.
VSSAUX_SENSE
VCCAUX_SENSE
DD17
DD18
20191224
Follow Internal review(200mA) 1D05V_VNN_BYPASS
3D3V_S5_VCCPRIM
(200mA)
C
VNN_CTRL_R
V1P05_CTRL_R
R2215
R2212
R2213
DA15
DA17
1D05V_S5_BYPASS
2 10KR2J-3-GP VRALERT#
VNN_CTRL
DY 22 0R2J-2-GP V1P05_CTRL
0R0402-PAD-7-NP-GP
20191112 modify
CORE_VID0
Follow Nakia
CORE_VID1
1
1
1
D2201
RB520S30-GP
A
K
PROCHOT#_CPU
AV9
AT9
DB39
DV12
DT12
DB37
DB38
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3
DCPRTC
VCCLDOSTD_0P85
VCCA_CLKLDO_1P8
VCCA_CLKLDO_1P8
VCCIN_AUX_VSSSENSE
VCCIN_AUX_VCCSENSE
VCCDPHY_1P24
VCCDSW_1P05
VCC_VNNEXT_1P05
VCC_VNNEXT_1P05
VCC1P05
VCC1P05
VCC1P05
VCC_V1P05EXT_1P05
VCC_V1P05EXT_1P05
VCCPRIM1P05_OUT_PCH
VCCPRIM1P05_OUT_PCH
VCCPRIM1P05_OUT_PCH
GPP_B2/VRALERT#
GPP_F22/VNN_CTRL
GPP_F23/V1P05_CTRL
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
VCCRTC
VCCDSW_3P3
VCCPGPPR
VCCGPPR
3.3V or 1.8V
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_1P8
VRALERT#
RSVD#AP12
20191210
83.R2003.A8M
Follow Nakia N7
Intel CRB and Intel review 2nd = 083.52030.008F
1 R2203 2
0R0805-PAD-NP-GP
CY18
CY20
CY24
CY26
DA18
DA20
DA22
DA24
DA26
DC18
DC20
DC22
DC24
DC26
DD20
DD22
DV22
C2204
SC1U10V2KX-1DLGP
Place cap within
3mm from SOC edge
20191112 modify
(200mA)
DA35
DC28
DC30
DD30
DV34
3D3V_RTC_EXT
DV46
0D85V_S5_VCCLDOSTD_OUT
DV16
DC15
1D8V_S5_CLKLDO (165mA)
DV28
1D24V_S5_VCCDPHY_OUT
DD38
1D05V_S5_VCCDSW _OUT
20200504(DVT2)
C2213 change to common
BR3
BR4
BT5
(1.5A) Supply to
VCCST & VCCSTG
1D05V_S5_OUT
C
DA31
DC33
DC31
1D05V_S5_VCCPRIM_OUT
3D3V_VCCDSW
20191112 modify
20191211
(3mA) Follow Nakia 1D8V_S5
R2202 3D3V_S5
DY 20R2J-2-GP
1 R2207 2
0R0402-PAD-7-NP-GP
RTC_AUX_S5
DC35
DD37
DA28
3D3V_VCCDSW
1
1D8V_GPPR_S5
CY31
CY33
CV39
(Output)
3D3V_S5_VCCPRIM
Must take care
this power layout
and add shield GND.
1D8V_S5_VCCPRIM
TP_VCCANA_EHV
AP12
1
TP2201
1D8V_S5
TGL-U-1-GP-U2
1D8V_S5_CLKLDO
(165mA)
1 R2204 2
0R0402-PAD-7-NP-GP
using 1.8V GPPR
2
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
1
B
C2203
DY
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SCD1U16V2KX-3DLGP
20191112 modify
Follow Nakia using 1.8V GPPR
1D05V_VNN_BYPASS
SC1U10V2KX-1DLGP
C2209
SC1U10V2KX-1DLGP
1
1D8V_GPPR_S5
DY
C2214
SCD1U16V2KX-L-GP
2
C2208
DY
2
2
2
SC1U10V2KX-1DLGP
1
C2247
DY
3D3V_VCCDSW
2
C2246
DY
1
1
1D05V_S5_OUT
1
C2248
SCD1U16V2KX-3DLGP
(200mA)
1D05V_S5_BYPASS
1D05V_S5_VCCPRIM_OUT
2
1
1
2
C2207
2
2
C2202
SC1U10V2KX-1DLGP
SCD1U16V2KX-3DLGP
(200mA)
C2206
3D3V_RTC_EXT
2
DY
1
C2201
RTC_AUX_S5
1
C2211
DY
2
2
1
C2210
DY
10/09,RN2201 Pin3 ->CORE_VID1,charon
20191112 modify
Follow Nakia
2
1
SRN10KJ-5-GP
3D3V_S5_VCCPRIM
1
1D8V_S5_VCCPRIM
C2216
SC22U6D3V3MX-1-DL-GP
CORE_VID0
CORE_VID1
SC22U6D3V3MX-1-DL-GP
1
C2215
(1.3A)
4
3
C2205
SC4D7U6D3V2MX-1-GP
20191126
For High Limit
C2213
SC2D2U6D3V2MX-DL-GP
1D8V_S5
RN2201
For CNVi
0D85V_S5_VCCLDOSTD_OUT
PH Same as SPI Programming Guide for details
1
2
20191126
For High Limit
Place cap within
3mm from SOC edge
3D3V_S5_VCCPRIM
Follow Nakia
B
D
1D24V_S5_VCCDPHY_OUT
1
D
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
2
CORE_VID1
1D05V_S5_VCCDSW _OUT
AB12
AC10
AE10
AK2
AR10
AT12
AU10
AW10
BV1
BV39
BW40
BY39
CC1
CD12
CF10
CG12
CH10
CJ1
CJ12
CK10
CL12
CM10
CP1
CP10
CR12
CT10
CU12
CY1
AK1
1
[40,50]
Trace width > 40mil
1D8V_S5
2
CORE_VID0
(1.3A)
1D8V_S5_VCCPRIM
1
[40,50]
14 OF 21
1D8V_CPU_AUX
2
VSSAUX_SENSE
1
VCCAUX_SENSE
[50]
1
2
[50]
2
SC1U10V2KX-1DLGP
Close to pin DD37
A
A
<Core Design>
(SR#1406479253)
20191112 modify
Follow Nakia
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A3
Date:
5
4
3
2
CPU (PCH-LP PWR&Caps)
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
22
of
A00
105
5
CPU1P
4
3
18 OF 21
D
C
B
A
A27
A32
A45
A49
AA41
AA48
AB5
AB7
AB8
AC44
AC49
AD4
AD48
AD8
AF4
AF8
AG41
AG42
AG44
AG45
AG47
AG48
AG53
AH4
AH8
AK12
AK4
AK48
AK5
AK7
AK8
AM1
AM2
AM4
AM8
AN41
AN42
AN44
AN45
AN47
AN48
AN53
AP4
AP8
AT4
AT48
AT51
AT8
AV12
AV39
AV4
AV5
AV7
AV8
AW1
AW2
AW48
AY4
AY41
AY42
AY44
AY45
AY47
AY8
AY9
B13
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
2
1
CPU1Q
16 OF 21
B19
B2
B23
B27
B32
B36
B39
B42
B48
B52
B8
BA48
BA53
BB4
BB8
BC1
BC2
BD12
BD4
BD48
BD8
BF39
BF4
BF41
BF42
BF44
BF45
BF47
BF5
BF7
BF8
BG48
BG53
BH1
BH2
BH4
BH8
BK12
BK4
BK48
BK8
BL49
BM1
BM4
BM41
BM42
BM44
BM45
BM47
BM8
BN48
BP41
BP49
BP5
BP50
BP7
BT44
BT48
BU49
BV3
BV48
BV5
BW10
BY41
BY42
K34
K48
K5
L22
L28
L34
L39
L41
L42
L44
L45
L47
L49
M1
M2
M50
N22
N28
N34
N39
N41
N48
P11
P14
P16
P18
P20
P22
P33
P35
P4
P49
P8
R39
R44
T19
T29
T33
T4
T48
T8
U19
U25
U39
U49
V19
V4
V8
W1
W16
W26
W30
W39
W41
W42
W44
W45
W47
W48
Y4
Y49
Y50
Y8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CPU1R
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BY44
BY45
BY47
BY49
BY9
C13
C19
C23
CA48
CB41
CC10
CC3
CC5
CD44
CD48
CD7
CE49
CG48
CG51
CG52
CG9
CH41
CH42
CH44
CH45
CH47
CJ3
CJ5
CJ9
CK39
CK48
CK53
CL9
CN12
CN48
CN51
CN52
CN9
CP3
CP41
CP42
CP44
CP45
CP5
CR48
CR53
CR9
CT5
CU4
CU9
CV10
CV48
CV5
CV51
CV52
CY17
CY22
CY35
CY41
CY42
DP53
DR11
DR16
DR22
DR28
DR34
DR40
DR46
DT4
DT50
DU11
DU16
DU22
DU28
DU34
DU40
DU46
DV1
DV40
DV52
DW51
E13
E19
E35
E48
G22
G28
G34
G39
G48
G51
G52
H12
H22
H28
H34
H8
J39
J49
K16
K18
K20
K22
K28
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D
C
B
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
TGL-U-1-GP-U2
Title
https://realschematic.com
CPU (VSS)
Size
A4
Document Number
Rev
MOCKINGBIRD_TGL
Date: Saturday, August 01, 2020
4
CY44
CY45
CY47
CY5
D27
D32
D36
D42
D49
D5
DA30
DA33
DA53
DC17
DD15
DD24
DD26
DD28
DD31
DD33
DD35
DD39
DD45
DD51
DD52
DE3
DE5
DF19
DF37
DG15
DG21
DG27
DG33
DG39
DG45
DG5
DG53
DG6
DJ1
DJ2
DJ4
DK51
DL3
DL5
DM10
DM15
DM21
DM27
DM33
DM39
DM4
DM45
DN1
DN2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TGL-U-1-GP-U2
<Core Design>
TGL-U-1-GP-U2
5
17 OF 21
3
2
Sheet
23
of
1
A00
105
A
3
D2401
1
2
1
1
DY
R2460
10KR2J-3-GP
R2458
10KR2J-3-GP
2
1
2
R2491
FPR_SCAN#
2
DY
1 10KR2J-3-GP TYPEC_DCIN1_EN#
LID_POWER_ON#
HW_ACAV_IN
FPR_SCAN#
PWM_FAN1
PECI_CPU
1
2
[26]
Need very close to EC,
PDG: <0.5 inches.
2
LCD_TST
DY
1
[55]
2
R2437
43R2J-GP
1
R2430
10KR2J-3-GP
C2405
SC100P50V2JN-3GP
D2403
FAN_TACH1
K
A
C
RB520S30-GP
[17]
83.R2003.A8M
2ND = 083.52030.008F
LCD_VCC_TEST_EN
ALL_SYS_PWRGD
1 R2464 2
0R0402-PAD-7-NP-GP
HW_ACAVIN_NB
1 R2475 2
0R0402-PAD-7-NP-GP
EC_PCH_SPI_EN
3D3V_S5
HW_ACAVIN_NB
3D3V_S5_KBC
2
EC G3 Flash Share
[3,22,44,46,72]
PROCHOT#_CPU
[4]
20200512
Change to 100R follow Intel PDG
JTAG_RST#
CABLE2_OCP#
SHD_IO3
SHD_IO2
SHD_IO1
SHD_IO0
SHD_CLK
SHD_CS0#
SHD_CS1#
NON_JTAG
1
2 100R2J-2-GP
2 100R2J-2-GP
2 100R2J-2-GP
2 100R2J-2-GP
2 100R2J-2-GP
1
0R0402-PAD-7-NP-GP
1
0R0402-PAD-7-NP-GP
G3
G3
G3
G3
G3
2
1
[55]
L_BKLT_EN
R2412 1
R2413 1
R2410 1
R2411 1
R2416 1
R2403 2
R2497 2
JTAG
KBC_PWRBTN#
B55
A51
A26
B29
A28
B24
A23
A2
RUNPWROK
HW_ACAVIN_NB_R
ESPI_RESET#
EC_PCH_SPI_EN
USB_PWR_SHR_EN_L#
USB_POWERSHARE_VBUS_EN
ESPI_CLK
ESPI_CS#
TYPEC_DCIN1_EN#
B52
B16
B63
A20
A16
B18
B17
A10
ESPI_IO0
ESPI_IO1
ESPI_IO2
ESPI_IO3
A17
A18
B20
A19
POWER_SW_IN#
LID_POWER_ON#
B67
A63
HW_ACAV_IN
ALWON
A61
B65
2
PCH_SUSCLK
nRESET_IN
JTAG_RST#
A62
B2
A40
For eSPI
1
1
1
1
1
2
2
1
2
1
1
1
2
2
GPIO050/ICT0_TACH0
GPIO051/ICT1_TACH1
GPIO052/ICT2_TACH2
GPIO053/PWM0
GPIO054/PWM1
GPIO055/PWM2/SHD_CS0#/BSS_STRAP
GPIO056/PWM3/SHD_CLK
GPIO057/VCC_PWRGD
GPIO060/KBRST/TST_CLK_OUT
GPIO061/ESPI_RESET#/PWM7_ALT/EC_SCI_ALT#
GPIO062(RESETO#)/I2C11_SCL
GPIO063/ESPI_ALERT#/PWM6_ALT/ICT8
GPIO064/PCI_RESET#
GPIO065/ESPI_CLK/I2C13_SCL/ICT5_ALT
GPIO066/ESPI_CS#/I2C13_SDA
GPIO067/VREF2_ADC
GPIO070/ESPI_IO0/I2C14_SDA
GPIO071/ESPI_IO1/I2C14_SCL
GPIO072/ESPI_IO2/I2C01_SDA_ALT
GPIO073/ESPI_IO3/I2C01_SCL_ALT
JTAG_TMS
KSO15
KSO14
BAT2_LED#
CLK_TP_SIO_I2C_DAT
DAT_TP_SIO_I2C_CLK
BREATH_LED#
1
BAT1_LED#
GPIO200/ADC00/TRACEDAT0
GPIO201/ADC01/TRACEDAT1
GPIO202/ADC02/TRACEDAT2
GPIO203/ADC03/TRACEDAT3
GPIO204/ADC04
GPIO205/ADC05
GPIO206/ADC06
GPIO207/ADC07/CMP_STRAP
GPIO221/32KHZ_OUT/SYS_SHDN#
GPIO222/PROCHOT_IN#
GPIO223/SHD_IO0
GPIO224/GPTP_IN0/SHD_IO1
GPIO226
GPIO227/SHD_IO2/PWRGD_STRAP
GPIO241/PWM0_ALT/CMP_VOUT0
GPIO242/CMP_VIN0
GPIO244/CMP_VIN1
GPIO246/CMP_VREF0
GPIO253/BGPO0
GPIO254/PWM1_ALT/CMP_VREF1
GPIO255
VCI_IN0#/GPIO163
VCI_IN1#/GPIO162
1
1
JTAG1
11
1
ECDEBUG
TP2403
HOST_DEBUG_TX
CCG6_I2C_INT#
PBAT_PRES#
B42
B56
A45
I_BATT
I_ADP
MODEL_ID
TOUCHPAD_INTR#
BOARD_ID
TBT_RESET_N_EC
USB_PWR_EN#
PCH_DPWROK
A1
B30
A22
B22
A3
B23
NB_MUTE#
PROCHOT
SHD_IO0
SHD_IO1
LCD_VCC_TEST_EN
SHD_IO2
A53
B6
A7
A5
GPU_PWR_LEVEL
PANEL_MONITOR
AC_DIS
M_BIST
A60
B7
A4
CABLE2_OCP#
SIO_PWRBTN#
ME_FWP
1
2
1
R2463
DY
JTAG
JTAG_PU
JTAG_TDI
JTAG_TMS
JTAG_CLK
JTAG_TDO
MSCLK
MSDATA
HOST_DEBUG_TX
DEBUG_TX
2
3
4
5
6
7
8
9
10
12
R24141
2
0R2J-2-GP
JTAG
ACES-CON10-28-GP-U
20.K0460.010
HOST_DEBUG_TX
A11
B12
A12
B13
A13
B14
A14
B15
R2456 R2449
1
RN2455
JTAG
2
JTAG
100KR2J-1-GP
SIO_PWRBTN#
2
R2485
R2455
DY 10KR2J-3-GP
SSD_SCP#
8
7
6
5
R2457
PCIE_WAKE#
A54
GPIO165/32KHZ_IN/CTOUT0
GPIO170/UART1_TX/JTAG_STRAP
GPIO171/UART1_RX
GPIO175/CMP_VOUT1/PWM8_ALT
1
A56
A30
A9
B54
A48
B51
B49
A50
3D3V_S5
3D3V_S5
KSO16
1
1
R2484
2
6K2R2F-GP
TP2402
R2401 1
C
DY
For USB TypeC
TBT_RESET_N_EC#
2 0R2J-2-GP
3D3V_S5_KBC
RN2413
SRN2K2J-1-GP
3D3V_S5
UPD1_SMBDAT
CABLE2_OCP#
2 R2419
UPD1_SMBCLK
1
100KR2J-1-GP
B66
NC#B66
R2421
330R2J-3-GP
VCI_OVRD_IN/GPIO172
VCI_OUT/GPIO250
C1
I_ADP
SUSCLK_IN
RESET_IN#
JTAG_RST#
2
AD_IA
1
C2435
SC2200P50V2KX-2DLGP
071.01515.0A03
Already pull low
on CPU side
non-G3
PCH_RSMRST#
R2405 2
PRIM_PWRGD
R2402 2
1 0R2J-2-GP
SHD_CS0#
1 0R2J-2-GP
SHD_IO2
DY
2
non-G3
K
DY
3D3V_S5
1 0R2J-2-GP
RN2405
D2406
R2461
10KR2J-3-GP
2
R2453
2
1
PRIM_PWRGD
2
0R0402-PAD-7-NP-GP
1 R2407
3D3V_S5_KBC
G3
A
RB520S30-GP
Q2416
PROCHOT
BAT2_LED#
1
PCH_RSMRST#
R2408
1
DY
2
PWR_VNN1D05V_PG
R2417
3D3V_S5
DY 100KR2J-1-GP
0R2J-2-GP
83.R2003.A8M
2nd = 083.52030.008F
CHG_AMBER_LED#
2
1
D2406_A
TP2401
1
SUSCLK
GPIO040/GPTP_OUT2/KSO00/UART1_CTS#
GPIO042/PECI_DAT/SB-TSI_DAT
GPIO043/SB-TSI_CLK
GPIO044/VREF_VTT
GPIO045/KSO01/PWM2_ALT/ICT14/CR_STRAP
GPIO046/KSO02/ICT11
GPIO047/KSO03/PWM3_ALT/ICT13
GPIO150/I2C15_SCL/JTAG_TMS/UART2_DTR#
GPIO151/ICT4/KSO15
GPIO152/KSO14
GPIO153/LED2
GPIO154/I2C02_SDA/PS2_CLK1B
GPIO155/I2C02_SCL/PS2_DAT1B
GPIO156/LED0
GPIO157/LED1
CAP_LED#
PTP_DIS#
LED_MASK#
UPD1_SMBDAT
UPD1_SMBCLK
JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG DEBUG CONN
20191217
Follow HC ICL
20191125
Follow Upsell
20191126
Due to High Limit
Change back to D2406 D2407
GPIO55 (BSS_STRAP)
TPAD14-OP-GP
PWR_VNN1D05V_PG
GPIO031/KSI6/GPTP_OUT1
GPIO030/KSI5/I2C10_SDA
GPIO032/KSI7/GPTP_OUT0/UART0_RI#
GPIO033/TACH3
GPIO035/PWM8/CTOUT1/ICT15
B53
B60
A57
B61
A58
B58
A55
B59
R2434
100KR2J-1-GP
USB_PWR_EN#
3D3V_S0
MEC1515H-D0-I-NB-GP
Power on sequence for G3 sharing
[72] UPD1_SMBCLK
[72] UPD1_SMBDAT
[18,61]
TACH_FAN1
LID_CL_SIO_TAB#
LCD_TST
KB_LED_PWM
NB_MODE#
SHD_CS0#
SHD_CLK
GPU_THM_SMBCLK
GPU_THM_SMBDAT
[18,25,91] SPI_CLK_ROM
[18,25,91] SPI_SO_ROM
[15,18,25,91]
SPI_SI_ROM
[15,18,25] SPI_WP_ROM
[15,18,25] SPI_HOLD_ROM
[18,25] SPI_CS_ROM_N0
[18,25] SPI_CS_ROM_N1
[40,54]
1 R2406
0R0402-PAD-7-NP-GP
[18,26,79]
[18,26,79]
A31
A37
B40
A38
B57
B44
A42
GPIO020/KSI1
GPIO021/KSI2
GPIO026/KSI3/UART0_DTR#/I2C12_SDA
GPIO027/KSI4/UART0_DSR#/I2C12_SCL
GND
SUSCLK
TOUCH_REPORT_SW
[64]
KSO00
PECI_EC
PANEL_BKEN_EC
PECI_VREF
KSO01
KSO02
KSO03
C2419
SC1U10V2KX-1DLGP
SPI_HOLD_ROM
SPI_WP_ROM
SPI_SO_ROM
SPI_SI_ROM
SPI_CLK_ROM
SPI_CS_ROM_N0
SPI_CS_ROM_N1
KSO01
100R2F-L1-GP-U
PM_LAN_ENABLE
DGPU_PWROK
BEEP
A32
A33
B33
B1
A6
2
R2450
100KR2J-1-GP
JTAG
R2409
DGPUHOT#
[66]
[55]
PCIE_LAN_WAKE#
PANEL_BKEN
1
1
R2498
AD_IA
[66]
[55]
[44,79]
[19,85]
TP2404
TP2405
2
GPIO045 (CR_STRAP)
ALWON
100KR2J-1-GP
[44]
1
[40]
1
[43,44]
A29
B31
B34
B35
KSI6
KSI5
KSI7
IMVP_VR_ON
PBAT_CHG_SMBDAT
PBAT_CHG_SMBCLK
LED_MASK#
3
4
SRN100KJ-6-GP
1
6
2
5
3
4
BATT_WHITE_LED#
Q2408
CAP_LED#
3D3V_S5
BAT1_LED#
3D3V_S0
PROCHOT#_CPU
2N7002KDW-1-GP
nRESET_IN
DY
CAP_LED#_R
PROCHOT
1 0R2J-2-GP
EC_PCH_SPI_EN
RB520S30-GP
3D3V_S0
R2474
DY 100KR2J-1-GP
R2489
100KR2J-1-GP
2
83.R2003.A8M
2nd = 083.52030.008F
2
A
4
1
G3
5
3
75.27002.F7C
1
2
R2452 2
D2407
K
6
2
2N7002KDW-1-GP
75.27002.F7C
R2438
100KR2J-1-GP G3
1
1
[66]
3D3V_S0
KSI1
KSI2
KSI3
KSI4
A25
B27
A49
3D3V_S5
R2436
100KR2J-1-GP
Dual Boot
2
[44,64]
[55]
1
3D3V_S5
R2496
100KR2J-1-GP
GPU_PWR_LEVEL
3D3V_S5
20191210
R2418
Follow CY20
2
1 DUAL_BOOT_EVENT#
0R2J-2-GP
KSO07
KSO08
KSO09
KSO10
KSO11
KSO12
KSO13
RTCRST_ON
100KR2J-1-GP
OPS
GPIO140/I2C06_SCL/ICT5/KSO17
GPIO141/I2C05_SDA/UART2_RTS#
GPIO142/I2C05_SCL/UART2_CTS#
GPIO143/I2C04_SDA/UART0_CTS#
GPIO144/I2C04_SCL/UART0_RTS#
GPIO145/I2C09_SDA/JTAG_TDI/UART2_RX
GPIO146/I2C09_SCL/JTAG_TDO/UART2_TX
GPIO147/I2C15_SDA/JTAG_CLK/UART2_DSR#
PCH_RSMRST#
1
0R0402-PAD-7-NP-GP
A34
B45
A43
B46
B10
B47
A44
A46
10KR2J-3-GP
LAN_WAKE#
GPIO010/I2C03_SCL/PS2_DAT0B
GPIO011/SMI_ALT#/PWM4/ICT7
GPIO012/I2C07_SDA
GPIO013/I2C07_SCL
GPIO014/PWM6/GPTP_IN2
GPIO016/GPTP_IN1/SHD_IO3/ICT3/DSW_PWROK
GPIO017/KSI0/UART0_DCD#
GPIO130/I2C01_SDA
GPIO131/I2C01_SCL
GPIO132/I2C06_SDA/KSO16
R2448
100KR2J-1-GP
TBT_RESET_N_EC#
10KR2J-3-GP
[17]
NB_MUTE#
B50
B21
B25
A24
A27
A21
B32
DY
3D3V_S5
2
SRN10KJ-6-GP
PTP_DIS#
PECI_CPU
[27]
LID_CL_SIO_TAB#
FPR_SCAN#
MASK_SATA_LED#
VCCDSW_EN
DGPU_PWROK_EC
PWM_FAN1
SHD_IO3
KSI0
GPIO000/SYSPWR_PRES/VCI_IN3#/I2C11_SDA
GPIO002/PWM5/SHD_CS1#
GPIO003/I2C00_SDA/UART2_RI#
GPIO004/I2C00_SCL/UART2_DCD#
GPIO007/I2C03_SDA/PS2_CLK0B
R2494
100KR2J-1-GP
1
2
3
4
2 R2483 1
0R0402-PAD-7-NP-GP
B68
B28
A59
B62
A47
2 R2404
1
49D9R2F-GP
[65]
[3]
[20,66]
2
2
Thermal,DGPU
PM_LAN_ENABLE
SYSPWR_PRES
SHD_CS1#
GPU_THM_SMBDAT
GPU_THM_SMBCLK
AUX_ON
GPIO120/KSO07
GPIO121/PVT_IO0/KSO08
GPIO122/PVT_IO1/KSO09
GPIO123/PVT_IO2/KSO10
GPIO124/PVT_CS#/KSO11/ICT12
GPIO125/PVT_CLK/KSO12
GPIO126/PVT_IO3/KSO13
GPIO127/A20M/UART1_RTS#
LID_CL_SIO#
0R0402-PAD-7-NP-GP
1
1 100KR2J-1-GP
VTR_PLL
VBAT
VTR_REG
VREF_ADC
VR_CAP
SYS_PWROK
2 R2473 1
KSO04
KSO05
KSO06
PCH_RSMRST#_R
LID_CL_SIO#
PS_ID
TABLE_MODE#
2
DY
R2454 2
C2418 2
GPIO112/KSO05
GPIO113/KSO06/ICT9
GPIO114/PS2_CLK0A/EC_SCI#
GPIO115/PS2_DAT0A
GPIO116
GPIO117
VTR2
VTR3
MSCLK
MSDATA
RESET_OUT#
B37
A35
B38
A36
B41
A39
1
3D3V_RTC
2 100KR2J-1-GP
VTR1_ADC
20191125
20191210
Follow CY20 Follow CY20
Follow NAKIA
SSD_SCP#
B64
B43
A41
B3
B36
2
1
R2420 1
3D3V_ECVBAT
3D3V_S5_KBC
3D3V_S5_KBC
JIO3_PCIE_WAKE#
B4
A64
B9
B11
B8
VTR_REG
VREF_ADC
1 SC1U10V2KX-1DLGP VR_CAP
M_BIST
PANEL_MONITOR
B26
B19
VTR_PLL
GPIO101/BGPO1
GPIO104/UART0_TX/TFDP_CLK/VTR2_STRAP
GPIO105/UART0_RX/TFDP_DATA/TRACECLK
GPIO106/PWROK
GPIO107/SMI#/KSO04/I2C10_SCL
1
SRN100KJ-6-GP
SRN100KJ-6-GP
Layout Note:
Place close to Mec1515
PBAT_CHG_SMBCLK
[61]
VTR2
2 0R0402-PAD-7-NP-GP
1 SCD1U16V2KX-3DLGP
3D3V_ECVBAT
VTR1
VTR1
VTR1
VTR1
VTR1
2
KSO07
KSO06
PS_ID
[55]
DGPU_PWROK
R2471 1
0R0402-PAD-7-NP-GP
2
R2426
10KR2J-3-GP
2
1
2
C2423 2
4
3
A15
1
R2462 1
RN2414
1
2
BEEP
HOST_DEBUG_TX
D
GPU_PWR_LEVEL
2
3
4
TABLE_MODE#
A8
B5
B48
B39
A52
VTR1_ADC
2
KSO05
KSO04
1D8V_S5_KBC
1
KSO11
KSO14
4
3
KSI4
KSI5
R2472
0R0402-PAD-7-NP-GP
1
4
3
4
3
U2401
1D8V_S5
KSI6
10KR2J-3-GP
1
2
For eSPI
3D3V_RTC
1
2
SSD_SCP#
[20]
DGPU_PWROK_EC
2
If don't need RTC alarm wake up,
can change to 3D3V_AUX_S5
KSI1
RN2403 10KR2J-3-GP
4
KSO15
3
KSO00
2
SRN10KJ-5-GP
1
2
1 R2477
DGPUHOT#
0R0402-PAD-7-NP-GP
2
1
2
RN2407
[64]
[68]
2
2
1
2
1
2
1
2
1
2
1
KSO09
KSO12
KSO13
KSO16
SRN100KJ-6-GP
R2433
1
2
[63]
C2416
SCD1U16V2KX-3DLGP
R2431 1
2
8
7
6
5
C2428
SCD1U16V2KX-3DLGP
[43]
RN2410
SRN100KJ-5-GP
SRN100KJ-6-GP
KB_LED_PWM
64.64925.6DL
3D3V_S5
RN2404
NB_MODE#
[27]
[43,44]
1
2
3
4
RN2411
IMVP_VR_ON
C2413
SCD1U16V2KX-3DLGP
PRIM_PWRGD
C2421
SCD1U16V2KX-3DLGP
PCH_DPWROK
TYPEC_DCIN1_EN#
PBAT_CHG_SMBDAT
[20]
KSI2
KSI0
KSI7
KSI3
64.49925.6DL
3D3V_S5_KBC
FAN_TACH1
[17,26]
8
7
6
5
C2414
SCD1U16V2KX-3DLGP
[17]
[53]
[65]
1
2
3
4
SRN10KJ-6-GP
[74]
[43,44]
AC_DIS
USB_PWR_EN#
BATT_WHITE_LED#
[26]
KSO08
KSO02
KSO10
KSO03
C2410
SCD1U16V2KX-3DLGP
[35,66]
CAP_LED#_R
CHG_AMBER_LED#
8
7
6
5
SRN100KJ-5-GP
RN2409
[43,44]
LID_CL_SIO#
R2444
100KR2F-L1-GP
64.10025.6DL
64.17825.6DL
1 0R0402-PAD-7-NP-GP
C2411
SCD1U16V2KX-3DLGP
[64]
3D3V_S5
C2412
SCD1U16V2KX-3DLGP
1
2
3
4
ALL_SYS_PWRGD
[65]
[20,64]
64.20035.6DL
R2446 2
TOUCHPAD_INTR#
[20,66]
[17,40,44,46]
BOARD_ID
3D3V_S5_KBC
RN2412
RTCRST_ON
BOARD ID 49K9R2F-L-GP
ID to A00
Mockingbird
PBAT_PRES#
PCH_RSMRST#
R2443
ID to X02
64.64925.6DL
64.82525.6DL
64.10735.6DL
R2441
100KR2F-L1-GP
3D3V_S5_KBC
CCG6_I2C_INT#
MASK_SATA_LED#
[98] ME_FWP
C2420
SCD1U16V2KX-3DLGP
[3,65]
83.R2003.A8M
2ND = 083.52030.008F
LID_POWER_ON#
[72]
SYS_PWROK
[25]
ESPI_IO0
ESPI_IO1
ESPI_IO2
ESPI_IO3
eDP backlight
Control from PCH
L_BKLT_EN
A
RB520S30-GP
1
[17]
[43,44]
[17,40]
[18,68]
[18,68]
[18,68]
[18,68]
[66]
64.17825.6DL
ID to X01
MODEL_ID
D2405
LED_MASK#
[20,64]
64.27025.6DL
ID to X00
2
ESPI_RESET#
64.10025.6DL
MODEL ID
2
ESPI_CLK
[18,68]
2
1
2
ESPI_CS#
[18,68]
20191203
Change board
20200131
Change board
20200330
Change board
20200730
Change board
C2408
SCD1U16V2KX-3DLGP
[18,68]
[64]
R2442
82K5R2F-GP
83.R2003.A8M
2ND = 083.52030.008F
K
1
3D3V_S5_KBC
Hellcat
MODEL ID
eDP backlight
Control from EC
C2407
SCD1U16V2KX-3DLGP
SIO_PWRBTN#
C2424
SCD1U16V2KX-3DLGP
[17]
DUAL_BOOT_EVENT#
VTR1_ADC
VTR2
C2422
SCD1U16V2KX-3DLGP
CLK_TP_SIO_I2C_DAT
[16]
VTR_PLL
C2425
SCD1U16V2KX-3DLGP
[65]
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
D
VCCDSW_EN
DAT_TP_SIO_I2C_CLK
VTR_REG
C2427
SCD1U16V2KX-3DLGP
[25]
[65]
VREF_ADC
C2432
SCD1U16V2KX-3DLGP
KSI[0..7]
PANEL_BKEN_EC
A
RB520S30-GP
PECI_VREF
SCD1U16V2KX-3DLGP
C2406
[65]
KSO00
KSO01
KSO02
KSO03
KSO04
KSO05
KSO06
KSO07
KSO08
KSO09
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
K
2
3D3V_S5_KBC
1
3D3V_S5_KBC
2
3D3V_S5_KBC
2
3D3V_S5_KBC
PANEL_BKEN
[65]
[65]
[65]
[65]
[65]
[65]
[65]
[65]
[65]
[65]
[65]
[65]
[65]
[65]
[65]
[65]
[65]
2
3D3V_S5
3D3V_S5_KBC
1D05V_VCCST
1
4
20200331
Follow Vendor requirement change to 1.05V_VCCST
2
5
Main Func = KBC
CAP_LED#
B
B
20191125
Follow CY20
D2402
3D3V_S5_KBC
LID_CL_SIO#
RN2402
PBAT_CHG_SMBCLK
PBAT_CHG_SMBDAT
3
4
2
1
K
TOUCH_REPORT_SW
A
LRB751V-40T1G-GP
83.00751.08F
SRN4K7J-8-GP
2nd = 83.R2004.G8F
3D3V_S5_KBC
PBAT_PRES#
R2415 1
2 100KR2J-1-GP
Power Switch Logic(PSL)
20191126
Follow ICL
D2410
3D3V_ECVBAT
A
DY
K JIO3_PCIE_WAKE#
2
3D3V_S5
RB520S30-GP
1
R2451
100KR2J-1-GP
POWER_SW_IN#
D2409
C2426
SC2D2U10V3KX-1DLGP-U
PCIE_WAKE#
A
2
1KR2J-1-GP
1
2
2
1
1
83.R2003.A8M
2ND = 083.52030.008F
R2495
1KR2J-1-GP
R2432
KBC_PWRBTN#
K
PCIE_LAN_WAKE#
RB520S30-GP
83.R2003.A8M
2ND = 083.52030.008F
D2408
LAN_WAKE#
A
K
RB520S30-GP
83.R2003.A8M
2ND = 083.52030.008F
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
https://realschematic.com
Title
Size
Custom
Date:
5
KBC Nuvoton NPCE285PA0DX
4
3
2
1
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
A00
24
of
105
5
4
Main Func = SPI Flash
3
2
1
20200421(DVT2)
Remove SKT251
1
3D3V_SPI
R2501
4K7R2J-2-GP
SPI_CS_ROM_N1
[18,24]
SPI_CS_ROM_N0
2
[18,24]
SPI_WP_ROM
1
2
3
4
20200512
Change to 15R follow Intel PDG
C2502
SCD1U16V2KX-3DLGP
3D3V_SPI
8M
CS#
DO/IO1
IO2
GND
8
7
6
5
VCC
IO3
CLK
DI/IO0
SPI_HOLD_ROM_R
SPI_CLK_ROM_R
SPI_SI_ROM_R
072.25Q64.0H01
2nd = 072.25647.000D
3rd = 072.02564.0H01
R2508
4K7R2J-2-GP
R2570 1
R2568 1
R2569 1
2 15R2F-2-GP
2 15R2F-2-GP
2 15R2F-2-GP
SPI_HOLD_ROM
SPI_CLK_ROM
SPI_SI_ROM
20200304
change R2572 R2573 to 0201
20200512
Change to 15R follow Intel PDG
W25Q64JVSSIQ-GP
3D3V_SPI
1
2
[15,18,24]
C10U6D3V3MX-DL-GP
SPI_HOLD_ROM
SPI_CS_ROM_N0
SPI_SO_ROM_R
SPI_WP_ROM_R
2 15R2F-2-GP
1 15R2F-2-GP
D
3D3V_SPI
U2503
2
C2501S
SPI_SI_ROM
DY
[15,18,24]
1
SPI_CLK_ROM
[15,18,24,91]
1
[18,24,91]
D
3D3V_S5
SPI_SO_ROM
R2507 1
R2571 2
2
[18,24,91]
SPI_SO_ROM
SPI_WP_ROM
20191224
Follow Internal review
20200225
change to 8M
U2501
SPI_SO_ROM
SPI_WP_ROM
3D3V_S5
R2509 1
R2575 2
SPI_CS_ROM_N1
SPI_SO_ROM_R1
SPI_WP_ROM_R1
2 15R2F-2-GP
1 15R2F-2-GP
3D3V_SPI
1 R2506 2
0R0402-PAD-7-NP-GP
1
2
3
4
CS#
DO/IO1
WP#/IO2
GND
16M
8
7
6
5
VCC
HOLD#/RESET#/IO3
CLK
DI/IO0
SPI_HOLD_ROM_R1
SPI_CLK_ROM_R1
SPI_SI_ROM_R1
R2574 1
R2572 1
R2573 1
SPI_HOLD_ROM
SPI_CLK_ROM
SPI_SI_ROM
2 15R2F-2-GP
2 15R1F-GP
2 15R1F-GP
W25Q128JVSIQ-GP
072.25128.0B51
2nd = 072.25128.0D61
3rd = 072.25128.0F0D
10/11 add 3D3V_SPI, follow 15 UPSELL
Main Func = RTC
3D3V_RTC
RTC_AUX_S5
Q2507
PJA3413-1-GP
3D3V_AUX_S5
RTC_RST
D
2
S
[24]
RTCRST_ON
084.03413.0031
2
RTC_DET#
VCCDSW_EN
G
[19]
[24]
1
C
R2502
0R2J-2-GP
2nd = 084.02301.0031
3rd = 84.00513.03B
1
1
SIO_SLP_SUS#
+RTC_VCC
3V_5V_PWRGD
C
RTC_3P3_EN_D
3D3V_RTC
[17,40]
[17,45]
R2505
4K7R2J-2-GP
RTC_RST
3D3V_RTC_SYS
R2503
DY47KR2F-GP
2
1
D2501
3
1
2
75.00054.A7D
2nd = 75.00054.T7D
2
BAT54C-12-GP
C2503
SCD47U25V3KX-1-DL-GP
R2567
2
+RTC_VCC
3
RTC_3P3_EN_G
R2518
1MR2J-1-GP
100KR2J-1-GP
4
RTC_3P3_EN_G
2
RTC_RST
1
5
1
C2517
SCD022U16V2KX-3DLGP
2
2
RTC_3P3_EN_D
RTC_DET#
2
Note:ZZ.27002.F7C01
R2504
10MR2J-L-GP
RTCRST_ON
6
1
1
Q2501
1
2N7002KDW-1-GP
RTC_RST
RTC_RST
75.27002.F7C
B
B
20191120 follow Nakia
3D3V_S5
1
3V_5V_PWRGD
2
R2514
R2520
D2504
1
2
1
3D3V_S5
BAT54A-11-GP
75.BAT54.07D
2nd = 075.00054.0A7D
3rd = 75.00054.I7D
4th = 075.00054.0Z7D
3D3V_S5
3V_5V_DSW_OK
2
20191224
Follow Internal review
10KR2J-3-GP
3
100KR2J-1-GP
VCCDSW_EN
20191120
Follow ICL
High limit don't change U2502
U2502
4
5
3D3V_VCCDSW
EN/EN#
VIN
FLG#
GND
VOUT
3D3V_S5_VCCPRIM
3
2
1
1
R2521 2
0R0603-PAD-7-NP-GP
RT9742CGJ5-GP
074.09742.0A9F
2nd = 074.51712.009F
3rd = 074.03553.007F
4th = 074.03553.0A7F
20191111 follow Nakia
A
A
<Core Design>
Wistron Corporation
20191112 modify
Follow Nakia
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Flash
Size
A2
Date:
5
4
3
2
Document Number
Rev
A00
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
25
of
105
5
4
3
2
1
PWM FAN1
Main Func = Thermal Sensor
Layout Note:
Signal Routing Guideline:
Trace width = 15mil
5V_FAN_VCC
1
DY
2
1
2
1
2
2
1
SC2200P50V2KX-2DLGP
C2603
DY
D2601
RB551V30-GP
RN2602
SRN2K2J-1-GP
SCD1U16V2KX-3DLGP
C2605
3D3V_S0
SC4D7U6D3V3KX-DLGP
C2604
3D3V_S0
D
K
5V_FAN_VCC
1 R2612 2
0R0402-PAD-7-NP-GP
A
5V_S0
83.R5003.H8H
D
Q2601
5
GPU_THM_SMBDAT
2
4
GPU_THM_SMBCLK
CPU_SMB_SDA_THM
1
7718
5V_FAN_VCC
3
FAN1
6
PWM_FAN1
FAN_TACH1
2N7002KDW-1-GP
75.27002.F7C
2
[40]
DY
PURE_HW_SHUTDOWN#
1
1
2nd = 075.27002.0E7C
GPU_THM_SMBCLK
DY
EC2601
SC10P50V2JN-4DLGP
IMVP_VR_ON
EC2602
SC10P50V2JN-4DLGP
[17,24]
4
3
2
CPU_SMB_SCL_THM
2
[18,24,79]
6
Note:ZZ.27002.F7C01
GPU_THM_SMBDAT
[18,24,79]
3
4
7718
1
5
AFTP2604
1
ACES-CON4-29-GP
20.F1639.004
2nd = 020.F0097.0004
2ND for MKB = 020.F1736.0004
2
1
5V_FAN_VCC
1
AFTP2601
AFTP2602
AFTP2603
C
7718
NCT7718_DXP
7718
1
PWM_FAN1
SCD1U16V2KX-3DLGP
C2602
SC10U6D3V3MX-DL-GP
C2601
DY
IMVP_VR_ON
CPU_SMB_SCL_THM
CPU_SMB_SDA_THM
ALERT#
8
7
6
5
74.07718.0B9
2nd = 074.00788.00B9
IMVP_VR_ON
2
Layout Note:
DY
NCT7718W-GP
R2601
0R0402-PAD-7-NP-GP
C2607 close THM2601
1
VDD
SCL
D+ 7718 SDA
DALERT#
T_CRIT#
GND
2
2
T_CRIT#
1
E
2
7718
84.T3904.H11
NCT7718_DXN
2nd = 084.03904.0I11
3rd = 084.03904.0H11
4th = 84.03904.T11 2.System Sensor, Put on palm rest
1
2
3
4
Q2602
G
D
THERM_SYS_SHDN#
PURE_HW_SHUTDOWN#
S
2N7002K-2-GP
Layout Note:
B
SCD1U16V2KX-3DLGP
C2608
1
C2607
SC2200P50V2KX-2DLGP
DY
B
C2606
SC470P50V3JN-2GP
C
THM261
Q2603
LMBT3904LT1G-GP
1
FAN_TACH1
1
[24]
3D3V_S0
2
PWM_FAN1
1
C
[24]
FAN_TACH1
84.2N702.J31
2ND = 084.27002.0N31
3rd = 084.27002.0L31
4th = 084.07002.0C31
Both DXN and DXP routing 10 mil trace width and 10 mil spacing.
B
3D3V_S0
R2603
1
R2604
1
7718
2 7K5R2F-1-GP
ALERT#
3D3V_S5
2 7K5R2F-1-GP T_CRIT#
7718
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A2
Date:
5
4
3
2
THERMAL NCT7718W/Fan
Document Number
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
26
Rev
A00
of
105
5
4
3
2
1
Main Func = Audio
[19]
HDA_SDIN0_CPU
HDA_SDOUT_CODEC
AUD_HP1_JACK_L
20191128
Follow Nakia
2
1
1
C2702
2
AUD_VREF
LDO1_CAP
MIC2_VREFO
22
21
LDO1-CAP
LINE1_VREFO
23
MIC2-VREFO
24
25
HP-OUT-L
LINE1-VREFO-L
HP-OUT-R
2
CBN
EC2701
EC2702
EC2703
ER2701
EC2705
1 DY
1 DY
1
DY
1
1
DY
2 SCD1U16V2KX-3DLGP
2 SCD1U16V2KX-3DLGP
2 SCD1U16V2KX-3DLGP
2 0R0402-PAD-7-NP-GP
2 SCD1U16V2KX-3DLGP
AUD_AGND
19
AUD_AGND
18
LINE1_L
17
LINE1_R
16
V3D3_STB
15
MIC_CAP
14
AUD_SLEEVE
R2704 1
R2705 1
R2706 1
Layout Note:
AUD_AGND
C2715 1
AUD_RING
AUD_HPJD_N
11
AUD_PC_BEEP
Tied at point only under
Codec or near the Codec
AUD_AGND
DC_DET
13
12
2
SC10U6D3V3MX-DL-GP
20R0402-PAD-7-NP-GP
20R0402-PAD-7-NP-GP
20R0402-PAD-7-NP-GP
10
C
Analog
Digital
+3V_1D8V_DVDD
moat
2
1
place close to pin8
DVSS
9
SYNC
PCBEEP
HDA_SYNC_CODEC
SDATA-IN
LDO3-CAP
DVDD-IO
8
6
7
HDA_CODEC_SDIN0
LDO3_CAP
1
BIT-CLK
5
HDA_BITCLK_CODEC_R
SDATA-OUT
GPIO1/DMIC-CLK
4
moat
AUD_AGND
For RTC Gen9 reset circuit change power rail.
20170921
Open drain output.
pull up to DVDD or
max. 5V
R2708 1
3D3V_RTC
C2722
SC10U6D3V3MX-DL-GP
R2716 1
3D3V_S0
DY
V3D3_STB
2
0R0402-PAD-7-NP-GP
2 100KR2J-1-GP
DVSS
2
20191204
For Vendor request
20200302
Stuff R2717
VREF
1
1
PDB_R
1 R2712 2
0R0402-PAD-7-NP-GP
C2721
HP/LINE1-JD_JD1
HDA_SDOUT_CODEC_R
GND
SCD1U16V2KX-3DLGP
NB_Mute#
2
27
CPVEE
SC2D2U10V3KX-1DLGP-U
26
CBN
CBP
PDB
RING2/MIC2-L
3D3V_S0
R2717
100KR2J-1-GP
CPVEE
28
29
30
PVDD2
3
SPK-R+
GPIO0/DMIC-DATA12
SLEEV/MIC2-R
ALC3204-CG-GP-U
3D3V_S0
MIC2-CAP
SPK-R-
DVDD
41
VD33STB
071.03204.0003
2
Speaker trace
width >40mil @
2W4ohm speaker
power
CPVDD
SC2D2U10V3KX-1DLGP-U
CBP
40
LINE1-R
QFN40 (5X5)
SPK-L-
1
1
2
1
1
39
PDB_R
SPK-L+
DMIC_SCL_CODEC
1
38
+5V_PVDD
AVSS1
LINE1-L
ALC3204
D
20
SC4D7U6D3V3KX-DLGP
2
1
AUD_SPK_R+
AVDD1
AVDD2
PVDD1
C2706
+5V_AVDD
C2723
2
37
SC10U6D3V3MX-DL-GP
C2720
20191112 modify
Follow Nakia
C2740
36
AUD_SPK_R-
place close to pin1
AUD_RING
DMIC_SCL_CODEC
DMIC_SDA_CODEC
C2741
SC2D2U10V3KX-1DLGP-U
[29,66]
[55]
[55]
AUD_SLEEVE
SCD1U16V2KX-3DLGP
[29,66]
AUD_SPK_L-
AUD_AGND
LDO2-CAP
DMIC_SDA_CODEC
+3V_1D8V_DVDD
1 R2715 2
0R0603-PAD-7-NP-GP
35
AVSS2
1
1D8V_S0
34
AUD_SPK_L+
1
LINE1_L
LINE1_R
33
+5V_PVDD
2
[29]
[29]
Layout Note:
C2718
SCD1U16V2KX-3DLGP
C
DVDD must >= DVDD_IO
C2717
32
2
AUD_HP1_JACK_L
AUD_HP1_JACK_R
C2714
1
[29]
[29]
MIC2_VREFO
C2713
2
[29]
LDO2_CAP
1
SC10U6D3V3MX-DL-GP
+3V_1D8V_AVDD
SCD1U16V2KX-3DLGP
LINE1_VREFO
SC10U6D3V3MX-DL-GP SC10U6D3V3MX-DL-GP
[29]
C2711 2
AUD_AGND
+5V_PVDD
2
1
2
moat
31
AUD_AGND
AUD_AGND
2
>2A
BEEP
AUD_SENSE
1
[24]
[66]
C2710
SC10U6D3V3MX-DL-GP
2
NB_Mute#
SPKR
2
[24]
U2701
1
1 R2719
2
0R0402-PAD-7-NP-GP
1D8V_S0
[20]
1.8V power rail should be supplied by
linear regulator, not awitching
regulator.if switch regulator is
unavilable, please make sure that switch
frequency operates at out-band(over 20KHz)
2
Digital
1
1 R2709 2
0R0402-PAD-7-NP-GP
AUD_SPK_L-
C2705
SC10U6D3V3MX-DL-GP
C2707
Analog
C2703
SC2D2U10V3KX-1DLGP-U
SCD1U16V2KX-3DLGP
1D8V_CPVDD
100KR2J-1-GP
R2702
[29]
1D8V_S0
SC2D2U10V3KX-1DLGP-U
AUD_SPK_L+
C2709
AUD_SPK_R-
[29]
C2708
AUD_SPK_R+
[29]
C2704
SCD1U16V2KX-3DLGP
[29]
1D8V_CPVDD
Place close to Pin 20
LDO1_CAP
SC2D2U10V3KX-1DLGP-U
5V_S0
1 R2703 2
0R0603-PAD-7-NP-GP
Layout Note:
+5V_PVDD
1 R2701 2
0R0805-PAD-NP-GP
1 R2707 2
0R0805-PAD-NP-GP
D
moat
+5V_AVDD
AUD_AGND
1
5V_S0
AUD_HP1_JACK_R
1
Audio Codec Chip ALC3204
2
HDA_BITCLK_CODEC
2
HDA_SYNC_CODEC
[19]
1
[19]
2
[19]
AUD_SENSE
3D3V_S0
R2711 1
200KR2F-L-GP
2
R2710 1
100KR2J-1-GP
2
AUD_HPJD_N
20191204
For Vendor request
Azalia I/F EMI
HDA_SDOUT_CODEC
HDA_BITCLK_CODEC
SPKR
R2741 1
1KR2J-1-GP
2
HDA_SPKR_R 1
BEEP
R2734 1
1KR2J-1-GP
2
KBC_BEEP_R
D2703
3
R2723 1
B
C2735
1
2
AUD_PC_BEEP_C
AUD_PC_BEEP
SCD1U16V2KX-3DLGP
2
1
HDA_BITCLK_CODEC
HDA_SDOUT_CODEC_R
2
0R0402-PAD-7-NP-GP
HDA_BITCLK_CODEC_R
2
0R0402-PAD-7-NP-GP
BAT54C-12-GP
75.00054.A7D
2nd = 75.00054.T7D
DY
SC100P50V3JN-2GP
C2739
R2722 1
1KR2J-1-GP
R2735
HDA_SDOUT_CODEC
1
HDA_CODEC_SDIN0
2
2 33R2J-2-GP
2
2
1
2
R2724 1
EC2710
SC10P50V2JN-4DLGP
EC2709
SC15P50V2JN-DL-GP
DY
1
HDA_SDIN0_CPU
B
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A2
Date:
5
4
3
2
Audio Codec ALC3204
Document Number
Sheet
1
27
Rev
A00
MOCKINGBIRD_TGL
Saturday, August 01, 2020
of
105
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A4
Document Number
4
3
Rev
MOCKINGBIRD_TGL
Date: Saturday, August 01, 2020
5
(Reserved)
2
Sheet
28
A00
of
1
105
A
5
4
3
2
Layout Note:
Main Func = Audio
1
Speaker
CONN Pin
Speaker trace width >40mil @ 2W4ohm speaker power
SPK1
7
AUD_SPK_R+
AUD_SPK_RAUD_SPK_LAUD_SPK_L+
AUD_SPK_L- R2901 1
AUD_SPK_R- R2903 1
AUD_SPK_R+ R2904 1
2 0R0603-PAD-7-NP-GP
AUD_SPK_L+_C
1
2 0R0603-PAD-7-NP-GP
2 0R0603-PAD-7-NP-GP
2 0R0603-PAD-7-NP-GP
AUD_SPK_L-_C
AUD_SPK_R-_C
AUD_SPK_R+_C
SPK_ID
2
3
4
5
6
1
2
2
1
1
2
1
2
2
DY
1
2
ED2905
AZ5725-01FDR7G-GP
DY
1
1
DY
ED2904
AZ5725-01FDR7G-GP
2
2
ED2903
AZ5725-01FDR7G-GP
1
2
DY
EC2903
20.F1639.006
EC2904
SC1KP50V2KX-1DLGP
EC2901
SC1KP50V2KX-1DLGP
EC2902
SC1KP50V2KX-1DLGP
DY
SPK_L+
Pin2
SPK_L-
Pin3
SPK_R-
Pin4
SPK_R+
Pin5
SPK_DET#
Pin6
GND
D
ACES-CON6-20-GP-U
SC1KP50V2KX-1DLGP
ED2902
AZ5725-01FDR7G-GP
SPK_ID
ED2901
AZ5725-01FDR7G-GP
[18]
SPK_ID
1: VECO
0: ZY
2nd = 020.F1263.0006
SPK2
5
1
2
3
4
AUD_SPK_L-_C
AUD_SPK_L+_C
AUD_SPK_R-_C
AUD_SPK_R+_C
SPK_ID
Hellcat
6
1
1
1
1
1
AFTP2901
AFTP2902
AFTP2903
AFTP2904
AFTP2911
ACES-CON4-29-GP
83.05725.0A0 83.05725.0A0 83.05725.0A0
83.05725.0A0 83.05725.0A0
C
MKB
8
AUD_SPK_R+_C
AUD_SPK_R-_C
AUD_SPK_L-_C
AUD_SPK_L+_C
SPK_ID
1
D
[27]
[27]
[27]
[27]
AUD_SPK_L+ R2902 1
Net name
Pin1
20.F1639.004
2nd = 020.F0097.0004
C
From Codec
RN2901
MIC2_VREFO
[27]
MIC2_VREFO
[27,29,66]
[27]
[27]
[27]
LINE1_L
LINE1_R
AUD_HP1_JACK_L
LINE1_L C2907 1
LINE1_R C2908 1
AUD_HP1_JACK_R
LINE1_VREFO
AUD_SLEEVE
[27]
LINE1_VREFO
2 LINE1-L_C
R2922 1
SC10U6D3V3MX-DL-GP
2 LINE1-L_R
R2921 1
SC10U6D3V3MX-DL-GP
R2908 1
2 10R2F-L-GP
R2910 1
2 10R2F-L-GP
AUD_RING
AUD_HP1_JACK_L1
2 1KR2J-1-GP
2 1KR2J-1-GP
AUD_HP1_JACK_R1
AUD_SLEEVE
D2901
AUD_HP1_JACK_R
[27,29,66]
Universal Jack (Moved to I/O Board)
3
4
SRN2K2J-1-GP
AUD_RING
AUD_HP1_JACK_L
[27]
2
1
A
K
LINE1_VREFO_D1
83.R2003.A8M
2ND = 083.52030.008F
RB520S30-GP
A
RB520S30-GP
K
D2902
LINE1_VREFO_D2
R2912 1
4K7R2J-2-GP
2
R2913 1
4K7R2J-2-GP
2
83.R2003.A8M
2ND = 083.52030.008F
B
To IO Board
[27,29,66]
AUD_RING
[66]
AUD_HP1_JACK_L1
[66]
AUD_HP1_JACK_R1
[27,29,66]
B
AUD_SLEEVE
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Audio IO
https://realschematic.com
Size
A3
Date:
5
4
3
2
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
29
of
A00
105
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
(Reserved)
https://realschematic.com
Size
A4
Document Number
Date:
5
4
3
Rev
A00
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
30
2
of
1
105
A
5
4
3
2
1
Main Func = LAN
D
D
C
C
B
B
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
LAN RTL8106
Size
Document Number
Custom
Rev
MOCKINGBIRD_TGL
Date:
5
https://realschematic.com
4
3
2
Saturday, August 01, 2020
Sheet
1
31
A00
of
105
5
4
3
2
1
Main Func = LAN
D
D
C
C
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A3
Date:
5
4
3
2
Document Number
XFOM&RJ45
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
32
A00
of
105
5
4
3
2
1
Main Func = Card Reader
D
D
C
C
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Card Reader-RTS5170
Size
A4
Document Number
MOCKINGBIRD_TGL
Date: Saturday, August 01, 2020
5
4
3
2
Sheet
33
A00
of
1
Rev
105
A
5
4
3
2
1
Main Func = USB2.0
D
D
C
C
B
B
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
Document Number
USB2.0 CONN
Rev
A00
MOCKINGBIRD_TGL
Date:
5
4
3
2
Saturday, August 01, 2020
Sheet
1
34
of
105
5
4
3
2
1
D
D
Main Func = USB3.0 Port1
5V_S5
5
[16]
C3507S
C1U10V2KX-1DLGP
2
1
USB_PWR_EN#
USB_PWR_EN#
IN
4
5V_USB30_VCCA
2A
U3502
[24,66]
OUT
GND
OC#
EN#
1
2
3
ED3502
2
USB1_USB20_CON_N
1
USB1_USB20_CON_P
Active Low
G524B2T11U-GP
3
074.00524.0C9F
2nd = 074.03553.007GUSB_OC0#_R
3rd = 074.09742.009F
2 R3512
1
USB_OC0#
0R0402-PAD-7-NP-GP
AZ5315-02F-GP
83.05315.0A0
2nd = 075.5V0X2.0070
3rd = 075.73022.0073
USB_OC0#
2020/02/29:swap EL3501
C
C
EL3501
[16]
USB1_USB20_N
[16]
USB1_USB20_P
USB1_USB20_N
1
2
USB1_USB20_CON_N
USB1_USB20_P
4
3
USB1_USB20_CON_P
USB3.0 Port1
FILTER-4P-132-GP
5V_USB30_VCCA
68.02002.061
1
USB1_USB20_CON_N
USB1_USB20_CON_P
5V_USB30_VCCA
USB1_USB30_RX_CON_P
ED3501
SCD1U16V2KX-3DLGP
[16]
[16]
USB1_USB30_TX_N
USB1_USB30_TX_P
[16]
[16]
USB1_USB30_RX_N
USB1_USB30_RX_P
FL3503
FL3502
4
2
3
1
068.24900.2021
2nd = 68.11800.201
3rd = 068.10129.2041
4
2
3
1
068.24900.2021
2nd = 68.11800.201
3rd = 068.10129.2041
USB1_USB30_RX_CON_N
8
3
1
10
USB1_USB30_RX_CON_N
USB1_USB30_RX_CON_P
2
9
USB1_USB30_RX_CON_P
USB1_USB30_TX_CON_N
4
7
USB1_USB30_TX_CON_N
USB1_USB30_TX_CON_P
5
6
USB1_USB30_TX_CON_P
1
1
C3509
2
C3510
2
1
C3508
2
2
USB1_USB30_RX_P
SC22U6D3V3MX-1-DL-GP
2
USB1_USB30_TX_CON_P
C3506
2
3
10
11
12
13
SC22U6D3V3MX-1-DL-GP
1
Stuff for ESD R2 spec
USB1_USB30_TX_CMC_P
SC1U10V2KX-1DLGP
C3512
SCD1U16V2KX-3DLGP
1
2A
USB1_USB30_TX_P
USB3
Layout Note: Close USB3
USB3.0 Port 1
2nd = 068.09002.2001
VBUS
STDA_SSRXSTDA_SSRX+
DD+
STDA_SSTXSTDA_SSTX+
10
11
12
13
GND
GND
5
6
USB1_USB30_RX_CON_N
USB1_USB30_RX_CON_P
8
9
USB1_USB30_TX_CON_N
USB1_USB30_TX_CON_P
4
7
SKT-USB13-510-GP
022.10064.0021
2nd = 022.10005.0LB1
3rd = 022.10005.0LD1
FILTER-4P-264-GP
FILTER-4P-264-GP
C3511
USB1_USB30_TX_N
1
2
USB1_USB30_TX_CMC_N
USB1_USB30_TX_CON_N
USB1_USB30_RX_N
USB1_USB30_RX_CON_N
SCD1U16V2KX-3DLGP
AZ1043-04F-R7G-GP
075.01043.0073
2nd = 075.08810.0A73
3rd = 075.73044.0003
B
B
A
A
<Core Design>
Wistron Corporation
https://realschematic.com
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
USB3.0 CONN
Size
A1
Date:
5
4
3
2
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
1
Sheet
35
A00
of
105
5
4
3
2
1
Main Func = USB Charger
D
D
C
C
B
B
<Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
USB Charger
Size
Document Number
Custom
Rev
MOCKINGBIRD_TGL
Date:
5
https://realschematic.com
4
3
2
Saturday, August 01, 2020
Sheet
1
36
A00
of
105
A
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
A
A
Title
Size
A4
https://realschematic.com
Document Number
4
3
Rev
MOCKINGBIRD_TGL
Date: Saturday, August 01, 2020
5
USB3.0 PORT
2
Sheet
A00
37
of
1
105
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
A
A
Title
Size
A4
https://realschematic.com
Document Number
4
3
Rev
MOCKINGBIRD_TGL
Date: Saturday, August 01, 2020
5
Reserved
2
Sheet
38
A00
of
1
105
5
4
3
2
1
D
D
C
C
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
(RSVD)
Size
A4
Document Number
Date: Saturday, August 01, 2020
5
4
3
Rev
MOCKINGBIRD_TGL
2
Sheet
39
A00
of
1
105
A
5
SIO_SLP_SUS#
PCH_PLTRST#
PWR_VDDQ_PG
[22,50]
CORE_VID0
[22,50]
CORE_VID1
3D3V_S5
2
2
1
1
2
SC1U10V2KX-1DLGP 6
7
1
1
2
DY
CPU_C10_GATE#
PURE_HW_SHUTDOWN#
074.02898.0093
074.05209.0093
3rd = 074.07110.0093
D
PWR_1D8V_EN
2019.10.08 Follow Nakia
PWR_1D8V_PG
VCCIN_AUX_PWRGD
PWR_1D05V_EN
PJA3413-1-GP
10KR2J-3-GP
1
1
C4039
DY
SCD1U16V2KX-3DLGP
1D05V_S5_OUT
1D8V_EN_R#
20KR2J-L2-GP
(300mA)
5V_S5
2
10/09 DY D4002 follow PDG,
Charon
3D3V_S5
D4008
1
DY
OUT#8
OUT#7
OUT#6
VBIAS
ON
GND
8
7
6
1
C4027
G5027CRD1D-GP-U
074.05027.0B93
2nd = 074.05201.0A93
R4049
1
0R2J-2-GP
2
[54]
PWR_VNN1D05V_VID1
2 0R2J-2-GP
SIO_SLP_S3#
SIO_SLP_SUS#
C4030
R4048
1
DSW 2
0R2J-2-GP
2 0R2J-2-GP
VNN_CTRL_R
BYPASS
DY
VCCIN_AUX_PWRGD
R4001
1
DY
2 0R2J-2-GP
R4022
1
K
A
2
SIO_SLP_S3#
R4012
VCCIN_AUX_PWRGD
10KR2J-3-GP
1
R4026
1
R4013
1
R4030
1
2 20KR2J-L2-GP
DY
2 10KR2J-3-GP
BYPASS
BYPASS
2
FLG#
GND
DSWVOUT
3
2
1
RB520S30-GP
U2502_OUT R4047 1
0R2J-2-GP
DSW
2
074.09742.0A9F
2nd = 074.51712.009F
3rd = 074.03553.007F
4th = 074.03553.0A7F
20191120
Follow Nakia
1
83.R2003.A8M2nd = 083.52030.008F
R4003
1
2
ALWON
10KR1J-GP
C4001
SC2D2U10V3KX-1DLGP-U
20191119
no need,
B
We use DDR4 upsell and nokia us LPDDR4
PWR_1D05V_EN
C4031
BYPASS
C4032
SCD1U16V2KX-3DLGP
SC1U10V2KX-1DLGP
2
0R0402-PAD-7-NP-GP
VIN
2
1
2
EN/EN#
PURE_HW_SHUTDOWN#
K
PWR_VNN_EN
10KR2J-3-GP
ALL_SYS_PWRGD
1 R4007
5
A
PWR_1D8V_PG
PWR_VNN1D05V_PG
2 0R2J-2-GP
BYPASS
RB520S30-GP
PWR_VDDQ_PG
PWR_VNN1D05V_PG
3D3V_S5
3D3V_S0
83.R2003.A8M
2nd = 083.52030.008F D4001
4
RT9742CGJ5-GP
20191223
For Internal Review
B
U2502_IN
3D3V_S5
SCD1U16V2KX-L-GP
3V_5V_EN
1
1
DY
PM_SLP_S3#
D4006
3D3V_S5_VCCPRIM
2
1
2
BYPASS
R4011
U4010
20KR2F-L-GP
R4002
R4010
PWR_VNN1D05V_VID1
3D3V_S5_VCCPRIM
DY
V1P05_CTRL_R
20200511(DVT2)
Follow intel suggestion change to 3D3V_S5_VCCPRIM
2
PWR_VNN1D05V_VID2
20191119
Follow ICL
High limit
PWR_1D8V_EN
2 4K7R2J-2-GP
1
[54]
PWR_VNN1D05V_VID2
C4003
Power Sequence / Pull High PWRGD
1 R4031 2
0R0402-PAD-7-NP-GP
R4025 1
1
SIO_SLP_SUS#
10/09
3V_5V_DSW_OK
change to SIO_SLP_SUS#,
Charon
R4016 2
0R0805-PAD-NP-GP
5
20191223
For Internal Review
1D05V_BYPASS_CTRL
1D05V_VCCST
SCD1U16V2KX-3DLGP
20191223
For Internal Review
R4009
SCD1U16V2KX-3DLGP
D
LRB751V-40T1G-GP
83.00751.08F 2nd = 83.R2004.G8F
A
K
DY
D4010
LRB751V-40T1G-GP
83.00751.08F 2nd = 83.R2004.G8F
IN#1
IN#2
IN#9
3
4
100KR2J-1-GP
S
1
2
9
VCCST_EN1 R4036 2 VCCST_EN_R
0R0402-PAD-7-NP-GP
C4004
20190501_NEAL
084.01900.0033
2nd = 084.00290.0033
C
1D05V_VCCST_FIP
C4002
LRB751V-40T1G-GP
SCD1U16V2KX-L-GP
SIO_SLP_S3#
84.2N702.J31
2ND = 084.27002.0N31
3rd = 084.27002.0L31
4th = 084.07002.0C31
VCCSTG_EN
SC1U10V2KX-1DLGP
Notice:ZZ.2N702.J3101
2N7002K-2-GP
5V_S5
2nd = 83.R2004.G8F
K
C4024
U4001
83.00751.08F
A
K 2nd = 83.R2004.G8F
D4005
20191223
For Internal Review
S
Q4002
PJQ1900-GP-U
G
A
CPU_C10_GATE#
5
074.05027.0B93
2nd = 074.05201.0A93
VCCST_EN
LRB751V-40T1G-GP
83.00751.08F
VCCST_READY
1D05V_VCCSTG
R4018 2
0R0402-PAD-7-NP-GP
6A/Rds(on):4.5mOhm/Tr:7~20us
1D05V_S5_OUT
2
3
DY
100KR2J-1-GP
GND
1
(1200mA)
LRB751V-40T1G-GP
1
2
D4009
G
20191112 modify
Follow Nakia
Remove C4007
20191223
For Internal Review
2nd = 83.R2004.G8F
2
CORE_VID1
K
83.00751.08F
A
K
VCCST_READY
D
20200420(DVT2)
Change to 084.01900.0033
VCCST_OVERRIDE
1
A
D4004
Q4001
VCCST_OVERRIDE_Q1
(1.05V)
CORE_VID0
R4006
100KR2J-1-GP
2
2
1
1
R4005
D4002
BAT54C-12-GP
1
SIO_SLP_S3#
3D3V_S5
2
C
VBIAS
ON
8
7
6
SCD1U16V2KX-3DLGP
PCH_RSMRST#
C4008
SC1U10V2KX-1DLGP
VNN_CTRL_R
100KR2J-1-GP
[22]
[17,24]
084.08408.0031
2nd = 084.00138.0E31
1D8V_EN#
OUT#8
OUT#7
OUT#6
G5027CRD1D-GP-U
C4010
C4028
SCD1U16V2KX-L-GP
ESPI_RESET#
PJE8408-R1-00001-GP
[81]
DY
IN#1
IN#2
IN#9
3
4
VCCSTG_EN_R
R4008
SCD1U16V2KX-3DLGP
20191223
For Internal Review
1
VCCSTG_EN 1 R4033 2
0R0402-PAD-7-NP-GP
1
D
Q4004
2
1D8V_EN#
S
1D05V_VCCSTG_FIP
U4002
1
2
9
PWR_VNN1D05V_PG
[18,24,68]
6A/Rds(on):4.5mOhm/Tr:7~20us
2
SC1U10V2KX-1DLGP
SIO_SLP_S3#
V1P05_CTRL_R
G
[24,54]
1D8V_S0
D
2
R4035
[22]
C4038
G
1
SCD1U16V2KX-3DLGP
3V_5V_EN
2
[45]
2
2
1
1
S
R4034
C4037
1
1D8V_S5
2
PWR_VNN_EN
084.03413.0031
2nd = 084.02301.0031
3rd = 84.00513.03B
150mA
Q4003
20191119
Follow ICL
High limit
1
20191120
we don't support LPDDR4
20191120
we don't support LPDDR4
2
ALWON
[54]
G2898KD1U-GP
C4006
2
[54]
[24]
15
1
[50]
C4005
11
GND
2
[50,53]
20200713
Remove ES1 Power
1
[53]
5V_S0
3D3V_S0
1
[26]
EN1
EN2
THERMAL_PAD
SCD22U10V2KX-2-GP
[17]
D
3
5
C4007
2
2
1
SC470P50V2KX-3DLGP
13
14
8
9
OUT1#13
OUT1#14
OUT2#8
OUT2#9
SC10U6D3V3MX-DL-GP
3V5V_S0_ON
1 R4014 2
0R0402-PAD-7-NP-GP
ALL_SYS_PWRGD
SC470P50V2KX-3DLGP
U4001_CT1 C4057 1
U4001_CT2 C4069
12
10
CT1
CT2
IN1#1
IN1#2
IN2#6
IN2#7
SC10U6D3V3MX-DL-GP
VCCST_OVERRIDE
VBIAS
1
SC1U10V2KX-1DLGP
SIO_SLP_S3#
[17]
1
U4005
4
C4071
C4070
[17,24,44,46]
2
5V_S5
5V_S5
[51]
3
RUN Power
2
[17]
[17,61,63,66,71,76,91]
4
20191119
Follow ICL
High limit
20200407
Add C4070~C4072 to prevent IC broken
20200410
Remove C4072, only need one
1
SIO_SLP_S3#
2
SIO_SLP_S4#
[17,55,81]
2
[17,51,66]
11/15 Follow Shuri
V-tree
20200305(DVT1)
For customer request
1
3D3V_S5
3D3V_S5
1
DY
R4051
R4054
100KR1J-GP
2
V-tree100KR1J-GP
2
Q4011_D
R4053
DY
1
1KR2J-1-GP
084.08408.0031
2nd = 084.00138.0E31
V-tree
PWR_1D05V_EN_R
G
C4033
DY
S
DY
ALL_SYS_PWRGD
D
2
S
Q4011
PJE8408-R1-00001-GP
S
2
G
Q4009
PJE8408-R1-00001-GP
2
V-tree
V-tree
1
VCCIN_AUX_PWRGD
D
1
G
R4052
1MR2J-1-GP
S
2D5V_S3
DY
G
D
Q4009_D
SC1U10V2KX-1DLGP
084.08408.0031
2nd = 084.00138.0E31
R4055
DPCH_RSMRST#_D
2
Q4012
PJE8408-R1-00001-GP
DY
1
PCH_RSMRST#
1KR2J-1-GP
084.08408.0031
2nd = 084.00138.0E31
Q4010
PJE8408-R1-00001-GP
084.08408.0031
2nd = 084.00138.0E31
A
A
<Core Design>
Wistron Corporation
https://realschematic.com
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A1
Date:
5
4
3
2
CPU (THML/JTAG)
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
1
Sheet
A00
40
of
105
5
4
3
2
1
D
D
C
C
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Connected_Standby(1/2)+DS3
https://realschematic.com
Size
A4
Document Number
Date: Saturday, August 01, 2020
5
4
3
Rev
MOCKINGBIRD_TGL
2
Sheet
41
1
A00
of
105
A
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Connected_Standby(2/2)
Size
A4
Document Number
Date:
5
4
3
Rev
A00
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
42
2
of
1
105
A
5
4
3
2
1
Main Func = ADT Input
[24,44]
AC_DIS
84.T3904.H11
2nd = 084.03904.0I11
3rd = 084.03904.0H11
4th = 84.03904.T11
PS_ID
5V_S5
3D3V_S5
1
D4302
LBAV99LT1G-1-GP
PSID_DISABLE#_R_C
R4309
100KR2J-1-GP
3
75.00099.O7D
2nd = 75.00099.E7D
3rd = 75.00099.B7D
4th = 075.00099.0E7D
ED4303
AZ5125-02S-R7G-GP
R4305
PS_ID_R1
S
1
2
D
PJA138KA-GP
1
084.00138.0A31
2nd = 084.01012.0031
R4304
2K2R2J-2-GP
D
Barrel Adapter Piug-in Detect
PS_ID
2
3D3V_S5
33R2J-2-GP
R4313
200KR2F-L-GP
2
2
1
2
1
2
1
2
EC4311
DY
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
1
1
EC4313
DY
1
R4314
10KR2J-3-GP
U4302
U4302-
1
2
3
INPUTGND
INPUT+
VCC
OUTPUT
5
2
1
2
1
2
1
2
U4302+
HW_ACAVIN_NB
4
2
2
R4319
15KR2F-GP
1
1
1
2
1
2
1
1
2
1
R4317
150KR2F-L-GP
2
LMUN5112T1G-GP-U
AONR21321-GP
084.21321.0037
2nd = 084.03307.0037
R4308
47KR2F-GP
AD_OFF_R
C
R4307
240KR3-GP
1
2
1
E
B
E
R2
LMUN5212T1G-GP
84.05212.B11
2nd = 84.00124.H1K
3rd = 084.00024.0B1K
EC4312
SC1KP50V2KX-1DLGP
DY
R1
1
1
2
1
2
K
A
2
B
AD_OFF_L
R1
AC_DIS
R4379
100KR2J-1-GP
PS_ID_R
R2
C
G
3D3V_S5
C4308
DY
084.05112.001K
2nd = 84.00124.K1K
3rd = 084.00024.0A1K
DY
C4307
AS331KTR-G1-GP
SC100P50V2JN-3DLGP
Q4305
Q4304
+DC_IN
D 8
D 7
D 6
D 5
100KR2F-L1-GP
C4302
SCD1U25V2KX-1-DL-GP
PU4301
S
S
S
20KR2J-L2-GP
R4316
EC4303
R4320
19V_AD+
1
2
3
SC10U25V5KX-DL-GP
C4306
DY
D4301
P6AF24A-R1-00001-GP
083.00624.00AM
2nd = 083.FJ24A.00AM
+DC_IN_C
AFTP4303
AFTP4304
+DC_IN
C4301
SC1U25V3KX-1-DLGP
20.F1295.008
2nd = 20.F2120.008
3rd = 020.F0834.0008
EC4302
SCD1U25V2KX-1-DL-GP
DY
SC1KP50V2KX-1DLGP
10
ACES-CON8-13-GP-U2
C
S1
75.05125.07D
2nd = 075.52215.007D
20191223
For EMC requirement
AFTP4301
SC100P50V2JN-3DLGP
1
+DC_IN_C
SCD01U25V2KX-3DLGP
C4303
2
3
4
5
6
7
8
2
1
4
9
3
60ohm@100MHz
DCR=0.02 ohm
Max current = 6000mA
DCIN1
1
PS_ID_R
+DC_IN
G
Q4301
1
20200430(DVT2)
Change 83.05725.0A0 to 75.05125.07D
1
2
2
Q4302
LMBT3904LT1G-GP
2
+DC_IN_C
D
[44,89]
B
2
PSID Layout width > 25mil
[44,89]
PQ3802_1
C
Layout Note:
3D3V_S5
R4303
10KR2J-3-GP
E
R4302
15KR2F-GP
HW_ACAVIN_NB
1
[24,44]
1
2
[24]
74.00331.H2F
2nd = 74.00391.02F
+DC_IN_C
PS_ID_R
C
B
B
PBAT_CHG_SMBCLK
Main Func = M-BAT Input
Placement: Close to Batt Connector
K
D4307
SMF18A-GP
A
BATT1
DY
11
1
PBAT_CHG_SMBCLK
PBAT_CHG_SMBDAT
PBAT_PRES#
2
1
3
4
1
2
PBAT_SMBCLK1
PBAT_SMBDAT1
PBAT_PRES1#
1 R4301 2 SYS_PRES1#
0R0402-PAD-7-NP-GP
1
1
2
1
2
2
DY
D4306
LBAV99LT1G-1-GP
DY
75.00099.O7D
75.00099.O7D
2
3D3V_S5_KBC
EC4306
SC10P50V2JN-4DLGP
DY
SC10P50V2JN-4DLGP
https://realschematic.com
SC10P50V2JN-4DLGP
DY
EC4310
D4305
LBAV99LT1G-1-GP
DY
75.00099.O7D
1
2
3
4
5
6
7
8
9
10
12
R4310
100R2J-2-GP
EC4309
D4304
LBAV99LT1G-1-GP
A
RN4302
SRN100J-3-GP
1
A
2
EC4307
DY
SCD1U25V2KX-1-DL-GP
3
1
1
2
DY
2
EC4308
SCD1U50V3KX-GP
20191218
For EMC required
PBAT_CHG_SMBCLK
BT+
20200324(DVT2)
EC4307 change to common
PBAT_CHG_SMBDAT
PBAT_PRES#
Batt Connecter
3
PBAT_PRES#
3
PBAT_CHG_SMBDAT
[24,44]
1
[24,44]
2
[24,44]
2nd = 75.00099.E7D
2nd = 75.00099.E7D
2nd = 75.00099.E7D
3rd = 75.00099.B7D
3rd = 75.00099.B7D
3rd = 75.00099.B7D
4th = 075.00099.0E7D
4th = 075.00099.0E7D
4th = 075.00099.0E7D
ETY-CON10-33-GP
1
1
1
AFTP4306
AFTP4307
AFTP4308
<Core Design>
020.F0667.0010
2nd = 20.F1240.010
PBAT_PRES1#
PBAT_SMBDAT1
PBAT_SMBCLK1
BT+
BT+
BT+
SYS_PRES1#
Wistron Corporation
1
1
1
1
1
1
1
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
AFTP4309
AFTP4310
AFTP4311
AFTP4312
AFTP4313
AFTP4314
AFTP4315
Title
Size
A1
Date:
5
4
3
2
DCIN
Document Number
Rev
A00
MOCKINGBIRD_TGL
Saturday, August 01, 2020
1
Sheet
43
of
105
5
4
3
Main Func = Charger
19V_DCBATOUT
+SDC_IN
20V_DCBATOUT
1
2
1
1
1
1
1
1
2
2
2
2
2
1
1
1
2
1
1
2
2
1
1
2
2
2
1
1
1
2
1
2
2
2
2
1
S
D
1
2
2
4
SC10U25V3MX-5-GP
SC10U25V3MX-5-GP
1
1
1
G
S
S
S
1
2
3
3
2
1
2
BGATE
PWR_CHG_UGATE2
PR4408
2D2R3-1-U-GP
4
PWR_CHG_BOOT2
2
2
PWR_CHG_CSOP
PC4439
SC1U25V2KX-4-GP
1
PWR_CHG_CSON
2
D 8
D 7
D 6
D 5
G
S
S
S
1
2
3
2
1
PC4423
SCD22U25V3KX-DL-GP
PWR_CHG_BT2_R
1
PC4424
SC1U25V2KX-4-GP
2
1
1
1
2
PR4410
316KR1F-GP
1
PR4413
1
PR44C4
PU44C1_EN_R
2
4
S
D
1
PC44D1
PR44C3
1
2
DY
2
2
B
DY
+SDC_IN
6
5
4
1
2
3
PQ44D0
2N7002KDW-1-GP
DY
2
PR44D3
0R2J-2-GP
1
DY
2
75.27002.F7C
OVP_PCH_PWROK
PWR_CHG_ACIN_A
1
DY
2
PR44D9
0R2J-2-GP
1 PWR_CHG_ACIN
DY
VCC
DY
OUTPUT
2
DY
5
4
OVP_PCH_PWROK_G
2
INPUTGND
INPUT+
PR44A4
10KR2F-2-GP
VCORE_OVP_OUT
AS331KTR-G1-GP
1
1
DY
DY
2
1
PR44A3
2
1
2
DY
PC44A1
SC100P50V2JN-3DLGP
2
PC44A9
75KR2F-GP
100KR2F-L1-GP
1
PU44A1
2
VCORE_OVP_+ 3
DY
1
74.00331.H2F
PD44A1
K
A
L1SS355T1G-GP
83.00355.G1F
DY
2
PR4473
100KR1F-GP
TypeC Prochot
Follow custormer circuits.
1
2
1
PR44A2
VCORE_OVP_- 1
SC100P50V2JN-3DLGP
19V_AD+
DY
VCORE_OVP_OUT
OVP_VR_EN_G_A
PC44D0
SCD22U25V3KX-DL-GP
PWR_IMVP_PWRGD
1
2
DY
PR44A1
CHECK EE
follow custormer circuits.
Vcore_OVP
2
PR44A8
0R2J-2-GP
DY200KR2F-L-GP
1
2
1
2N7002KDW-1-GP
75.27002.F7C
2nd = 075.27002.0E7C
VCORE_OVP_+A
DY PR44D7
0R2J-2-GP
2
1
205KR2F-GP
PWR_CHG_PROCHOT#
1
PR44D6
0R2J-2-GP
2
PR44D5
1KR2F-3-GP
2
1
1
DY
VCORE_OVP_PWR
VCORE_OVP_+A
1
PR44A7
0R2J-2-GP
PR44A6
0R2J-2-GP
PR44A0
PR4435
100KR1F-GP
DY
0R2J-2-GP
VDD
2
1
DY
3D3V_S5
2
OVP_VR_EN_G
PR44D1
CPU_Core
PWR_CHG_PROCHOT#_CPU
PR44D4
OVP_VR_EN_A
DY
PR44D2
4K99R2F-L-GP
G
DY
DY 200KR2F-L-GP
+3D3V_VDD_+SDC_IN
DY
Note:ZZ.27002.F7C01
PC44C2
DY SC2D2U10V3KX-1DLGP-U
PC44C1
DY SC100P50V2JN-3DLGP
1V_CPU_CORE
PQ4416
PR44C2
R1DY16K9R2F-GP
R2DY10KR2F-2-GP
1
OPS
2N7002K-2-GP
84.2N702.J31
2ND = 084.27002.0N31
3rd = 084.27002.0L31
4th = 084.07002.0C31
PU +VCCSTG = 1.0 V on CPU side
Vout=1.24*(1+(R1/R2))
1
100KR2F-L1-GP
PR44C1
DY 10KR2F-2-GP DY
OVP_VR_EN
1
2
PU44C1_EN 1
DY
0R2J-2-GP
1
2
1
74.02204.03F
2nd = 074.02920.003F
PC4431
SCD01U25V2KX-3DLGP
2
PWR_CHG_PROCHOT#_R
S
084.21319.0031
PR44D0
2
SCD1U25V2KX-1-DL-GP
G
ADJ
AP2204K-ADJTRG1-GP
2
2
PC44C3
ALL_SYS_PWRGD
4
DYSC10U25V3MX-5-GP
DY 13K3R2F-L1-GP
PQ44D1
AOSS21319C-GP
+3D3V_VDD_+SDC_IN
5
OUT
DY
2
PR44C7
VIN
GND
EN
2
1
1
3
PU44C1
1
2
3
1
75.00054.A7D
2nd = 75.00054.T7D
20V>+DC_IN>4.7V
PU44C1_VIN
1
2
2
+3D3V_VDD_DCIN
PD44C1
BAT54C-12-GP
1
2
PWR_CHG_COMP_R
D
DGPUHOT#
PU 3V3_AON_S0 on GPU side
2
1
+DC_IN
2
20V_VCCPD_VBUS
PC4432
SC1KP50V2KX-1DLGP
1
DY
PQ4402
B
6
2
CHGR_PSYS_IMVP
0R0201-PAD-GP
PWR_CHG_IMON
1
2
SC1KP50V2KX-1DLGP
PWR_CHG_PROCHOT#_R
1
2
PU44C1_ADJ
0523
2
084.21307.0037
2nd = 084.01403.0A37
2
2
PR4411
499R2F-2-GP
PC4433
3
BT+
10K2R2F-GP
1 PR4442
DY
5
PC4429
1
PR4426
196KR2F-GP
75.27002.F7C
2nd = 075.27002.0E7C
4
PU4412
AONR21307-GP
S
D 8
S
D 7
S
D 6
D 5
G
2
1
2N7002KDW-1-GP
PR4472
100KR1F-GP
2
2
1
PWR_CHG_BGATE
PWR_CHG_VBAT1
PWR_CHG_PSYS
PWR_CHG_AMON
PWR_CHG_COMP
PWR_CHG_PROG
PWR_CHG_OTGPG
PWR_CHG_BATGONE
1
2
PG4408
GAP-CLOSE-PWR-3-GP
3D3V_S5
1
2
3
1
6
1
PR4478
100R1F-GP
PQ4405_3
0R0402-PAD-7-NP-GP
PC4428
1
TP4402
TPAD14-OP-GP
1
2
2
PWR_CHG_VBATIN
PC4427
1
AC_IN#
PR4476
5
2
100KR1F-GP
PC4430
SC10P50V2JN-4DLGP
1
PR4412
HW_ACAV_IN
2
0R0402-PAD-7-NP-GP
0R0402-PAD-7-NP-GP
3
1
2
PQ4415
4
1
PR4429
100KR2F-L1-GP
2
PQ4418_3
ACOK#
2
2
PR4427
100KR2F-L1-GP
PR4498
2
PG4406
GAP-CLOSE-PWR-3-GP
PC4440
SC1U25V3KX-1-DLGP
PWR_CHG_PROCHOT#_CPU
0R0402-PAD-7-NP-GP
PR4425 1PWR_CHG_CSON_R
1R2F-GP
2
DY
PC4426
SC1U25V2KX-4-GP
1
1
2
2
PR4407
D005RL3720F-1-GP
SC4700P50V2KX-1DLGP
PR4409
PBAT_PRES#
1
SC10U25V5KX-DL-GP
VDD
2
SC10U25V5KX-DL-GP
VDD
PR4430
1PWR_CHG_CSOP_R
1R2F-GP
PC4425
SC1U25V2KX-4-GP
2
1
PBAT_CHG_SMBCLK
PWR_CHG_PROCHOT#
PG4405
GAP-CLOSE-PWR-3-GP
PR4424
2
33
GND
C
2
DY
1
1
5
2
32
VBAT
31
PBAT_CHG_SMBDAT
PWR_CHG_PHASE2
3
CSON
PSYS
ACOK
PWR_CHG_LGATE2
2
CSOP
PWR_CHG_VDDP
1
PROCHOT#
DY PC4435
SC1KP50V2KX-1DLGP
8
7
6
1
4
2
VSYS
PC4421
SC4D7U10V3KX-DL-GP
PU4406
AON7380-GP
2
LGATE1
BOOT2
SCL
DY PR4416
2D2R5J-1-GP
1 PWR_CHG_SNB
9
10
13
CSIN
ASGATE
BOOT1
UGATE1
14
CSIP
PHASE1
UGATE2
SDA
25
24
PHASE2
ISL9538CHRTZ-T-2-GP
074.09538.0C73
CMIN
AMON/BMON
1
23
ACIN
COMP
2
22
PROG
2
21
LGATE2
30
20
PR4417
100KR1F-GP
VDDP
VDD
1
5
6
7
8
4
3
2
1
PWR_CHG_UGATE1
PWR_CHG_PHASE1
PWR_CHG_BOOT1
PWR_CHG_ASGATE
12
11
PWR_CHG_CSIN
PU4404
AON7380-GP
PWR_CHG_LGATE1
DCIN
28
PWR_CHG_OTGEN
1
19
CMOUT
2
18
27
17
PWR_CHG_ACIN
BATGONE
PWR_CHG_DCIN
29
Note:ZZ.27002.F7C01
D 8
D 7
D 6
D 5
5
6
7
8
2
2
PWR_CHG_CSIP
16
15
ADP
2
PC4422
SC4D7U10V3KX-DL-GP
2
2
VDD
PU4401
26
1
PC4419
SC4D7U25V5KX-DL-GP
1
1
4
PL4401
1
10R5J-GP
PR4405
4D7R2F-GP
PWR_CHG_VDDP
2
1
1
1
2
PWR_ADP_19V_A
2
1
PWR_CHG_ACOK
E3
PR4402
2D2R3-1-U-GP
084.07380.0037
2nd = 084.03323.0037
PR4403
2
+DC_IN
PWR_CHG_VBATIN
084.07380.0037
2nd = 084.03323.0037
1
S
S
S
K
83.R2003.A8M
2ND = 083.52030.008F
PR4406
100KR2F-L1-GP
2
G
PC4420
SCD1U25V2KX-1-DL-GP
PWR_CHG_BT1_R
1
2nd = 084.03323.0037
084.07380.0037
K
A
ALL_SYS_PWRGD
1
D
2nd = 68.2R21F.10V
PWR_CHG_DCIN_R
PWR_IMVP_PWRGD
1
PC4442
DY
IND-2D2UH-447-GP
068.2R210.2351
CHGR_PSYS_IMVP
C
PC4436
SCD22U25V3KX-DL-GP
2
D
D
D
D
A
PR4404
402KR2F-GP
PU4405
084.07380.0037
AON7380-GP
2nd = 084.03323.0037
DCR=8mm~9m Ohm,
Idc=13A, Isat=16A
10.0mm x 11.5mm x 3.0mm
1
RB520S30-GP
1
SC10U25V3MX-5-GP
DC_IN_OFF
+SDC_IN
PROCHOT#_CPU
SC10U25V3MX-5-GP
6
PD4401
20200121 DVT1
Follow 15 upsell
PC4414
SC10U25V3MX-5-GP
HW_ACAVIN_NB
83.R2003.A8M
2ND = 083.52030.008F
[3,22,24,46,72]
PC4413
SC10U25V3MX-5-GP
5
19V_DCBATOUT
S
S
S
4
2
DGPUHOT#
90815-SA_James add PR4430
PC4412
SC10U25V3MX-5-GP
4
TPAD14-OP-GP
3
1
[66]
PC4411
SC10U25V3MX-5-GP
PU4403
AON7380-GP
TP4401
2N7002KDW-1-GP
75.27002.F7C
2nd = 075.27002.0E7C
PD4407
RB520S30-GP
+SDC_IN
[43,89]
PC4410
PC4417
SC1U25V2KX-4-GP
+SDC_IN
PQ4452
HW_ACAVIN_NB
[17,24,40,46]
SCD1U25V2KX-1-DL-GP
PR4464
100KR2F-L1-GP
AC_DIS
[17,46]
PC4409
1
G
From NXP ACK
[46]
PC4408
SC4D7U25V5KX-DL-GP
PC4416
SC1U25V2KX-4-GP
D
D
D
D
VCCPD_VBUS_ACK
[24,79]
DY
SC10U25V3MX-5-GP
2
PR4467
10KR2F-2-GP
PBAT_PRES#
VCCPD_VBUS_ACK
[24,43]
PC4405
PC4407
PC4415
PWR_CHG_IMON
0R0402-PAD-7-NP-GP
[74]
PC4404
SC10U25V3MX-5-GP
1 PR4494 2
SC10U25V3MX-5-GP
AD_IA
PBAT_PRES#
PC4403
PC4406
PR4423
1R2F-GP
ISL9538 AMON/BMON to EC
[24]
[24,43]
PC4402
SC10U25V3MX-5-GP
PR4422
1R2F-GP
0R0402-PAD-7-NP-GP
PWR_CHG_CSIN_R
20191223
For high limit
1 PR4465 2
PWR_ADP_19V_G
PG4402
GAP-CLOSE-PWR-3-GP
AC_DIS
PQ4451
SM2421PSANC-TRG-GP
084.02421.0031
PWR_ADP_19V_F
PG4401
PWR_CHG_CSIP_R
084.21321.0037
PWR_ADP_19V_E
G
GAP-CLOSE-PWR-3-GP
[24,43]
AC_IN#
PC4401
SC10U25V5KX-DL-GP
[17]
PR4466
100KR2F-L1-GP
SC1500P50V2KX-2-DL-GP
G
To EC
D
PC4469
PR4468
PU4415
AONR21321-GP
S 1
S 2
S 3
8 D
7 D
6 D
5 D
HW_ACAV_IN
100KR2J-1-GP
HW_ACAV_IN
2
SC10U25V3MX-5-GP
PBAT_CHG_SMBCLK
PBAT_CHG_SMBCLK
[24,64]
PR4401
D01R6F-11-GP
2
1
1
I2C form EC
2
S2
PBAT_CHG_SMBDAT
PBAT_CHG_SMBDAT
2
19V_AD+
1
EE needs check it!!
[24,43]
1
ISL9538C For Charger
OFFPAGE
[24,43]
2
1
PQ4418_3
5
1
6
PC4438
2
1
PQ4405_5
1
2
PR4497
240KR1F-GP
NTZD3154N5G-2-GP
75.03154.07C
2nd = 075.PX5D8.007C
2
2
PR4432
10KR1F-GP
3D3V_S5
TypeC_F
1
2
2
1
PR4463
0R1J-GPDY
PR4450
10KR1F-GP
3D3V_S5
<Core Design>
Wistron Corporation
PR4474
240KR1F-GP
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2
1
G1
S1
1
D1
1
PR4475
680KR1F-GP
2
D2
G2
2
4
PQ4405_6
G
3
SCD1U16V2KX-3DLGP
VCCPD_VBUS_ACK
PQ4405_2
19V_DCBATOUT
PWR_CHG_ACOK
084.03K35.0031
2nd = 84.2N022.031
PQ4405
PC4449
TypeC_F
SSM3K35AMFV-GP
PWR_CHG_ACOK
TypeC_F
A
PQ4408
MMBT3906FN3-GP-U
84.03906.010
2nd = 084.03906.0B13
1
S2
6
NTZD3154N5G-2-GP
75.03154.07C
2nd = 075.PX5D8.007C
PQ4418_6
S
SCD1U16V2KX-3DLGP
D
B
83.00355.H1F
2nd = 083.00016.0A1F
S1
1
PR4499
0R1J-GPDY
PQ4417
A PD4403_A
1SS355VMTE-17-GP
PQ4418_5
G1
2
K
4
TypeC_F
5
2
PD4404
2
1
PQ4418
3
PQ4418_2
C
PR4431
100KR1F-GP
D1
TypeC_F
E PQ4408_E
2
1
A
PQ4405_3
D2
DY
G2
PR4436
1MR1J-GP
S2
3D3V_S5
Title
Size
Custom
Date:
5
https://realschematic.com
4
3
2
1
Power (Charger_ISL9538)
Document Number
Rev
A00
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
44
of
105
5
4
3
SSID = PWR.Plane.Regulator_5V
OFFPAGE-Signal
PWR_5V_EN
PU4551
TDC=8.62A
ICCMAX=6.034A
7.2408A<OCP<9.6544A
BS
2
14
PWR_5V_VOUT
13
PWR_5V_FB
15
PWR_5V_LDO
DY
PG4562
GAP-CLOSE-PWR-3-GP
1
2
DY
LDO
2
PR4555
1KR2F-3-GP
PC4563
SC1KP50V2KX-1DLGP
1
PC4557
PC4558
PC4559
DY
PC4560 PC4561
1
PC4556
For 2cell use
PC4551
SC4D7U6D3V3KX-DLGP
21
8
2
18
074.08288.0B43
PC4564
DY
C
PWR_5V_FB
1
PR4558
499KR2F-1-GP
C
SY8288CRAC-GP
2
PR4557
499KR2F-1-GP
1
2
1
19V_DCBATOUT
7
2
GND
GND
GND
PR4556
1MR2J-1-GP
GND
1
1
EN2
2PWR_5V_FB_A
1
EN1
PC4565
SC22U6D3V3MX-1-DL-GP
11
Trace used 10 mil
SC22U6D3V3MX-1-DL-GP
OUT
68.1R510.10KIND-1D5UH-23-GP-U
2ND = 68.1R51A.10F
3rd = 068.1R510.1691
20
VCC
FF
PWR_5V_EN2
19
NC#16
2
1
LX#20
1
SC22U6D3V3MX-1-DL-GP
12
LX#19
PWR_5V_PH
SC22U6D3V3MX-1-DL-GP
PWR_5V_EN
NC#10
6
D
5V_S5
PL4502
IN#5
SC22U6D3V3MX-1-DL-GP
17
Cyntec. 6.8 x7.3 x 3.0mm
DCR: 14~15mOhm
Idc : 9A , Isat : 18A
2
SC22U6D3V3MX-1-DL-GP
PWR_5V_VCC
PC4562
SC2D2U10V3KX-1DLGP-U
1
2
16
1 PR4554 2PWR_5V_BOOT_A
0R0603-PAD-7-NP-GP
1
10
PWR_5V_BOOT
PC4553
SCD1U25V2KX-1-DL-GP
LX#6
PWR_5V_PG
1
IN#4
2
5
IN#3
1
1
2
2
4
PG
IN#2
SCD1U16V2KX-3DLGP
1
DY
3
PC4555
SC10U25V5KX-DL-GP
PC4554
SC10U25V5KX-DL-GP
DY
SCD1U25V2KX-1-DL-GP
PC4552
1
PWR_5V_PG
2
2
2
0R0402-PAD-7-NP-GP
2
1
1
3V_5V_PWRGD
PWR_5V_PG
1
PR4561
[17,25,45]
9
2
19V_DCBATOUT
PH on EE Side
2
2
0R0402-PAD-7-NP-GP
1
PR4559
2
1
SY8288C For 5V
OFFPAGE-GAP
1
3V_5V_EN
1
2
[40,45]
D
2
2
1
SCD1U25V2KX-1-DL-GP
PR4551
2
DY348KR2F-GP
EN rating 25V
EN Rising Threshold : 0.8V
Ilimt : 8A
SSID = PWR.Plane.Regulator_3D3V
1
7
8
18
21
PC4507
SC4D7U6D3V3KX-DLGP
TPS51393PRJER-GP
Place another side , make GND plan bigger
1
PC4513
DY
PC4512
DY
2
1
PC4511
2
PC4510
1
PC4509
2
68.1R510.10K
2ND = 68.1R51A.10F
3rd = 068.1R510.1691
1
1
2
GND
GND
GND
GND
PWR_3D3V_LDO
2
IND-1D5UH-23-GP-U
SC22U6D3V3MX-1-DL-GP
BOOT
PGOOD
FB
VOUT
NC#10
LDO
NC#16
1
PWR_3D3V_LDO
10
15
16
SC22U6D3V3MX-1-DL-GP
EN
ENLDO
6
19
20
SC22U6D3V3MX-1-DL-GP
1MR2J-1-GP
PR4514
12
11
PWR_3D3V_BOOT 1
PWR_3D3V_PG
9
PWR_3D3V_FB
13
14
SW#6
SW#19
SW#20
B
3D3V_S5
SC22U6D3V3MX-1-DL-GP
PWR_3D3V_EN
PWR_3D3V_EN2
VIN
VIN
VIN
VIN
Design Current : 8A
PL4501
PWR_3D3V_PH
SC22U6D3V3MX-1-DL-GP
2
2
3
4
5
PC4503
SC10U25V3MX-5-GP
PC4502
SC10U25V3MX-5-GP
PC4501
SCD1U25V2KX-1-DL-GP
PG4518
GAP-CLOSE-PWR-3-GP
1
2
2
2
0R0402-PAD-7-NP-GP
1
1
2
3V_5V_PWRGD
PU4501
PG4517
GAP-CLOSE-PWR-3-GP
1
2
1
[17,25,45]
PWR_3D3V_PG
2
PWR_DCBATOUT_3D3V
PR4562
Cyntec. 6.8 x7.3 x 3.0mm
DCR: 14~15mOhm
Idc : 9A , Isat : 18A
PC4522
SC2D2U10V3KX-1DLGP-U
1
PH on EE Side
TDC=7.11713A
ICCMAX=10.1009A
12.12108A<OCP<16.16144A
2
Vin Operating range : 4.5V~24V
Vin_Max : 26V
PG4516
GAP-CLOSE-PWR-3-GP
1
2
PC4506
SCD1U25V2KX-1-DL-GP
PWR_3D3V_BOOT 2 PR4501 1 PWR_3D3V_BOOT_A 2
1
0R0603-PAD-7-NP-GP
PWR_3D3V_VCC
1
0R0402-PAD-7-NP-GP
B
PG4515
GAP-CLOSE-PWR-3-GP
1
2
2
PWR_3D3V_EN
1
2
2
1
3V_5V_EN
PWR_DCBATOUT_3D3V
17
PR4560
[40,45]
TPS51393 For 3D3V
OFFPAGE-GAP
19V_DCBATOUT
VCC
OFFPAGE-Signal
074.51393.0A43
Close to PC4511
1
19V_DCBATOUT
PG4530
GAP-CLOSE-PWR-3-GP
1
2
PWR_3D3V_VOUT
2
PR4509
300KR2J-GP
PC4526
1
2
SC470P50V2KX-3DLGP
PWR_3D3V_FB2
PR4506
1
2
240KR2F-L-GP
1
EN rating :5.5V
EN Rising Threshold :1.5V
EN Falling Threshold : 0.4V
Trace used 10 mil
PR4508
100KR2J-1-GP
A
2
A
DY PR4505
100KR2J-1-GP
3D3V_AUX_S5
3D3V_AUX_S5
1
<Core Design>
2
PG4532
GAP-CLOSE-PWR-3-GP
PWR_3D3V_LDO
2
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
POWER (SY8288_5V/3D3V)
https://realschematic.com
Size
A2
Date:
5
4
3
2
Document Number
Rev
A00
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
45
of
105
5
4
3
2
Main Func = CPU_CORE
Close to VR IC
1
Close to VR IC
PC4626
SC1U10V2KX-1DLGP
DY
C4601
SCD1U25V2KX-1-DL-GP
1
1
1
2
PR4604
PR4605
PR4606
to
2
1
OFFPAGE
20200511(DVT2)
Remove PR4632~PR4634 to Keep away PWR_VCORE_SDIO_R
PWR_VGA_NVVDDS_LGATE1 40mil
SVID
1
1D05V_VCCST
SVID_CLK_CPU
[7]
SVID_DATA_CPU
DY
2
2
2
[7]
100R2F-L1-GP-U
56R2F-1-GP
43R2F-2-GP
D
[7]
1D05V_VCCSTG_TERM
SVID_ALERT#_CPU
D
SVID_CLK_CPU
1
SVID_ALERT#_CPU
SVID_DATA_CPU
PR4603
DY 1KR2F-3-GP
2
5V_S5
1
1
1
PR4617
1
DY
20200302(DVT1)
Change PC4609 to 0201
20200313(DVT1)
2
Change to 25V
SC330P25V1KX-GP
PC4609
1
20200221(DVT1)
changes to 90.9K
VCCCORE_SENSE
VSSCORE_SENSE
1
PR4608
CHGR_PSYS_IMVP
PWR_VCORE_IMON
PWR_VCORE_NTC
PWR_VCORE_COMP
PWR_VCORE_FB
PWR_VCORE_RTN
PWR_VCORE_ISUMN1
2
90K9R2F-GP
VCCCORE_SENSE
1
[7]
VSSCORE_SENSE
1
2
3
4
5
6
7
8
PSYS
IMON
NTC
COMP
FB
RTN
ISUMN
ISUMP
1
2
PR4620
9K31R2F-GP
ISL95869HRTZ-T-GP
074.95869.0073
24
23
22
21
20
19
18
17
PWR_VCORE_PROG1
PWR_VCORE_PROG2
PWR_VCORE_BOOT1
PWR_VCORE_UGATE1
PWR_VCORE_PHASE1
PWR_VCORE_LGATE1
PROG1
VBOOT:0V
F=750kHz
C
PC4610
SCD22U25V2KX-4-GP
1 PR4621 2 PWR_VCORE_BOOT1_N
1
2
0R0603-PAD-7-NP-GP
PWR_VCORE_VDDP
2 PR4625 1
0R0402-PAD-7-NP-GP
5V_S5
PC4625
SC1U10V2KX-1DLGP
9
10
11
12
13
14
15
16
2
2
ISEN1
ISEN2
ISEN3
FCCM
BOOT2
UGATE2
PHASE2
LGATE2
PR4616
10KR2F-2-GP
PROG1
PROG2
BOOT1
UGATE1
PHASE1
LGATE1
PWM3
VDDP
1
[7]
GND
VCORE SENSE
PU4601
PR4619
78K7R2F-GP
2
ALL_SYS_PWRGD
ALL_SYS_PWRGD
33
[17,24,40,44]
32
31
30
29
28
27
26
25
C
1
ALL_SYS_PWRGD
2
PR4602
12K1R2F-L1-GP
1
2
2
1
PC4613
SC1U10V2KX-1DLGP
PWR_VCORE_VRHOT
PWR_VCORE_SCLK
PWR_VCORE_ALERT#
PWR_VCORE_SDIO
PWR_VCORE_VDD
PWR_VCORE_VIN
PC4612
SC4700P50V2KX-1DLGP
PWR_VCORE_VR_READY
1 PR4636 2
0R0402-PAD-7-NP-GP
19V_DCBATOUT
PC4601 SCD22U25V2KX-4-GP
1
PWR_VCORE_VR_READY
2
PR4609
10KR2J-3-GP
CHGR_PSYS_IMVP
VR_ENABLE
VR_READY
VR_HOT#
SCK
ALERT#
SDA
VDD
VIN
[44] CHGR_PSYS_IMVP
20191119
check with Nakia need change
netname to PWR_VCORE_VR_READY or
not
[17,44] PWR_IMVP_PWRGD
1
PROCHOT#_CPU
PROCHOT#_CPU
0R0402-PAD-7-NP-GP
0R0402-PAD-7-NP-GP
0R0402-PAD-7-NP-GP
[3,22,24,44,72]
1
2
2
2
2
2
0R0402-PAD-7-NP-GP
3D3V_S0
PR4601
0R0402-PAD-7-NP-GP
1
2
PR4622
PR4623
PR4624
PR4607
100R2F-L1-GP-U
1
2
PROCHOT#_CPU
PR4615
1K5R2F-2-GP
2
1
1
PC4615
SCD01U25V2KX-3DLGP
2 DY 1
PR4666
0R0402-PAD-7-NP-GP
VSSCORE_SENSE
2
PR4630
11KR2F-L-GP
1
2
1
PWR_VCORE_ISUMNP_2
PR4650
NTC-10K-29-GP-U
69.60011.201
B=3370
PWR_VCORE_ISUMN
PC4603
SCD01U25V2KX-3DLGP
20200212
Change to 0.1u 25V
PR4626
100R2F-L1-GP-U
2
1
A
SC330P50V2KX-3-DL-GP
PC4605
SC330P50V2KX-3-DL-GP
PC4638
2
1
PC4602
2
1
PC4616
2
3K48R2F-GP
1 PR4629 2PWR_VCORE_ISUMP_N
0R0402-PAD-7-NP-GP
2
2
PR4627
511R2F-2-GP
1
2
1V_CPU_CORE
PWR_VCORE_FB3
PR4628
1
1
SC2200P50V2KX-2DLGP
2
1 PR4665 2
0R0402-PAD-7-NP-GP
PWR_VCORE_ISUMN_N
PR4653
2K61R2F-1-GP
1
1
2
2
PR4640
100R2F-L1-GP-U
1
2
PC4604
SC820P50V2KX-1-DL-GP
2
1PWR_VCORE_FB2
1
1
1
2
PWR_VCORE_FB4
PR4667
0R0402-PAD-7-NP-GP
2
SCD1U16V2KX-3DLGP
DY
1
PC4618
SCD022U16V2KX-3DLGP
PC4606
SC330P50V2KX-3-DL-GP
PC4623
VCCCORE_SENSE
PC4614
SCD022U16V2KX-3DLGP
DY
PWR_VCORE_ISUMP
PR4612
392R2F-GP
SCD022U16V2KX-3DLGP
PC4607
PR4613
2K87R2F-1-GP
PR4614
2KR2F-3-GP
SCD01U25V2KX-3DLGP
2
PWR_VCORE_ISEN2
PWR_VCORE_ISEN1
2
PWR_VCORE_ISUMN
1PWR_VCORE_FB1
PWR_VCORE_ISUMP
PR4668
2
PWR_VCORE_ISUMN
B
DY 0R1J-GP
2
PWR_VCORE_ISUMP
[47]
1
[47]
PWR_VCORE_ISEN1
1
PWR_VCORE_ISEN1
PC4608
2
[47]
PWR_VCORE_ISEN2
PWR_VCORE_COMP_N
PWR_VCORE_ISEN2
SC82P50V2JN-3-DL-GP
[47]
1 PR4611 2 PWR_VCORE_BOOT2_N 1
2
0R0603-PAD-7-NP-GP
PC4611
SCD22U25V2KX-4-GP
5V_S5
1
PWR_VCORE_LGATE2
2
2
PWR_VCORE_PHASE2
1
PWR_VCORE_LGATE2
2
[47]
1
PWR_VCORE_PHASE2
20200221(DVT1)
changes to 2K
20200227(DVT1)
change back to1.3K
20200522(DVT2)
changes to 1.5K
2
PWR_VCORE_UGATE2
[47]
PR4618
2
[47]
PWR_VCORE_UGATE2
B
B=4500
1
PWR_VCORE_LGATE1
1
[47]
PWR_VCORE_LGATE1
PR4655
27K4R2F-GP
1
PWR_VCORE_PHASE1
PWR_VCORE_PHASE1
069.60012.0001
PWR_VCORE_UGATE1
NTC-470K-17-GP
[47]
2
PWR_VCORE_UGATE1
[47]
PWR_VCORE_BOOT2
PWR_VCORE_UGATE2
PWR_VCORE_PHASE2
PWR_VCORE_LGATE2
1
PWR_VCORE_NTC_N
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
POWER (95869_CPUCORE(1/3))
https://realschematic.com
Size
A2
Date:
5
4
3
2
Document Number
Rev
A00
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
46
of
105
5
4
3
2
1
Main Func = VCCIN
19V_DCBATOUT
19V_DCBATOUT
PWR_VCORE_ISEN1
[46]
PWR_VCORE_ISUMP
[46]
PWR_VCORE_ISUMN
PWR_VCORE_ISEN1
PWR_VCORE_ISUMP
PWR_VCORE_ISUMN
2
PU4701
Cyntec 6.8mmx7.6mmx3.0mm
DCR: 0.9m ohm +/-7%
Idc : 38A , Isat : 45A
PL4701
IND-D15UH-33-GP
S2
PWR_VCORE_UGATE1
1
G1
PWR_VCORE_PHASE1
2
Q1
S1/D2
3
4
19V_DCBATOUT
G2
8
Q2
D2/S1
7
D1
D2/S1
6
D1
D2/S1
5
PWR_VCORE_PHASE1
1
AOE6932-GP
PG4711
GAP-CLOSE-PWR-3-GP
2
075.06932.0A73
2nd = 075.16038.0073
2
068.R1510.1171
2nd = 068.R1510.1141
DY PR4705
2D2R6J-3-GP
D1
9
D
1V_CPU_CORE
1
[46]
PWR_VCORE_ISEN2
PWR_VCORE_LGATE1
PWR_VCORE_SNB1
PG4712
GAP-CLOSE-PWR-3-GP
2
PWR_VCORE_ISEN2
20191202
Change PL4703 PL4704 to R4701 R4702
Follow Pinehills MLK parts
20200508
Change to L4701 L4702
20200728
Change back to R4701 R4702 for Power team request
2
[46]
PWR_VCORE_LGATE2
PT4701
SE330U2D5VDM-2GP
79.3371V.2PL
2nd = 80.3371V.L01
1
1
PWR_VCORE_LGATE2
2
PWR_VCORE_PHASE2
[46]
PWR_VCORE_PHASE2
1
[46]
TGL_U42 28W
Baseline
TDC=36A
ICCMAX=55A
PWR_VCORE_UGATE2
1
PWR_VCORE_UGATE2
TC4701
ST100U25VDM-1-GP
20191202
For acoustic noice
Follow Pinehills MLK parts
20191213
For spacing using TC4701 only
20200415(DVT2)
Change to 100u
10
[46]
K
1
D
PD4701
DY
A
1
PC4706
2
1
2
1
1
2
2
PWR_VCORE_LGATE1
PC4705
PJSD24W-GP
1st = 83.PJSD2.0AF
2nd = 083.04024.0AA1
PWR_VCORE_LGATE1
PC4704
SCD1U25V2KX-1-DL-GP
[46]
PC4703
SC10U25V3MX-5-GP
PWR_VCORE_PHASE1
PC4702
PWR_VCORE_PHASE1
SC10U25V3MX-5-GP
[46]
PWR_VCORE_UGATE1
SC10U25V3MX-5-GP
PWR_VCORE_UGATE1
SC10U25V3MX-5-GP
[46]
2
1
OFFPAGE
PC4710
1
PR4721
100KR2F-L1-GP
PR4709
10R2F-L-GP
PWR_VCORE_ISEN2
PWR_VCORE_LGATE2
Cyntec 6.8mmx7.6mmx3.0mm
DCR: 0.9m ohm +/-7%
Idc : 38A , Isat : 45A
10
1
2
1
2
1
2
1
PC4718
SCD1U25V2KX-1-DL-GP
PC4715
SC10U25V3MX-5-GP
PC4716
SC10U25V3MX-5-GP
PC4714
SC10U25V3MX-5-GP
SC10U25V3MX-5-GP
2
1
19V_DCBATOUT
2
C
PR4708
3K65R2F-1-GP
PWR_VCORE_ISUMN
PC4717
PR4722
100KR2F-L1-GP
DY
2
2
C
PWR_VCORE_ISUMN_GA
1
PWR_VCORE_ISUMP
2
2
1
1
2
PWR_VCORE_ISEN1
PWR_VCORE_ISUMP_GA
DY SC1KP50V2KX-1DLGP
PU4702
4
19V_DCBATOUT
Q1
S1/D2
Q2
D2/S1
7
D1
D2/S1
6
D2/S1
5
D1
PWR_VCORE_PHASE2
DY PR4714
2D2R6J-3-GP
9
D1
B
1
AOE6932-GP
PG4713
GAP-CLOSE-PWR-3-GP
2
075.06932.0A73
2nd = 075.16038.0073
2
068.R1510.1171
2nd = 068.R1510.1141
2
3
PWR_VCORE_SNB2
B
PG4714
GAP-CLOSE-PWR-3-GP
1
1
2
8
2
PWR_VCORE_PHASE2
G2
1
G1
1
1
1V_CPU_CORE
PL4702
IND-D15UH-33-GP
S2
PWR_VCORE_UGATE2
PC4713
2
PWR_VCORE_ISUMP
1
PWR_VCORE_ISUMN_GB
1
PR4723
100KR2F-L1-GP
2
1
1
PR4715
10R2F-L-GP
2
PR4716
3K65R2F-1-GP
PR4724
100KR2F-L1-GP
DY
2
2
PWR_VCORE_ISEN2
PWR_VCORE_ISUMP_GB
DY SC1KP50V2KX-1DLGP
PWR_VCORE_ISUMN
PWR_VCORE_ISEN1
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
POWER (95829_CPUCORE(2/3))
Size
A2
Date:
5
4
3
2
Document Number
Rev
A00
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
47
of
105
5
4
3
2
1
Main Func = CPU_CORE
D
D
C
C
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A3
Date:
5
4
3
2
Document Number
Rev
A00
Saturday, August 01, 2020
Sheet
1
48
of
105
5
4
3
2
1
D
D
C
C
B
B
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
A
Title
Size
A
https://realschematic.com
(RSVD)
Document Number
Rev
MOCKINGBIRD_TGL
Date: Saturday, August 01, 2020
5
4
3
A
2
Sheet
49
of
1
A00
105
5
4
3
2
1
Main Func = VCCIN_AUX
19V_DCBATOUT
PC5009
SC1U10V2KX-1DLGP
2
1
TGL_U42 28W
Baseline
TDC=14A
ICCMAX=27A
32.4A<OCP<43.2A
K
1
2
1
1
PWR_VCCIN_AUX_PG
20
19V_DCBATOUT
11
PWR_VCCIN_AUX_UG
19V_DCBATOUT
PWR_VCCIN_AUX_EN_R
1
2
PR5005
2D2R2J-GP
16
UG
PWR_VCCIN_AUX_PG
4
PWR_VCCIN_AUX_EN
19
PH
17
18
LG
PWR_VCCIN_AUX_FSW
9
7
6
5
1
PWR_VCCIN_AUX_LG
Cyntec. 6.8 x 7.3 x 3mm
DCR: 2.5~2.8 mOhm
Idc : 23A , Isat : 40A
9
8
VID1
VID0
FSWSEL
FB
21
AGND
10KR2J-3-GP
RGND
1D8V_CPU_AUX
PL5001
1
PGND
COMP
1
7
6
5
9
2
14
FDMS3600-02-RJK0215-COLAY-GP
EN
VOUT
DY
13
PU5003
2
3
4
10
PG
PR5003
2
PWR_VCCIN_AUX_LX
8
ISENSEN
PWR_VCCIN_AUX_VID0
12
VCC
ISENSEP
PWR_VCCIN_AUX_VID1
1
PVCC
2
PWR_VCCIN_AUX_ISENP
3
PWR_VCCIN_AUX_ISENN
8
1D8V_CPU_AUX
5
PWR_VCCIN_AUX_COMP
6
PWR_VCCIN_AUX_FB
7
PWR_VCCIN_AUX_RGND
075.07321.0073
2nd = 075.34304.0073
FDMS3600-02-RJK0215-COLAY-GP
075.07321.0073
IND-D22UH-37-GP
PR5021
17K8R2F-GP
68.R2210.10V
2nd = 068.R2210.1521
PC5011
SCD1U25V2KX-1-DL-GP
2
1
PR5008
332R2F-1-GP
1
2 PWR_VCCIN_AUX_RC
PR5016
PR5022
634R2F-1-GP
1
2
0R0402-PAD-7-NP-GP
PC5010
SC1U10V2KX-1DLGP
2
C
PC5008
SC1U10V2KX-1DLGP
15
1
2 PR5018 1 PWR_VCCIN_AUX_RGND
0R0402-PAD-7-NP-GP
PWR_VCCIN_AUX_VCC
1
PR5004
10KR2J-3-GP
2
3
4
10
PR5007
100R2F-L1-GP-U
C
PT5001
SE330U2D5VDM-2GP
79.3371V.2PL
2nd = 80.3371V.L01
PR5023
NTC-10K-29-GP-U
1
2
RT6543AGQW-GP
074.06543.0073
PWR_VCCIN_AUX_FB_O
VSYS
1
CS_DIS
2
1
PR5001
2D2R2J-GP
2
1
1
1
2
PU5001
PWR_VCCIN_AUX_CS
2
VSSAUX_SENSE
2
PU5002
2 PR5017 1 PWR_VCCIN_AUX_FB_O
0R0402-PAD-7-NP-GP
1
[22]
VCCAUX_SENSE
2
[22]
1
5V_S5
3D3V_S5
BOOT
PR5002
124KR2F-GP
VCCIN_AUX SENSE
10
0R0402-PAD-7-NP-GP
1
2 PR5013 1
PWR_VCCIN_AUX_BOOT
2
VCCIN_AUX_PWRGD
2 PR5012 1 PWR_VCCIN_AUX_EN_R
0R0402-PAD-7-NP-GP
D
2
[40]
PD5001
DY
A
PWR_1D8V_PG
PR5015
2 PWR_VCCIN_AUX_VID1
0R0402-PAD-7-NP-GP
2
2
[40,53]
1
PC5013
PJSD24W-GP
1st = 83.PJSD2.0AF
2nd = 083.04024.0AA1
CORE_VID1
PC5012
SC10U25V3MX-5-GP
CORE_VID0
[22,40]
PC5007
SC10U25V3MX-5-GP
[22,40]
1 PR5014 2 PWR_VCCIN_AUX_VID0
0R0402-PAD-7-NP-GP
SC10U25V3MX-5-GP
D
PC5006
SC10U25V3MX-5-GP
VID
2
1
OFFPAGE
B=3370K
PC5003
SC2200P50V2KX-2DLGP
PWR_VCCIN_AUX_COMP_R
1
2
PR5011
10KR2F-2-GP
1
2
PC5002
SC470P50V2KX-3DLGP
PWR_VCCIN_AUX_FB_R
2
1
DY
DY
PC5004
SC22P50V2JN-4DLGP
2
1
PR5009
1K6R2F-GP
2
1
PR5010
5K62R2F-GP
2
1
B
B
PR5006
100R2F-L1-GP-U
1
1
2
2
PR5020
0R0402-PAD-7-NP-GP
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
RT6543A_VCCIN_AUX
Size
A2
Date:
5
4
3
2
Document Number
Rev
A00
Saturday, August 01, 2020
Sheet
1
50
of
105
5
4
OFFPAGE
OFFPAGE_GAP
2
1
19V_DCBATOUT
D
1
2
PC5137
DY
2
2
IND-4D7UH-352-GP
068.4R710.1111
2nd = 068.4R710.1981
5V_S5
PU5101
Cyntec. 6.6 x 7.3 x 3.0 mm
DCR: 4.8m~5.3 mOhm
Idc : 16 A , Isat : 17 A
1D2V_S3
PL5101
2
1
C
2
16
20191219
For high limit
PWR_VDDQVTT
DY
PR5110
2D2R6J-3-GP
PC5106
PC5107
PC5109
1
PWR_VDDQ_VTTREF
9
PC5113
PC5108
DY
2
6
68.R6810.20J
2nd = 068.R6810.1271
3rd = 068.R6810.1651
1
COIL-D68UH-9-GP
PWR_VDDQ_SNB
PC5127
2
PGND
PC5130
DY PC5128
DY
PR5113
PC5115
SC1500P50V2KX-2-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
put as close as PU5101 pin2
put as close as PU5101 pin6
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
0R0402-PAD-7-NP-GP
074.51486.0043
PC5110
SCD1U25V2KX-1-DL-GP
2
1
4
SCD47U10V2KX-1-GP
AGND
TPS51486RJER-GP
PWR_VDDQ_BOOTA
2
2
VTT_CNTL
1
1
VTTSNS
SLP_S4
PR5111
5D1R3F-GP
1
VTT
PGOOD
PGND_VPP
3
5
PWR_VDDQ_SENSE
2
10
PWR_VDDQ_PH
2
VDDQSNS
VLDOIN
VTTREF
VTT_CNTL
PWR_VDDQ_BOOT
17
2
11
18
1D2V_S3
TDC=9.6A
ICCMAX=6.72A
11.52A<OCP<15.36A
1
BST
VCC_5V
PR5118
1
2
0R0402-PAD-7-NP-GP
1
SIO_SLP_S4#
8
PWR_VDDQVPP_SENSE
2
1D2V_VTT_PWRGD
PWR_VDDQVPP_PH
12
PVIN_VPP
SW
PWR_VDDQ_VLDOIN 1
15
1
VPPSNS
2
13
SW_VPP
PVIN
1
7
14
2
PWR_VDDQ_VCC
1
1
1
2
2
1
2
1
2
19V_DCBATOUT
PC5136
SC10U6D3V3MX-DL-GP
C
PC5134
SC10U6D3V3MX-DL-GP
SC1U10V2KX-1DLGP
PWR_VDDQ_VLDOIN
PR5116
100KR2J-1-GP DY
PC5135
1
1 PR5117 2
0R0402-PAD-7-NP-GP
3D3V_S5
PC5126
2
1D2V_VTT_PWRGD
2
1 R5101 2
0R0402-PAD-7-NP-GP
1
PWR_VDDQ_PG
SC22U6D3V3MX-1-DL-GP
PL5102
1
SC22U6D3V3MX-1-DL-GP
PH on EE Side
[40]
1
PWR_VDDQ_V2P5
murata. 2.5 x 2.0 x 1.2 mm
DCR:240mOhm
Idc : 1.3A , Isat : 1.5 A
2
1
2
2D5V
Design Current : 0.105A
1
A
VTT_CNTL
PC5101
SC10U25V5KX-DL-GP
VTT_CNTL
[5]
PC5105
SC10U25V5KX-DL-GP
S3
PC5102
SCD1U25V2KX-1-DL-GP
DY
PD5101
PJSD24W-GP
1st = 83.PJSD2.0AF
2nd = 083.04024.0AA1
SIO_SLP_S4#
1
SIO_SLP_S4#
[17,66]
2
S5
K
D
3
VTT
Design Current : 0.42A
B
B
1D2V_S3
PWR_VDDQ_VLDOIN
PG5115
GAP-CLOSE-PWR-3-GP
1
2
VTT
0D6V_S0
PWR_VDDQVTT
1
2
PG5111
GAP-CLOSE-PWR-3-GP
A
A
<Core Design>
2D5V
2D5V_S3
Wistron Corporation
PWR_VDDQ_V2P5
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
PG5118
2
1
Title
GAP-CLOSE-PWR-3-GP
051_POWER (TPS51486R_VDDQ/VTT)
Size
Document Number
Custom
Rev
MOCKINGBIRD_TGL
Date:
5
https://realschematic.com
4
3
2
Saturday, August 01, 2020
1
Sheet
51
A00
of
105
5
4
3
2
1
SSID = PWR.Plane.Regulator_1D0V
D
D
C
C
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
POWER (AOZ2262Q_1D0V)
https://realschematic.com
Size
A3
Date:
5
4
3
2
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
52
of
A00
105
4
3
2
1
TDC=1.029A
ICCMAX=1.47A
1.764A<OCP<2.352A
PWR_1D8V_EN
PWR_1D8V_EN
PG5304
GAP-CLOSE-PWR-3-GP
2
1
20191125
Follow Upsell
C [40,50]
PWR_1D8V_PG
PWR_1D8V_PG
074.05797.0073
2nd = 074.02822.0A43
PR5304
49K9R2F-L-GP
R2
1
2
1
PC5302
PC5303
PWR_1D8V_EN
Vo=0.6x(1+R1/R2)
=0.6x(1+100/49.9)
=1.802V
PC5307
DY SC1U10V2KX-1DLGP
PG5305
GAP-CLOSE-PWR-3-GP
2
1
1
1
PWR_1D8V_FB
PC5305
2
1
DY PR5305
100KR2F-L1-GP
DY
2
[40]
R1
RT5797ALGQW-GP
2
PG5303
GAP-CLOSE-PWR-3-GP
2
1
PR5309
100KR2F-L1-GP
3D3V_S5
SC22U6D3V3MX-1-DL-GP
PWR_1D8V
D
PL5301
068.1R010.1281
IND-1UH-300-GP
PWR_1D8V_PH 1
22nd = 068.1R010.1131
PWR_1D8V_EN
SC22U6D3V3MX-1-DL-GP
1D8V_S5
NC#5
LX
EN
SGND
5
6
7
8
SC22P50V2JN-L-GP
20191112 modify
Follow Nakia change to P.40
20191120
add offpage net
SC22U6D3V3MX-1-DL-GP
PC5301
PGND
VIN
PG
FB
9
1
PWR_1D8V_VIN
PWR_1D8V_PG
PG5302
GAP-CLOSE-PWR-3-GP
1
2
1
PWR_1D8V_PG
1 PR5307 2
0R0402-PAD-7-NP-GP
4
3
2
1
2
PRIM_PWRGD
PGND
1
[24]
PWR_1D8V_VIN
2
PG5301
GAP-CLOSE-PWR-3-GP
1
2
PH on EE Side
PWR_1D8V
Chilisin. 2.5mm×2.0mmX1.2mm
DCR: 59m Ohm
Idc : 3 A , Isat : 4A
PWR_1D8V_VIN
PU5301
2
D
3D3V_S5
PR5308
10KR2J-3-GP
2
1
3D3V_S5
2
5
Main Func = 1D8V/1D2V
OFFPAGE
OFFPAGE_GAP
C
B
B
<Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
LCD&CAM&DMC&Touch
Size
B
Document Number
Date: Saturday, August 01, 2020
5
https://realschematic.com
4
3
2
Rev
MOCKINGBIRD_TGL
Sheet
1
53
A00
of
105
A
5
4
3
2
1
Main Func = 1D05V
OFFPAGE
PH on EE Side
20191119
Check with UPSELL and Nakia
follow which one
PW R_VNN_EN
VCCIN_AUX_PWRGD
D
[40]
OFFPAGE-GAP
PW R_VNN_EN
3D3V_S5
D
PR5420 1 DY
100KR2J-1-GP
PW R_VNN
1D05V_BP_PWRGD
[24,40]
2
PW R_VNN1D05V_PG
1D05V_VNN_BYPASS
PW R_VNN1D05V_PG
TDC=0.28A
PW R_VNN1D05V_PG
R5499 1
[40]
BYPASS 2
Murata. 2.7mm×2.2mmX1.2mm
ICCMAX=0.4A
DCR: 59m Ohm
0.48A<OCP<0.64A
Idc : 3A , Isat : 3A
PL5401
PW R_VNN
068.1R010.1281
IND-1UH-300-GP
1
BYPASS22nd = 068.1R010.1131
0R2J-2-GP
PW R_1D05V_EN
PW R_1D05V_EN
PW R_1D05V
1D05V_S5_BYPASS
PU5401
PW R_VNN1D05V_VID1 13
2SCD1U25V2KX-1-DL-GPPW R_VNN1D05V_BOOTA
BYPASS
2SCD1U25V2KX-1-DL-GPPW R_VNN1D05V_BOOTB
BYPASS
2
3
VIN1
VIN2
VID1
LX1
BYPASS
LX2
VOUT2
VOUT1
BOOT1
BOOT2
AGND
PW R_VNN1D05V_PHA
PW R_VNN1D05V_PHB
5
PW R_VNN1D05V_FB2
16
PW R_VNN1D05V_VOUT1
PR54231
2
BYPASS
0R2F-1-GP PW R_VNN1D05V_PHB
2
BYPASS
0R2F-1-GP PW R_VNN1D05V_PHA
DY
VID2
POK
PGND
PGND
PR5419
9
12
1
APW 8743CQBI-TRG-GP
DY
2
PW R_VNN
0R0402-PAD-1-GP
PR5430
0R2J-L-GP
PC5414
PR5408
BYPASS BYPASS
DY
PC5410
PR5407
0R2J-L-GP
PC5413
TDC=0.28A
ICCMAX=0.4A
0.48A<OCP<0.64A
3D3V_S5 3D3V_S5
PR5426
10KR2F-2-GP
1
DY 2 PW R_VNN1D05V_VID1
B
C
0R2J-2-GP
BYPASS
1
074.08743.0A73
PR54011
IND-10UH-330-GP
17
2
SCD1U16V2KX-L-GP
1
4
SC22U6D3V3MX-1-DL-GP
DY 2
PW R_VNN_EN
PW R_1D05V_EN
SC22U6D3V3MX-1-DL-GP
PC5406 1
PW R_VNN1D05V_VID2 14
PW R_VNN1D05V_PG
7
Murata. 2.7mm×2.2mmX1.2mm
DCR: 460m Ohm
Idc : 0.85A , Isat : 1A
PW R_1D05V
68.1001S.10K
PL5402
2nd = 068.10010.1691
1
2
BYPASS
15
6
1
PW R_VNN1D05V_BOOTA_A PC5404 1
PW R_VNN1D05V_BOOTB_A PC5405 1
PW R_VNN1D05V_VINA 11
PW R_VNN1D05V_VINB 10
EN1
EN2
SC100P50V2JN-3GP
BYPASS
A
1 BYPASS
2
PC5403
SC4D7U25V3KX-2-GP
PD5401
PJSD24W-GP
1st = 83.PJSD2.0AF
2nd = 083.04024.0AA1
K
19V_DCBATOUT
VCC
2
1 PR5422 2 0R0402-PAD-1-GP
1 PR5410 2 0R0402-PAD-1-GP
C
8
1
PW R_VNN1D05V_VCC
1
PC5402 SC4D7U25V3KX-2-GP
1 BYPASS
2
PW R_VNN1D05V_VID1
PW R_VNN1D05V_VID1
2
PM_SLP_S3#
[40]
2
2
2D2R2F-GP
2
BYPASS2
2
PR5413 1
1
5V_S5
SC22U6D3V3MX-1-DL-GP
2 SC1U10V2KX-1DLGP
PC5401 1BYPASS
PW R_VNN1D05V_VID2
PW R_VNN1D05V_VID2
PC5412
BYPASS BYPASS
10/11 change PU5401 to APW8743C
SC22U6D3V3MX-1-DL-GP
[40]
PC5411
1
0R2J-2-GP
1
BYPASS 2
1D05V_BYPASS_CTRL
2
R5498 1
1
PH on EE Side
B
2
PR5428
BYPASSBYPASS
10KR2F-2-GP
2
PR5433
10KR2F-2-GP
1
1
PR5427
10KR2F-2-GP
1
DY 2 PW R_VNN1D05V_VID2
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
POWER(APW8738A_VNN1D05)
https://realschematic.com
Size
A3
Date:
5
4
3
2
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
54
of
A00
105
5
Main Func = LCD
4
3
2
1
INVERTER POWER
From CPU
LCD2
43
20191023 Mao Lee (EVT1)
Follow upsell change net name
add 0 ohmn for debug
Touch Panel
Sensor
Camera
DMIC
eDP_VDD_EN
L_BKLT_CTRL
From EC
PANEL_BKEN
I2C0_SDA_TS
I2C0_SCL_TS
TOUCH_REPORT_SW
TOUCH_PANEL_PD#
TOUCH_PANEL_INTR#
Touch Panel
R5566 1
R5567 1
R5568 1
R5569 1
2 0R0201-PAD-GP
2 0R0201-PAD-GP
2 0R0201-PAD-GP
2 0R0201-PAD-GP
1
SENSOR_I2C_SCL_R
SENSOR_I2C_SDA_R
GSEN_INT1_C_R
FOR TESTING
Sensor Board
DBC_PANEL_EN
Trace width = 80mil
PANEL_MONITOR
[66]
3D3V_LCDVDD_R
eDP
1
1
DBC_PANEL_EN
C5538
R5504 1
2
DY
SCD1U16V2KX-3DLGP
[24]
C5546
SC1U10V2KX-1DLGP
C5558
Display
2
3D3V_LCDVDD_S0
LCD_TST
CABLE2_OCP#
SC22U6D3V3MX-1-DL-GP
[24]
1
LCD_VCC_TEST_EN
[24]
2
[24]
CPU_I2C_SDA_TS_R
CPU_I2C_SCL_TS_R
TOUCH_REPORT_SW_R
TOUCH_PANEL_PD#_R
DMIC_CLK_EDP
DMIC_DATA_EDP
SENSOR_I2C_SCL_CON
CCD_USB20_CON_N
CCD_USB20_CON_P
SENSOR_I2C_SDA_CON
R5544
100KR2J-1-GP
DY
CCD& CAM
[20]
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SIO_SLP_S3#
20191023 Mao Lee (EVT1)
Follow Dell_CY20 change net name
TOUCH_PANEL_DET#
eDP_TX_CPU_P0
eDP_TX_CPU_N0
eDP_TX_CPU_P1
eDP_TX_CPU_N1
eDP_AUX_CPU_P
eDP_AUX_CPU_N
C5524
C5525
C5522
C5523
C5526
C5521
1
1
1
1
1
1
1
R5570
2 100R2J-2-GP DBC_EN_R
EDP_HPD_CONN
LCD_TST_C
LCD_BRIGHTNESS
BLON_OUT_C
2 0R0201-PAD-GPTOUCH_PANEL_DET#_R
2SCD1U16V2KX-3DLGP
2SCD1U16V2KX-3DLGP
2SCD1U16V2KX-3DLGP
2SCD1U16V2KX-3DLGP
2SCD1U16V2KX-3DLGP
2SCD1U16V2KX-3DLGP
3D3V_HINGE_S0
3D3V_HINGE_S0
3D3V_HINGE_S0
3D3V_HINGE_S0
1
eDP_TX_CON_P0
eDP_TX_CON_N0
eDP_TX_CON_P1
eDP_TX_CON_N1
eDP_AUX_CON_P
eDP_AUX_CON_N
SENSOR_I2C_SCL
SENSOR_I2C_SDA
GSEN_INT1_C
GSEN_INT1_C
3D3V_LCDVDD_S0
eDP_TX_CON_P0
eDP_TX_CON_N0
eDP_TX_CON_P1
eDP_TX_CON_N1
eDP_AUX_CON_P
eDP_AUX_CON_N
eDP_TX_CPU_P2 C5532
eDP_TX_CPU_N2 C5533
eDP_TX_CPU_P3 C5536
eDP_TX_CPU_N3 C5537
1HC172SCD1U16V2KX-3DLGP
1
2SCD1U16V2KX-3DLGP
1HC17
HC172SCD1U16V2KX-3DLGP
1
2SCD1U16V2KX-3DLGP
HC17
Hinge up cable protection
A
STM-CON50-GP
C
Brightness
1
I2C0_SCL_TS
I2C0_SDA_TS
1
1
DMIC_DATA_EDP
DMIC_CLK_EDP
1
1
3D3V_HINGE_S0
1
AFTP5504 AFTE14P-GP
AFTP5505 AFTE14P-GP
EC (BIST MODE)
LCD_TST
2
TOUCH_PANEL_INTR#
75.00054.A7D
2nd = 75.00054.T7D
AFTP5509 AFTE14P-GP
AFTP5510 AFTE14P-GP
K
SIO_SLP_S3#
OUT1
FLAG1
GND
FLAG2
OUT2
THERMAL_PAD
C5543
EDP_HPD_CONN
DBC_EN_R
3D3V_LCDVDD_S0
DCBATOUT_LCD
CABLE2_R_OCP#
3D3V_HINGE_R
1
1
1
1
AFTP5521 AFTE14P-GP
AFTP5522 AFTE14P-GP
AFTP5523 AFTE14P-GP
AFTP5525 AFTE14P-GP
11
G2895BLK21U-GP
074.02895.0A73
PANEL_PWRGD CIRCUIT
CABLE1_OCP#
1
CABLE2_R_OCP#
1
CABLE2_OCP#
R5527 2
0R0402-PAD-7-NP-GP
19V_DCBATOUT
R5528 2
0R0402-PAD-7-NP-GP
Q5503_B B
1
R5564 2
3D3V_LCDVDD_R
0R1206-DB-GP
3D3V_S5
Q5502
LMBT3906LT1G-1-GP
C
Q5503_C
2
DCBATOUT_LCD
3D3V_HINGE_R
84.T3906.E11
2nd = 84.T3906.I11
3rd = 084.03906.0B11
4th = 084.03906.0C11
Q5503_E
2 R5551 1
0R0402-PAD-7-NP-GP
3D3V_LCDVDD_S0
3D3V_HINGE_S0
B
LCD_TST_C
EDP_HPD_CONN
RN5503
SRN100J-3-GP
RN5502
SRN100KJ-5-GP
83.R2003.A8M
2ND = 083.52030.008F
3D3V_LCDVDD_R
CABLE1_OCP#
10
9
8
7
6
E
2
1
2
1
3D3V_S5
SC4D7U6D3V3KX-DLGP
SC1U10V2KX-1DLGP
C5542
IN1
EN1
VB
EN2
IN2
4
3
1 R5563 2
0R1206-DB-GP
R5554
10KR2F-2-GP
B
R5546
4K7R2F-GP
B
Q5505
LMBT3904LT1G-GP
1
84.T3904.H11
2nd = 84.03904.K11
84.T3906.E11
2nd = 84.T3906.I11
3rd = 084.03906.0B11
Q5505_E
2 R5550 1
0R0402-PAD-7-NP-GP
E
3D3V_S0
Gen 10 LCD-BIST
Check if 3V and B+ is power on before doing
panel self-test. It’s using for judge MB or panel
damaged.
Q5501 4th = 084.03906.0C11
LMBT3906LT1G-1-GP
C
Q5504_B B
1
2
2
2
1
C5530
RB520S30-GP
R5552
200KR2F-L-GP
83.R2003.A8M
2ND = 083.52030.008F
2020/02/29:swap EL5501
1
2
CCD_USB20_CON_N
CCD_USB20_P
4
3
CCD_USB20_CON_P
1
2
ED5502
DY
I/O3
2
1
84.T3904.H11
2nd = 084.03904.0I11
3rd = 084.03904.0H11
4th = 84.03904.T11
4
3
3
4
DMIC_SCL_CODEC
DMIC_SDA_CODEC
AZC099-04S-2-GP
075.09904.0A7C
C5553
C5554
RN5504
SRN33J-5-GP-U
<Core Design>
DY_DMICtoCODEC
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
LCD&CAM&DMC&Touch
Size
Document Number
Custom
4
3
2
Rev
MOCKINGBIRD_TGL
Date:
5
A
DMIC_PCH_CLK_Q
DMIC_PCH_DATA_Q
5
4
1
I/O2
DMIC_CLK_EDP
DMIC_DATA_EDP
2
https://realschematic.com
VDD
5V_S0
2
DMIC_PCH_CLK_Q
DMIC_PCH_DATA_Q
GND
6
SC33P50V2JN-3DLGP
DMIC_SCL_CODEC
DMIC_SDA_CODEC
[19]
[19]
3
I/O4
SC33P50V2JN-3DLGP
[27]
[27]
2
I/O1
1
1
Q5504
LMBT3904LT1G-GP
SRN33J-5-GP-U
RN5505
FILTER-4P-132-GP
CCD_USB20_N
CCD_USB20_P
B
2020/02/29:swap RN5505
EL5501
CCD_USB20_N
68.02002.061
2nd = 068.09002.2001
[16]
[16]
C
LCDVDD_PG
C5535
SC2200P50V2KX-2DLGP
E
C5552
DY
LCDVDD_PWRGD
2
1
DY
SCD1U16V2KX-3DLGP
1
Main Func = CAMERA
1
1
2
C5556
C5551
2
1
2
2
1
1
2
1
1
2
2
DY
SC10U6D3V3MX-DL-GP
DY
SC4D7U6D3V3KX-DLGP
C5555
SCD1U16V2KX-3DLGP
C5550
DY
SC33P50V2JN-3GP
DY
SC4D7U6D3V3KX-DLGP
SC10U6D3V3MX-DL-GP
SCD1U16V2KX-3DLGP
A
C5549
C5559
K
1
3D3V_HINGE_S0
R5561
4K7R2F-GP
D5505
A
SCD1U25V2KX-1-DL-GP
C5548
R5553
10KR2F-2-GP
3D3V_LCDVDD_S0
3D3V_HINGE_S0
1
3D3V_HINGE_S0
3D3V_HINGE_S0
Q5504_C
TOUCH PANEL POWER
SENSOR POWER
2
CAMERA POWER
2
POWER
MIC
2 R5545 1 PANEL_MONITOR
0R0402-PAD-7-NP-GP
C5529
SCD1U16V2KX-3DLGP
2
C
2
DCBATOUT_LCD_PG
C5531
SC2200P50V2KX-2DLGP
E
1
R5555
2
1
RB520S30-GP
200KR2F-L-GP
83.R2003.A8M
2ND = 083.52030.008F
PANEL_PWRGD_R
R5549
1MR2F-GP
2
SCD1U25V2KX-1-DL-GP
2
2
1
C5528
DY
2
1
1
C5545
DY
SCD1U16V2KX-3DLGP
SC1U25V3KX-1-DLGP
SC22U6D3V3MX-1-DL-GP
2
C5544
1
KDCBATOUT_LCD_PWRGD
A
DY
1
D5504
C5557
R5547
100KR2F-L1-GP
1
1
TOUCH_PANEL_PD#
2
TOUCH_PANEL_DET#
1
2
3
4
5
BLON_OUT_C
LCD_BRIGHTNESS
1
2
8
7
6
5
LCDVDD_EN
4
3
LCD_TST
EDP_HPD
LCDVDD_EN
RB520S30-GP
U5501
5V_S5
C5505
1
2
AFTP5511 AFTE14P-GP
3D3V_S5
TOUCH_REPORT_SW
RN5501
SRN100J-3-GP
PANEL_BKEN
BKLT_CTRL
1
2
3
4
LCD_VCC_TEST_EN A
D5503
BAT54C-12-GP
L_BKLT_CTRL
3
RB520S30-GP
83.R2003.A8M
2ND = 083.52030.008F
HC17
020.F1253.0050
LCDVDD_EN
K
D
2nd = 020.F0688.0050
3rd = 020.F0574.0050
D5502
20191023(EVT1)
Follow Dell_CY20 change net name
20200420(DVT2)
Change C5542 to 0402 for layout limit
I2C0_SDA_TS
I2C0_SCL_TS
SC4D7U6D3V3KX-DLGP
[3]
eDP_TX_CON_P2
eDP_TX_CON_N2
eDP_TX_CON_P3
eDP_TX_CON_N3
DCBATOUT_LCD
D5506
[20]
DBC_EN_R
EDP_HPD_CONN
LCD_TST_C
LCD_BRIGHTNESS
BLON_OUT_C
TOUCH_PANEL_DET#_R
2nd = 020.F1427.0040
3rd = 20.F2406.040
eDP_VDD_EN
[24]
HC17
020.F0847.0040
Main Func = Touch panel
[20]
R5577 1
DMIC_CLK_EDP
DMIC_DATA_EDP
2 0R1J-GP SENSOR_I2C_SCL_CON
CCD_USB20_CON_N
CCD_USB20_CON_P
2 0R1J-GP SENSOR_I2C_SDA_CON
STAR-CON40-8-GP
C
[20]
[20]
HC17
2
[20]
R5576 1
R5573 1
2 0R1J-GP SENSOR_I2C_SCL_R
HC/MKB
R5574 1 HC/MKB
2 0R1J-GP SENSOR_I2C_SDA_R
R5575 1 HC/MKB
2 0R1J-GP GSEN_INT1_C_R
HC/MKB
44
SENSOR_I2C_SDA
SENSOR_I2C_SCL
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
54
52
CPU_I2C_SDA_TS_R
CPU_I2C_SCL_TS_R
TOUCH_REPORT_SW_R
TOUCH_PANEL_PD#_R
TOUCH_PANEL_INTR#
42
[20,70]
[20,70]
HC17
2 GSEN_INT1_C_CON
0R1J-GP
1
[17,40,81]
3D3V_HINGE_S0
3D3V_HINGE_S0
3D3V_HINGE_S0
3D3V_HINGE_S0
2
[24]
HC/MKB
R5578 1
41
GSEN_INT1_C_CON
EDP_HPD
51
53
1
2 D01R5F-GP
1
R5571
DCBATOUT_LCD
LCD1
1
[4]
[4]
20200115 DVT1
For 17" Co-Layout
LCD2 only for 17". Colay with LCD1
I2C0_SCL_TS
I2C0_SDA_TS
eDP_AUX_CPU_P
eDP_AUX_CPU_N
[4]
20200121 Mao Lee (DVT)
ADD R5571 R5573 R5574 R5575 R5576 R5577 R5578
For Colay 17"
R5518
4K7R2J-2-GP
TS_I2C
2
R5517
4K7R2J-2-GP
TS_I2C
2
[4]
[4]
C5514
1
1
D
C5513
1
C5512
2
69.50007.A31
2nd = 69.50007.G71
2
eDP_TX_CPU_N3
eDP_TX_CPU_P3
POLYSW-1D1A24V-GP-U
1
[4]
[4]
1
2
eDP_TX_CPU_N2
eDP_TX_CPU_P2
3D3V_S0
DCBATOUT_LCD
F5503
2
1
[4]
[4]
19V_DCBATOUT
2
eDP_TX_CPU_N1
eDP_TX_CPU_P1
SC10U25V5KX-DL-GP
[4]
[4]
SC1KP50V2KX-1DLGP
eDP_TX_CPU_N0
eDP_TX_CPU_P0
SCD1U25V2KX-1-DL-GP
[4]
[4]
Saturday, August 01, 2020
1
Sheet
55
A00
of
105
5
4
3
2
1
Main Func = CRT
D
D
C
C
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CRT(Reserved)
https://realschematic.com
Size
A3
Date:
5
4
3
2
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
56
A00
of
105
5
4
3
2
1
SSID = HDMI Level Shifter/Connector
1
1
2 SCD1U16V2KX-3DLGP
2 SCD1U16V2KX-3DLGP
HDMI_DDI_TX_CON_N3
HDMI_DDI_TX_CON_P3
C5705
C5703
1
1
2 SCD1U16V2KX-3DLGP
2 SCD1U16V2KX-3DLGP
HDMI_DDI_TX_CON_N0
HDMI_DDI_TX_CON_P0
F5701
POLYSW-1D1A6V-9-GP-U
5V_S0
HDMI_DDI_TX_CON_N0
1
2
2ND = 69.50011.081
HDMI_DDI_TX_N1
HDMI_DDI_TX_P1
C5707
C5706
1
1
2 SCD1U16V2KX-3DLGP
2 SCD1U16V2KX-3DLGP
HDMI_DDI_TX_CON_N1
HDMI_DDI_TX_CON_P1
HDMI_DDI_TX_N2
HDMI_DDI_TX_P2
C5708
C5709
1
1
2 SCD1U16V2KX-3DLGP
2 SCD1U16V2KX-3DLGP
HDMI_DDI_TX_CON_N2
HDMI_DDI_TX_CON_P2
HDMI_DDI_TX_CON_P0
CPU_DPB_CTRL_DATA
5V_S0
HDMI_DDI_TX_CON_N1
ER5702
180R2J-1-GP
HDMI CONN
5V_HDMI
HDMI_PLL_GND
HDMI1
20191218
For EMC required
18
+5V_POWER
HDMI_DDI_TX_CON_P1
1
2
1
A
A
HDMI_DDI_TX_CON_N2
D5702
RB520S30-GP
ER5703
180R2J-1-GP
HDMI_DDI_TX_CON_P0
HDMI_DDI_TX_CON_N0
HDMI_DDI_TX_CON_P1
HDMI_DDI_TX_CON_N1
HDMI_DDI_TX_CON_P2
HDMI_DDI_TX_CON_N2
7
9
4
6
1
3
TMDS_DATA0+
TMDS_DATA0TMDS_DATA1+
TMDS_DATA1TMDS_DATA2+
TMDS_DATA2-
8
5
2
SCL
SDA
CEC
DDC/CEC_GROUNG
HOT_PLUG_DETECT
RESERVED#14
TMDS_DATA0_SHIELD
TMDS_DATA1_SHIELD
TMDS_DATA2_SHIELD
11
10
12
HDMI_DDI_TX_CON_P3
HDMI_DDI_TX_CON_N3
2
83.R2003.A8M
2ND = 083.52030.008F
K
K
D5701
RB520S30-GP
83.R2003.A8M
2ND = 083.52030.008F
SCD1U16V2KX-3DLGP
C5702
PJE8408-R1-00001-GP
084.08408.0031
2nd = 084.00138.0E31
SCD1U16V2KX-3DLGP
EC5711
5V_S0
Q5701
1
D
470R2F-GP
470R2F-GP
470R2F-GP
470R2F-GP
470R2F-GP
470R2F-GP
470R2F-GP
470R2F-GP
2
S
2
2
2
2
2
2
2
2
1
R5705 1
R5759 1
R5773 1
R5774 1
R5775 1
R5776 1
R5777 1
R5778 1
G
CPU_DISP_HPDB
D
20191122
Follow Nakia
20191127
For High limit
change back to follow ICL
CPU_DPB_CTRL_CLK
[4]
5V_HDMI
69.48001.081
20200420(DVT2)
Change to 180R
2
[4]
C5701
C5704
HDMI_DDI_TX_N0
HDMI_DDI_TX_P0
ER5701
180R2J-1-GP
D
[4]
HDMI_DDI_TX_N3
HDMI_DDI_TX_P3
1
HDMI_DDI_TX_N0
HDMI_DDI_TX_P0
HDMI_DDI_TX_N1
HDMI_DDI_TX_P1
HDMI_DDI_TX_N2
HDMI_DDI_TX_P2
HDMI_DDI_TX_N3
HDMI_DDI_TX_P3
2
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
TMDS_CLOCK_SHIELD
TMDS_CLOCK+
HDMI
TMDS_CLOCK(A_Type)
GND
GND
GND
GND
HDMI_SCL_CON
HDMI_SDA_CON
15
16
13
17
19
14
20
21
22
23
HDMI_DDI_TX_CON_P2
4
HDMI_SCL_CON
E
1 R5712 2 HDMI_HPD_E
0R0402-PAD-7-NP-GP
CPU_DISP_HPDB
2
Part Reference = Q5702
3
1
CPU_DPB_CTRL_CLK
Q5703
LMBT3904LT1G-GP
B HDMI_HPD_B R5710 1
HDMI_DDI_TX_CON_P3
CPU_DPB_CTRL_DATA
R5711
200KR2F-L-GP
2
1
2
6
Note:ZZ.27002.F7C01
R5709
5
2 150KR2F-L-GP HDMI_DET_CON
84.T3904.H11
2nd = 084.03904.0I11
3rd = 084.03904.0H11
4th
= 84.03904.T11
100KR2J-1-GP
1
1
ER5704
180R2J-1-GP
1
2
RN5702
SRN2K2J-1-GP
C
2
HDMI_DDI_TX_CON_N3
4
3
3D3V_S0
022.10025.0651
2nd = 022.10025.0701
3rd = 022.10025.0711
3D3V_S0
C
HDMI_SCL_R
HDMI_SDA_R
SKT-HDMI23-235-GP
C
2N7002KDW-1-GP
75.27002.F7C
2nd = 075.27002.0E7C
HDMI_SDA_CON
EMI Request:
1
1
ED5714
2
2
2
2
2
2
1
1
1
1
2
2
2
2
1
1
1
1
1
083.5V0H1.00AF
083.5V0H1.00AF
2nd = 083.58017.00AF
2nd = 083.58017.00AF
B
PESD5V0H1BSFYL-GP-U1
ED5713
PESD5V0H1BSFYL-GP-U1
2
HDMI_SDA_CON
HDMI_SCL_CON
083.5V0H1.00AF
2nd = 083.58017.00AF
2nd = 083.58017.00AF
ED5712
PESD5V0H1BSFYL-GP-U1
083.5V0H1.00AF 083.5V0H1.00AF
2nd = 083.58017.00AF
2nd = 083.58017.00AF
ED5711
PESD5V0H1BSFYL-GP-U1
ED5710
PESD5V0H1BSFYL-GP-U1
083.5V0H1.00AF
HDMI_DET_CON
HDMI_DDI_TX_CON_N3
HDMI_DDI_TX_CON_P3
ED5709
PESD5V0H1BSFYL-GP-U1
083.5V0H1.00AF
2nd = 083.58017.00AF
2nd = 083.58017.00AF
HDMI_DDI_TX_CON_N2
083.5V0H1.00AF
ED5708
PESD5V0H1BSFYL-GP-U1
2nd = 083.58017.00AF
HDMI_DDI_TX_CON_P2
083.5V0H1.00AF
2nd = 083.58017.00AF
ED5707
PESD5V0H1BSFYL-GP-U1
083.5V0H1.00AF
ED5706
PESD5V0H1BSFYL-GP-U1
ED5705
PESD5V0H1BSFYL-GP-U1
083.5V0H1.00AF
PESD5V0H1BSFYL-GP-U1
ED5704
HDMI_DDI_TX_CON_N1
HDMI_DDI_TX_CON_P1
HDMI_DDI_TX_CON_N0
HDMI_DDI_TX_CON_P0
B
2nd = 083.58017.00AF
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
HDMI
Size
Custom
Date:
5
4
3
2
Document Number
Rev
A00
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
57
of
105
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
A
A
Title
(Reserved)
Size
A4
https://realschematic.com
Document Number
Date: Saturday, August 01, 2020
5
4
3
Rev
MOCKINGBIRD_TGL
2
Sheet
A00
58
of
1
105
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
A
A
Title
(Reserved)
Size
A4
https://realschematic.com
Document Number
Date: Saturday, August 01, 2020
5
4
3
Rev
MOCKINGBIRD_TGL
2
Sheet
A00
59
of
1
105
5
4
3
2
1
Main Func = HDD
E
E
D
D
C
C
B
B
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
A
A
Title
SATA IF_HDD/ODD
Size
A4
https://realschematic.com
Document Number
Date:
5
4
3
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
2
60
of
1
A00
105
5
4
3
Main Func = WLAN
2
3D3V_S5
PCIE
1
3D3V_W LAN
3D3V_W LAN
[18]
[18]
W IFI_RF_EN_R
2 R6144 1
0R0402-PAD-7-NP-GP
W LAN_RF_DIS#
W LAN_CLK_CPU_N
W LAN_CLK_CPU_P
1
1
3D3V_W LAN
AFTP6101
AFTP6105
AFTP6106
AFTP6107
AFTP6108
AFTP6109
AFTP6110
AFTP6111
1 3D3V_W LAN
1 CLK_PCIE_W LAN_REQ#
1 W IFI_RF_EN_R
1 BLUETOOTH_EN_R
1 PCH_PLTRST#
1 BT_USB20_CON_N
1 BT_USB20_CON_P
1 JIO3_PCIE_W AKE#
D
1
CLK_PCIE_W LAN_REQ#
2
2
2
PCIE_CLK
C6109
SCD1U16V2KX-3DLGP
D
SC10U6D3V3MX-DL-GP
R6145
10KR2J-3-GP
W LAN_PCIE_RX_N
W LAN_PCIE_RX_P
C6106
2
1
1.1A
C6110
SCD1U16V2KX-3DLGP
[16]
[16]
W LAN_PCIE_TX_N
W LAN_PCIE_TX_P
1
[16]
[16]
[18]
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
1 R6140 2
0R0805-PAD-NP-GP
R6146
10KR2J-3-GP
2
USB2.0
BT_RADIO_DIS#
[16] BT_USB20_P
[16] BT_USB20_N
BLUETOOTH_EN_R
2 R6143 1
0R0402-PAD-7-NP-GP
Single end
[19]
C
BT_RADIO_DIS#
[16] W LAN_RF_DIS#
[17,63,66,71,76,91]
PCH_PLTRST#
[18,24] SUSCLK
3D3V_W LAN
Debug
CLKIN_XTAL_LCP_R
2 R6106 1
DY
10KR2J-3-GP
Power EN (Madesimo)
R6135 1
SUSCLK
[21]
[21]
CNV_BRI_DT_R
CNV_RGI_DT_R
[21]
[21]
CLKREQ_CNV
CNV_RF_RESET#
W IFI_RF_EN_R
BLUETOOTH_EN_R
PCH_PLTRST#
2 33R2J-2-GP SUSCLK_W LAN
CNV_RGI_RSP
R6109 1
2 49D9R2F-GP
CNV_BRI_DT_R
CNV_RGI_RSP_R
CNV_RGI_DT_R
CNV_BRI_RSP
R6118 1
2 49D9R2F-GP
CNV_BRI_RSP_R
B
1
BT_PCMOUT_CLKREQ0_R
BT_PCMFRM_CRF_RST_N
3D3V_W LAN
1
CNV_RF_RESET#
R6141
233R2J-2-GP
R6142
233R2J-2-GP
1
CNV_W T_DN0
CNV_W T_DP0
CNV_W T_DN1
CNV_W T_DP1
CNV_W T_CLKN
CNV_W T_CLKP
1
R6134
75KR2F-GP
R6133
[21]
[21]
[21]
[21]
[21]
[21]
[21]
[21]
A
[24]
2
DY 71K5R2F-1-GP
2
[21]
[21]
[21]
[21]
[21]
[21]
CLKREQ_CNV
CNV_W R_DN0
CNV_W R_DP0
CNV_W R_DN1
CNV_W R_DP1
CNV_W R_CLKN
CNV_W R_CLKP
W LAN1
76
74
72
70
68
66
64
62
60
58
56
54
52
50
48
46
44
42
40
38
36
34
32
22
20
18
16
14
12
10
8
6
4
2
NP2
C
76
3_3VAUX
3_3VAUX
RESERVED#70
RESERVED#68
RESERVED#66
GPIO0_NFC_RESET#/MGPIO7
NFC_I2C_IRQ/MGPIO5
NFC_I2C_SM_CLK
NFC_I2C_SM_DATA
W_DISABLE#1
RESERVED#54/W_DISABLE#2
PERST0#
SUSCLK_32KHZ
COEX1
COEX2
COEX3
CLINK_CLK
CLINK_DATA
CLINK_RESET
UART_CTS
UART_RTS
UART_TX
UART_RX
UART_WAKE
GND
LED#2
PCM_OUT
PCM_IN
PCM_SYNC
PCM_CLK
LED#1
3_3VAUX
3_3VAUX
77
GND
RESERVED#73
RESERVED#71
GND
RESERVED#67/2ND_LANE_PERN1
RESERVED#65/2ND_LANE_PERP1
GND
RESERVED#61/2ND_LANE_PETN1
RESERVED#59/2ND_LANE_PETP1
GND
PEWAKE0#
CLKREQ0#
GND
REFCLKN0
REFCLKP0
GND
PERN0
PERP0
GND
PETN0
PETP0
GND
NGFF_KEY_E_75P
NP2
SDIO_RESET
SDIO_WAKE
SDIO_DAT3
SDIO_DAT2
SDIO_DAT1
SDIO_DAT0
SDIO_CMD
SDIO_CLK
GND
USB_DUSB_D+
GND
NP1
77
75
73
71
69
67
65
63
61
59
57
55
53
51
49
47
45
43
41
39
37
35
33
23
21
19
17
15
13
11
9
7
5
3
1
CNV_W T_CLKP
CNV_W T_CLKN
CNV_W T_DP0
CNV_W T_DN0
CNV_W T_DP1
CNV_W T_DN1
JIO3_PCIE_W AKE#
CLK_PCIE_W LAN_REQ#
W LAN_CLK_CPU_N
W LAN_CLK_CPU_P
W LAN_PCIE_RX_N
W LAN_PCIE_RX_P
W LAN_PCIE_TX_CON_N
W LAN_PCIE_TX_CON_P
C6107 1
C6108 1
2 SCD1U16V2KX-3DLGP
2 SCD1U16V2KX-3DLGP
W LAN_PCIE_TX_N
W LAN_PCIE_TX_P
CNV_W R_CLKP
CNV_W R_CLKN
B
CNV_W R_DP0
CNV_W R_DN0
CNV_W R_DP1
CNV_W R_DN1
BT_USB20_CON_N
BT_USB20_CON_P
20200722
Remove EL6101
NP1
BT_USB20_CON_P
BT_USB20_P
1 R6111 2
0R0402-PAD-7-NP-GP
SKT-NGFF75P-164-GP
062.10003.0B11
2nd = 062.10007.0371
3rd = 062.10007.0511
CNV_BRI_RSP
CNV_RGI_RSP
BT_USB20_CON_N
JIO3_PCIE_W AKE#
<Core Design>
1 R6110 2
0R0402-PAD-7-NP-GP
BT_USB20_N
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A3
Date:
5
4
3
2
NGFF_WLAN CONN
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
A00
61
of
105
5
4
3
2
1
Main Func = WWAN
D
D
C
C
B
B
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
A
A
Title
WWAN
Size
A4
https://realschematic.com
Document Number
Rev
MOCKINGBIRD_TGL
Date: Saturday, August 01, 2020
5
4
3
2
Sheet
62
of
1
A00
105
5
4
3
2
1
Main Func = M.2 SSD
3D3V_SSD1
3D3V_S0
1
1
[18] SSD_CLK_CPU_P
[18] SSD_CLK_CPU_N
SSD_PCIE_RX_N0
SSD_PCIE_RX_P0
[16]
[16]
SSD_PCIE_TX_P3
SSD_PCIE_TX_N3
[16]
[16]
[16]
[16]
[16]
[16]
[16]
[16]
3D3V_SSD1
3D3V_SSD1
SSD_PCIE_TX_P2
SSD_PCIE_TX_N2
SSD_PCIE_RX_P2
SSD_PCIE_RX_N2
SSD_PCIE_TX_P1
SSD_PCIE_TX_N1
SSD_PCIE_RX_P1
SSD_PCIE_RX_N1
[24]
SSD1
10/9 SSD1 PCIE from CPU, not have port to detect SATA, need remove SATA function? such as DEVSLP, PEDET?
R6353
SSD_PCIE_RX_P3
SSD_PCIE_RX_N3
[64]
1
SSD_PCIE_TX_P0
SSD_PCIE_TX_N0
[16]
[16]
[16]
[16]
D
SSD M.2 CONN
M2_PCIE_LED#
SSD_SCP#
3D3V_SSD1
C
NP2
76
74
72
70
68
58
56
54
SSD_CLKREQ_CPU_N
52
PCH_PLTRST#
50
48
46
44
42
40
38
36
34
32
30
28
26
3D3V_SSD1
24
22
20
18
16
14
12
M2_PCIE_LED# R6354
M2_PCIE_LED#_R 10
1 0R0402-PAD-7-NP-GP
2
SSD_SCP#
SSD_SCP1#
8
1
2
R6356
6
0R0402-PAD-7-NP-GP
4
2
NP2
76
3_3VAUX
3_3VAUX
3_3VAUX
SUSCLK_32KHZ
NC#58
NC#56
PEWAKE#/NC#54
CLKREQ#/NC#52
PERST#/NC#50
NC#48
NC#46
NC#44
NC#42
NC#40
DEVSLP
NC#36
NC#34
NC#32
NC#30
NC#28
NC#26
NC#24
NC#22
NC#20
3_3VAUX
3_3VAUX
3_3VAUX
3_3VAUX
DAS/DSS#
NC#8
NC#6
3_3VAUX
3_3VAUX
NP1
77
GND
GND
GND
PEDET(OC_PCIE/GND_SATA)
NC#67
GND
REFCLKP
REFCLKN
GND
D_PERP0/SATA_A+/H_PETP0
D_PERN0/SATA_A-/H_PETN0
GND
D_PETP0/SATA_B-/H_PERP0
D_PETN0/SATA_B+/H_PERN0
GND
D_PERP1/H_PETP1
D_PERN1/H_PETN1
GND
D_PETP1/H_PERP1
D_PETN1/H_PERN1
GND
D_PERP2/H_PETP2
D_PERN2/H_PETN2
GND
D_PETN2/H_PERP2
D_PETP2/H_PERN2
GND
D_PERP3/H_PETP3
D_PERN3/H_PETN3
GND
D_PETN3/H_PERP3
D_PETP3/H_PERN3
GND
GND
NGFF_KEY_M 75P
NP1
77
75
73
71
69
67
57
55
53
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
MKB100KR2J-1-GP
2
[16]
[16]
2
C6341MKB C6340
MKB
2
1
1
MKB
2
2
1
2
1
2
2
DY
SC10U6D3V3MX-DL-GP
DY
SC10U6D3V3MX-DL-GP
D
DY
C6334
SCD1U16V2KX-3DLGP
DY
C6348
SCD047U25V2KX-4-GP
PCH_PLTRST#
C6338
SCD047U25V2KX-4-GP
SSD_CLKREQ_CPU_N
C6347
SC33P50V2JN-3DLGP
C6336
SC33P50V2JN-3DLGP
[18]
[17,61,66,71,76,91]
1
1 R6355 2
0R0805-PAD-NP-GP
PCIE:1 SATA:0
20191028 Mao Lee (EVT1)
For PCIE only
M2_SSD_PEDET
SSD_CLK_CPU_P
SSD_CLK_CPU_N
SSD_SATA_TX_CON_P3
SSD_SATA_TX_CON_N3
1
1
2 C6343
2 C6345
MKB
MKB
SSD_PCIE_TX_CON_P2
SSD_PCIE_TX_CON_N2
1
1
2 C6344
2 C6346
MKB
MKB
SSD_PCIE_TX_P3
SSD_PCIE_TX_N3
SCD22U10V2KX-2-GP
SCD22U10V2KX-2-GP
SSD_PCIE_RX_N3
SSD_PCIE_RX_P3
SSD_PCIE_TX_P2
SSD_PCIE_TX_N2
SCD22U10V2KX-2-GP
SCD22U10V2KX-2-GP
SSD_PCIE_RX_P2
SSD_PCIE_RX_N2
SSD_PCIE_TX_CON_P1
SSD_PCIE_TX_CON_N1
1
1
2 C6339
2 C6342
MKB
MKB
SSD_PCIE_TX_P1
SSD_PCIE_TX_N1
SCD22U10V2KX-2-GP
SCD22U10V2KX-2-GP
SSD_PCIE_RX_P1
SSD_PCIE_RX_N1
SSD_PCIE_TX_CON_P0
SSD_PCIE_TX_CON_N0
1
1
2 C6335
2 C6337
MKB
MKB
SSD_PCIE_TX_P0
SSD_PCIE_TX_N0
SCD22U10V2KX-2-GP
SCD22U10V2KX-2-GP
SSD_PCIE_RX_P0
SSD_PCIE_RX_N0
C
SKT-NGFF75P-224-GP
062.10003.0F31
2nd = 062.10003.0481
3rd = 062.10003.0F21
MKB
3D3V_S0
3D3V_SSD2
1 R6351
2
SSD_PCIE_TX_P12
SSD_PCIE_TX_N12
SSD_PCIE_RX_P12
SSD_PCIE_RX_N12
[18]
[18]
[18]
SSD2_CLK_CPU_P
SSD2_CLK_CPU_N
SSD2_CLKREQ_CPU_N
1
1
2
2
1
1
2
2
1
2
1
2
2
M2_DEVSLP1
[16]
1 R6350 2 MSATA_DEVSLP2_R
0R0402-PAD-7-NP-GP
M2_DEVSLP1
3D3V_SSD2
[16]
SSD2
3D3V_SSD2
SSD2_CLKREQ_CPU_N
PCH_PLTRST#
M2_PEDET1
A
3D3V_SSD2
SSD_SCP#
M2_PCIE_LED#
SSD_SCP2#
1 R6357 2
0R0402-PAD-7-NP-GP
3D3V_SSD2
SSD M.2 CONN
1
[16]
[16]
[16]
[16]
B
NP2
76
74
72
70
68
58
56
54
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
NP2
76
3_3VAUX
3_3VAUX
3_3VAUX
SUSCLK_32KHZ
NC#58
NC#56
PEWAKE#/NC#54
CLKREQ#/NC#52
PERST#/NC#50
NC#48
NC#46
NC#44
NC#42
NC#40
DEVSLP
NC#36
NC#34
NC#32
NC#30
NC#28
NC#26
NC#24
NC#22
NC#20
3_3VAUX
3_3VAUX
3_3VAUX
3_3VAUX
DAS/DSS#
NC#8
NC#6
3_3VAUX
3_3VAUX
NP1
77
GND
GND
GND
PEDET(OC_PCIE/GND_SATA)
NC#67
GND
REFCLKP
REFCLKN
GND
D_PERP0/SATA_A+/H_PETP0
D_PERN0/SATA_A-/H_PETN0
GND
D_PETP0/SATA_B-/H_PERP0
D_PETN0/SATA_B+/H_PERN0
GND
D_PERP1/H_PETP1
D_PERN1/H_PETN1
GND
D_PETP1/H_PERP1
D_PETN1/H_PERN1
GND
D_PERP2/H_PETP2
D_PERN2/H_PETN2
GND
D_PETN2/H_PERP2
D_PETP2/H_PERN2
GND
D_PERP3/H_PETP3
D_PERN3/H_PETN3
GND
D_PETN3/H_PERP3
D_PETP3/H_PERN3
GND
GND
NGFF_KEY_M 75P
R6349
100KR2J-1-GP
NP1
77
75
73
71
69
67
57
55
53
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
PCIE:1 SATA:0
2
SSD_PCIE_TX_P11
SSD_PCIE_TX_N11
SSD_PCIE_RX_P11
SSD_PCIE_RX_N11
C6323
SC10U6D3V3MX-DL-GP
[16]
[16]
[16]
[16]
C6333
SC10U6D3V3MX-DL-GP
SSD_PCIE_TX_P10
SSD_PCIE_TX_N10
SSD_PCIE_RX_P10
SSD_PCIE_RX_N10
DY
C6309
SCD1U16V2KX-3DLGP
[16]
[16]
[16]
[16]
DY
C6319
SCD047U25V2KX-4-GP
SSD_PCIE_TX_P9
SSD_PCIE_TX_N9
SSD_PCIE_RX_N9
SSD_PCIE_RX_P9
DY
C6332
SCD047U25V2KX-4-GP
[16]
[16]
[16]
[16]
DY
C6310
SC33P50V2JN-3DLGP
C6320
SC33P50V2JN-3DLGP
M.2 SSD2
B
1
0R0805-PAD-NP-GP
M2_PEDET1
SSD2_CLK_CPU_P
SSD2_CLK_CPU_N
SSD_SATA_TX_CON_P12
SSD_SATA_TX_CON_N12
1
1
2 C6324
2 C6325
SSD_PCIE_TX_P12
SSD_PCIE_TX_N12
SCD22U10V2KX-2-GP
SCD22U10V2KX-2-GP
SSD_PCIE_RX_N12
SSD_PCIE_RX_P12
SSD_PCIE_TX_CON_P11
SSD_PCIE_TX_CON_N11
1
1
2 C6326
2 C6327
SCD22U10V2KX-2-GP
SCD22U10V2KX-2-GP
SSD_PCIE_TX_CON_P10
SSD_PCIE_TX_CON_N10
1
1
2 C6328
2 C6329
SCD22U10V2KX-2-GP
SCD22U10V2KX-2-GP
SSD_PCIE_TX_P11
SSD_PCIE_TX_N11
SSD_PCIE_RX_P11
SSD_PCIE_RX_N11
SSD_PCIE_TX_P10
SSD_PCIE_TX_N10
SSD_PCIE_RX_P10
SSD_PCIE_RX_N10
SSD_PCIE_TX_CON_P9
SSD_PCIE_TX_CON_N9
1
1
2 C6330
2 C6331
SCD22U10V2KX-2-GP
SCD22U10V2KX-2-GP
<Core Design>
Wistron Corporation
SKT-NGFF75P-224-GP
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
062.10003.0F31
2nd = 062.10003.0481
3rd = 062.10003.0F21
https://realschematic.com
Title
Size
A2
Date:
5
4
3
A
SSD_PCIE_TX_P9
SSD_PCIE_TX_N9
SSD_PCIE_RX_P9
SSD_PCIE_RX_N9
2
mSATA
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
63
of
A00
105
5
4
3
2
1
NONE FINGER PRINT 才才才才
Main Func = Power BTN
Power button
KBC_PWRBTN#
KBC_PWRBTN#_R
83.05725.0A0
2
KBC_PWRBTN#_R
DY
D
1
1
2
DY
2
1
SC1KP50V2KX-1DLGP
[66]
ED6401
AZ5725-01FDR7G-GP
2
EC6403
KBC_PWRBTN#
GAP-OPEN
G6402
KBC_PWRBTN#_R
[24]
D
GAP-OPEN
G6401
1
2 R6419 1
0R0402-PAD-7-NP-GP
Layout note:
G6401 place to buttom
G6402 place to top
Main Func = Battery LED
Low actived from KBC GPIO
Battery LED1 (AMBER_LED)
5V_S5
1 R6408 2
0R0402-PAD-7-NP-GP
Q6403
R2
2
BATT_WHITE_LED#_Q
3
DY
CHG_AMBER_LED#
CHG_AMBER_LED#_Q
6
5
LED_MASK#
4
BATT_WHITE_LED#
[20,24]
AMBER_LED_BAT
C
LDTA144VLT1G-GP
084.00144.0B11
2nd = 84.00144.P11
2N7002KDW-1-GP
75.27002.F7C
C
E
B
R6407 1
499R2F-2-GP
1
1
LED_MASK#
2
BAT_AMBER
EC6402
DY SCD1U25V2KX-1-DL-GP
2
Q6406
CHG_AMBER_LED#
R1
[24]
LED_MASK#
Note:ZZ.27002.F7C01
[24]
C
LED2
BATT_WHITE_LED#
1 R6409 2
0R0402-PAD-7-NP-GP
1 +
Yellow
2 +
White
-
3
LED-YW-5-GP
5V_S5
083.1212A.0070
2nd = 083.00327.0070
Q6404
R2
E
B
WHITE_LED_BAT
SATA HDD LED
LOW actived from PCH GPIO
Main Func = HDD LED
3D3V_S0
DY
SATA_LED#
2
[63]
M2_PCIE_LED#
1
1
MASK_SATA_LED#
B
D6401
SATA_LED#
[20]
R6415
10KR2J-3-GP
2
DY
2
[18]
B
R6411
10KR2J-3-GP
Battery LED2 (WHITE_LED)
R6403
10KR2J-3-GP
1
MASK_SATA_LED#
BAT_WHITE
2
1D8V_S0
3D3V_S0
1
[20,24]
R6406 1
549R2F-GP
DY EC6404
SCD1U25V2KX-1-DL-GP
2
R1
C
LDTA144VLT1G-GP
084.00144.0B11
2nd = 84.00144.P11
K
SATA_LED#_D
SATA_LED#_D
A
RB520S30-GP
83.R2003.A8M
2ND = 083.52030.008F
D6402
M2_PCIE_LED#
K
A
RB520S30-GP
83.R2003.A8M
2ND = 083.52030.008F
Main Func = M-BIST
R6405
330R2J-3-GP
1DY
2
3D3V_S5
Q6407
PM_RSMRST#
[24,44]
HW_ACAV_IN
K
Q6408
LMBT3904LT1G-GP
084.05112.001K
R6413
2nd = 84.00124.K1K 150R2F-1-GP
3rd = 084.00024.0A1K
A
83.R2003.A8M
2nd = 083.52030.008F
A
Q6407_C
E
D6403
RB520S30-GP
HW_ACAV_IN
C
2
1
M_BIST
1
PM_RSMRST#
[24]
B
KBC_PWRBTN#
C6405
SC1U10V2KX-1DLGP
2
[17]
C
LMUN5112T1G-GP-U
DY
M_BIST
CHG_AMBER_LED#_Q
E
B
2
R6404
2MR2F-GP
1
1
Q6407_B
R1
2
R2
R6414
330KR2F-L-GP
84.T3904.H11
2nd = 084.03904.0I11
3rd = 084.03904.0H11
4th = 84.03904.T11
A
<Core Design>
M-BIST(Mainboard Built-In Self Test)Check if
MB is damage while press power button.
There is a LED will light up to indicate the MB
is damage by
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
LED Board&Power Button
Size
A2
Date:
5
4
3
2
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
A00
64
of
105
5
4
3
2
1
Main Func = KB
[24]
Internal Keyboard Connector
Keyboard Backlight (Reserved)
CAP_LED#_R
KB1
5V_S0
31
1
+5V_KB_BL
KB_LED_DET_C
KB_BL_CTRL#
DY
2
2
KBBL
C6501
SCD1U16V2KX-3DLGP
KBBL1
5
1
KB_LED_PWM
R6503
KB_LED_BL_DET
1
1
KSO00
KSO01
KSO02
KSO03
KSO04
KSO05
KSO06
KSO07
KSO08
KSO09
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KBBL 2
KB_LED_DET_C
51KR2J-1-GP
KB_BL_CTRL#
R6507
100KR2J-1-GP
2
3
4
6
KBBL
020.K0298.0004
2nd = 020.K0311.0004
CAP LED Control
LOW actived from KBC GPIO
ACES-CON4-90-GP-U
2
KBBL
1
CAP_LED#_R
D
KBBL
KB Backlight Power Consumption: 285mA max.
KB_LED_PWM
Q6501
PJA3402-R1-00001-GP
S
C
R6506
CAP_LED_Q
1
LDTA144VLT1G-GP
084.03402.0031
2nd = 084.02306.0031
1
R6505
100KR2J-1-GP
E
B
G
DY
5V_S0
Q6502
AFTP6565
R1
[24]
[24]
[24]
[24]
[24]
[24]
[24]
[24]
[24]
[24]
[24]
[24]
[24]
[24]
[24]
[24]
[24]
DY
R2
[24]
CAP_LED
KSO10
KSO11
KSO09
KSO14
KSO13
KSO15
KSO16
KSO12
KSO00
KSO02
KSO01
KSO03
KSO08
KSO06
KSO07
KSO04
KSO05
KSI0
KSI3
KSI1
KSI5
KSI2
KSI4
KSI6
KSI7
KB_DET#
EC6503
SCD1U16V2KX-3DLGP
D
69.48001.081
2nd = 69.50011.081
KB_DET#
KB_LED_BL_DET
SCD1U16V2KX-3DLGP
[4]
[20]
EC6501
2
1
2
1
KBBL
1
F6502
1
POLYSW-1D1A6V-9-GP-U
+5V_KB_BL
2
CAP_LED
1KR2J-1-GP
084.00144.0B11
2nd = 84.00144.P11
1
020.K0254.0030
2nd = 020.K0274.0030
3rd = 20.K0750.030
2
C
KSI[0..7]
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KB_LED_DET_C
1
KB_BL_CTRL#
1
D
ACES-CON30-29-GP
AFTP6506
[24]
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
32
AFTP6566
AFTP6567
Main Func = TPAD
TP_VDD
3D3V_S0
C
1 R6502 2
0R0402-PAD-7-NP-GP
Need to check if it is Active High or Active Low
and check if there is PH on TPAD side.
TP_VDD
TP side has pull high
TOUCHPAD_INTR# 1
R6511
2
10KR2J-3-GP
Support PTP
PS2
DAT_TP_SIO_I2C_CLK
CLK_TP_SIO_I2C_DAT
R6514 1
R65151
20R0402-PAD-7-NP-GP
20R0402-PAD-7-NP-GP
R6513 1
R6512 1
20R0402-PAD-7-NP-GP
2
0R0402-PAD-7-NP-GP
Precision Touch Pad Connector
TP_VDD
B
B
10
8
7
6
5
4
3
2
EC6502
1
I2C1_SDA_R
I2C1_SCL_R
2
2
2
PCH_I2C1_SCL_TP
PCH_I2C1_SDA_TP
TP1
TOUCHPAD_INTR#
PTP_DIS#
1
9
1
AFTP6531
PTWO-CON8-16-GP
020.K0255.0008
2nd = 020.K0151.0008
2
1
TP_VDD
C6505
SCD1U16V2KX-3DLGP
[20,66]
[20,66]
DY
I2C1_SCL_R
I2C1_SDA_R
SC33P50V2JN-3GP
CLK_TP_SIO_I2C_DAT
DAT_TP_SIO_I2C_CLK
EC6504
SC33P50V2JN-3GP
[24]
[24]
DY
1
PCH_I2C1_SCL_TP
PCH_I2C1_SDA_TP
1
I2C
Pin number Pin name
1
VDD
2
DAT(I2C)
3
4
5
CLK(I2C)
6
7
GPIO
8
CLK(PS2)
GND
ATTN
DAT(PS2)
RN6503
3
4
SRN2K2J-1-GP
I2C1_SCL_R
I2C1_SDA_R
[3,24]
[24]
TP_VDD
1
AFTP6529
I2C1_SCL_R
I2C1_SDA_R
TOUCHPAD_INTR#
PTP_DIS#
1
1
1
1
AFTP6528
AFTP6527
AFTP6525
AFTP6526
TOUCHPAD_INTR#
PTP_DIS#
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Key Board&Touch Pad
Size
A2
Date:
5
4
3
2
Document Number
Rev
A00
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
65
of
105
5
4
3
2
1
Main Func = IO Connector
USB2.0 Power
Pin define by follow layout routing
5V_S5
USB30_VCCC
U6601
[27,29]
1
2
2
LID sensor
AUD_HP1_JACK_R1
A
R6627 1
LID_CL_NB#
K
20200305(DVT1)
C6605 change from
78.10523.5FLDL to
078.47510.05FD
Q6701_G
USB3.0
C6603 1
5
R6628
6
2
1
3D3V_AUX_S5
680KR2F-GP
75.27002.F7C
2nd = 075.27002.0E7C
Q6701_G_D
A RB520S30-GP
83.R2003.A8M
2ND = 083.52030.008F
USB2_USB30_RX_N
USB2_USB30_RX_P
USB2_USB30_TX_N
USB2_USB30_TX_P
[16]
[16]
2
2N7002KDW-1-GP
2 SC1U10V2KX-1DLGP
D6602 K
PORT1
4
1
C6605
HOST_SD_WP#
[16]
[16]
[16]
[16]
Q6601
3
2 680KR2F-GP
RB520S30-GP
83.R2003.A8M
2ND = 083.52030.008F
LID_WAKE
2
SC4D7U6D3V3KX-DLGP
20191210
Follow CY20
1
SCD1U16V2KX-3DLGP
LID_POWER_ON#
D6601
LID_CL_SIO#
CRD
CARD1_USB20_N
CARD1_USB20_P
D
C6604
2 0R2J-2-GP
R6633 1
NON_LID_WAKE
AUD_SENSE
20191125
Follow CY20
[18]
USB_OC1#
074.00524.0C9F
2nd = 074.03553.007G
3rd = 074.09742.009F
AUD_RING
[27]
[16]
[16]
1
2
3
AUD_SLEEVE
AUD_HP1_JACK_L1
[29]
OUT
GND
OC#
EN#
Note:ZZ.27002.F7C01
D
IN
4
G524B2T11U-GP
1
[29]
USB_PWR_EN#
2
[27,29]
C6602S
DY
C8D2P50VCN-2-GP
SC1U10V2KX-1DLGP
AUDIO
1
5
C6601
USB2_USB20_N
USB2_USB20_P
USB CONTROL
[4]
[24,35]
20191211
Stuff EL6601 for EMC requirement
CRD
EL6601
USB_OC1#
CARD1_USB20_N
4
USB_PWR_EN#
CARD1_USB20_P
1
3
CARD1_USB20_CON_N
2
CARD1_USB20_CON_P
I/O Board Connector
IOBD1
FILTER-4P-132-GP
68.02002.061
2nd = 068.09002.2001
20191219
Follow ICL
3D3V_S0
R6601 1
SIO_SLP_S4#
HC14 2
R6602 1
0R2J-2-GP
3D3V_FPR
2 0R2J-2-GP
AUDIO
NON_HC14
1 R6608 2
0R0402-PAD-7-NP-GP
USB3.0 PORT1
USB2_USB20_N
USB2_USB20_CON_N
USB2_USB20_P
USB2_USB20_CON_P
AUD_HP1_JACK_R1 AUD_AGND
AUD_RING
AUD_RING
AUD_RING
AUD_SLEEVE
AUD_SLEEVE
AUD_SLEEVE
AUD_SENSE
AUD_HP1_JACK_L1
AUD_AGND
USB30_VCCC
C
3D3V_S5
[18]
[18]
[18]
LAN_PCIE_RX_N
LAN_PCIE_RX_P
LAN_PCIE_TX_N
LAN_PCIE_TX_P
2
[16]
[16]
[16]
[16]
20200722
Remove
EL6602
EL6603
RTC
R6615
100KR2J-1-GP
1 R6610 2
0R0402-PAD-7-NP-GP
FP
LAN_CLK_CPU_N
LAN_CLK_CPU_P
1 R6606 2
0R0402-PAD-7-NP-GP
LID_CL_NB#
KBC_PWRBTN#_R
3D3V_FPR
FPR_SCAN#
FINGER PRINTER
1
LAN
LID_CL_SIO_TAB#
HOST_SD_WP#
CLK_PCIE_LAN_REQ#
[24]
PM_LAN_ENABLE
[24]
PCIE_LAN_WAKE#
R6614 1
R6613 1
3D3V_AUX_S5
3D3V_S5
3D3V_S0
+RTC_VCC
20R0402-PAD-7-NP-GP FPR_LID_SW_R#
FPR_SSO_SW#
2
0R0402-PAD-7-NP-GP
FP1_USB20_N
FP1_USB20_CON_N
LID_CL_SIO_TAB#
FP1_USB20_P
FP1_USB20_CON_P
PCIE_LAN_WAKE#
1
2IN1
2 0R2J-2-GP
R6617 1
LAN
2 0R2J-2-GP
R6611
PCH_PLTRST#
CLK_PCIE_LAN_REQ#
PCIE_LAN_WAKE#_R
PM_LAN_ENABLE
FP1_USB20_CON_P
FP1_USB20_CON_N
USB2_USB20_CON_P
USB2_USB20_CON_N
R6607 2
0R0402-PAD-7-NP-GP
1
FP
Card Reader
[16]
[16]
FP1_USB20_N
FP1_USB20_P
[24]
[64]
LAN
FPR_SCAN#
KBC_PWRBTN#_R
[17,51]
SIO_SLP_S4#
[20,24]
LID_CL_SIO#
USB3.1 PORT1
CARD1_USB20_CON_N
CARD1_USB20_CON_P
LAN_PCIE_RX_N
LAN_PCIE_RX_P
LAN_PCIE_TX_N
LAN_PCIE_TX_P
LAN_CLK_CPU_N
LAN_CLK_CPU_P
USB2_USB30_TX_P
USB2_USB30_TX_N
USB2_USB30_RX_P
USB2_USB30_RX_N
020.F1253.0050
1
53
51
STM-CON50-GP
PCH_PLTRST#
3D3V_S0
3D3V_LCDVDD_S0
R6650
0R2J-2-GP
R6651
0R2J-2-GP
E3
R6655
0R2J-2-GP
1
R6654
0R2J-2-GP
E3
E3
2
R6643
0R2J-2-GP
E3
2
PWR_CHG_VBATIN_E3
R6644
0R2J-2-GP
E3
19V_VCOREA_E3
PWR_VCOREA_E3
19V_VCCIN_AUX_E3
R6645
0R2J-2-GP
E3
PWR_VCCIN_AUX_E3
E3
3D3V_S5_E3
3D3V_WLAN_E3
2
2
R6646
0R2J-2-GP
R6647
0R2J-2-GP
E3
R6648
0R2J-2-GP
1
E3
19V_DCBATOUT
1
R6642
0R2J-2-GP
19V_DCBATOUT
3D3V_WLAN
2
2
E3
1
1
R6641
0R2J-2-GP
1
E3
2
3D3V_S5
2
19V_DCBATOUT
2
1
R6639
0R2J-2-GP
3D3V_SSD2_E3
3D3V_SSD1_E3
19V_VDDQ_E3
PWR_VDDQ_E3
1
3D3V_SSD1_E3_R
19V_DCBATOUT
19V_DCBATOUT
2
1
PWR_CHG_VBATIN
19V_DCBATOUT
E3
19V_CHARGER_E3
E3
3D3V_SSD2_E3_R
3D3V_LCDVDD_S0_E3
19V_DCBATOUT
R6640
0R2J-2-GP
R6653
0R2J-2-GP
E3
DCBATOUT_LCD_R_E3
3D3V_LCDVDD_R_E3
E3
R6652
0R2J-2-GP
2
19V_DCBATOUT_E3
1
1
E3
2
E3
B
3D3V_SSD2
2
R6649
0R2J-2-GP
2
E3
3D3V_S0
3D3V_SSD1
1
R6638
0R2J-2-GP
1
1
19V_DCBATOUT
2
19V_DCBATOUT
2
3D3V_LCDVDD_R
1
[55]
1
PWR_CHG_VBATIN
2
PCH_I2C1_SCL_TP
PCH_I2C1_SDA_TP
[44]
1
[20,65]
[20,65]
2
B
C
2nd = 020.F0688.0050
3rd = 020.F0574.0050
LID_POWER_ON#
LID_CL_SIO_TAB#
1 3D3V_LCDVDD_R
[24]
[20,24]
[17,61,63,71,76,91]
52
54
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
A
A
E3
WLAN input
3D3V_SSD1
SSD
IN2+
IN2-
3D3V_SSD1_E3_R
3D3V_SSD2_E3_R
R6632
R6631
1
1
3D3V_SSD2
2 0R2J-2-GP
2 0R2J-2-GP
IN1+
IN1-
3D3V_SSD1_E3
3D3V_SSD2_E3
VDDQ input
VCCIN AUX input
IN7IN7+
IN8IN8+
3D3V_S5_E3
3D3V_WLAN_E3
R6656
R6657
1
1
2 0R2J-2-GP 3D3V_SSD1
2 0R2J-2-GP 3D3V_SSD2
PWR_VDDQ_E3
19V_VDDQ_E3
PWR_VCCIN_AUX_E3
19V_VCCIN_AUX_E3
3D3V_S0_E3
3D3V_SSD
PCH_I2C1_SCL_TP
1
2
3
5
7
9
11
13
15
17
19
4
6
8
10
12
14
16
18
20
19V_DCBATOUT_E3
IN4+
3D3V_LCDVDD_R_E3
DCBATOUT_LCD_R_E3
PCH_I2C1_SDA_TP
3D3V_LCDVDD_S0_E3
IN4IN3+
IN3-
PWR_CHG_VBATIN_E3
3D3V_S0
PWR_VCOREA_E3
19V_VCOREA_E3
19V_CHARGER_E3
IN6IN6+
IN5IN5+
LCD BACKLIGHT
Panel logic power
CPU Core input
<Core Design>
System power source
HRS-CONN20A-2-GP
https://realschematic.com
Wistron Corporation
20.F1450.020
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
IO Board Connector
Wistron Confidential document, Anyone can not
Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
Size
A1
Date:
5
4
3
2
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
1
Sheet
66
A00
of
105
5
4
3
2
1
Main Func = HALL SENSOR
D
D
C
C
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A3
Date:
5
4
3
2
Document Number
Reserved
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
67
A00
of
105
5
4
3
Main Func = Debug
2
1
ESPI Debug Connector
Follow upsell remove 3D3V_DB1
DBG1
3D3V_S5
ESPI
3D3V_S0
D
[18,24]
R6820 1
ESPI_CLK
ESPI_RESET#
[18,24]
ESPI_CS#
[18,24]
[18,24]
[18,24]
[18,24]
DY
ESPI_CLK
2 0R2J-2-GP
R6821 1
2 0R2J-2-GP
R6801 1
2 0R2J-2-GP
ESPI_RESET#
ESPI_CS#
ESPI_IO3
ESPI_IO2
ESPI_IO1
ESPI_IO0
3D3V_DB1
HOST_DEBUG_TX_CON
DEBUG
HOST_DEBUG_TX
ESPI_IO0
ESPI_IO1
ESPI_IO2
ESPI_IO3
UART_2_CTXD_DRXD R6802
UART_2_CRXD_DTXD R6803
DEBUG
1DEBUG2
1
2
UART_2_CTXD_DRXD_CON
UART_2_CRXD_DTXD_CON
0R2J-2-GP
0R2J-2-GP
DEBUG
2
3
4
5
6
7
8
9
10
11
12
13
14
16
DEBUG
D
20.F0765.014
[18,24]
15
1
20191119
add net name
DM-ACES-CON14-5-GP-01
ZZ.F0765.01401
20191212
3D3V_S0 Follow CY20
R6804
C
1
R6805 1
UART
[24]
DEBUG2
51KR2J-1-GP
2 51KR2J-1-GP
C
UART_2_CTXD_DRXD
UART_2_CRXD_DTXD
DEBUG
HOST_DEBUG_TX
[20]
UART_2_CTXD_DRXD
[20]
UART_2_CRXD_DTXD
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A4
Document Number
MOCKINGBIRD_TGL
Date: Saturday, August 01, 2020
5
4
3
Dubug connector
2
Sheet
68
A00
of
1
Rev
105
A
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A4
Document Number
4
3
Rev
MOCKINGBIRD_TGL
Date: Saturday, August 01, 2020
5
Reserved
2
Sheet
69
A00
of
1
105
A
5
4
3
2
1
SSID = User.interface
Mantis Accelerometer for adaptive thermal and HDD protection
D
D
3D3V_GSEN2
3D3V_S0
GSEN2_INT1_C
FFS_INT2
1
2
FFS_INT1
[19]
2
[20]
Free Fall Sensor + G Sensor
C7003
C7004
C7004 near pin9
SENSOR_I2C_SDA
SC10U6D3V3MX-DL-GP
SENSOR_I2C_SCL
[20,55]
SCD1U16V2KX-3DLGP
[20,55]
11uA
1 R7004 2
0R0402-PAD-7-NP-GP
1
[20]
3D3V_GSEN2
U7001
9
10
VDD
CS
RES
VDD_IO
INT1
INT2
3D3V_GSEN2
R7005 1
DY
SENSOR_I2C_SCL
SENSOR_I2C_SDA
2 10KR2J-3-GP
1
4
3
SCL/SPC
SDA/SDI/SDO
SDO/SA0
GSENSOR_SDO
2 R7007 1
0R0402-PAD-7-NP-GP
GND
GND
GND
2
5
GSENSOR_CS
12
11
GSEN2_INT1_C
GSEN2_INT2_C
R7006
2
1
10KR2J-3-GP
6
7
8
Note:
LNG2DMTR-GP
074.LNG2D.00BZ
-
HellCat using 8 Bits:074.LNG2D.00BZ
Mocking Bird using 12 Bits :074.LIS2D.M002
C
no via, trace, under the sensor (keep out area around 2mm)
stay away from the screw hole or metal shield soldering joints
design PCB pad based on our sensor LGA pad size (add 0.1mm)
solder stencil opening to 90% of the PCB pad size
mount the sensor near the center of mass of the NB as possible as you can
C
GSEN2_INT1_C
GSEN2_INT2_C
R7011 1
FFS_INT2
R7012 1
1
FFS_INT1
2
0R0402-PAD-7-NP-GP
2
0R0402-PAD-7-NP-GP
2
R7001 DY
1MR2J-1-GP
B
B
Note:
(1) Keep all signals are the same trace width. (included VDD, GND).
(2) No VIA under IC bottom.
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A2
Date:
5
4
3
2
Free Fall Sensor
Document Number
Sheet
1
70
Rev
A00
MOCKINGBIRD_TGL
Saturday, August 01, 2020
of
105
5
4
Main Func = TBT
BB2
BB2
SCD22U10V1KX-1-GP
SCD22U10V1KX-1-GP
USB1_TCSS_TX_C_P0
USB1_TCSS_TX_C_N0
J1
J2
USB1_TCSS_RX_P0
USB1_TCSS_RX_N0
C7105
C7102
1
1
BB22
BB
SCD22U10V1KX-1-GP
SCD22U10V1KX-1-GP
USB1_TCSS_RX_C_P0
USB1_TCSS_RX_C_N0
G1
G2
USB1_TCSS_TX_P1
USB1_TCSS_TX_N1
C7103
C7107
1
1
BB22
BB
SCD22U10V1KX-1-GP
SCD22U10V1KX-1-GP
USB1_TCSS_TX_C_P1
USB1_TCSS_TX_C_N1
C1
C2
USB1_TCSS_RX_P1
USB1_TCSS_RX_N1
C7108
C7106
1
1
BB22
BB
SCD22U10V1KX-1-GP
SCD22U10V1KX-1-GP
TBT_LSX0_TXD
TBT_LSX0_RXD
[73]
[73]
USB1_SSRX_RC_N0
USB1_SSTX_RC_N0
[73]
[73]
USB1_SSRX_RC_P0
USB1_SSTX_RC_P0
[73]
[73]
USB1_SSRX_RC_N1
USB1_SSTX_RC_P1
DY
ASSRXP2
ASSRXN2
ASSTXP2
ASSTXN2
PA_LSTX_SBU1
PA_LSRX_SBU2
PA_AUX_P
PA_AUX_N
BB
BSSTXP1
BSSTXN1
BSSRXP2
BSSRXN2
BSSTXP2
BSSTXN2
PB_SBU1
PB_SBU2
HP team on applying ,only murata
have sample can meet Intel request
J12
J11
USB1_TCSS_RX_RT_P0 R7114
USB1_TCSS_RX_RT_N0 R7115
1
1
BB
BB
2 2D2R1J-GP
2 2D2R1J-GP
USB1_SSRX_RC_P0
USB1_SSRX_RC_N0
C7141 1
C7142 1
G12
G11
USB1_TCSS_TX_RT_P0
R7120
USB1_TCSS_TX_RT_N0
R7121
1
1
BB
BB
2 2D2R1J-GP
2 2D2R1J-GP
USB1_SSTX_RC_P0
USB1_SSTX_RC_N0
C7111 1
C7112 1
C12
C11
USB1_TCSS_RX_RT_P1
R7116
USB1_TCSS_RX_RT_N1
R7117
1
1
BB
BB
2 2D2R1J-GP
2 2D2R1J-GP
USB1_SSRX_RC_P1
USB1_SSRX_RC_N1
C7143 1
C7144 1
E12
E11
USB1_TCSS_TX_RT_P1
R7129
USB1_TCSS_TX_RT_N1 R7130
1
1
BB
BB
2 2D2R1J-GP
2 2D2R1J-GP
USB1_SSTX_RC_P1
USB1_SSTX_RC_N1
C7113 1
C7114 1
M10
L10
USB1_BB_SBU1
USB1_BB_SBU2
2
BB 2 SCD33U6D3V1MX-GP
BB SCD33U6D3V1MX-GP
SCD22U10V1KX-1-GP
BB 22 SCD22U10V1KX-1-GP
BB
DY
R7197 1
U7101A
R7190 1
R7191 1
2 220KR1J-GP
2 220KR1J-GP
USB1_SSTX_CON_P1
USB1_SSTX_CON_N1
R7194 1
R7195 1
2 220KR1J-GP
2 220KR1J-GP
Follow Hellcat15 Upsell TGL
WPN
DPN
TBT
071.00TBT.0F0U
M11GX
NON_TBT
071.00TBT.0D0U
7DYVG
D
20200113 (DVT1)
Add for 8010 FW update
20200226(DVT1)
Follow Nakia
M11
R7118
BB
BB_TCP1_TEST_PWR_GOOD
2
100R1F-GP
0R1J-GP
R7171 1
R7173 1
2
2
DY
DY
TP_TCP1_ATEST_P
TP_TCP1_ATEST_N
L9
M9
XTL_25M_X1_TBT1
XTL_25M_X2_TBT1
R7111 1
R7113 1
L5
L4
BB_TCP1_RSENSE
BB_TCP1_RBIAS_1
BB
BB
DY
R7178 1
TBT_FORCE_PWR
2 0R0201-PAD-GP
2 10KR1F-GP
2 10KR1F-GP
TBT_I2C_SDA
2 2K2R2F-GP
5
3D3V_S0_TCP1
R7179 1
3D3V_SX_TCP1_D
DY
TBT_I2C_SCL
2 2K2R2F-GP
TBT_I2C_SDA
3D3V_S5
BB
MONDC
NC#A12
MONDC_SVR
B3
B11
TEST_PWR_GOOD
TEST_EN
A1
A2
Main
RESET#
2
3
3D3V_S0_TCP1
TCP_SMBUS_SDA
DY
TC_RETIMER_FORCE_PWR
XTAL_25_IN
XTAL_25_OUT
RSENSE
RBIAS
2 0R0201-PAD-GP
2 0R0201-PAD-GP
R7112 1
BB
XTL_25M_X1_TBT1_R
XTL_25M_X2_TBT1_R
X7101
2 4K75R2D-GP
2
BB
Must use Metal shielded crystal for
better noise immunity.
Recommended Crystal List:
FW2500025Z by Pericom
XRCGB25M00F3L12R0 by Murata
3
1
1
BURNSIDE-BRIDGE-GP-U1
2
3D3V_S5
4
Suggest adding GND shield across
Crystal and 18pF caps for better
RFI.
C7109
BB
XTAL-25MHZ-302-GP
SC33P25V1JN-GP
ZZ.000IC.002
C
3D3V_S0
C7110
BB SC33P25V1JN-GP
082.30005.0501
2nd = 082.30005.0C81
R7141 1
R7132 1
R7155 1
R7145 1
20191224
Follow Internal review
20200226(DVT1)
Follow Nakia
1
2
DY0R2J-2-GP
20200225(DVT1)
Change to 0402 size 20200504(DVT2)
C7115 change to common
C7115
BB SC2D2U6D3V2MX-DL-GP
1
1
R7133
R7134
2 0R0201-PAD-GP
2 0R0201-PAD-GP
2
BB_TCP1_FLASH_CS_N_R
BB_TCP1_FLASH_DO_R
BB_TCP1_FLASH_WP_N
1
2
3
4
DY
2 10KR1F-GP
DY
DY
DY
2 10KR1F-GP
2 10KR1F-GP
2 10KR1F-GP
BB_TCP1_FLASH_SHARE_EN
BB_TCP1_GPIO_12
BB_TCP1_FLASH_MSTR_SLV
R7138 1
R7158 1
R7147 1
BB
DY
DY
2 10KR1F-GP
2 10KR1F-GP
2 10KR1F-GP
R7162
4K7R1F-GP-U
R7166 1
DY
[17,61,63,66,76,91]
R7170
20KR1F-GP
PCH_PLTRST#
DY
1
2 0R1J-GP
R7167
TCP1_RETIMER_PERST_R_N
2
0R0201-PAD-GP
2
U7103
BB_TCP1_FLASH_CS_N
BB_TCP1_FLASH_DO
R7143 1
2
DY
1
1 R7198
BB_TCP1_FLASH_CS_N
BB_TCP1_FLASH_DO
BB_TCP1_FLASH_WP_N
BB_TCP1_FLASH_HOLD_N
BB_TCP1_GPIO_6
3D3V_S5_VCCPRIM
PCH_TBT_PERST#
2 2K2R1J-GP
2 2K2R1J-GP
2 3K32R1F-GP
2 3K32R1F-GP
2 10KR1F-GP
C
3D3V_SX_TCP1_D
BB
BB
BB
BB
BB
3D3V_SX_TCP1
20200225(DVT1)
Change to 0201
20200302
Change to 27p for vendor
suggestion
20200313
Change for resource shortage
20200512
Change to 33p for vendor
suggestion
3D3V_SX_TCP1_D
2
R7136 1
0R0201-PAD-GP
3D3V_SX_TCP1
1
1
1
1
R7149
10KR1F-GP
BB_RST
ATEST_P
ATEST_N
20191213
Change U7103 for High limit
R7146
10KR1F-GP
2N7002KDW-1-GP
75.27002.F7C
BB
2 0R0201-PAD-GP
0R1J-GP
R7125
R7126
R7127
R7128
TBT_I2C_SCL
1
DY
4
BB TO PCH(NON-TBT)
1
TBT_I2C_SDA
TBT_I2C_SCL
R7177 1
2
R7168 1
R7131 1
R7119 1
1
1
TEST_EDM
FUSE_VQPS_64
A11
A12
L12
DEBUG
TBT_FORCE_PWR
TCP1_RESET_N
TCP_SMBUS_SCL 6
0R1J-GP
DY
2
M12
B2
BB_I2C_SCL
BB_I2C_SDA
L11
BB_TCP1_FLASH_BUSY_N
BB_TCP1_GPIO_5
BB_TCP1_GPIO_6
TCP1_RETIMER_PERST_R_N
TCP_SMBUS_SCL
TCP_SMBUS_SDA
BB_TCP1_FLASH_SHARE_EN
BB_TCP1_FLASH_MSTR_SLV
BB_TCP1_GPIO_12
SML0_SMBCLK
SML0_SMBDATA
2 0R1J-GP
2 0R1J-GP
DY
DY
Q7101
THERMDA
0R1J-GP
20200221(DVT1)
Follow reference circuits NC _A12
RETIMER_PWREN
BB_I2C_SCL
BB_I2C_SDA
BB_I2C_PD_INT#
R7174 1
TC_RETIMER_FORCE_PWR
BB TO PCH(TBT)
TCP_SMBUS_SCL R7156 1
TCP_SMBUS_SDAR7159 1
1
TDI
TMS
TCK
TDO
POC GPIO
A3
C3
B5
C5
I2C_SCL
I2C_SDA
I2C_INT
FORCE_PWR
FLASH_BUSY#
POC_GPIO_5
POC_GPIO_6
PERST#
SMBUS_SCL
SMBUS_SDA
FLASH_SHARE_EN
FLASH_MASTER_SLAVE
POC_GPIO_12
NC_L3
C9
E7
A10
B10
A9
B9
A8
B8
A7
B7
A4
A5
A6
L3
2 TCP_SMBUS_SCL
1KR2F-3-GP
2 TCP_SMBUS_SDA
1KR2F-3-GP
2
[20]
[20]
2 TP_TCP1_THERMDA
DY
PCH_TBT_PERST#
Type-C PD
[72]
[72]
BB_TCP1_TDI
BB_TCP1_TMS
BB_TCP1_TCK
BB_TCP1_TDO
2 10KR1F-GP
2 10KR1F-GP
2 10KR1F-GP
2 10KR1F-GP
BB
BB
BB
BB
MISC &
DEBUG
EE_DI
EE_DO
EE_CS#
EE_CLK
DY
1D8V_S5
1 OF 4
FLASH
C6
B4
B6
C7
JTAG
R7103 1
R7104 1
R7105 1
R7106 1
R7169 1
[16,72]
USB1_SSRX_AR_P1
USB1_SSRX_AR_N1
Note:ZZ.27002.F7C01
BB_TCP1_FLASH_DI
BB_TCP1_FLASH_DO
BB_TCP1_FLASH_CS_N
BB_TCP1_FLASH_CLK
BB_RST
[72]
DY
R7196 1
USB1_BB_SBU1
USB1_BB_SBU2
[16,17]
2 220KR1J-GP
2 220KR1J-GP
ZZ.000IC.002
3D3V_LC_TCP1
[72]
[72]
2 220KR1J-GP
2 220KR1J-GP
R7192 1
R7193 1
BURNSIDE-BRIDGE-GP-U1
20200225(DVT1)
Remove TP7104~TP7107
SML0_SMBCLK
SML0_SMBDATA
[72]
R7188 1
R7189 1
USB1_SSTX_CON_P0
USB1_SSTX_CON_N0
R7110
Vincent
USB1_TCSS_AUX_P
USB1_TCSS_AUX_N
[18]
[18]
USB1_SSRX_AR_P0
USB1_SSRX_AR_N0
20200226(DVT1)
Remove R7107 R7108
3D3V_S0_TCP1
[4]
[4]
20191212
Follow Nakia
2
BB 2 SCD33U6D3V1MX-GP
BB SCD33U6D3V1MX-GP
SCD22U10V1KX-1-GP
BB 2
BB 2 SCD22U10V1KX-1-GP
1
USB1_SSTX_RC_N1
USB1_SSRX_RC_P1
R7109
ASSTXP1
ASSTXN1
BSSRXP1
BSSRXN1
1
2
[73]
[73]
L8
M8
1
USB1_SSRX_AR_P0
USB1_SSRX_AR_N0
USB1_SSRX_AR_P1
USB1_SSRX_AR_N1
2
20191216
Follow SPEC change to 25V
20200324(DVT2)
Change to common part 0.33u
1MR1F-GP
[73]
[73]
[73]
[73]
M7
L7
USB1_TCSS_AUX_P
USB1_TCSS_AUX_N
1MR1F-GP
USB1_SSTX_CON_P0
USB1_SSTX_CON_N0
USB1_SSTX_CON_P1
USB1_SSTX_CON_N1
USB1_TCSS_TXD_R
USB1_TCSS_RXD_R
2 0R0201-PAD-GP
2 0R0201-PAD-GP
2
D
[73]
[73]
[73]
[73]
R7101 1
R7102 1
USB1_TCSS_RX_C_P1E1
USB1_TCSS_RX_C_N1
E2
TBT PORTS
ASSRXP1
ASSRXN1
Port B - TypeC Side
1
1
Port A - Host Side
TBT_LSX0_TXD
TBT_LSX0_RXD
C7101
C7104
1
[4]
[4,15]
USB1_TCSS_TX_P0
USB1_TCSS_TX_N0
2
USB1
USB1_TCSS_TX_N0
USB1_TCSS_TX_P0
USB1_TCSS_TX_N1
USB1_TCSS_TX_P1
USB1_TCSS_RX_N0
USB1_TCSS_RX_P0
USB1_TCSS_RX_N1
USB1_TCSS_RX_P1
4 OF 4
U7101D
220nF AC cap must be placed on RX lines close to SOC side
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
3
HP team on applying, only murata have
sample can meet Intel request
CS#
DO/IO1
WP#/IO2
GND
8
7
6
5
VCC
HOLD#/IO3
CLK
DI/IO0
BB_TCP1_FLASH_HOLD_N
BB_TCP1_FLASH_CLK_R
BB_TCP1_FLASH_DI_R
R7135 1
R7137 1
BB_TCP1_FLASH_CLK
BB_TCP1_FLASH_DI
2 0R0201-PAD-GP
2 0R0201-PAD-GP
9
GND
W25Q80DVZPIG-GP
BB
072.25Q80.0B01
2nd = 072.25803.0A03
B
B
3D3V_SX_TCP1
0D9V_SVR_TCP1
U7101B
2 OF 4
3D3V_S0_TCP1
20191213
for High limit
BURNSIDE-BRIDGE-GP-U1
BB
1
1
BB
BB
3 OF 4
GND
BB
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
F12
G7
H1
H2
H11
H12
J9
K1
K2
K11
K12
VSS
VSS
VSS
BB
1
1
1
BB
2
BB
C7146
C7131
2
BB
C7130
2
BB
C7129
2
BB
J6
C7128
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
F3
F5
G5
GND
1
M2
M3
C7127
2
SVR_VSS
SVR_VSS
VCC0P9_LVR
VCC0P9_LVR_SENSE
C7126
2
VCC0P9_LC
C7125
1
2
SC2D2U6D3V2MX-DL-GP
VCC0P9_SVR_PB_ANA
VCC0P9_SVR_PB_ANA
C7124
SC18P25V1JN-2-GP
L6
M6
1
BB 2
68.1R01F.10Y
2nd = 068.1R010.1I61
B1
B12
D1
D2
D11
D12
F1
F2
F7
F9
F11
20200226(DVT1)
Follow Intel
SC47U6D3V3MX-2-GP
J3
VCC0P9_LVR_1
+VCC0P9_SVR_TCP1_PHASE
20200225(DVT1)
Change to 0402 size
20200504(DVT2)
change to Common
0D9V_SVR_TCP1
L7102
IND-1UH-257-GP
SC2D2U6D3V2MX-DL-GP
VCC0P9_LC_1
2 R7175
SC2D2U6D3V2MX-DL-GP
BB2
SC10U6D3V2MX-2-GP
L1
M1
DY
0R1J-GP
SC2D2U6D3V2MX-DL-GP
C7138 1
2 SC2D2U6D3V2MX-DL-GP
BB
BB2
SVR_IND
SVR_IND
U7101C
3D3V_A_S0_TCP1
U7101_J5 1
SC2D2U6D3V2MX-DL-GP
C7123 1
VCC0P9_SVR
VCC0P9_SVR
M4
M5
J5
J7
SC2D2U6D3V2MX-DL-GP
E9
G9
C7122 1
VCC0P9_SVR_ANA
VCC0P9_SVR_ANA
E6
SC2D2U6D3V2MX-DL-GP
E3
G3
VCC3P3_SVR
VCC3P3_SVR
NC#J5
VCC3P3A
BB
SC47U6D3V3MX-2-GP
20200324(DVT2)
C7122 change to common
VCC3P3_LC
1
1
F6
G6
C7117
BB SC2D2U6D3V2MX-DL-GP
VCC3P3_SX
2
E5
3D3V_LC_TCP1
VCC3P3_ANA
1
L2
2
+VCC3P3_ANA_TCP1
2
BB 1 C7118
SC2D2U6D3V2MX-DL-GP
Power
2
ZZ.000IC.002
BURNSIDE-BRIDGE-GP-U1
ZZ.000IC.002
3D3V_S0
20200324(DVT2)
C7135 change to common
3D3V_S5
R7172
1
DY
2 0R2J-2-GP
3D3V_S0_TCP1
3D3V_S0_TCP1
3D3V_A_S0_TCP1
20200225(DVT1)
Change to 0402 size
U7102_CT
0R0402-PAD-7-NP-GP
C7137 1
2SC220P50V2KX-3DLGP
1
20200113 (DVT1)
Follow Spec.
1
1
C7134
BB
2
1
1
1
2
2
1
2
C7133
BB
2
BB
A
<Core Design>
1
C7139
BB
BB
C7132
20191213
for High limit
3D3V_SX_TCP1
1 R7181 2
0R0603-PAD-7-NP-GP
2
https://realschematic.com
BB
SC10U6D3V2MX-2-GP
074.22975.0093
2nd = 74.03526.093
SCD1U10V1KX-DL-GP
TPS22975-GP
C7145
BB
1 R7161 2
0R0402-PAD-7-NP-GP
2
2
2
9
1
GND
1 R7123
2
BB
8
7
6
5
1
1
1
2
VOUT#8
VOUT#7
CT
GND
BB
C7140S
SC18P25V1JN-2-GP
VIN#1
VIN#2
ON
VBIAS
BB
C7121
C2D2U6D3V2MX-DL-GP
5V_S5
1
2
3
4
BB
C2D2U6D3V2MX-DL-GP
RETIMER_PWREN
3D3V_RT_TCP1_FIP
U7102
C7120S
SC2D2U6D3V2MX-DL-GP
3D3V_RT_TCP1
R7176
100KR1F-GP
SC47U6D3V3MX-2-GP
BB
SC10U6D3V2MX-2-GP
A
C7119
SC2D2U6D3V2MX-DL-GP
C7136
SC10U6D3V2MX-2-GP
1 R7180 2
0R0603-PAD-7-NP-GP
2
C7135
SC1U10V2KX-1DLGP
2
BB
20200225(DVT1)
Change to 0402 size
20200504(DVT2)
C7116 Change to common
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
BB SC2D2U6D3V2MX-DL-GP
2
1
3D3V_RT_TCP1
3D3V_S5
Title
Size
A1
Date:
5
4
3
2
EXT IO (Thunderbolt(1/3)/Type C Re-driver)
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
1
Sheet
71
of
A00
105
5
4
VDDD
1
C7212
2
1
2
1
PROCHOT#_CPU
C7211
D
SOC_OC_FAULT
[71]
BB_RST
[17]
TBT_PD_ALERT#
1 R7260
1 R7261
USB1_CON_SBU1 0R0402-PAD-7-NP-GP 2
USB1_CON_SBU2 0R0402-PAD-7-NP-GP 2
USB1_BB_SBU1 0R0402-PAD-7-NP-GP
2
USB1_BB_SBU2 0R0402-PAD-7-NP-GP
2
RETIMER_PWREN
TBT_FORCE_PWR
Type-C PD
[71]
[71]
C
[18]
[18]
23
22
18
19
USB1_USB20_CMCB_P
USB1_USB20_CMCB_N
20
21
1 R7203 SBU1
1 R7204 SBU2
1 R7205 SBU1_SYS
1 R7206 SBU2_SYS
42
43
41
40
VBUS_CSP
VBUS_CSN
39
38
PD_XRES
34
VBUS_P
VBUS_P
VBUS_P
VBUS_P
DP_SYS
DM_SYS
DP_TOP
DM_TOP
VCCD
DP_BOT
DM_BOT
VDDD
VDDIO
SBU1
SBU2
SBU1_SYS
SBU2_SYS
CSP
CSN
EC I2C
BB_I2C_SCL
BB_I2C_SDA
XRES
1 R7252 2
0R0402-PAD-7-NP-GP
SML1_SMBCLK
SML1_SMBDATA
49_THM
Q7201
1
2
UPD1_SMBDA_Q
DY
UPD1_SMBCLK_Q
6
Note:ZZ.27002.F7C01
UPD1_SMBCLK
3D3V_S5_KBC
5
3
3D3V_S5_KBC
UPD1_SMBDAT
4
2N7002KDW-1-GP
THERMAL_PAD
VSYS
V5V
I2C_SDA_SCB1/P0.2
I2C_SCL_SCB1/P0.3
I2C_INT_TBT/P0.4
SWD_CLK/P1.0
SWD_IO/P1.1
I2C_INT_EC/P1.2
UART_RX/P1.3
UART_TX/P1.4
HPD/P2.0
I2C_SDA_SCB2/P2.1
I2C_SCL_SCB2/P2.2
P2.3
P2.4
P3.0
I2C_SDA_SCB3/P3.1
I2C_SCL_SCB3/P3.2
P3.3
I2C_SCL_SCB0/P4.0
I2C_SDA_SCB0/P4.1
PG7202
VBUS_CSN_R
PG7201
4
5
6
7
VBUS_CSP_R
VDDD
C7203
PD_VCCD 1
2
SCD1U16V2KX-3DLGP
9
1
2
1
2
3D3V_S5
VBUS_CSN
GAP-CLOSE-PWR-3-GP
VBUS_CSP
R7202
10KR2F-2-GP
GAP-CLOSE-PWR-3-GP
3D3V_S5
11
DY
3D3V_S5
BB_RST
10
5V_VCONN_P1
5V_S5
8
45
16
13
17
15
14
26
25
24
27
28
29
30
31
35
36
37
12
32
33
2 R7220 1
0R0603-PAD-7-NP-GP
CCG6_I2C_SDA R7225 1
2 0R0402-PAD-7-NP-GP SML1_SMBDATA
CCG6_I2C_SCL R7224 1
2 0R0402-PAD-7-NP-GP SML1_SMBCLK
CCG6_I2C_INT
2 0R0402-PAD-7-NP-GP TBT_PD_ALERT#
R7223 1
20191220
CCG6_I2C_ADDR
Follow 13" TGL
RETIMER_PWREN_R
RETIMER_PWREN
0R0402-PAD-7-NP-GP
2
R7221 1
INT#_Typec_R R7222 1
CCG6_I2C_INT#
20R0402-PAD-7-NP-GP
CCG6_UART_RX
UPD1_SMBDA_Q
2
R7259 1
0R0402-PAD-7-NP-GP
CCG6_UART_TX
UPD1_SMBCLK_Q
1
2
R7258
0R0402-PAD-7-NP-GP
BB_RST
BB_I2C_SDA
BB_I2C_SCL
SOC_FRC_RETIMER_PWR R7262 1
2 0R2J-2-GP TBT_FORCE_PWR
DY
SOC_OC_FAULT_R
SOC_OC_FAULT
2
1
R7264 1
TP7205
VBUS_C_CTRL_P0_GPIO
0R0402-PAD-7-NP-GP
CCG6_PROCHOT#
CCG6_ID_1
PD to SOC
R7210
100KR2F-L1-GP
C7217
SCD1U16V2KX-3DLGP
[71]
[16,71]
USB4_USB20_PD_P
USB4_USB20_PD_N
USB1_USB20_CMCT_P
USB1_USB20_CMCT_N
CC1
CC2
2 D005R6F-3-GP
1
2
3
48
1
USB4_USB20_P 0R0402-PAD-7-NP-GP
2
USB4_USB20_N 0R0402-PAD-7-NP-GP
2
46
44
VBUS_C
VBUS_C
VBUS_C
VBUS_C
PD to EC
PD to BB
UPD1_SMBCLK_Q
UPD1_SMBDA_Q
1
USB1_BB_SBU1
USB1_BB_SBU2
[4]
USB1_CON_CC1
USB1_CON_CC2
VBUS_C_CTRL
C7216
R7263
10KR2F-2-GP
2
[71]
[71]
47
R7350 1
20V_VCCPD_VBUS
U7202
PD_VBUS_C_CTRL1
2
USB1_CON_SBU1
USB1_CON_SBU2
1
[73]
[73]
2
USB1_USB20_CMCT_P
USB1_USB20_CMCT_N
USB1_USB20_CMCB_P
USB1_USB20_CMCB_N
1
[73]
[73]
[73]
[73]
PD Function
Normal: High
Avtive : Low
5V_S5
2
USB4_USB20_P
USB4_USB20_N
SC1U10V2KX-1DLGP
[16]
[16]
20200213
Change from BGA96P to QFN48P
20200506
using 071.06127.0B03 for DVT2
1
VBUS_C_CTRL_P0_GPIO
2
[74]
2
1
2
USB1_CON_CC1
USB1_CON_CC2
C7210
SC1U10V2KX-1DLGP
[73]
[73]
[3,22,24,44,46]
1
Close to Pin31
SCD1U16V2KX-3DLGP
D
C7207
SCD1U16V2KX-3DLGP
PD_VBUS_C_CTRL1
SC1U10V2KX-1DLGP
[74]
C7201
SCD1U16V2KX-3DLGP
UPD1_SMBCLK
UPD1_SMBDAT
CCG6_I2C_INT#
1
Close to Pin32
[24]
[24]
[24]
2
3D3V_S5
2
Main Func = TypeC
3
Follow Hellcat15 Upsell TGL
SOC_OC_FAULT
C
PD to EC
75.27002.F7C
CYPD6127-48LQXI-GP
1 R7253 2
0R0402-PAD-7-NP-GP
DVT2.2
Using 071.06127.0D03
USB1_CON_CC2
C7213
1
2 SC390P50V2KX-1-GP
USB1_CON_CC1
C7208
1
2 SC390P50V2KX-1-GP
1
VDDD
1
VDDD
071.06127.0003
R7213
1KR2J-1-GP
DY
R7215
4K7R2J-2-GP
2
2
0x08
B
1
3D3V_S5
1
VDDD
R7256
R7257
100KR2J-1-GP DY 100KR2J-1-GP
2
2
1
DY
2
R7201
1KR2J-1-GP
DY
C7214
SCD1U25V2KX-1-DL-GP
2
PD_XRES
1
CCG6_I2C_ADDR
B
PROCHOT#_CPU
A
D7201
CCG6_PROCHOT#
K
RB520S30-GP
83.R2003.A8M
2ND = 083.52030.008F
R7226 1
20191210(EVT)
Follow vendor review value
(TBT)
R7216 -> DY
R7218 -> 100K
RN7202
2
1
3
4
(NON_TBT)
R7216 -> 300K
R7218 -> 100K
1
R7216
300KR2F-GP
NON_TBT
CCG6_ID_1
1
DY
20191218
Layout requre
20200212
change RN7204 to RN7101
UPD1_SMBDA_Q
UPD1_SMBCLK_Q
20R2J-2-GP
2
3D3V_S5
DY
VDDD
SRN2K2J-1-GP
R7218
100KR2F-L1-GP
2
20200221(DVT1)
Remove R7214
R7267
1
2
CCG6_I2C_INT#
2K2R2J-2-GP
A
R7268
1
TBT_PD_ALERT#
2
20191129(EVT)
TP for vendor request
20200227(DVT1)
Remove TP for space
A
20191220
Follow 13" TGL
2K2R2J-2-GP
VDDD
<Core Design>
RN7203
2
1
3
4
Wistron Corporation
BB_I2C_SCL
BB_I2C_SDA
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
SRN2K2J-1-GP
Title
https://realschematic.com
EXT IO (Thunderbolt(2/3)/Type C CC Logic)
Size
A2
Date:
5
4
3
2
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
72
of
A00
105
3
Main Func = TypeC
[72]
[72]
[72]
[72]
USB1_USB20_CMCT_P
USB1_USB20_CMCT_N
USB1_USB20_CMCB_P
USB1_USB20_CMCB_N
[72]
[72]
USB1_CON_CC1
USB1_CON_CC2
USB1_CON_SBU1
USB1_CON_SBU2
[71]
[71]
USB1_SSTX_RC_N1
USB1_SSRX_RC_P1
[71]
[71]
USB1_SSRX_RC_N0
USB1_SSTX_RC_N0
[71]
[71]
USB1_SSRX_RC_P0
USB1_SSTX_RC_P0
[71]
[71]
20191211
Follow Connector list 1210
20200416
change to the part which HC17 use
C7303
1
C7301
1
2
USB1_SSRX_AR_N0
USB1_SSRX_AR_P0
13
14
15
16
CHASSIS#13
CHASSIS#14
CHASSIS#15
CHASSIS#16
20V_VCCPD_VBUS
USB1_CON_CC2
USB1_USB20_CONB_P
USB1_USB20_CONB_N
USB1_CON_SBU2
20191216
For layout requirement
[72]
[72]
Follow Hellcat15 Upsell TGL
20V_VCCPD_VBUS
USB1_SSTX_CON_P1
USB1_SSTX_CON_N1
2
USB1_SSRX_AR_P0
USB1_SSRX_AR_N0
USB1_SSRX_AR_P1
USB1_SSRX_AR_N1
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
GND
SSTXP2
SSTXN2
VBUS#B4
CC2
DP2
DN2
RFU2
VBUS#B9
SSRXN1
SSRXP1
GND
DY
C7307
SC10U25V3MX-5-GP
[71]
[71]
[71]
[71]
GND
SSTXP1
SSTXN1
VBUS#A4
CC1
DP1
DN1
RFU1
VBUS#A9
SSRXN2
SSRXP2
GND
SCD1U25V2KX-1-DL-GP
USB1_SSTX_CON_P0
USB1_SSTX_CON_N0
USB1_SSTX_CON_P1
USB1_SSTX_CON_N1
A1
A2
A3
A4
USB1_CON_CC1
A5
USB1_USB20_CONT_P A6
USB1_USB20_CONT_N A7
USB1_CON_SBU1
A8
A9
USB1_SSRX_AR_N1
A10
USB1_SSRX_AR_P1
A11
A12
USB1_SSTX_CON_P0
USB1_SSTX_CON_N0
SCD1U25V2KX-1-DL-GP
D
[71]
[71]
[71]
[71]
1
USB1
20V_VCCPD_VBUS
USB1
2
1
4
2
5
20200504
Remove C7302 C7304
Change C7301 C7302 to 0402 size
D
SKT-USB28-27-GP-U
062.10009.M042
2nd = 062.10009.M060
20200722
Remove R7301
R7302 R7303 R7304
2020/02/29:swap EL7302/EL7301
FILTER-4P-132-GP
USB1_SSRX_RC_N1
USB1_SSTX_RC_P1
EL7301
USB1_USB20_CMCT_P
3
4
USB1_USB20_CONT_P
USB1_USB20_CMCB_P
3
4
USB1_USB20_CONB_P
USB1_USB20_CMCT_N
2
1
USB1_USB20_CONT_N
USB1_USB20_CMCB_N
2
1
USB1_USB20_CONB_N
FILTER-4P-132-GP
EL7302
C
68.02002.061
2nd = 068.09002.2001
C
68.02002.061
2nd = 068.09002.2001
20200213
Follow EMC requestment
USB1_CON_SBU2
USB1_CON_SBU1
USB1_CON_CC1
USB1_CON_CC2
USB1_CON_SBU1
USB1_CON_SBU2
USB1_USB20_CONT_P
2
C7305
1
DY
2
1
1
2
2
1
1
2
2
1
1
ED7308
DY
B
20191212
Follow Nakia
C7306
SC100P50V2JN-3-LL-GP
1
ED7307
SC100P50V2JN-3-LL-GP
ED7306
PESD5V0H1BSFYL-GP-U1
ED7305
PESD5V0H1BSFYL-GP-U1
PESD5V0H1BSFYL-GP-U1
PESD5V0H1BSFYL-GP-U1
1
ED7304
PESD5V0H1BSFYL-GP-U1
ED7303
PESD5V0H1BSFYL-GP-U1
ED7302
PESD5V0H1BSFYL-GP-U1
PESD5V0H1BSFYL-GP-U1
1
2
2
2
2
083.5V0H1.00AF
083.5V0H1.00AF
083.5V0H1.00AF
083.5V0H1.00AF
083.5V0H1.00AF
083.5V0H1.00AF
083.5V0H1.00AF
083.5V0H1.00AF
2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF
ED7301
USB1_SSRX_RC_N1
USB1_SSRX_RC_P1
USB1_SSTX_RC_N1
USB1_SSTX_RC_P1
USB1_SSRX_RC_N0
USB1_SSRX_RC_P0
USB1_SSTX_RC_N0
USB1_SSTX_RC_P0
ED7316
PESD5V0H1BSFYL-GP-U1
PESD5V0H1BSFYL-GP-U1
PESD5V0H1BSFYL-GP-U1
PESD5V0H1BSFYL-GP-U1
PESD5V0H1BSFYL-GP-U1
PESD5V0H1BSFYL-GP-U1
PESD5V0H1BSFYL-GP-U1
PESD5V0H1BSFYL-GP-U1
1
ED7315
1
ED7314
1
ED7313
1
ED7312
1
ED7311
1
ED7310
1
ED7309
https://realschematic.com
<Core Design>
2
2
2
2
2
2
2
2
083.5V0H1.00AF
083.5V0H1.00AF
083.5V0H1.00AF
083.5V0H1.00AF
083.5V0H1.00AF
083.5V0H1.00AF
083.5V0H1.00AF
083.5V0H1.00AF
2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF
1
A
USB1_USB20_CONT_N
USB1_USB20_CONB_P
USB1_USB20_CONB_N
B
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
EXT IO (Thunderbolt(3/3)/Type C Conn)
Size
A3
Date:
5
4
3
A
2
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
73
of
A00
105
5
[72]
[72]
PD_VBUS_C_CTRL1
[24]
TYPEC_DCIN1_EN#
[44]
VCCPD_VBUS_ACK
4
3
2
1
VBUS_C_CTRL_P0_GPIO
D
D
20V_VCCPD_VBUS
USB_ADT
+SDC_IN
GND
GND
GND
U7419
NX20P5090UK-GP
C3
D3
E3
074.20509.007Z
2nd = 074.05007.0A9Z
1 R7403
2
084.03413.0031
2nd = 084.02301.0031
3rd = 84.00513.03B
20191218
For ESD SPEC
20191223
For High limit
LPS_SW_B
0R0402-PAD-7-NP-GP
2
LPS_SW_C
2
1
2
Q7406
3
4
D2
5
G2
D2
G1
1
LPS_SW_D
20191128
Follow vendor sugestion
075.00138.0A7C
2nd = 075.00139.007C
3rd = 075.00138.0F7C
4
S2
2
1
6
D1
S1
R7428
100KR1F-GP
G1
S1
PJT138KA-GP
3
PD_VBUS_C_CTRL1_R
6
D1
Q7407
TYPEC_DCIN1_EN#
5
1
1MR1J-GP
Form EC (CY18 add)
2
G2
2
S2
LPS_SW_A
1
1
R7405
100KR1F-GP
TYPEC_DCIN1_EN#
1 R7422
2
2
Q7408
PJA3413-1-GP
R7402
200KR1F-GP
3D3V_S5
PD_VBUS_C_EN
R7430
1MR1J-GP
S
2
G
R7404
1MR1J-GP
VCCPD_VBUS_ACK
R7427
100KR1F-GP
1
1
20200212
Change partnumber
20200424(DVT2)
change to 1M for Power leakage prevent
R7406
100KR1F-GP
D
1
VINT
VINT
VINT
VINT
2
084.21321.0037
2nd = 084.03307.0037
3rd = 084.20P03.0033
2
A1
B1
C1
D1
B2
C2
D2
E1
E2
VBUS
VBUS
VBUS
VBUS
VBUS
OVLO
EN#
ACK
A3
A2
B3
1
2
G
AONR21321-GP
LPS_SW
R7424
100KR2J-1-GP
C
1
2
3
C7401
SC1500P50V2KX-2-DL-GP
R7401
1MR1J-GP
3D3V_S5
U7418
S
S
S
4
1
8 D
7 D
6 D
5 D
1
C
R7407
1
PJT138KA-GP
2
075.00138.0A7C
2nd = 075.00139.007C
3rd = 075.00138.0F7C
2
200KR1F-GP
20V_VCCPD_VBUS
B
1
B
R7410
1
1
1
DY
2
PD_VBUS_C_CTRL1_R
0R2J-2-GP
2
R7409
R7411
750KR1J-GP
VBUS_C_CTRL_P0_GPIO
3
PD_VBUS_C_CTRL1_R 2
2
10KR1F-GP
4
5
PD_VBUS_C_CTRL1_R_R
2
1
20191128
Change net name
6
2N7002KDW-1-GP
1
PD_VBUS_C_EN_A
2nd = 075.27002.0E7C
75.27002.F7C
R7408
200KR1F-GP
2
2
100KR1F-GP
PD_VBUS_C_CTRL1
Form PD control
Note:ZZ.27002.F7C01
1
20V_VCCPD_VBUS
R7426
100KR1F-GP
Q7405
R7425
20191127
Follow vendor request
A
A
<Core Design>
Wistron Corporation
https://realschematic.com
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
GPU(2/5)DIGITALOUT
Size
A1
Date:
5
4
3
2
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
1
Sheet
74
of
A00
105
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A3
Date:
5
4
3
2
Document Number
Reserved
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
75
A00
of
105
5
4
3
2
1
Main Func = dGPU
1.05V +/- 30mV
3.3A
dGPU Reset
1D8V_AON_S0
B
VCC
A
OPS
Y
5
SYS_PEX_RST_MON#
4
GND
1D8V_AON_S0
OPS
1
2
2
2
OPS
OPS
Place close Chip
2
1/14 PCI_EXPRESS
1
1
OPS
OPS
Place close VDD ball
1 OF 14
GPU1A
2
1
2
1
OPS
C7626
SC22U6D3V3MX-1-DL-GP
VGACORE_VDD_SENSE_1
VGACORE_GND_SENSE_1
OPS
C7623
SC10U6D3V3MX-DL-GP
[85]
[85]
1D8V_VGA_S0
C7625
SC10U6D3V3MX-DL-GP
PCH_PLTRST#
C7612 C7610
SC1U10V2KX-1DLGP
DGPU_HOLD_RST#
C7611
SC4D7U6D3V3KX-DLGP
[18]
[17,61,63,66,71,91]
C7613
R7606
OPS 10KR2J-3-GP
SC4D7U6D3V3KX-DLGP
73.01G08.L04
2nd = 073.7SZ08.000G
3rd = 73.01G08.IHG
4th = 73.7SZ08.DAH
GFX_CLK_CPU_P
GFX_CLK_CPU_N
SC4D7U6D3V3KX-DLGP
[18]
[18]
1
D
74LVC1G08GW-1-GP
1
3
1
2
2
PCH_PLTRST#
D
1V_VGA_S0
U7601
2
1
2
DGPU_HOLD_RST#
AE15
AF15
AC18
AB18
AG15
AG16
AB19
AC19
AF16
AE16
AD20
AC20
AE18
AF18
AC21
AB21
AG18
AG19
AD23
AE23
AF19
AE19
AF24
AE24
AE21
AF21
AG24
AG25
AG21
AG22
A
PEX_RX4
PEX_RX4_N
NC FOR GF119
PEX_TX5
PEX_TX5_N
PEX_PLL_HVDD
PEX_PLL_HVDD
PEX_RX5
PEX_RX5_N
PEX_TX6
PEX_TX6_N
PEX_RX6
PEX_RX6_N
PEX_TX7
PEX_TX7_N
NC#AB8
AA8
AA9
3.3V +/- 5%
210mA
C7629
C7627
OPS
1
1
2
C7628
OPS
OPS
2
1
OPS
2
1
C7620
OPS
C
Place close Chip
1D8V_VGA_S0
AB8
C7616
Place close Chip
OPS
PEX_RX7
PEX_RX7_N
PEX_TX8
PEX_TX8_N
C7615
DY
C7624
SC4D7U6D3V3KX-DLGP
AD17
AC17
B
C7621
Place close VDD ball
SC4D7U6D3V3KX-DLGP
AF13
AE13
OPS
PEX_TX4
PEX_TX4_N
SCD1U16V2KX-3DLGP
AB16
AC16
PEX_RX3
PEX_RX3_N
C7631
SC22U6D3V3MX-1-DL-GP
AC15
AB15
AG12
AG13
OPS
SC10U6D3V3MX-DL-GP
AE12
AF12
PEX_TX3
PEX_TX3_N
C7630
OPS
SC4D7U6D3V3KX-DLGP
AD14
AC14
OPS
C7622
OPS
SC4D7U6D3V3KX-DLGP
AF10
AE10
PEX_RX2
PEX_RX2_N
C7614
SC1U10V2KX-1DLGP
AB13
AC13
PEX_TX2
PEX_TX2_N
SC1U10V2KX-1DLGP
AC12
AB12
AG9
AG10
PEX_RX1
PEX_RX1_N
AA10
AA12
AA13
AA16
AA18
AA19
AA20
AA21
AB22
AC23
AD24
AE25
AF26
AF27
SC1U10V2KX-1DLGP
AE9
AF9
PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_TX1
PEX_TX1_N
SC1U10V2KX-1DLGP
AD11
AC11
C
PEX_RX0
PEX_RX0_N
SC10U6D3V3MX-DL-GP
AF7
AE7
2
AB10
AC10
1
OPS
2
GFX_PCIE_RX_CON_P1
GFX_PCIE_RX_CON_N1
C7603 1
2 SCD22U10V1KX-1-GP
C7604 1 OPS
2 SCD22U10V1KX-1-GP
GFX_PCIE_TX_P1
GFX_PCIE_TX_N1
1D8V_VGA_S0
PEX_TX0
PEX_TX0_N
1
GFX_PCIE_RX_P1
GFX_PCIE_RX_N1
AC9
AB9
AG6
AG7
2
GFX_PCIE_RX_CON_P0
GFX_PCIE_RX_CON_N0
SCD22U10V1KX-1-GP
SCD22U10V1KX-1-GP
AA22
AB23
AC24
AD25
AE26
AE27
1
OPS
PEX_REFCLK
PEX_REFCLK_N
2
C7601 1
2
2
C7602 1 OPS
GFX_PCIE_TX_P0
GFX_PCIE_TX_N0
PEX_CLKREQ#
1
GFX_PCIE_RX_P0
GFX_PCIE_RX_N0
PEX_DVDD
PEX_DVDD
PEX_DVDD
PEX_DVDD
PEX_DVDD
PEX_DVDD
PEX_RST_N
2
PJE8408-R1-00001-GP
084.08408.0031
2nd = 084.00138.0E31
AE8
AD8
1
GFX_PCIE_RX_P1
GFX_PCIE_RX_N1
GFX_PCIE_TX_P1
GFX_PCIE_TX_N1
AC6
2
[16]
[16]
[16]
[16]
AC7
1
GFX_CLK_CPU_P
GFX_CLK_CPU_N
2
GPU_PEX_RST#
1 R7613 2
0R0402-PAD-7-NP-GP
GPU_CLKREQ#
1
SYS_PEX_RST_MON#
S
2
OPS
1
D
Q7601
2
CLK_PCIE_PEG_REQ#
NC FOR GM108
GFX_PCIE_RX_P0
GFX_PCIE_RX_N0
GFX_PCIE_TX_P0
GFX_PCIE_TX_N0
NC#AB6
DY
PEX_RX8
PEX_RX8_N
B
PEX_TX9
PEX_TX9_N
VDD_SENSE
PEX_RX9
PEX_RX9_N
GND_SENSE
F2
VGACORE_VDD_SENSE_1
F1
VGACORE_GND_SENSE_1
POWER IC
PEX_TX10
PEX_TX10_N
PEX_RX10
PEX_RX10_N
PEX_TX11
PEX_TX11_N
PEX_RX11
PEX_RX11_N
PEX_TX12
PEX_TX12_N
PEX_RX12
PEX_RX12_N
PEX_TX13
PEX_TX13_N
PEX_RX13
PEX_RX13_N
PEX_TX14
PEX_TX14_N
NC FOR GF117/GK208/GM108
OPS 10KR2J-3-GP
1
[16]
[16]
[16]
[16]
AB6
R7603
CLK_PCIE_PEG_REQ#
G
[18]
NC#AF22
NC#AE22
NC#AA14
NC#AA15
PEX_RX14
PEX_RX14_N
NVJTAG_SEL
PEX_TX15
PEX_TX15_N
AF22
AE22
AA14
AA15
R7602
2
AD9 TESTMODE 1 OPS
10KR2F-2-GP
PEX_RX15
PEX_RX15_N
A
PEX_TERMP
AF25 PEX_TERMP 1
R7601
OPS
2
<Core Design>
2K49R2F-GP
N17S-G1-A1-GP
Wistron Corporation
071.0N17S.0000
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
GPU(1/5)PEG
Size
Custom
Document Number
5
https://realschematic.com
4
3
2
Rev
MOCKINGBIRD_TGL
Date: Saturday, August 01, 2020
1
Sheet
76
A00
of
105
5
4
3
2
1
Main Func = dGPU
5 OF 14
GPU1H
5/14 IFPC
T6
4 OF 14
DVI/HDMI
XVDD
W7
IFPA_L1_N
IFPA_L1
IFPAB_PLLVDD
IFPA_L0_N
IFPA_L0
NC FOR GF117/GM108
IFP_IOVDD
Y6
IFP_IOVDD
IFPB_L3_N
IFPB_L3
NC FOR GF117/GM108
W6
IFPA_AUX_SDA_N
IFPA_AUX_SCL
IFPB_L2_N
IFPB_L2
IFPB_L1_N
IFPB_L1
IFPB_L0_N
IFPB_L0
IFPB_AUX_SDA_N
IFPB_AUX_SCL
C
AA5
AA4
NC
AF2
NC#AF2
N17S-G1-A1-GP
1V_VGACORE1_S0
AD2
AD3
GF117
GPIO23
GPIO22
NC
NC
NC#AE3
NC#AE4
NC
NC#AG3
NC
NC#AF4
NC
NC#AF3
GM108
GF117
K7
T3
T2
GPIO15
XVDD
AD5
AD4
T7
R7
XVDD
VGA_B7
XVDD
TXC
TXC
TXC
TXC
XVDD
XVDD
TXD0
TXD0
TXD0
TXD0
XVDD
XVDD
TXD1
TXD1
TXD1
TXD1
XVDD
XVDD
TXD2
TXD2
TXD2
TXD2
XVDD
XVDD
XVDD
XVDD
TXC
TXC
XVDD
XVDD
TXD0
TXD0
XVDD
XVDD
TXD1
TXD1
XVDD
XVDD
TXD2
TXD2
XVDD
XVDD
GPIO17
HPD_E
J1
K1
K3
K2
M3
M2
M1
N1
HPD_E
GPIO18
C2
NC FOR GF117
DVI-DL
P4
P3
R5
R4
T5
T4
IFPF
V4
V3
D4
AE3
AE4
DVI-SL/HDMI
DP
I2CZ_SDA
I2CZ_SCL
XVDD
XVDD
TXC
TXC
XVDD
XVDD
TXD0
TXD0
XVDD
XVDD
TXD4
TXD4
TXD1
TXD1
XVDD
XVDD
TXD5
TXD5
TXD2
TXD2
XVDD
XVDD
TXD3
TXD3
U4
U3
GF117
NC
J3
J2
GF119/GK208
XVDD
XVDD
B3
R6
J6
DP
I2CX_SDA
I2CX_SCL
XVDD
IFPD
XVDD
XVDD
NC FOR GK208
6 OF 14
1V_VGACORE1_S0
DP
I2CY_SDA
I2CY_SCL
XVDD
C3
GF119/GK208
DVI-SL/HDMI
XVDD
R1
T1
XVDD
TSEN_VREF
NC
J7
I2CY_SDA
I2CY_SCL
IFPE
DVI/HDMI
R7701
OPS 10KR2J-3-GP
B7
A7
GF119/GK208
DVI-DL
K6
NC
1V_VGACORE1_S0
1V_VGACORE1_S0
H6
U6
GM108/GK208
NC
NC
XVDD
XVDD
R3
R2
7/14 IFPEF
GF117
GPU1I
1
NC
XVDD
XVDD
TXD2
TXD2
N3
N2
7 OF 14
GPU1J
6/14 IFPD
AD1
AE1
3 OF 14
GF117/GM108
TS_VREF
XVDD
2
GPIO14
XVDD
XVDD
N5
N4
AB2
AB3
3/14 DACA
NC#W5
XVDD
XVDD
1D8V_AON_S0
GPU1K
W5
P6
AB4
AB5
N17S-G1-A1-GP
AE2
TXC
TXC
TXD1
TXD1
AA1
AB1
GF117
IFPAB
XVDD
XVDD
TXD0
TXD0
AA2
AA3
D
I2CW_SDA
I2CW_SCL
NC FOR GF117/GM108
V7
Y3
Y4
DP
NC FOR GF117/GM108
IFPA_L2_N
IFPA_L2
NC FOR GF117/GM108
IFPAB_RSET
XVDD
XVDD
NC FOR GF117/GM108
AA6
AC4
AC3
NC FOR GF117/GM108
IFPA_L3_N
IFPA_L3
M7
N7
1V_VGACORE1_S0
GF119/GK208
XVDD
4/14 IFPAB
D
NC FOR GF117/GK208/GM108
GPU1G
IFPC
NC FOR GF117/GM108
1V_VGACORE1_S0
H4
H3
J5
J4
C
K5
K4
L4
L3
M5
M4
NC FOR GK208
HPD_F
GPIO19
F7
NC FOR GF117
N17S-G1-A1-GP
AG3
N17S-G1-A1-GP
AF4
AF3
GK208
N17S-G1-A1-GP
B
B
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A2
Date:
5
4
3
2
GPU(2/5)DIGITALOUT
MOCKINGBIRD_TGL
Document Number
Saturday, August 01, 2020
Sheet
1
77
of
Rev
A00
105
5
4
3
2
1
Main Func = dGPU
D18
C18
D17
D16
T24
U24
V24
V25
FBA_WCK01
FBA_WCK01#
FBA_WCK23
FBA_WCK23#
FBA_WCK45
FBA_WCK45#
FBA_WCK67
FBA_WCK67#
OPS
C7810
2
1
C7815
DY
1
1
OPS
2
1
1
OPS
2
C7811
2
1
C7816
2
1
1
2
2
1
1
2
1
2
1
1
1
2
2
2
2
1
1
2
1
2
1
2
1
2
2
1
2
2
OPS
DY
FB_CAL_PD_VDDQ
D22
FB_CAL_PU_GND
C24
FB_CAL_TERM_GND
B25
FB_CAL_PD_VDDQ
FB_CAL_PU_GND
FB_CAL_TERM_GND
1
1
OPS
R7806
60D4R2F-GP
GDDR5:60.4R071.0N17S.0000
2
GDDR3:51.1R
Under GPU
Near GPU
L7801
35mA
1D8V_FBA_PLL_AVDD
1
2
OPS
C7809
C7805
C7806
SCD1U16V2KX-3DLGP
SCD1U16V2KX-3DLGP
SCD1U16V2KX-3DLGP
SCD1U16V2KX-3DLGP
1
C7808
2
2
2
2
FB_VREF
C7818
OPS
MHC1608S300QBP-GP
68.00335.051
2nd = 68.00334.051
3rd = 68.00214.081
30ohm@100MHZ(ESR=0.01ohm)
Sourcer suggest to change to
68.00335.051 from 68.00084.H41.
Note:
Reference NV-DDR5 CRB and DOH70 by GDDR5
2
2
1D35V_VGA_S0
R7816
R7824
1
OPS
10KR2F-2-GP
10KR2F-2-GP
1
C7812
1D8V_VGA_S0
62mA
P22
1
F16
H22
071.0N17S.0000
OPS
OPS
2
FBA_CLK0P
FBA_CLK0N
FBA_CLK1P
FBA_CLK1N
N17S-G1-A1-GP
FBA_CMD14
FBA_CMD30
OPS
C
D24
D25
N22
M22
OPS OPS OPS OPS
B
C7826
C7824
F22
J22
GF117
D23
D
C7829
B19
2
FB_REFPLL_AVDD
C7822
OPS
N17S-G1-A1-GP
SC22U6D3V3MX-1-DL-GP
FB_PLLAVDD
1
OPS
40D2R2F-GP
1
FB_PLL_AVDD
C7821
OPS
SC10U6D3V3MX-DL-GP
FB_PLL_AVDD
NC
C7820
Under GPU
R7805
2
R7807
40D2R2F-GP
GF119
Modify by change to GDDR5
OPS OPS
SC10U6D3V3MX-DL-GP
FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N
C7817
OPS
C7819
OPS
SC22U6D3V3MX-1-DL-GP
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
C7823
DY
SC22U6D3V3MX-1-DL-GP
FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
C7814
DY
SC22U6D3V3MX-1-DL-GP
FBA_CMD34
FBA_CMD35
C7813
SC10U6D3V3MX-DL-GP
FBA_DEBUG0
FBA_DEBUG1
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
OPS
SC1U10V2KX-1DLGP
FBA_CMD32
C7807
1D35V_VGA_S0
GF117/GF119
GK208
NC
OPS
SC1U10V2KX-1DLGP
F19
C14
A16
A22
P25
W22
AB27
T27
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
H24
H26
J21
K21
C7825
DY
SC10U6D3V3MX-DL-GP
E19
C15
B16
B22
R25
W23
AB26
T26
C27
C26
E24
F24
D27
D26
F25
F26
F23
G22
G23
G24
F27
G25
G27
G26
M24
M23
K24
K23
M27
M26
M25
K26
K22
J23
J25
J24
K27
K25
J27
J26
C7802
OPS
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
DY
SC1U10V2KX-1DLGP
FBA_EDC0
FBA_EDC1
FBA_EDC2
FBA_EDC3
FBA_EDC4
FBA_EDC5
FBA_EDC6
FBA_EDC7
C
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
GF117
GF119
GK208
C7801
Near GPU
SC10U6D3V3MX-DL-GP
D19
D14
C17
C22
P24
W24
AA25
U25
B26
C25
E23
E26
F14
F21
G13
G14
G15
G16
G18
G19
G20
G21
L22
L24
L26
M21
N21
R21
T21
V21
W21
SC4D7U6D3V3KX-DLGP
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
SC1U10V2KX-1DLGP
FBA_WCK01
FBA_WCK01#
FBA_WCK23
FBA_WCK23#
FBA_WCK45
FBA_WCK45#
FBA_WCK67
FBA_WCK67#
F3
SC4D7U6D3V3KX-DLGP
[81]
[81]
[81]
[81]
[82]
[82]
[82]
[82]
GNDS_SENSE
SC1U10V2KX-1DLGP
FBA_CLK0P
FBA_CLK0N
FBA_CLK1P
FBA_CLK1N
NC
GF119
SC1U10V2KX-1DLGP
[81]
[81]
[82]
[82]
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
SC1U10V2KX-1DLGP
FBA_D[32..63]
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
E18
F18
E16
F17
D20
D21
F20
E21
E15
D15
F15
F13
C13
B13
E13
D13
B15
C16
A13
A15
B18
A18
A19
C19
B24
C23
A25
A24
A21
B21
C20
C21
R22
R24
T22
R23
N25
N26
N23
N24
V23
V22
T23
U22
Y24
AA24
Y22
AA23
AD27
AB25
AD26
AC25
AA27
AA26
W26
Y25
R26
T25
N27
R27
V26
V27
W27
W25
SC1U10V2KX-1DLGP
[82]
FBA_EDC0
FBA_EDC1
FBA_EDC2
FBA_EDC3
FBA_EDC4
FBA_EDC5
FBA_EDC6
FBA_EDC7
[81]
[81]
[81]
[81]
[81]
[81]
[81]
[81]
[81]
[81]
[81]
[81]
[81]
[81]
[81]
[81]
[82]
[82]
[82]
[82]
[82]
[82]
[82]
[82]
[82]
[82]
[82]
[82]
[82]
[82]
[82]
[82]
1D35V_VGA_S0
Under GPU
12/14 FBVDDQ
2/14 FBA
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
SCD1U16V2KX-3DLGP
D
GPU1D
12 OF 14
2 OF 14
GPU1B
SCD1U16V2KX-3DLGP
[81]
[81]
[81]
[81]
[82]
[82]
[82]
[82]
1.35V +/- 3%
4.88A
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
1
[81]
[81]
[81]
[81]
[82]
[82]
[82]
[82]
FBA_D[0..31]
1
[81]
B
2
2
FBA_CMD29
FBA_CMD13
R7820
1
1
R7821
OPS
10KR2F-2-GP
10KR2F-2-GP
OPS
A
A
<Core Design>
Wistron Corporation
https://realschematic.com
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A1
Date:
5
4
3
2
GPU(3/5)VRAMI/F
Document Number
MOCKINGBIRD_TGL
Sheet
Saturday, August 01, 2020
1
Rev
A00
78
of
105
5
4
3
2
1
Main Func = dGPU
1D8V_AON_S0
1D8V_VGA_S0
1D8V_VGA_PLL
Under GPU
L7901
[85]
VGA_CORE_PSI
[18,86]
GM108
GC6_FB_EN
GPU_THM_SMBDAT
[18,24,26]
GPU_THM_SMBCLK
GPIO16
GPIO20
GPIO21
GK208
GF117
GPIO16
GPIO20
GPIO8
GPIO8
NC
GPIO16
GPIO20
GPIO21
NC
GPIO8
1
B10
20PF 5% 50V +/-0.25PF 0402
1
1
2
2
1
R7902
10KR2J-3-GP
OPS
R7903
1MR2J-1-GP
1 DY
2
XTL_27M_OUT_GPU
2
1D8V_AON_S0
OVERT_GPU#
GPIO9_ALERT
GPIO10_FBVREF
OPS
PWR_LEVEL
OPS1KR2J-1-GP
4
1
1
R7905
100KR2J-1-GP
2
D7902
A
K
3
XTL_27M_X2
OPS
DGPUHOT#
OPS
L1SS355T1G-GP
C7907
SC20P50V2JN-1-DL-GP
83.00355.G1F
2nd = 83.00355.D1F
D5
E6
C4
R7904
X7901
GPIO5_GC6_PWR_EN
1 R7936 2
0R0402-PAD-7-NP-GP
VGA_CORE_PSI
GF119
NC
NC
NC
C10 N12P_XTAL_OUTBUFF
N17S-G1-A1-GP
XTL_27M_IN_GPU
3V3_MAIN_EN is an open-drain GPIO.
GPIO5_GC6_PWR_EN_GPU
VGA_CORE_VID
[18,24,26]
XTAL_OUT
OPS
XTAL-27MHZ-192-GP
2
DGPUHOT#
GPIO10_FBVREF
[85]
XTAL_OUTBUFF
XTAL_IN
082.30008.0421
2ND = 082.30008.0431
OPS
1
[24,44]
[81]
GF117/GM108
XTAL_SSIN
PDP-06877-006
C11
2
1
GK208
GM108
OVERT
A10
1
OPS10KR2J-3-GP
NC
D
VIDEO_CLK_XTAL_SS
10KR2J-3-GP
2
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
OVERT
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
R7912
GPU_EVENT#
GPIO5_GC6_PWR_EN
VID_PLLVDD
GF119/GK208
OPS R7901
GPIO5_GC6_PWR_EN
2
[3]
[85,86]
1
R7933
GC6_20 10KR2J-3-GP
XS_PLLVDD
SP_PLLVDD
2
VGA_CORE_VID
GC6_FB_EN_GPU
GPU_EVENT_GPU#
2
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST_N
1
C6
B2
D6
C7
F9
A3
A4
B6
A6
F8
C5
E7
D7
B4
SRN2K2J-1-GP
AE5
AD6
AE6
AF6
AG4
N12P_JTAG_TRST
N6
1
THERMDP
I2CB_SCL
I2CB_SDA
9/14 XTAL_PLL
1
NC
NC
9 OF 14
GPU1M
L6
M6
C7902
OPS
1D8V_AON_S0
SRN2K2J-1-GP
RN7905
4
1
3
OPS 2
GF117
THERMDN
1
2
C7906
OPS
2
C9
C8
I2CB_SCL
I2CB_SDA
OPS
OPS
2
F12
SMBC_THERM_NV
SMBD_THERM_NV
RN7904
I2CC_SCL
4
I2CC_SDA
3
C7935
1
E12
A9
B9
D9
D8
OPS
SCD1U16V2KX-3DLGP
I2CC_SCL
I2CC_SDA
OPS
SCD1U16V2KX-3DLGP
I2CS_SCL
I2CS_SDA
C7905
C7934
SC22U6D3V3MX-1-DL-GP
1D8V_AON_S0
8/14 MISC1
D
30ohm@100MHZ
(ESR=0.01ohm)
SC4D7U6D3V3KX-DLGP
68.00335.051
2nd = 68.00334.051
3rd = 68.00214.081
OPS
8 OF 14
2
MHC1608S300QBP-GP
SRN10KJ-5-GP
GPU1N
OPS
2
1
4
3
SCD1U16V2KX-3DLGP
1
2
2
RN7910
OVERT_GPU#
GPIO9_ALERT
C7908
SC20P50V2JN-1-DL-GP
3rd = 082.30008.0441
4th = 082.30008.0401
E9
N17S-G1-A1-GP
1D8V_AON_S0
1D8V_VGA_S0
GPIO10_FBVREF
1
4
3
DA-05691-001_V05 P15
GPIO20/21 NC : for ALL
RN7901
OPS SRN4K7J-8-GP
GPU_THM_SMBDAT
6
D1
S1
1
OPS
R7910
100KR2J-1-GP
5
G2
OPS G1
2
4
S2
D2
3
C
2
C
1
2
Q7901
SMBD_THERM_NV
PJT138KA-GP
075.00138.0A7C
2nd = 075.00139.007C SMBC_THERM_NV
3rd = 075.00138.0F7C
GPU_THM_SMBCLK
1D8V_AON_S0
1D8V_AON_S0
STRAP5
C1
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
B12
A12
C12
GPU_ROM_SI
GPU_ROM_SO
GPU_ROM_SCLK
BUFRST_N
F6
NC#F6
F4
F5
GF117
GK208
GM108
VDDS_SENSE
NC
NC#F5
NC
NC
GF117
GK208
GM108
NC#D10
R7921
OPS
D11
2
1
1
OPS
2
2
1
2
1
2
1
1
2
2
OPS
1
GM108
STRAP5
R7929
100KR2F-L1-GP
OPS
Micron/Samsung_G5
Hynix/Micron
R7926
100KR2F-L1-GP
R7915
100KR2F-L1-GP
R7911
100KR2F-L1-GP
R7908
100KR2F-L1-GP
OPS
B
100KR2F-L1-GP
R7939
2
1
2
1
D12
2
1
1
2
2
1
2
1
2
ROM_CS#
ROM_SI
ROM_SO
ROM_SCLK
R7935
OPS
NC FOR
1
D1
D2
E4
E3
D3
R7920
OPS
D10
100KR2F-L1-GP
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
R7918
OPS
NC#E10
NC#F10
100KR2F-L1-GP
10/14 MISC2
E10
F10
100KR2F-L1-GP
1
R7928
DY
100KR2F-L1-GP
2
R7925
100KR2F-L1-GP
DY
100KR2F-L1-GP
R7914
DY
1D8V_AON_S0
10 OF 14
GPU1L
R7909
100KR2F-L1-GP
OPS
100KR2F-L1-GP
100KR2F-L1-GP
100KR2F-L1-GP
R7919
2
R7938
DY
1
Hynix/Samsung_G3_G5
GF119
B
N17S-G1-A1-GP
3D3V_S0
2
1D8V_AON_S0
2
1D8V_AON_S0
1
GPU_EVENT_GPU#
GC6_20
DY
G
GC6_20
R7948
10KR2J-3-GP
1
R7949
10KR2J-3-GP
D
GPU_EVENT#
S
Q7906
PJA138KA-GP
084.00138.0A31
2nd = 084.01012.0031
3D3V_AUX_S5
A
2
A
GC6_20R7952
10KR2J-3-GP
1
GC6_FB_EN_GPU
R7927
10KR2J-3-GP
1
S1
D1
6
2
G1
OPS G2
5
3
D2
S2
4
GC6_FB_EN_GPU_L
1
Q7907
<Core Design>
R7953 1
2
GC6_20 10KR2J-3-GP
2
3D3V_S0
OPS
PJT138KA-GP
Wistron Corporation
075.00138.0A7C
2nd = 075.00139.007C
3rd = 075.00138.0F7C
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
GC6_FB_EN
Size
Custom
GPU(4/5)GPIO/STRAP
Document Number
MOCKINGBIRD_TGL
Date: Saturday, August 01, 2020
5
https://realschematic.com
4
3
2
1
Sheet
79
of
Rev
A00
105
5
4
3
2
Main Func = dGPU
1
GPU1F
13 OF 14
13/14 GND
A2
AB17
AB20
AB24
AC2
AC22
AC26
AC5
AC8
AD12
AD13
A26
AD15
AD16
AD18
AD19
AD21
AD22
AE11
AE14
AE17
AE20
AB11
AF1
AF11
AF14
AF17
AF20
AF23
AF5
AF8
AG2
AG26
AB14
B1
B11
B14
B17
B20
B23
B27
B5
B8
E11
E14
E17
E2
E20
E22
E25
E5
E8
H2
H23
H25
H5
K11
K13
K15
K17
L10
L12
L14
L16
L18
L2
L23
L25
L5
M11
1V_VGACORE1_S0
Under GPU
11 OF 14
GPU1E
1
1
2
1
2
1
C8011
OPS
2
2
2
1
2
1
2
2
2
1
2
1
2
1
2
1
2
1
2
1
2
C8012
OPS
SC1U10V2KX-1DLGP
1
C8013
OPS
OPS
SC1U10V2KX-1DLGP
2
1
C8019
OPS
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
2
OPS
SC4D7U6D3V3KX-DLGP
C8014
OPS
SC4D7U6D3V3KX-DLGP
C8018
C8020
OPS
SC1U10V2KX-1DLGP
OPS
SC4D7U6D3V3KX-DLGP
SC4D7U6D3V3KX-DLGP
C
OPS
C8015
OPS
C8021
OPS
C8001
OPS
SC4D7U6D3V3KX-DLGP
OPS
C8002
OPS
SC4D7U6D3V3KX-DLGP
C8025
SC4D7U6D3V3KX-DLGP
SC4D7U6D3V3KX-DLGP
C8009
C8016
C8023
OPS
SC4D7U6D3V3KX-DLGP
OPS
SC4D7U6D3V3KX-DLGP
C8008
SC4D7U6D3V3KX-DLGP
SC4D7U6D3V3KX-DLGP
C8022
D
1
1
1
11/14 NVVDD
K10
K12
K14
K16
K18
L11
L13
L15
L17
M10
M12
M14
M16
M18
N11
N13
N15
N17
P10
P12
P14
P16
P18
R11
R13
R15
R17
T10
T12
T14
T16
T18
U11
U13
U15
U17
V10
V12
V14
V16
V18
VDD
VDD
VDD
VDD
VDD
VDDS
VDD
VDD
VDDS
VDD
VDD
VDDS
VDD
VDD
VDD
VDD
VDD
VDD
VDDS
VDDS
VDD
VDDS
VDDS
VDD
VDD
VDD
VDD
VDD
VDD
VDDS
VDD
VDD
VDDS
VDD
VDD
VDDS
VDD
VDD
VDD
VDD
VDD
N17S-G1-A1-GP
1
C8047
2
OPS
C8046
OPS
2
1
1
2
2
1
1
2
1
1
2
2
2
1
1
C8045
OPS
SC10U6D3V3MX-DL-GP
2
C8043
OPS
SC10U6D3V3MX-DL-GP
1
C8042
OPS
SC10U6D3V3MX-DL-GP
2
1
C8041
OPS
SC10U6D3V3MX-DL-GP
2
1
C8040
OPS
SC10U6D3V3MX-DL-GP
2
1
C8039
OPS
SC10U6D3V3MX-DL-GP
2
1
C8038
SC10U6D3V3MX-DL-GP
OPS
SC10U6D3V3MX-DL-GP
OPS
SC10U6D3V3MX-DL-GP
2
1
C8010
OPS
SC22U6D3V3MX-1-DL-GP
OPS
SC22U6D3V3MX-1-DL-GP
2
C8017
C8024
OPS
SC4D7U6D3V3KX-DLGP
C8026
OPS
SC4D7U6D3V3KX-DLGP
C8030
OPS
SC4D7U6D3V3KX-DLGP
C8031
OPS
SC4D7U6D3V3KX-DLGP
SC4D7U6D3V3KX-DLGP
C8032
2
1
Near GPU
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
M13
M15
M17
N10
N12
N14
N16
N18
P11
P13
P15
P17
P2
P23
P26
P5
R10
R12
R14
R16
R18
T11
T13
T15
T17
U10
U12
U14
U16
U18
U2
U23
U26
U5
V11
V13
V15
V17
Y2
Y23
Y26
Y5
D
C
GND
GND
AA7
AB7
N17S-G1-A1-GP
1D8V_VGA_S0
Near GPU
Under GPU
1
2
1
2
1
2
1
1
2
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
C8004
SC4D7U6D3V3KX-DLGP
OPS
C8036
OPS
OPS
SC1U10V2KX-1DLGP
W1
W2
W3
W4
OPS
SCD1U16V2KX-3DLGP
C8044
POWER CHANNELS
V1
V2
Near GPU
C8035
CONFIGURABLE
A
1V_VGACORE1_S0
Under GPU
* nc on substrate
G1
G2
G3
G4
G5
G6
G7
OPS
1D8V_AON_S0
XVDD
XVDD
SCD1U16V2KX-3DLGP
SCD1U16V2KX-3DLGP
OPS
GPCPLL_AVDD
1
V5
V6
C8037
2
F11
G8
G9
G10
G12
VDD18
VDD18
1V8_AON
1V8_AON
B
1
GM108
3V3_AON
3V3_AON
OPS
3.3V +/- 5%
85mA
2
NC#AD10
NC#AD7
2
1
2
AD10
AD7
1
Under GPU
2
1D8V_VGA_PLL
SC4D7U6D3V3KX-DLGP
14/14 XVDD/VDD33
C8003
C8028
SC1U10V2KX-1DLGP
14 OF 14
GPU1C
OPS
SCD1U16V2KX-3DLGP
OPS
C8029
SCD1U16V2KX-3DLGP
C8034
B
XVDD
XVDD
A
<Core Design>
XVDD
XVDD
XVDD
XVDD
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
N17S-G1-A1-GP
https://realschematic.com
Title
Size
Custom
Date:
5
4
3
2
GPU(5/5)PWR/GND
MOCKINGBIRD_TGL
Document Number
Saturday, August 01, 2020
Sheet
1
80
Rev
A00
of
105
5
4
3
2
1
SSID = VRAM
Place close VDD ball
1
2
[17,40,55]
FBA_CMD8
FBA_CMD12
FBA_CMD0
FBA_CMD15
FBA_CMD5
J4
G3
G12
L3
L12
FBA_CLK0P
FBA_CLK0N
FBA_CMD14
J12
J11
J3
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
D2
D13
P13
P2
J2
2
OPS
1
1
2
OPS
1
R8110
2
FBA_SEN0
FBA_ZQ0
FBA_MF1
J10
J13
J1
FBA_WCK01
FBA_WCK01#
D4
D5
FBA_WCK23
FBA_WCK23#
P4
P5
2
1
2
1
1
2
2
2
2
1
1
1
1
2
1
2
1
2
1
2
1
2
1
2
Place close VDDQ ball
Un-termination
50%
0.749V
High
Termination
70%
1.0617V
Low
OPS
OPS
1
1
1
OPS
OPS
2
OPS
2
1
C8112
OPS
2
1
C8111
OPS
2
1
C8110
OPS
2
1
1
C8114
OPS
1D35V_VGA_S0
2
GPU_GPIO10
2
Voltage
2
C8113
FBVREF Termination
1
1D35V_VGA_S0
2
1
2
1
2
1
1
2
2
Place close VDDQ ball
C
A5
U5
2 OF 2
OPS
A8/A7
A9/A1
A10/A0
A11/A6
A12/RFU#J5/NC#J5
BA0/A2
BA1/A5
BA2/A4
BA3/A3
ABI#
RAS#
CS#
CAS#
WE#
CK
CK#
CKE#
DBI0#
DBI1#
DBI2#
DBI3#
RESET#
SEN
ZQ
MF
WCK01
WCK01#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
EDC0
EDC1
EDC2
EDC3
WCK23
WCK23#
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
C2
C13
R13
R2
FBA_EDC0
FBA_EDC1
FBA_EDC2
FBA_EDC3
Byte 0
0~7
B
Byte 1
8~15
Byte 2
16~23
Byte 3
24~31
H5GQ2H24AFR-T2C-GP
FBA_CLK0P
FBA_CLK0N
A
R8102
40D2R2F-GP
SIO_SLP_S3#
OPS
R8101
40D2R2F-GP
OPS
<Core Design>
FBA_CLK0_MIDPT
1
1D8V_EN#
OPS
C8101
SCD01U25V2KX-3DLGP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2
[40]
DY
1
FBA_CMD13
H11
K10
K11
H10
1
[78,81]
FBA_CMD2
FBA_CMD4
FBA_CMD3
FBA_CMD1
2
FBA_CMD14
K4
H5
H4
K5
J5
2
[78,81]
FBA_CMD6
FBA_CMD11
FBA_CMD10
FBA_CMD7
FBA_CMD9
FBA_CMD13
R8111
1KR2J-1-GP
A
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_WCK23
FBA_WCK23#
FBA_WCK01
FBA_WCK01#
OPS
Normal(MF=0)
R8108
121R2F-GP
[78]
[78]
[78]
[78]
OPS
72.05224.A0U
[78,81]
FBA_EDC0
FBA_EDC1
FBA_EDC2
FBA_EDC3
OPS
VREFD
VREFD
[78,81]
0R0402-PAD-7-NP-GP
[78]
[78]
[78]
[78]
OPS
H5GQ2H24AFR-T2C-GP
B
[78]
[78]
[78]
[78]
OPS
2N7002KDW-1-GP
75.27002.F7C
VRAM1B
FBA_D[0..31]
SIO_SLP_S3#
4
SCD1U16V2KX-3DLGP
C8119
FBA_D[0..31]
5
SCD1U16V2KX-3DLGP
C8118
FBA_CMD8
FBA_CMD15
FBA_CMD5
FBA_CMD12
FBA_CMD0
OPS
SCD1U16V2KX-3DLGP
C8117
[78,81]
[78,81]
[78,81]
[78,81]
[78,81]
3
SCD1U16V2KX-3DLGP
C8116
FBA_CMD3
FBA_CMD1
FBA_CMD2
FBA_CMD4
VPP/NC#A5
VPP/NC#U5
2
SCD1U16V2KX-3DLGP
C8125
[78,81]
[78,81]
[78,81]
[78,81]
OPS
VREFC
1D8V_EN#
FBVREF%
D
FBA_VREF_FET_L
SC1U10V2KX-1DLGP
FBA_CMD10
FBA_CMD7
FBA_CMD6
FBA_CMD11
FBA_CMD9
SC820P50V2KX-1-DL-GP
[78,81]
[78,81]
[78,81]
[78,81]
[78,81]
A10
U10
GPIO10_FBVREF
6
SC1U10V2KX-1DLGP
J14
C8126
FBA_VREF_FET_L
Type
OPS
1D35V_VGA_S0
1
SC1U10V2KX-1DLGP
FBA_VREFC0
Place close VDD ball
SC1U10V2KX-1DLGP
[78,81]
OPS
Q8101
SC10U6D3V3MX-DL-GP
FBA_D[0..31]
C
C8109
OPS
SCD1U16V2KX-3DLGP
C8124
[78,81]
C8107
OPS
SCD1U16V2KX-3DLGP
C8123
FBA_D[0..31]
OPS OPS
C8106
OPS
SCD1U16V2KX-3DLGP
C8122
FBA_CMD13
A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
U1
U3
U12
U14
SCD1U16V2KX-3DLGP
C8121
GPIO10_FBVREF
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
FBA_VREFC0
C8105
OPS
SCD1U16V2KX-3DLGP
C8115
FBA_VREFC0
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
OPS
OPS
SCD1U16V2KX-3DLGP
C8120
[79]
[78,81]
B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14
R8106
549R2F-GP
Note:ZZ.27002.F7C01
[82]
1D35V_VGA_S0
C8104
SCD1U16V2KX-3DLGP
C8108
FBA_CLK0P
FBA_CLK0N
FBA_CMD14
1D35V_VGA_S0
SC1U10V2KX-1DLGP
[78]
[78]
[78,81]
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1D35V_VGA_S0
SC1U10V2KX-1DLGP
FBA_CMD8
FBA_CMD12
FBA_CMD0
FBA_CMD15
FBA_CMD5
OPS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10
SC1U10V2KX-1DLGP
[78,81]
[78,81]
[78,81]
[78,81]
[78,81]
C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10
Frame Buffer Patition A-Lower Half
1 OF 2
SC1U10V2KX-1DLGP
FBA_CMD2
FBA_CMD4
FBA_CMD3
FBA_CMD1
VRAM1A
R8104
931R2F-1-GP
[78,81]
[78,81]
[78,81]
[78,81]
Place close VDD ball
1D35V_VGA_S0
1D35V_VGA_S0
R8107
1K33R2F-GP
FBA_CMD6
FBA_CMD11
FBA_CMD10
FBA_CMD7
FBA_CMD9
SC10U6D3V3MX-DL-GP
D
[78,81]
[78,81]
[78,81]
[78,81]
[78,81]
Title
GPU-VRAM1,2 (1/4)
Size
Document Number
Custom
MOCKINGBIRD_TGL
Date:
5
https://realschematic.com
4
3
2
Saturday, August 01, 2020
1
Sheet
81
Rev
A00
of
105
5
4
3
2
1
SSID = VRAM
[78,82]
1D35V_VGA_S0
2
[78]
[78]
[78]
[78]
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
R8206
40D2R2F-GP
OPS
FBA_EDC4
FBA_EDC5
FBA_EDC6
FBA_EDC7
R8208
40D2R2F-GP
C8201
SCD01U25V2KX-3DLGP
OPS
FBA_CMD26
FBA_CMD23
FBA_CMD22
FBA_CMD27
FBA_CMD25
K4
H5
H4
K5
J5
FBA_CMD19
FBA_CMD17
FBA_CMD18
FBA_CMD20
H11
K10
K11
H10
FBA_CMD24
FBA_CMD31
FBA_CMD21
FBA_CMD28
FBA_CMD16
J4
G3
G12
L3
L12
FBA_CLK1P
FBA_CLK1N
FBA_CMD30
J12
J11
J3
FBA_DQM7
FBA_DQM6
FBA_DQM5
FBA_DQM4
D2
D13
P13
P2
FBA_CLK1_MIDPT
FBA_CMD29
OPS
2
[78]
[78]
[78]
[78]
1
FBA_WCK67
FBA_WCK67#
FBA_WCK45
FBA_WCK45#
1
FBA_CMD29
[78]
[78]
[78]
[78]
2
FBA_CMD30
[78,82]
2
[78,82]
1
2
1
1
2
1
2
1
2
1
2
1
2
1
OPS
1
1
OPS
OPS
2
OPS
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
2
OPS
Mirrored(MF=1)
VRAM4B
1
FBA_CMD24
FBA_CMD31
FBA_CMD21
FBA_CMD28
FBA_CMD16
72.05224.A0U
SCD1U16V2KX-3DLGP
C8225
[78,82]
[78,82]
[78,82]
[78,82]
[78,82]
OPS
H5GQ2H24AFR-T2C-GP
SCD1U16V2KX-3DLGP
C8223
FBA_CMD19
FBA_CMD17
FBA_CMD18
FBA_CMD20
A5
U5
SCD1U16V2KX-3DLGP
C8222
[78,82]
[78,82]
[78,82]
[78,82]
VPP/NC#A5
VPP/NC#U5
VREFD
VREFD
1D35V_VGA_S0
SCD1U16V2KX-3DLGP
C8221
FBA_CMD26
FBA_CMD23
FBA_CMD22
FBA_CMD27
FBA_CMD25
VREFC
C
Place close VDDQ ball
1D35V_VGA_S0
SCD1U16V2KX-3DLGP
C8209
B
[78,82]
[78,82]
[78,82]
[78,82]
[78,82]
[78,82]
A10
U10
SC820P50V2KX-1-DL-GP
OPS
FBA_D[32..63]
J14
C8202
C8217
OPS
Place close VDD ball
SCD1U16V2KX-3DLGP
C8210
1
FBA_VREFC0
C8216
OPS
1
Low
C8215
OPS
2
1.0617V
70%
OPS
Place close VDDQ ball
1
High
1
GPU_GPIO10
0.749V
2
Termination
Voltage
50%
2
FBVREF%
Un-termination
SCD1U16V2KX-3DLGP
C8226
[78,82]
OPS
SC1U10V2KX-1DLGP
Type
FBA_D[32..63]
OPS
D
SCD1U16V2KX-3DLGP
C8220
FBA_CMD29
OPS
SC1U10V2KX-1DLGP
[78,82]
C
C8219
OPS
SC1U10V2KX-1DLGP
FBVREF Termination
OPS
1D35V_VGA_S0
C8206
OPS
Place close VDD ball
SC1U10V2KX-1DLGP
FBA_VREFC0
OPS
SC1U10V2KX-1DLGP
[81]
OPS
C8205
OPS
SCD1U16V2KX-3DLGP
C8214
FBA_CLK1P
FBA_CLK1N
FBA_CMD30
1D35V_VGA_S0
A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
U1
U3
U12
U14
C8204
OPS
SC1U10V2KX-1DLGP
[78]
[78]
[78,82]
Place close VDD ball
SCD1U16V2KX-3DLGP
C8213
FBA_CMD24
FBA_CMD28
FBA_CMD16
FBA_CMD31
FBA_CMD21
C8224
OPS
SCD1U16V2KX-3DLGP
C8212
[78,82]
[78,82]
[78,82]
[78,82]
[78,82]
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
SC10U6D3V3MX-DL-GP
FBA_CMD18
FBA_CMD20
FBA_CMD19
FBA_CMD17
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
OPS
C8218
[78,82]
[78,82]
[78,82]
[78,82]
B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14
B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10
SCD1U16V2KX-3DLGP
C8211
FBA_CMD22
FBA_CMD27
FBA_CMD26
FBA_CMD23
FBA_CMD25
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SC1U10V2KX-1DLGP
1D35V_VGA_S0
[78,82]
[78,82]
[78,82]
[78,82]
[78,82]
OPS
SC1U10V2KX-1DLGP
[78,82]
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
SC10U6D3V3MX-DL-GP
FBA_D[32..63]
C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10
1 OF 2
C8207
D
VRAM4A
1
1D35V_VGA_S0
Frame Buffer Patition A-Upper Half
2
FBA_D[32..63]
1
R8209
2
1
0R0402-PAD-7-NP-GP
OPS
R8213
121R2F-GP
2
1D35V_VGA_S0
2
R8210
OPS
J2
FBA_SEN2
FBA_ZQ3
FBA_MF4
1
1KR2J-1-GP
FBA_WCK67
FBA_WCK67#
J10
J13
J1
FBA_WCK45
FBA_WCK45#
P4
P5
D4
D5
2 OF 2
A8/A7
A9/A1
A10/A0
A11/A6
A12/RFU#J5/NC#J5
OPS
BA0/A2
BA1/A5
BA2/A4
BA3/A3
ABI#
RAS#
CS#
CAS#
WE#
CK
CK#
CKE#
DBI0#
DBI1#
DBI2#
DBI3#
RESET#
SEN
ZQ
MF
WCK01
WCK01#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
EDC0
EDC1
EDC2
EDC3
WCK23
WCK23#
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
FBA_D54
FBA_D55
FBA_D52
FBA_D50
FBA_D48
FBA_D49
FBA_D51
FBA_D53
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D35
FBA_D33
FBA_D34
FBA_D32
FBA_D36
FBA_D37
FBA_D38
FBA_D39
C2
C13
R13
R2
FBA_EDC7
FBA_EDC6
FBA_EDC5
FBA_EDC4
B
Byte 7
56~63
Byte 6
48~55
Byte 5
40~47
Byte 4
32~39
H5GQ2H24AFR-T2C-GP
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
GPU-VRAM3,4 (2/4)
Size
Document Number
Custom
MOCKINGBIRD_TGL
Date:
5
https://realschematic.com
4
3
2
Saturday, August 01, 2020
1
Sheet
82
Rev
A00
of
105
5
4
3
2
1
D
D
C
C
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
GPU-VRAM5,6 (3/4)
https://realschematic.com
Size
A3
Date:
5
4
3
2
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
A00
83
of
105
5
4
3
2
1
D
D
C
C
B
B
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
A
A
Title
GPU-VRAM7,8 (4/4)
Size
A4
https://realschematic.com
Document Number
Date:
5
4
3
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
2
A00
84
of
1
105
5
4
OFFPAGE-Signal
[79]
OFFPAGE-GAP
2 R8544 1 PWR_VGA_NVVDDS_PSI
0R0402-PAD-7-NP-GP
VGA_CORE_PSI
3
2
1
VGA_CORE_VID
PG8553
GAP-CLOSE-PWR-3-GP
2
1. Check EE side
2. Modify DAT
R8542
[76]
VGACORE_VDD_SENSE_1
2
[76]
VGACORE_GND_SENSE_1
2
OPS
VGA : N17S-G3/G5
EDP-Peak : 69.9A
1
1
1
PG8551
GAP-CLOSE-PWR-3-GP
PWR_VGA_NVVDDS_VSEN1_P
2
1
3D3V_S0
0R2J-2-GP
DY
1
PWR_VGA_NVVDDS_VSEN1_N
PG8554
GAP-CLOSE-PWR-3-GP
2
0R2J-2-GP
1
OPS
PH on EE side
PWR_VGA_NVVDDS_PG
1D8V_AON_S0
PWR_VGA_NVVDDS_PG
1
PWR_VGA_NVVDDS_PG
PR8559
[85,86]
OPS 6K04R2F-GP
2
2
PR8557
100KR2J-1-GP
2
PG8555
GAP-CLOSE-PWR-3-GP
PWR_VGA_NVVDDS_PG
[85,86]
20200221(DVT1)
changes to 3D3V_S0
D
R8543
1
D
1
[79]
PWR_VGA_NVVDDS_VID
0R0402-PAD-7-NP-GP
1
RT8816B For NVVDDS
19V_DCBATOUT
PWR_DCBATOUT_DGPUA
PG8552
GAP-CLOSE-PWR-3-GP
PH on EE side
2 R8545
2
PG8556
GAP-CLOSE-PWR-3-GP
PWR_DCBATOUT_DGPUA
PWR_VGA_NVVDDS_PSI
1
PR8563
1
8
PC8555
4
DGPU_PWROK
PC8560
SC1KP50V2KX-1DLGP
[19,24]
GND
1
2
74LVC1G08GW-1-GP
PC8562
SCD1U25V2KX-1-DL-GP
1
DY
2
OPS
5
PWR_VGA_NVVDDS_EN
3
VID
2
2
OPS
PWR_VGA_NVVDDS_REFIN
PR8568
4K32R2F-GP
7
15
PWR_VGA_NVVDDS_BOOT2
BOOT2
VREF
UGATE2
LGATE2
14
PWR_VGA_NVVDDS_HG2
PR8564
160KR2F-GP
16
PWR_VGA_NVVDDS_PHASE2
17
PWR_VGA_NVVDDS_LGATE2
10
PWR_VGA_NVVDDS_VSEN1_N
REFIN
RT8816BGQW-GP
VSNS
11
PWR_VGA_NVVDDS_VSEN1_P
3
PWR_VGA_NVVDD_OR#
[86]
2
1
PWR_VGA_NVVDDS_REFIN_R
PC8567
SCD01U25V2KX-3DLGP DY
1
2
1
2
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
C
1V_VGACORE1_S0
SS setting
OPS
PT8551 OPS
PT8553 OPS
79.33719.20C
2nd = 077.53377.0001
2
PT8554 79.33719.20C
79.33719.20C
2nd = 077.53377.0001
Place Near GPU (NVVDDS)
1X330uF (Poscap) - PT8511 (Page85)
OPS
PC8564
SC33P50V2JN-3DLGP
DY
2nd = 077.53377.0001
PR8577
100R2F-L1-GP-U
1
1
PWR_VGA_NVVDD_OR#
[86]
DY
2
OPS
1
OPS
1
1V_VGA_EN_R
OPS
DY
PR8570
16K5R2F-2-GP
PC8565
SC4700P50V2KX-1DLGP
2
OPS D2
2
PC8559
PC8566
SC33P50V2JN-3DLGP
PWR_DCBATOUT_DGPUB
1V_VGACORE1_S0
DY
2
S2
G1
1
DY
2
1
PWR_VGA_NVVDDS_VSEN1_N
R8529
PU8554
OPS10KR2J-3-GP
Q8504
1
1
PWR_VGA_NVVDD_OR#
G
2
3
4
10
PU8552 PU855
For G3: 075.07321.0073
For G5: 075.07362.0073
OPS
PC8568
1
1
PC8573
OPS
2
2
OPS
PC8551
SC10U25V5KX-DL-GP
PR8572
309R2F-GP
SCD1U25V2KX-1-DL-GP
OPS
SC10U25V5KX-DL-GP
1D8V_VGA_S0
2
PJT138KA-GP
075.00138.0A7C
2nd = 075.00139.007C
3rd = 075.00138.0F7C
1
2
2
4
G2
OPS
S1
PC8563
SC33P50V2JN-3DLGP
2
2
5
GPIO5_GC6_PWR_EN
D1
PC8561
SC33P50V2JN-3DLGP
1
1
[79,86]
6
1
2
Q8509
PWR_VGA_NVVDD_OR#
PC8558
PR8569
100R2F-L1-GP-U
1
OPS
C8501
DY
160K ohm for OCP around 96.2A setting
1
074.08816.0A73
RGND
OPS
OCP setting
REFADJ
PWR_VGA_NVVDDS_REFIN
R8541
10KR2J-3-GP
OPS
068.R1510.1171
2nd = 068.R1510.1141
OPS
EN
2
OPS
PWR_VGA_NVVDDS_OCSET
PSI
PHASE2
1
PWR_VGA_NVVDDS_LGATE1
SE330U2VDM-4-GP
6
PWR_VGA_NVVDDS_PHASE1
12
SE330U2VDM-4-GP
8
PWR_VGA_NVVDDS_REFADJ
OCSET/SS
20
19
SE330U2VDM-4-GP
PWR_VGA_NVVDDS_VREF
PR8567
6K19R2F-GP
PWR_VGA_NVVDDS_REFADJ_R
3D3V_S0
4
PWR_VGA_NVVDDS_VID
PR8566
OPS 20K5R2F-GP
For VGA_CORE sequence
EE need check
PWR_VGA_NVVDDS_PSI
LGATE1
PGOOD
1
73.01G08.L04
2nd = 073.7SZ08.000G
3RD = 73.01G08.IHG
4th = 73.7SZ08.DAH
13
2
1
OPS Y
PHASE1
PWR_VGA_NVVDDS_PG
1
2
A
UGATE1
TON
1
5
1V_VGACORE1_S0
PL8552
IND-D15UH-33-GP
1
3
VCC
PWR_VGA_NVVDDS_HG1
2
C
2
B
9
PG8562
GAP-CLOSE-PWR-3-GP
U8502
2
1
R8531 2 DGPU_PWROK_L 1
0R0402-PAD-7-NP-GP
2 1D35V_PGOOD_L 2
0R0402-PAD-7-NP-GP
1 R8530
Cyntec 6.8mmx7.6mmx3.0mm
DCR: 0.9m ohm +/-7%
Idc : 37A , Isat : 41A
OPS
1
1D35V_PGOOD
1
OPS
SCD1U10V1KX-DL-GP
[86]
1V_VGA_S0_PG
BOOT1
PR8551
PC8556
2D2R3-1-U-GP
SCD1U25V2KX-1-DL-GP
PWR_VGA_NVVDDS_BOOT11
2 PWR_VGA_NVVDDS_BOOT1_A 1
2
2
PWR_VGA_NVVDDS_TON
3D3V_S0
[86]
PVCC
FDMS3600-02-RJK0215-COLAY-GP
1st = 075.07321.0073
1
1
1
GND
2
PU8551
18
2
2
OPS
1
1
VGA : N17S-G3/G5
EDP-Peak : 69.9A
83.88A<OCP<97.86A
2
2
OPS
PC8553
OPS
2
PR8561
2D2R3-1-U-GP
1
1
2
19V_DCBATOUT
1
PG8561
GAP-CLOSE-PWR-3-GP
21
2
OPS
ID:31/54A ,
Rdson: 6.8~8.6/2.8~3.5m (Q1/Q2)
OPS
SC1U10V2KX-1DLGP
OPS
PR8562
499KR2F-1-GP
7
6
5
PC8552
OPS
9
2
1
1
2
PG8560
GAP-CLOSE-PWR-3-GP
PU8552 PU855
For G3: 075.07321.0073
For G5: 075.07362.0073
2
3
4
10
PU8552
PWR_VGA_NVVDDS_PVCC
1
1
2
1
OPS 2D2R3-1-U-GP
PC8554
SCD1U25V2KX-1-DL-GP
PWR_VGA_NVVDDS_TON_1
1
2
DY
2
2
2
PR8556
1
2
2
PG8559
GAP-CLOSE-PWR-3-GP
TC8501
ST22U25VBM-GP
PG8558
GAP-CLOSE-PWR-3-GP
PC8572
OPS
5V_S0
SC10U25V5KX-DL-GP
OPS 12K1R2F-L1-GP
1
SCD1U25V2KX-1-DL-GP
2
SC10U25V5KX-DL-GP
PC8557
SCD01U25V2KX-3DLGP DY
PG8557
GAP-CLOSE-PWR-3-GP
2
EE need check
PWR_DCBATOUT_DGPUB
1
19V_DCBATOUT
1
1
2
9
D
OPS
PWR_VGA_NVVDDS_EN
8
S
7
6
5
OPS
ID:31/54A ,
Rdson: 6.8~8.6/2.8~3.5m (Q1/Q2)
2N7002K-2-GP
1st = 075.07321.0073
PWR_VGA_NVVDDS_PHASE2
1V_VGACORE1_S0
PL8551
IND-D15UH-33-GP
1
PWR_VGA_NVVDDS_LGATE2
B
Cyntec 6.8mmx7.6mmx3.0mm
DCR: 0.9m ohm +/-7%
Idc : 37A , Isat : 41A
OPS
2
068.R1510.1171
2nd = 068.R1510.1141
DY
PC8570
DY
1
OPS
PC8571
2
OPS
PWR_VGA_NVVDDS_HG2
1
PR8573
PC8569
2D2R3-1-U-GP
SCD1U25V2KX-1-DL-GP
PWR_VGA_NVVDDS_BOOT21
2 PWR_VGA_NVVDDS_BOOT2_A 1
2
2
B
FDMS3600-02-RJK0215-COLAY-GP
84.2N702.J31
2nd = 084.27002.0N31
3rd = 084.27002.0L31
4th = 084.07002.0C31
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
A
A
<Core Design>
Wistron Corporation
https://realschematic.com
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
GPU (RT8816A_VGA)
Size
A1
Date:
5
4
3
2
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
1
Sheet
85
A00
of
105
5
4
3
2
1
Main Func = dGPU
Main Func = dGPU
dGPU Power Discharge Circuit
3D3V_AUX_S5
1
4
D2
2
S1
G1
S
G D
1D8V_AON_S0
11
1V_VGA_EN_R
1V_VGA_S0_DISCHG
15
1D8V_AON_S0
C8607
1V_VGACORE1_S0
Need to fine tune.
R8624
100R2J-2-GP
Q8605
OPS
3D3V_AUX_S5
G
OPS
2
S
OPS
1
1D35V_VGA_EN#
1D35V_VGA_S0
100KR2J-1-GP
1D8V_AON_S0 to 1D8V_VGA_S0
S1
1
5
G2
G1
2
4
S2
OPS D2
3
D1
1
4
1
5
4
S2
G2
2
1D35V_VGA_EN
R8625
100R2J-2-GP
OPS
2
3
2
OPS
75.27002.F7C
2nd = 075.27002.0E7C
1
2
Q8612
6
5
6
100KR2J-1-GP
Q8614
2N7002KDW-1-GP
1D8V_VGA_EN_OR#
OPS
1D35V_VGA_S0_DISCHG
Need to fine tune.
R8634
10KR2J-3-GP
GPIO5_GC6_PWR_EN
R8622
100R2J-2-GP
OPS
1D8V_AON_S0
1
OPS
[79,85,86]
1D8V_AON_S0
DGPU_PWR_EN#
1
OPS
075.00138.0A7C
2nd = 075.00139.007C
3rd = 075.00138.0F7C
S1
2
3D3V_S0
Q8616
PJT138KA-GP
D2
84.2N702.J31
2nd = 084.27002.0N31
3rd = 084.27002.0L31
4th = 084.07002.0C31
D1
6
Need to fine tune.
2N7002K-2-GP
3D3V_AUX_S5
R8613
1D35V_VGA_S0
R8616
VGA_CORE_DISCHG
D
G1
PWR_VGA_NVVDD_OR#
3
[85]
2
OPS
1
C8606
OPS
VGA_CORE
1
1D8V_VGA_S0
074.02898.0093
074.05209.0093
3rd = 074.07110.0093
1
R8618
10R2J-2-GP-U
OPS
1D8V_VGA_S0
SC1U10V2KX-1DLGP
2
D
OPS
3
SC470P50V2KX-3DLGP
SC1500P50V2KX-2-DL-GP
OPS
1V_VGA_S0
S
2
1
2
2
1
OPS 22
1
SC10U6D3V3MX-DL-GP
1
C8610
C8612
OPS C8613
C1U10V2KX-1DLGP
2
GND
12
10
13
14
8
9
G2898KD1U-GP
C8608S
DY
EN1
EN2
THERMAL_PAD
DGPU_PWR_EN_R
1 PR8621 2
0R0402-PAD-7-NP-GP
DGPU_PWR_EN
OUT1#13
OUT1#14
OUT2#8
OUT2#9
SC10U6D3V3MX-DL-GP
[19,86]
CT1
CT2
OPS
IN1#1
IN1#2
IN2#6
IN2#7
3
5
C8605S
OPS
C1U10V2KX-1DLGP
DY
SC1U10V2KX-1DLGP
1
1D8V_VGA_EN
C8609
VBIAS
1
2
6
7
1
4
5V_S0
075.00138.0A7C
2nd = 075.00139.007C
3rd = 075.00138.0F7C
2
1
2
C1U10V2KX-1DLGP
DY
VGA_CT_1
AON_CT_2
G
2
U8601
C8611S
1
R8602 2
0R0603-PAD-7-NP-GP
Q8615
PJT138KA-GP
2
1
1D8V_S5
3D3V_1D8V_S0
D1
6
D
1
D
1V_VGA_S0
PWR_VGA_NVVDD_PG#
2
R8612
100KR2J-1-GP
5
OPS
S2
1
G2
[DG-07158-001 Rev03]Power up sequence:
1.8V ==> NVVDD (VGA_CORE) ==> PEX_VDD (1.05V) ==> FBVDD/Q (1.35V)
1D8V_AON_S0_DISCHG
PWR_VGA_NVVDDS_PG
[85,86]
1D8V_VGA_EN_OR#
[19,86]
DGPU_PWR_EN
PJT138KA-GP
075.00138.0A7C
2nd = 075.00139.007C
3rd = 075.00138.0F7C
1D8V_VGA_S0
1D8V_VGA_S0
Need to fine tune.
1
1
1D8V_AON_S0
R8623
OPS
1D8V_VGA_EN_OR
D
100R2J-2-GP
G
1D8V_VGA_S0_DISCHG
D
OPS
1D8V_VGA_EN
1 PR8603 2
0R0402-PAD-7-NP-GP
OPS
2
G
Q8603
1D8V_VGA_EN_OR#
2
1D8V_VGA_EN_OR#
R8637
10KR2J-3-GP
OPS
Q8602
S
S
2N7002K-2-GP
2N7002K-2-GP
84.2N702.J31
2nd = 084.27002.0N31
3rd = 084.27002.0L31
4th = 084.07002.0C31
84.2N702.J31
2nd = 084.27002.0N31
3rd = 084.27002.0L31
4th = 084.07002.0C31
RT5797 for 1V_VGA_S0
C
PWR_1V_PVDD
3D3V_S0
PG8605
OPS
Y
A
1
2
1
2
1V_VGA_EN_Y
1V_VGA_EN_R
1
1
34K8R2F-1-GP
R1
OPS
OPS
[85]
3D3V_S0
Close Pin1
PWR_1V_FB
R2
PR8625
OPS 10KR2J-3-GP
PR8620
51KR2F-L-GP
PWR_VGA_S0_PG
1 PR8623 2 1V_VGA_S0_PG
0R0402-PAD-7-NP-GP
1V_VGA_S0_PG
[85]
2
GAP-CLOSE-PWR-3-GP
PG8607
1
PC8632
2
GAP-CLOSE-PWR-3-GP
PC8628
OPS
OPS
PC8631
OPS
SC22U6D3V3MX-1-DL-GP
2
PG8608
2
SC22U6D3V3MX-1-DL-GP
C8603
DY
SCD1U16V2KX-3DLGP
1 R8615 2
0R0402-PAD-7-NP-GP
OPS
Vo=0.6x(1+R1/R2)
=0.6x(1+34.8/51)
=1.009
RT5797ALGQW-GP
4
GND
74LVC1G08GW-1-GP
19V_DCBATOUT
1
IND-1UH-344-GP
068.1R010.1661
2nd = 068.1R010.1911
PR8613
1
A
3
73.01G08.L04
2nd = 073.7SZ08.000G
3RD = 73.01G08.IHG
4th = 73.7SZ08.DAH
1V_VGA_S0
PL8602
1V_VGA_EN_R
PWR_1V_PHASE
9
1
VCC
2
PWR_VGA_NVVDDS_PG
PGND
2
[85,86]
SGND
EN
LX
NC#5
5
SC22P50V2JN-4DLGP
2nd = 084.01012.0031
FB
PG
VIN
PGND
OPS
B
2
3D3V_S0
U8604
1
8
7
6
5
1
Y
GND
73.01G08.L04
2nd = 073.7SZ08.000G
3RD = 73.01G08.IHG
4th = 73.7SZ08.DAH
PWR_1V
1
2
3
4
1
OPS
PWR_1V_FB
PWR_VGA_S0_PG
74LVC1G08GW-1-GP
OPS
Q8601 084.00138.0A31
PJA138KA-GP
TDC=0.2A
ICCMAX=0.3A
0.36A<OCP<0.48A
PU8603
GPIO5_GC6_PWR_1V
4
2
3
GPIO5_GC6_PWR_B
5
1
GAP-CLOSE-PWR-3-GP
1
G
VCC
A
GAP-CLOSE-PWR-3-GP
PG8606
2
OPS
2
D
1D8V_AON_S0
B
PC8629
1
1
GPIO5_GC6_PWR_EN
2
1
[79,85,86]
10KR2J-3-GP
1
DGPU_PWR_EN
PC8627
DY
2
OPS
S
[19,86]
2
K
2
U8605
R8635
PC8630
OPS
SC1U10V2KX-1DLGP
074.05797.0073
2nd = 074.02822.0A43
3D3V_S0
SC10U6D3V3MX-DL-GP
PJSD24W-GP
1st = 83.PJSD2.0AF
2nd = 083.04024.0AA1
DY
For tuning VGA_CORE sequence.
SC10U6D3V3MX-DL-GP
PD8602
3D3V_S0
1
2
2
C
1D35V_VGA_S0
PWR_DCBATOUT_1D35V
1D35V_PWR
1D35V_VGA_S0
PG8614
1
2
PG8621
1
GAP-CLOSE-PWR-3-GP
PG8615
1
2
GAP-CLOSE-PWR-3-GP
2
PG8610
1
GAP-CLOSE-PWR-3-GP
2
GAP-CLOSE-PWR-3-GP
PG8609
1
2
GAP-CLOSE-PWR-3-GP
PG8611
1
SY8288RAC for 1D35V
R8604
1MR2J-1-GP
2
PWR_1D35V_IMAX
PWR_1D35V_VFB1
16A
Float
12A
Low
8A
OPS
GND
GND
GND
GND
PR8627
15KR2F-GP
7
8
18
21
PWR_1D35V_BYP
1
BS
PG
EN
ILMT
FB
BYP
OPS
OPS
PC8613
OPS
1
1
PC8611
PC8614
OPS
2
OPS
1
1
PC8621
2
1
OPS
2
PWR_1D35V_PHASE
PWR_1D35V_PGOOD
PWR_1D35V_LDO_P5
2
6
19
20
10
12
16
PC8620
1
NC#10
NC#12
NC#16
PC8602
OPS SC330P50V2KX-3-DL-GP
OPS
PC8618
SC1U10V2KX-1DLGP
R1
3D3V_S0
PR8634
1
1
074.08288.0043
OCP setting
68.1R010.20R
2nd = 068.1R010.1111
PG8613
GAP-CLOSE-PWR-3-GP
LX#6
LX#19
LX#20
IN#2
IN#3
IN#4
IN#5
SY8288RAC-GP
High
B
1D35V_PWR
2
2
VCC
OPS
COIL-1UH-73-GP
1
1
2
1
1
DY
PR8632
0R2J-2-GP
1
9
11
13
14
15
1
2
Vo=0.6x(1+R1/R2)
=0.6x(1+150/120)
=1.35V
0R0402-PAD-7-NP-GP
2
2
1
GC6_20
2SCD1U25V2KX-1-DL-GP
2
1
2
75.00054.A7D
2nd = 75.00054.T7D
PWR_1D35V_BOOT
1
OPS
2
3
4
5
PC8616
PC8619
2
1
DY
PWR_1D35V_BOOT_R
PU8602
17
PWR_1D35V_EN
2
PWR_1D35V_VFB
1
1 PR8631 2
0R0402-PAD-7-NP-GP
VENH:0.8V
1V_VGA_S0_PG
2
1
0R0402-PAD-7-NP-GP
1D35V_VGA_EN
SCD1U16V2KX-3DLGP
VENH:3.3V
2
K
A
1D35V_PGOOD
2
1
2
3
BAT54C-12-GP
1 PR8633
0R0603-PAD-7-NP-GP
SCD1U16V2KX-3DLGP
[85]
D8601
2
Design Current=3.2A
PL8603
PWR_1D35V_BOOT
SC22U6D3V3MX-1-DL-GP
1
GC6_20
PWR_1D35V_PGOOD
1 PR8630 2
Cyntec 5 x 5 x
3.0mm
DCR: 13~14mOhm
Idc :7A , Isat : 11A
PC8617
SC2D2U10V3KX-1DLGP-U
OPS
SC22U6D3V3MX-1-DL-GP
GC6_FB_EN
PC8612
SC22U6D3V3MX-1-DL-GP
[18,79]
1D35V_PGOOD
DY
SC22U6D3V3MX-1-DL-GP
VENH:3.3V
PC8609
OPS
PWR_1D35V_LDO_P5
VGA enable need EE check
PC8610
SC10U25V5KX-DL-GP
OPS
DY
SC10U25V5KX-DL-GP
OPS
SCD01U25V2KX-3DLGP
PD8601
PJSD24W-GP
1st = 83.PJSD2.0AF
2nd = 083.04024.0AA1
PR8611
100KR2F-L1-GP
B
2
TDC=5.8A
ICCMAX=7.4A
8.88A<OCP<11.84A
3D3V_S0
2
PWR_DCBATOUT_1D35V
GAP-CLOSE-PWR-3-GP
R2
OPS
2
PR8626
12KR2F-L-GP
A
A
<Core Des ign>
Wistron Corporation
21F, 88, Sec.1, Hs in Tai Wu Rd., Hs ichih,
Taipei Hs ien 221, Taiwan, R.O.C.
https://realschematic.com
Title
Size
A0
Date:
5
4
3
2
1
DISCRETE VGA POWER
Docum ent Num ber
Rev
MOCKINGBIRD_TGL
Saturday, Augus t 01, 2020
Sheet
86
A00
of
105
5
4
3
2
1
Main Func = dGPU
D
D
C
C
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A3
Date:
5
4
3
2
Document Number
Reserved
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
87
A00
of
105
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
A
A
Title
Size
A4
https://realschematic.com
Document Number
4
3
Rev
MOCKINGBIRD_TGL
Date: Saturday, August 01, 2020
5
Reserved
2
Sheet
88
A00
of
1
105
5
4
3
2
1
Main Func = UnusedParts
HS1
STF237R113H91-GP
H5
HOLE335R178-GP
20191202
Follow Connector list
change to 434.0HH0K.0001
ZZ.PAD01.V91
1
1
1
H1
HOLE256R142-1-GP
ZZ.00PAD.7F1
434.0HH0K.0001
D
D
20191126
Follow Upsell
TYPEC SKREW HOLE
ZZ.00PAD.2T1
1
1
1
1
2
1
1
2
1
DY
2
1
2
1
2
1
2
1
2
EC8968
DY
1
1
2
EC8967
2
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
2
1
EC8987
EC8986
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
2
2
2
1
1
1
2
1
1
2
1
2
1
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
2
1
1
2
2
1
1
2
2
1
2
1
2
1
2
2
2
1
1
1
2
1
2
1
1
2
1
2
2
DY
PWR_DCBATOUT_1D35V
SCD1U25V2KX-1-DL-GP
優優優優PC4717旁旁
或或或PC4717的Top層
20V_DCBATOUT
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
優優優優PC4705旁旁
或或或PC4705的Top層
EC8985
EC8983
SCD1U25V2KX-1-DL-GP
DY
EC8982
SCD1U25V2KX-1-DL-GP
DY
EC8977
SCD1U16V2KX-3DLGP
DY
EC8976
SCD1U16V2KX-3DLGP
EC8975
SCD1U16V2KX-3DLGP
DY
19V_DCBATOUT
19V_DCBATOUT
EC8932
SCD1U25V2KX-1-DL-GP
DY
EC8913
SCD22U25V3KX-DL-GP
2
EC8974
SCD1U25V2KX-1-DL-GP
1
EC8973
SCD1U25V2KX-1-DL-GP
2
EC8972
SCD1U25V2KX-1-DL-GP
1
EC8971
SCD1U25V2KX-1-DL-GP
DY
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
2
EC8970
EC8966
DY
SCD1U16V2KX-3DLGP
EC8969
EC8965
DY
SCD1U16V2KX-3DLGP
1V_CPU_CORE
EC8961
SCD1U16V2KX-3DLGP
DY
EC8949
SCD1U16V2KX-3DLGP
DY
EC8948
SCD1U16V2KX-3DLGP
DY
EC8947
SC1KP50V2KX-1DLGP
DY
EC8939
SC1KP50V2KX-1DLGP
DY
EC8938
SC1U10V2KX-1DLGP
DY
EC8937
SC1U10V2KX-1DLGP
DY
EC8936
SC1U10V2KX-1DLGP
DY
EC8935
SC1U10V2KX-1DLGP
EC8934
SC1U10V2KX-1DLGP
EC8933
SC1U10V2KX-1DLGP
EC8963
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
B
EC8962
C
5V_S5
19V_DCBATOUT
EC8957
DY
1V_VGACORE1_S0
20191224
For EMC required
20191213
for High limit
EC8912
SC1KP50V2KX-1DLGP
DY
EC8910
SC1KP50V2KX-1DLGP
DY
EC8909
SC1KP50V2KX-1DLGP
DY
DY
EC8964
SCD1U16V2KX-3DLGP
SCD1U16V2KX-3DLGP
DY
EC8959
SCD1U16V2KX-3DLGP
EC8956
5V_S0
SC1U10V2KX-1DLGP
DY
DY
EC8954
SCD1U16V2KX-3DLGP
20191204
For EMC request
優優 R4701 R4702旁
SC1U10V2KX-1DLGP
+SDC_IN
EC8930
SC1KP50V2KX-1DLGP
DY
EC8927
SC1KP50V2KX-1DLGP
EC8926
SC1KP50V2KX-1DLGP
EC8924
SC1KP50V2KX-1DLGP
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
EC8923
DY
EC8953
SC1U10V2KX-1DLGP
EC8922
EC8908
DY
EC8952
SC1U10V2KX-1DLGP
19V_DCBATOUT
EC8921
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
EC8920
EC8907
SCD1U16V2KX-3DLGP
DY
SC1KP50V2KX-1DLGP
EC8918
20191224
For EMC required
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
DY
EC8929
EC8906
SC1KP50V2KX-1DLGP
DY
SC1KP50V2KX-1DLGP
EC8904 EC8905
SC1KP50V2KX-1DLGP
19V_DCBATOUT
SC1KP50V2KX-1DLGP
20200324(DVT2)
change .1u 50V to common .1u 25V
EC8902 EC8903
SC1KP50V2KX-1DLGP
EC8925
SC1KP50V2KX-1DLGP
EC8901
SC1KP50V2KX-1DLGP
DY
20191218
For EMC required
SC1U10V2KX-1DLGP
EC8951
20191218
For EMC required
EC8928
SCD1U25V2KX-1-DL-GP
EC8915
19V_DCBATOUT
3D3V_S0
EC8958
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
DY
C
ZZ.0HOLE.XXX
ZZ.PAD01.V91
20191224
For EMC required
19V_DCBATOUT
EC8919
EC8917
ZZ.PAD01.V91
1D2V_S3
H2
HOLE
H15
HOLE256R142-1-GP
+DC_IN_C
1
[43,44]
HDMI SKREW HOLE
H14
HOLE256R142-1-GP
ZZ.00PAD.2T1
ZZ.00PAD.2T1
Main Func = EMI Capacitors
Mind the voltage rating of the caps.
H13
HOLE276R154-GP
H12
HOLE276R154-GP
1
1
1
1
1
H11
HOLE276R154-GP
1
H10
HOLE233R150-GP
H9
HOLE233R150-GP
2
H8
HOLE233R150-GP
H7
HOLE233R150-GP
1
GPU/CPU SKREW HOLE
Main Func = RF Capacitors
B
Mind the voltage rating of the caps.
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
FC8933
2
1
2
1
2
1
2
1
2
1
1
2
1
2
1
2
1
2
1
2
2
1
2
1
1
2
1
2
1
2
1
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
FC8964
FC8935
SC15P25V1JN-GP
FC8934
SC15P25V1JN-GP
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
2
FC8963
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
FC8932
SC15P25V1JN-GP
FC8931
SC15P25V1JN-GP
FC8953
SC15P25V1JN-GP
FC8930
SC15P25V1JN-GP
FC8929
SC15P25V1JN-GP
FC8928
SC15P25V1JN-GP
FC8927
SC15P25V1JN-GP
FC8926
SC15P25V1JN-GP
1
FC8962
SC8D2P50VCN-2-GP
FC8961
SC8D2P50VCN-2-GP
FC8960
SC8D2P50VCN-2-GP
FC8959
SC8D2P50VCN-2-GP
SC4D7P50V2BN-2-GP
FC8957
1D8V_CPU_AUX
SC15P25V1JN-GP
FC8925
SC15P25V1JN-GP
FC8958
FC8924
SCD1U25V2KX-1-DL-GP
FC8923
SCD1U25V2KX-1-DL-GP
FC8920
SCD1U25V2KX-1-DL-GP
FC8921
SC4D7P50V2BN-2-GP
FC8922
SC4D7P50V2BN-2-GP
FC8918
SC4D7P50V2BN-2-GP
FC8917
SC1U25V2KX-4-GP
FC8916
SC1U25V2KX-4-GP
FC8956
SC8D2P50VCN-2-GP
FC8955
SC8D2P50VCN-2-GP
2
FC8943
SCD1U16V2KX-3DLGP
FC8942
SCD1U16V2KX-3DLGP
FC8908
SCD1U16V2KX-3DLGP
SCD1U16V2KX-3DLGP
FC8940
1V_CPU_CORE
SCD1U16V2KX-3DLGP
FC8954
SC8D2P50VCN-2-GP
FC8952
SCD1U16V2KX-3DLGP
FC8951
SC8D2P50VCN-2-GP
FC8950
SCD1U16V2KX-3DLGP
FC8949
FC8909
SCD1U16V2KX-3DLGP
SC8D2P50VCN-2-GP
FC8941
SC4D7P50V2BN-2-GP
FC8907
1D2V_S3
SC4D7P50V2BN-2-GP
SC4D7P50V2BN-2-GP
FC8948
FC8906
SC8D2P50VCN-2-GP
FC8939
SC4D7P50V2BN-2-GP
FC8938
SC6D8P50V2CN-DL-GP
FC8937
SC6D8P50V2CN-DL-GP
FC8936
SCD1U16V2KX-3DLGP
FC8905
SC4D7P50V2BN-2-GP
FC8904
SCD1U16V2KX-3DLGP
FC8903
SC8D2P50VCN-2-GP
FC8901
3D3V_S0
A
19V_DCBATOUT
5V_S5
SC8D2P50VCN-2-GP
1
3D3V_S5
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
UNUSED PARTS/EMI Capacitors
https://realschematic.com
Size
A2
Date:
5
4
3
2
Document Number
Rev
A00
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
89
of
105
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
A
A
Title
Size
A4
https://realschematic.com
Document Number
4
3
Rev
MOCKINGBIRD_TGL
Date: Saturday, August 01, 2020
5
Reserved
2
Sheet
90
A00
of
1
105
5
4
Main Func = TPM
2
1
2
D
SPI_CS_ROM_N2
3D3V_TPM
1
[18]
TPM
SCD1U16V2KX-3DLGP
C9113
TPM_SPI_IRQ#
D
TPM
SCD1U16V2KX-3DLGP
C9112
[20]
TPM
SC10U6D3V3MX-DL-GP
C9109
1 R9150 2
0R0402-PAD-7-NP-GP
1
3D3V_TPM
1
3D3V_S0
SPI_CLK_ROM
SPI_SI_ROM
SPI_SO_ROM
1
3D3V_TPM
DY ST_TPM
PCH_PLTRST#
[18,24,25]
[15,18,24,25]
[18,24,25]
2
3D3V_S5
R9149
0R2J-2-GP
1
2
2
[17,61,63,66,71,76]
3
3D3V_SPI
1
R9151
10KR2J-3-GP
TPM
2
R9148
10KR2J-3-GP
3D3V_TPM
SPI_CS2#_IC
TPM C9104
SCD1U16V2KX-3DLGP
1
2
2
TPM
SCD1U16V2KX-3DLGP
C9108
SC10U6D3V3MX-DL-GP
C9106
1
2
40mA
TPM
1
SPI_SI_ROM
SPI_SO_ROM
SPI_CS_ROM_N2
SPI_CLK_ROM
R9133 1
R9132 1
R9130 1
R9138 1
TPM
TPM
TPM
TPM
1 R9123 2
0R0402-PAD-7-NP-GP
TPM_SPI_IRQ#
20191211
follow Nakia
U9101
8
22
3D3V_S5
C
SPI_IRQ#_TPM2
1
1
5mA
2
C9114 TPM
SC10U6D3V3MX-DL-GP
2
TPM
20191212
Add C9114 for vendor request
20200420
Change to 0603 size
2
2
2
2
15R2J-GP
15R2J-GP
15R2J-GP
15R2J-GP
20200512
Change to 15R follow Intel PDG
SPI_SI_ROM_TPM
SPI_SO_ROM_TPM
SPI_CS2#_IC
SPI_CLK_ROM_TPM
21
24
20
19
PCH_PLTRST#
17
Close to U2501
16
23
33
2
U9101_2_GND
R9152
0R2J-2-GP
1
DY ST_TPM
2
3
5
VHIO
VHIO
SDA/GPIO0
SCL/GPIO1
PIRQ#/GPIO2
GPIO3
GPIO4
PP/GPIO6
VSB
MOSI/GPIO7
MISO
SCS#/GPIO5
SCLK
PLTRST#
TPM
GND
GND
GND
NC#2
NC#3
NC#5
NC#7
NC#9
NC#10
NC#11
NC#12
NC#14
NC#15
NC#25
NC#26
NC#27
NC#28
NC#31
NC#32
29
30
18
6
13
4
TPM_GPIO0
1
TPM_GPIO1
SPI_IRQ#_TPM2
TPM_GPIO3
TPM_GPIO4
R9118 1
TPM_GPIO6_PP
TP9101
1
TP9102
1
SPI_CS_ROM_N2
1
TP9103
C
DY
2 2K2R2F-GP
TP9104
7
9
10
11
12
14
15
25
26
27
28
31
32
NPCT750JADYX-GP
071.00750.M003
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A3
Date:
5
4
3
2
INT IO (TPM)
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
91
of
A00
105
5
4
3
2
1
SSID = Finger Print
D
D
C
C
B
B
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
A
Title
Finger Print
Size
A4
https://realschematic.com
Document Number
4
3
Rev
MOCKINGBIRD_TGL
Date: Saturday, August 01, 2020
5
A
2
Sheet
92
A00
of
1
105
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A3
Date:
5
4
3
2
Document Number
(Reserved)
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
93
A00
of
105
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A3
Date:
5
4
3
2
Document Number
(Reserved)
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
94
A00
of
105
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A3
Date:
5
4
3
2
Document Number
(Reserved)
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
95
A00
of
105
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
A
A
Title
Size
A4
https://realschematic.com
Document Number
4
3
Rev
MOCKINGBIRD_TGL
Date: Saturday, August 01, 2020
5
(Reserved)
2
Sheet
96
A00
of
1
105
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
A
A
Title
LVDS_Switch
Size
A4
https://realschematic.com
Document Number
Date:
5
4
3
Rev
A00
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
2
97
of
1
105
5
4
3
2
1
Main Func = Firmware SW
[19]
ME_FW P_SW
[24]
ME_FW P
D
D
Firmware SW
ME_FW P
ME_FW P_SW
R9801
MESW 1_B
2
1
MESW
20191224
Follow Internal review
3D3V_S5_VCCPRIM
7
ME_FW P_SW
2 R9806 1
0R0402-PAD-7-NP-GP
6
ME_FW P
3
2
1
NP2
MESW
1KR2J-1-GP
NP1
62.40018.641
5
4
1
R9802
4K7R2F-GP
MESW 1
SW -SLIDE3P-11-GP
2
DY
A
B
Low
High
C
C
ME_FWP
Normal Operation
(Default)
Override
3
LOW
1
HIGH
ME_FWP
Normal Operation
(Default)
Override
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CRT_Switch
https://realschematic.com
Size
A3
Date:
5
4
3
2
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
98
of
A00
105
5
4
3
2
1
D
D
C
C
B
B
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Debug (XDP debug)
Size
A4
Document Number
Rev
MOCKINGBIRD_TGL
Date: Saturday, August 01, 2020
5
4
3
2
Sheet
99
of
1
A00
105
A
5
4
3
2
1
CLK Block Diagram
D
D
TBD
C
C
B
B
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
CLK Block Diagram
Size
A2
Date:
5
4
3
2
Document Number
Rev
A00
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
100
of
105
5
4
3
2
1
Change notes -
D
D
C
C
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Size
A3
Date:
5
4
3
2
Change History
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
1
101
A00
of
105
5
4
3
2
1
D
D
TBD
C
C
B
B
A
A
<Core Des ign>
Wistron Corporation
21F, 88, Sec.1, Hs in Tai Wu Rd., Hs ichih,
Taipei Hs ien 221, Taiwan, R.O.C.
https://realschematic.com
Title
Size
A0
Date:
5
4
3
2
1
Power Sequence
Docum ent Num ber
Rev
MOCKINGBIRD_TGL
Saturday, Augus t 01, 2020
Sheet
102
A00
of
105
5
4
3
2
1
D
D
TBD
C
C
B
B
A
A
<Core Design>
Wistron Corporation
https://realschematic.com
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Power Block Diagram
Size
A1
Date:
5
4
3
2
Document Number
Rev
MOCKINGBIRD_TGL
Saturday, August 01, 2020
1
Sheet
103
A00
of
105
A
B
C
D
E
3D3V_S0
PCH SMBus Block Diagram
‧
DIMM 1
3D3V_S0
‧
‧
‧PCH_SMBCLK
PCH_SMBDATA
‧
RN1803
KBC SMBus Block Diagram
SMBus Address:0xA0/0xA1
3D3V_S5
SDA
SCL
SMBus Address:0xA0/0xA1
1
SMBDATA
CPU_SMB_SDA
SMBCLK
CPU_SMB_SCL
‧
DIMM 2
‧
SMBus Address:
PCH_SMBCLK
PCH_SMBDATA
‧
1
SCL
I2C02_SDA
SDA
I2C02_SCL
2N7002KDW
‧
DAT_TP_SIO_I2C_CLK
‧
I2C1_SCL_R
DAT_TP_SIO_I2C_DAT
TouchPad Conn.
I2C1_SDA_R
3D3V_S5_KBC
TPAD
R6513
GPP_C19/I2C1_SCL
PCH_I2C1_SCL_TP
I2C1_SCL_R
GPP_C18/I2C1_SDA
PCH_I2C1_SDA_TP
I2C1_SDA_R
‧
SCL
VDD
SDA
SRN4K7J-8-GP
R6512
SRN100J-3-GP
GPIO130/I2C01_SDA
GPIO131/I2C01_SCL
SMBus Address:
PD CCG6
I2C_SCL_SCB2 BB_I2C_SCL
CCG6_I2C_SCL I2C_SCL_SCB1
R7224
SML1_SMBCLK
SML1CLK
BB_I2C_SDA
CCG6_I2C_SDA I2C_SDA_SCB1
I2C_SDA_SCB2
SML1_SMBDATA
SML1DATA
3D3V_S0_TCP1
R7225
SMBus Address:0x82/0x83
PBAT_CHG_SMBCLK
‧
‧
PBAT_CHG_SMBDAT
‧
‧
PBAT_SMBCLK1
PBAT_SMBDAT1
‧
‧
SRN1KJ-7-GP
SMBus Address:
KBC
MEC1515H
Battery Conn.
CLK_SMB
DAT_SMB
SMBus address:16
ISL9538CHRTZ
PBAT_CHG_SMBCLK
SCL
PBAT_CHG_SMBDAT
SDA
SMBus address:12
TBT Bridge
2
2
0R1J-GP
TCP_SMBUS_SCL
0R1J-GP
TCP_SMBUS_SDA
‧
‧
SMBUS_SCL
I2C_SCL
SMBUS_SDA
I2C_SDA
PCH
GPU_THM_SMBCLK
GPIO004/SCL
‧
GPU_THM_SMBDAT
GPIO003/SDA
GPIO143/I2C04_SDA
GPIO144/I2C04_SCL
3D3V_S0
SRN1KJ-7-GP
‧
‧
SML0CLK
SML0_SMBCLK
SML0DATA
SML0_SMBDATA
‧
3D3V_S5
SRN2K2J-1-GP
3D3V_S0
SMBus Address:
0x94/0x95/0x96/0x97
‧
‧
SMBus Address:0x98/0x99
THM_SML1_CLK
SCL
THM_SML1_DATA
SDL
Thermal
NCT7718W
SMBus Address:0x82/0x83
2N7002KDW
‧
1D8V_AON_S0
3
3
SMBus Address:0x9E/0x9F
SRN4K7J-8-GP
‧
1D8V_VGA_S0
‧
‧
‧
dGPU
N17S-G3/G5
SMBC_THERM_NV
SMB_CLK
SMBD_THERM_NV
SMB_DATA
2N7002KDW
ISH
R2052
GPP_B6/I2C0_SCL
GPP_B5/I2C0_SDA
ISH_I2C0_ACC_SCL
SENSOR_I2C_SCL
ISH_I2C0_ACC_SDA
SENSOR_I2C_SDA
SCL
SDA
R2051
3D3V_S0
5V_HDMI
3D3V_S0
‧
‧
4
‧
SRN2K2J-1-GP
4
SRN2K2J-1-GP
<Core Design>
DDPB_CTRLCLK
DDPB_CTRLDATA
‧CPU_DPB_CTRL_CLK
‧ CPU_DPB_CTRL_DATA
https://realschematic.com
HDMI_SCL_CON
HDMI_SDA_CON
‧
‧
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
HDMI CONN
Title
2N7002KDW
Size
A2
Date:
A
B
C
D
SMBUS Block Diagram
Document Number
MOCKINGBIRD_TGL
Saturday, August 01, 2020
Sheet
E
104
Rev
A00
of
105
A
B
C
D
Thermal Block Diagram
E
Audio Block Diagram
1
1
3D3V_S5_PCH
3D3V_S0
PAGE28
PCH
D+
NCT7718_DXP
SPKR_L+
SPKR_LSPKR_RSPKR_R+
MMBT3904-3-GP
SC2200P50V2KX-2GP
Thermal
NCT7718
SML1DATA/GPIO74
SML1CLK/GPIO75
SML1_DATA
‧
‧
‧
D-
Place near CPU
PWM CORE
Codec
ALC3246
CPU_SMB_SDA_THM SDA
2N7002
‧
‧ ‧
SML1_CLK
SPEAKER
NCT7718_DXN
‧
CPU_SMB_SCL_THM SCL
‧
MMBT3904-3-GP
AUD_HP1_JACK_R
SML1_CLK
SML1_DATA
PAGE20
3D3V_S0
T_CRIT#
2N7002
PURE_HW_SHUTDOWN#
D
EN
3V/5V
SLEEVE
PCH_PWROK
G
‧
PAGE27
THERM_SYS_SHDN#
S
2
RING2
2
Put under CPU(T8 HW shutdown)
PAGE86
GPIO74
KBC
MEC1404
HP MIC
COMBO
AUD_HP1_JACK_L
T8
GPIO73
SMB_CLK_VGA_R
I2CS_SCL
SMB_DATA_VGA_R
I2CS_SDA
2N7002
GPIO4
GPIO56
DMIC_DATA_R
DMIC_CLK_R
GPIO1/DMIC_CLK
R2714
0R2J-2-GP
R2716
Digital
MIC
DMIC_DATA
DMIC_CLK
0R2J-2-GP
MESO-LE
GB2-64 (23x23)
FAN1_DAC_1
FAN_TACH1
GPIO94
VGA
GPIO0/DMIC_DATA
3
3
TACH
FAN
FAN_VCC1
VIN
5V
VIN
VSET
VOUT
FAN CONTROL
APL5606AKI
PAGE28
4
4
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
https://realschematic.com
Thermal/Audio Block Diagram
Size
Document Number
Custom
Date:
A
B
C
D
Saturday, August 01, 2020
Sheet
E
105
Rev
A00
MOCKINGBIRD_TGL
of
105