erence; 1972
ECE 485
DUT 2019
Homework 2
1. [10] Consider the communication interface below. The data communication is one
way between sender and receiver. The sender places data on the DATA lines and
asserts a pulse on DATA READY. Upon receipt of the data, the receiver sends a DATA
ACCEPT pulse.
-controlled, one-way
ation
evised to retain the
communication behile overcoming the
-time error response 2.
of clock skew. Error
oes not impede the
al can be deferred as
requires. This is not
onous bus since there
e to all devices. Acbus is idle, because
more communication
y all devices. So an
Data Error signal for
y whatever transfer
o device is using the
so the one or more
he last N words have
r response. The semiblem by generating
serve as pseudoclock
bus is idle. Only N 3.
ontinuous oscillation
l bus operation.
depends on the bus
rally controlled, the
e bus condition and
A decentrally conion be performed by
DATA
DATA READY
DATA ACCEPT/
BUS AVAILABLE
|4- t2 * | + t 4 » |
[5] WhatFigure
happens
if there is a spurious
(noise) pulse on the DATA READY line?
20—Semisynchronous,
non-interlocked,
request/acknowledge communication
(Data Accept/Bus Available)
[5] What happens if there is a spurious (noise) pulse on the DATA ACCEPT line?
the last device to use the bus. The replication of logic
adds Consider
cost, and the
if this
last device should
fail while gen- request/acknowledge scheme
[15]
asynchronous,
half-interlocked,
erating
the
pseudoclocks,
the
entire
bus
will
be down.
depicted below. What happens if t3 > t4?
Draw a timing diagram reflecting this
Like asynchronous busses, semisynchronous busses
and indicate what happens as a result.
may be either One-Way Command or Request/
Acknowledge.
Figure 18 illustrates how the timing of a semisynchronous source-controlled bus resembles that of its
asynchronous counterpart (there is no corresponding
destination-controlled case). Instead of the source
device sending a Data Ready to signal the presence of
new data, it sends a Bus Available to define the end of
its time slot and the beginning of the next. During a
time slot, the bus assignment for the following slot is
made; Bus Available then causes the next device to
place its destination address and data on the bus. The
selected destination then waits for the data to settle,
loads it, and generates another Bus Available.
Combining the function of Data Ready with that of
Bus
Available
(a line generally
required
bycomplex
an asyn-but it also incurs additional delay.
[5] The
fully interlocked
scheme
is more
chronous
bus)
is
a
benefit
which
accrues
to
all semiHow much time is required for a transfer using
this scheme? Be specific.
synchronous busses. The semisynchronous One-Way
Command interface does avoid the real-time error response, but it is still highly susceptible to noise, and
incompatible with devices of differing speeds.
DATA
DATA READY/
BUS AVAILABLE
DATA ACCEPT
4. [10] Assuming the Intel 8086 microprocessor and the schematic below, complete the
table to indicate which I/O addresses the ports and register respond to.
Register/Port
Port A
Port B
Port C
Control Register
Address (Hex)
What hexadecimal value should be written to the control register to configure the
ports so that processor can read 8-bit data from port A and write 8-bit data to ports
B and C? Assume no handshaking. Note if you're unfamiliar with the 74ALS138 you
can use Google to find a data sheet.
Locate an on-line copy of the PDP-11 processor handbook or other descriptions of the
PDP-11 architecture to answer the following questions.
5. [5] Give the complete name, date, and URL of every reference you consulted for
your answers below.
6. [5] What names does the PDP-11 use for asynchronous exceptions caused by I/O
devices?
7. [5] What PDP-11 instruction is used to return from an interrupt?
8. [10] How does the PDP-11 determine the address of an interrupt service routine?
9. [10] Does the PDP-11 have any instructions that can be used specifically to cause
exceptions/interrupts? If so, what are they?
10. [10] Other than asynchronous exceptions caused by I/O devices and any instructions
from (9) above, what other events/conditions can invoke the interrupt mechanism?