1
IEEE CICC 2022
A 10b 700MS/s single-channel 1b/cycle SAR ADC using a
monotonic-specific feedback SAR logic with powerdelay-optimized unbalanced N/P-MOS sizing
Mingqiang Guo1, Sai-Weng Sin1,2, Liang Qi3, Gangjun Xiao4, Rui P.
Martins1,5
of Macau, Macau, China; 2Zhuhai UM Science &
Technology Research Institute, Zhuhai, China; 3Shanghai Jiao
Tong University, Shanghai, China; 4Amicro Semiconductor Co., Ltd,
Zhuhai, China; 5University of Lisboa, Lisbon, Portugal
2022 IEEE Custom Integrated Circuits Conference (CICC) | 978-1-6654-0756-4/22/$31.00 ©2022 IEEE | DOI: 10.1109/CICC53496.2022.9772843
1University
A SAR ADC comprises only a T/H, a comparator, SAR logics, and a
capacitive DAC, thus exhibiting a power-efficient topology with low
complexity, low power consumption, and friendly process technology
scaling down. Consequently, it has a wide utilization in high-speed
applications (like in time-interleaved SARs). Previous works
improved the 1b/cycle topology to speed up SAR ADC conversions,
leading to multi-bit/cycle [1] and N-bits N-comparators [2] structures.
Compared with the above architectures, the conventional 1b/cycle
topology still has apparent advantages related to low complexity,
less parasitic, and less offset problems. Therefore, currently, the
1b/cycle is still the first choice for the majority of high-speed TI SAR
ADCs [3]. The popularization of the high-speed SAR ADC with
redundant bit structures can lead to a very short settling time required
for the DACs [4]. However, the speed of the SAR is still a bottleneck,
especially limited by the digital SAR logic [2].
This work proposes a power-delayed-optimized SAR feedback loop
composed of unbalanced N/P-MOS sizing, reducing the SAR logic
delay to overcome the single-channel SAR ADC’s speed bottleneck.
Based on the characteristics of the commonly used monotonicswitching SAR ADC [4] that switches the DAC in only a single
direction, we can reduce the comparator-to-DAC delay by sizing the
N/P-MOS of the logic gates unilaterally (Fig. 1) along the path of the
monotonic switching DAC drivers, the DAC switch control logic, and
the asynchronous control logic. The proposed technique enhances
the speed of the logic on those critical edge transitions, and reduces
the size of the transistors for those non-critical edge directions. This
can simultaneously improve the speed, and reduce the power and
area of the SAR ADC, breaking the traditional power-delay tradeoffs
of the SARs. Furthermore, it does not change the classic 1b/cycle
structure, which allows all its advantages to be maintained.
The monotonic switching SAR ADC [4] resets the bottom plates of
all DAC capacitors to VDD in the sampling phase. The subsequent
switching of each bit's capacitor bottom plate to GND (critical edge
direction) or keeping it unchanged at VDD (non-critical edge direction)
depends on the comparator's digital output (OUTP/OUTN) and the
corresponding internal SAR clocks (CLKi). From Fig. 1, the speedcritical edge direction for the i-th bit capacitor's bottom plate (Ci) is
always the falling edge in the monotonic switching DAC. Thus, we
can determine that the rising edge is the critical direction for the
corresponding DAC switch control signal (DACi). Similarly, the
corresponding critical direction for the asynchronous control clocks
(CLKi) must be from 0 to 1, with all DFFs in the asynchronous control
logic reset in the sampling phase. In summary, speed-critical edges
from the capacitor's bottom plate Ci to the DAC drivers, the DAC
switch control signal DACi, and the asynchronous control clocks CLKi
are definite and unidirectional.
Under normal circumstances, we use N/P-MOS gm-balanced digital
buffers to drive the switch control signals of the DAC. This can
ensure symmetrical rising and falling edges of the digital buffers with
similar delays. However, for the logic drivers of the monotonic
switching DAC, they are unidirectional in each conversion cycle. It
means that we only need to optimize the corresponding unilateral
direction of the data transmission. Fig. 2 presents the fast one-sided
digital buffer in the driver circuits of the monotonic switching DAC,
composed of the un-balanced N/P-MOS. In the conversion phase,
the node ‘OUT’, which is the bottom plate of Ci, switches to either the
GND or does not change. Therefore, the speed-critical edges in the
nodes ‘OUT/C/B/A’ are always falling/rising/falling/rising edges,
respectively.
From Fig.2, in the traditional digital buffer, the ratio of the widths of
NMOS (MN1, MN2, MN3, MN4) to PMOS (MP1, MP2, MP3, MP4) is
approximately equal to the mobility ratio of PMOS and NMOS, such
as
W P2(N/P)WN2,
W N3(P/N)W P3. The proposed
65m
Bootstrap Switch
power-delay-optimized
digital
Cap Array
Comparator
buffer reduces the corresponding
35m
widths of NMOS or PMOS
transistors by a shrink factor α<1,
like
W N1(P/N)αW P1,
W P2(N/P)αW N2. The utilization of
the shrink factor α for W P2 reduces Die micrograph.
CL,A when compared with the
traditional buffer; the delay time becomes Tdelay-proposed(1+α)/2·Tdelayregular. Moreover, each node of the logic path's capacitive load and
the power consumption fall by a factor of (1+α)/2.
We can extend this concept to other digital logic circuits, such as
NAND, NOR, the logic gates in the DFFs, etc., by using unbalanced
N/P-MOS sizing to reduce delay and power consumption. We can
set the actual value of ‘α’ differently for different logic locations. Fig.
3 displays how to use the proposed method to optimize the delay in
a monotonic switching SAR according to specific situations. There
are 3 critical delay paths for the SAR logic loop. Path 1 (red in Fig. 3)
controls the strobe and reset of the comparator during the conversion
phase. Both the rising and falling edges in this path are critical for the
speed of SAR conversion phase, so we use traditional regular-sizing
logic within this path 1. From the ‘Ready’ signal generated based on
the output of the comparator to the asynchronous control clock CLKi
(path 2, blue), then to the DAC switch control logic DACi and the
bottom plates of Ci (path 3, brown), we intentionally place the noncritical edges in the sampling phase and the critical edges in the SAR
conversion phase. Considering the CLKi as an example, they have
more than the time of the entire sampling phase to complete the noncritical edge transitions (reset) without affecting the performance of
the ADC. α can be as small as possible (between 0.1 and 0.25 here).
In the SAR logic feedback loop, registers such as DFFs generally
occupy the main part of the delay time and power. Using the
proposed unbalanced N/P-MOS sizing method, we re-optimize the
DFF’s design. On one hand, we reduce the number of gates required
for the critical propagation path in the DFF. On the other hand, using
unbalanced logic further reduces the critical path delay. For path 3
from DACi to Ci, it is necessary to pay attention to the reset of Ci
while performing unilateral optimization. The slowest reset of C i will
affect the sampling accuracy of the ADC. In this work, we use the
sampling clock ‘S’ to reset DACi directly. In the path from DACi to
Ci, we choose α from 0.25 to 0.5 to improve the one-way high-speed
propagation during the conversion phase while maintaining the
moderate reset capability of the DAC in sampling phase. Finally, the
unbalanced N/P-MOS sizing method reduces the total capacitive
loads along the paths. An important consequence is the significant
reduction of the number of buffer stages to drive them. Therefore, it
contributes to a further reduction of the logic delay and the power.
To verify the proposed power-delay-optimized unbalanced N/P-MOS
sizing technique, we fabricated a 10-bit SAR ADC in 28nm CMOS.
This 10-bit SAR ADC has 11 cycles (1bit redundant), the first two
MSBs use a monotonic splitting structure, and the remaining bits are
pure monotonic. We used a custom-designed MOM capacitor array
with a total single-ended ADC input capacitance of 180fF to deliver
a 10b-level INL of -0.51/+0.60 LSB. It achieves the Nyquist
SNDR/SFDR of 56.39/71.95dB at 600MS/s @0.9V, and
56.42/73.27dB at 700MS/s @0.95V (Fig. 4). Fig. 5 presents the
robustness measurement, including the dynamic performance
versus supply voltage, different chip samples, and ambient
temperature. Fig. 6 compares the performance with recently
published ADCs of similar performance.
Acknowledgment: funded by National Key R&D Program of China
(2019YFB1310000) and The Science and Technology Development
Fund, Macao S.A.R (File no. 0052/2020/AGJ).
References:
[1] C. Chan et al., JSSC, Feb. 2016.
[2] T. Jiang et al., JSSC, Oct. 2012.
[3] J. P. Keane et al., ISSCC, Feb. 2017.
[4] C. Liu et al., JSSC, Nov. 2015.
978-1-6654-0756-4/22/$31.00 ©2022 IEEE
Authorized licensed use limited to: Universidade de Macau. Downloaded on August 02,2022 at 06:34:28 UTC from IEEE Xplore. Restrictions apply.
IEEE CICC 2022
comp
Capacitive DAC
Ci
Monotonic C1 C2
Switching
Asynchronous Control Logic
Ready
OUTP
VIN
DFFA
DFFA
D Q
D Q
CLKi
S
Reset
DAC1
DFFD
DFFD
DFFD
D Q
D Q
D Q
MN1
comp
Unbalanced Buffer:
n
p
WP2  αWN2 WN3  αWP2 α<1
p
n
OUT
MN3
MP1
MP2
MN4
tdigital
MN1
Fig. 1. Unidirectional data transmission path in monotonic switching
SAR ADC.
Delay:
OUTN
DFFA
2. Unidirectional
Logic with
DFFA
D Q
DFFA
D Q
CLK2
CLK1
D Q
CLKi
0.1≤α≤0.25
S
DAC Switch Control Logic
3. Unidirectional
Logic with
0.25≤α≤0.5
OUTP/OUTN
DFFD
DFFD
DFFD
D Q
D Q
D Q
DAC1
SAR Conversion
Ready
comp
Ready
2
tDFFA+tDFFD
Critical
Non-critical
Fig. 3. Optimization of 3 delay paths in monotonic switching SAR.
fin=349.3MHz, fs=700MS/s @0.95V
SNDR=56.42dB, SFDR=73.27dB
Decimated by 25
-20
4
6
8
Frequency [MHz]
10
12
-40
-60
-80
100
120 0
80
80
70
fin=299MHz @ 0.9V
fin=349MHz @ 0.95V
60 SNDR
400
500
600
700
Sampling Frequency [MHz]
2
6
8
10
Frequency [MHz]
12
14
fs=600MS/s
fs=700MS/s
70
Nyquist
<3dB SNDR
drop
@1GHz
60 SNDR
50
0
800
4
SFDR
SFDR
tDFFA
DAC1
1+α
Pregular
2
Pproposed
0
-80
100
120 0
50
CLK1
P ∝[(WN2+WP2)+(WN3+WP3)]
MN4
-60
SNDR & SFDR [dB]
DACi
Sampling
MN3
fin=299.3MHz, fs=600MS/s @0.9V
SNDR=56.39dB, SFDR=71.95dB
Decimated by 25
-40
Reset
DAC2
S
OUT
Magnitude [dB]
Ci
C2
Ready Asynchronous Control Logic
Ready
Magnitude [dB]
OUTP
MN2
MP4
C
0
-20
Capacitive DAC
B
nWN2
1+α
Tdelay-proposed
Tdelay-regular
2
Power:
Fig. 2. Proposed power-delay-optimized unbalanced N/P-MOS
sizing buffer.
CLK11 (CLK11 is the last CLKi)
comp
MP3
A
IN
1. Regular Two-way
Transmission
p
WN3  WP2
n
pWP1
tDAC
SNDR & SFDR [dB]
C
Unbalanced Buffer
Ci
SNDR [dB] SFDR [dB]
MN2
MP4
Tdelay∝ tpLH,A+tpHL,B ∝ WN2+WP2 + WN3+WP3
CLKi
SNDR & SFDR [dB]
B
1+α
Tdelay-regular
2
Regular Buffer:
n
WP2  WN2
p
tcomp
DACi
C1
MP3
A
IN
OUTP/OUTN
VIN
MP2
Tdelay-proposed
OUT
Tdelay-proposed
Regular Buffer
DACi
tcomp
IN
IN
MP1
Tdelay-Regular
OUT
Unbalanced Buffer
Only need to
optimize a
single
direction
Reset
DAC2
IN
OUTN
Ci
OUT
DAC Switch Control Logic
OUTP/OUTN
Ready
C2
D Q
CLK2
CLK1
C1
DFFA
Regular Buffer
OUTP
OUTN
Only need to
optimize a
single
direction
S
Monotonic Switching
Capacitive DAC
S
VIN
SNDR & SFDR [dB]
S
2
400
800
1200
Input Frequency [MHz]
1600
Fig. 4. Measured 16384-point output spectrum with a sampling rate
of 600MS/s @0.9V and 700MS/s @0.95V, measured performance
vs. sampling frequencies and input frequencies.
80
SFDR
This Work
70
fin=299MHz @ fs=600MS/s
fin=349MHz @ fs=700MS/s
60
50
0.85
0.9
0.95
1
Power Suppluy Volatge [V]
1
2
3
4
5
6
7
8
9
10
fin=29MHz @ fS=700MS/s
57
56
80
1
2
3
4
5
6
Chip ID
7
8
9
10
SFDR
70
60
fin=29MHz @ fS=700MS/s
50 -50
-20
0
20
40
60
Ambient Temperature [°C]
Fig. 5. Measured SNDR & SFDR vs supply, samples, temperature.
VLSI-21
S. Baek
J. Lagos
SAR
Pipe-SAR
Pipe
Pipe-SAR-DSM
Pipe-SAR
√
×
×
×
×
20nm
14nm
16nm
7nm
16nm
10
10
10
11
12
12
Supply Volatge
0.9
0.95
0.9
1
0.7
0.95
0.85
0.8
0.9
600
700
160
320
950
1500
600
600
500
SNDR @ Nyq. [dB]
56.39
56.42
57.1
50.7
50.3
50.1
60.2
55.3
62.9 62.3*
2.26
6.92
6
13
2.8
3.3*
8.9
17.7
12
45.6
4.9
6.2*
167.2
158.9
172.4 171.1*
0.037
0.037
0.0084
Power [mW]
1.49
2.02
0.68
1.52
FOMWalden [fJ/c-s]
4.6
5.3
7.3
16.5
169.4
168.8
Active Area [mm2]
SNDR
ISSCC-21
B. Hershberg
Sampling Rate [MS/s]
FOMSchreier [dB]
Chip-1
Chip-2
ISSCC-19
L. Kull
√
Resolution [bit]
70
58
Process
ISSCC-17
C. C. Liu
28nm
Calibration Free
75
65
SAR
Architecture
SNDR
JSSC-15
0.0023
167.8 160.9 163.5 160.4
0.0012
0.0016
*: Reference regulation on.
Fig. 6. Performance summary and comparison with state-of-theart.
Authorized licensed use limited to: Universidade de Macau. Downloaded on August 02,2022 at 06:34:28 UTC from IEEE Xplore. Restrictions apply.