An Instructor’s Solutions Manual to Accompany
FUNDAMENTALS OF LOGIC DESIGN,
7TH EDITION
CHARLES H. ROTH, JR.
LARRY L. KINNEY
ISBN-13: 978-1-133-62849-1
ISBN-10: 1-133-62849-4
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INSTRUCTOR'S SOLUTIONS MANUAL
TO ACCOMPANY
FUNDAMENTALS OF
LOGIC DESIGN
SEVENTH EDITION
CHARLES H. ROTH, JR.
University of Texas at Austin
LARRY L. KINNEY
University of Minnesota, Twin Cities
TABLE OF CONTENTS
I. INTRODUCTION
1.1 Using the Text in a Lecture Course
1.2 Some Remarks About the Text
1.3 Using the Text in a Self-Paced Course
1.4 Use of Computer Software
1.5 Suggested Equipment for Laboratory Exercises
1
1
2
2
4
5
II. SOLUTIONS TO HOMEWORK PROBLEMS
Unit 1 Problem Solutions
Unit 2 Problem Solutions
Unit 3 Problem Solutions
Unit 4 Problem Solutions
Unit 5 Problem Solutions
Unit 6 Problem Solutions
Unit 7 Problem Solutions
Unit 8 Problem Solutions
Unit 9 Problem Solutions
Unit 10 Problem Solutions
Unit 11 Problem Solutions
Unit 12 Problem Solutions
Unit 13 Problem Solutions
Unit 14 Problem Solutions
Unit 15 Problem Solutions
Unit 16 Problem Solutions
Unit 17 Problem Solutions
Unit 18 Problem Solutions
Unit 19 Problem Solutions
Unit 20 Problem Solutions
7
7
17
23
31
41
57
71
91
97
113
119
125
145
157
177
201
215
229
245
257
III. SOLUTIONS TO DESIGN, SIMULATION,
AND LAB EXERCISES
Unit 8 Design Problems
Unit 10 Design and Simulation Problems
Unit 12 Design and Simulation Problems
Unit 16 Design and Simulation Problems
Unit 17 Simulation and Lab Problems
Unit 20 Lab Design Problems
263
263
283
297
303
313
321
IV. SAMPLE UNIT TESTS
351
iii
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
iv
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
I: INTRODUCTION
The text, Fundamentals of Logic Design,7th edition, has been designed so that it
can be used either for a standard lecture course or for a self-paced course. The text is divided
into 20 study units in such a way that the average study time for each unit is about the same.
The units have undergone extensive class testing in a self-paced environment and have been
revised based on student feedback. The study guides and text material are sufficient to allow
almost all students to achieve mastery of all of the objectives. For example, the material on
Boolean algebra and algebraic simplification is 2½ units because students found this topic
difficult. There is a separate unit on going from problem statements to state graphs because
this topic is difficult for many students.
The textbook contains answers for all of the problems that are assigned in the study
guides. This Instructor’s Manual contains complete solutions to these problems. Solutions
to the remaining homework problems as well as all design and simulation exercises are also
included in this manual. In the solutions section of this manual, the abbreviation FLD stands
for Fundamentals of Logic Design (7th ed.).
Information on the self-paced course as previously taught at the University of Texas
using an earlier edition of the textbook is available from Prof. Charles H. Roth, croth@
austin.rr.com. In addition to the textbook and study guides, teaching a self-paced course
requires that a set of tests be prepared for each study unit. This manual contains a sample
test for each unit.
1.1 Using the Text in a Lecture Course
Even though the text was developed in a self-paced environment, the text is well
suited for use in a standard lecture course. Since the format of the text differs somewhat
from a conventional text, a few suggestions for using the text in a lecture course may be
appropriate. Except for the inclusion of objectives and study guides, the units in the text
differ very little from chapters in a standard textbook. The study guides contain very basic
questions, while the problems at the end of each unit are of a more comprehensive nature.
For this reason, we suggest that specific study guide questions be assigned for students to
work through on their own before working out homework problems selected from those
at the end of the unit. The unit tests given in Part IV of this manual provide a convenient
source of additional homework assignments or a source of quiz problems. The text contains
many examples that are completely worked out with detailed step-by-step explanations.
Discussion of these detailed examples in lecture may not be necessary if the students study
them on their own. The lecture time is probably better spent discussing general principles
and applications as well as providing help with some of the more difficult topics. Since all
of the units have study guides, it would be possible to assign some of the easier topics for
self-study and devote the lectures to the more difficult topics.
At the University of Texas a class composed largely of Electrical Engineering and
Computer Science sophomores and juniors covers 18 units (all units except 6 and 19) of
the text in one semester. Units 8, 10, 12, 16, 17, and 20 contain design problems that are
suitable for simulation and lab exercises. The design problems help tie together and review
the material from a number of preceding units. Units 10, 17, and 20 introduce the VHDL
1
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hardware description language. These units may be omitted if desired since no other units depend
on them.
1.2 Some Remarks About the Text
In this text, students are taught how to use Boolean algebra effectively, in contrast with
many texts that present Boolean algebra and a few examples of its application and then leave it to
the student to figure out how to use it effectively. For example, use of the theorem x + yz = (x + y)
(x + z) in factoring and multiplying out expressions is taught explicitly, and detailed guidelines are
given for algebraic simplification.
Sequential circuits are given proper emphasis, with over half of the text devoted to this
subject. The pedagogical strategy the text uses in teaching sequential circuits has proven to be very
effective. The concepts of state, next state, etc. are first introduced for individual flip-flops, next
for counters, then for sequential circuits with inputs, and finally for more abstract sequential circuit
models. The use of timing charts, a subject neglected by many texts, is taught both because it is
a practical tool widely used by logic design engineers and because it aids in the understanding of
sequential circuit behavior.
The most important and often most difficult part of sequential circuit design is formulating
the state table or graph from the problem statement, but most texts devote only a few paragraphs
to this subject because there is no algorithm. This text devotes a full unit to the subject, presents
guidelines for deriving state tables and graphs, and provides programmed exercises that help the
student learn this material. Most of the material in the text is treated in a fairly conventional
manner with the following exceptions:
(1) The diagonal form of the 5-variable Karnaugh map is introduced in Unit 5. (We find
that students make fewer mistakes when using the diagonal form of 5-­variable map in
comparison with the side-by-side form.) Unit 5 also presents a simple algorithm for finding
all essential prime implicants from a Karnaugh map.
(2) Both the state graph approach (Unit 18) and the SM chart approach (Unit 19) for designing
sequential control circuits are presented.
(3) The introduction to the VHDL hardware description language in Units 10, 17, and 20
emphasizes the relation between the VHDL code and the actual hardware.
1.3 Using the Text in a Self-Paced Course
This section introduces the personalized system of self-paced instruction (PSI) and offers
suggestions for using the text in a self-paced course. PSI (Personalized System of Instruction)
is one of the most popular and successful systems used for self-paced instruction. The essential
features of the PSI method are
(a) Students are permitted to pace themselves through the course at a rate commensurate with
their ability and available time.
(b) A student must demonstrate mastery of each study unit before going onto the next.
(c) The written word is stressed; lectures, if used, are only for motivation and not for
transmission of critical information.
(d) Use of proctors permits repeated testing, immediate scoring, and significant personal
interaction with the students.
These factors work together to motivate students toward a high level of achievement in a well2
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
designed PSI course.
The PSI method of instruction and its implementation are described in detail in the following
references:
1. Keller, Fred S. and J. Gilmour Sherman, The Keller Plan Handbook, W. A. Benjamin, Inc.,
1974.
2. Sherman, J.G., ed., Personalized System of Instruction: 41 Germinal Papers, W. A.
Benjamin, Inc., 1974.
3. Roth, C. H., The Personalized System of Instruction – 1962 to 1998, presented at the 1999
ASEE Annual Conference. (Go to http://search.asee.org and search under Conference
Papers for “The Personalized System of Instruction”.)
Results of applying PSI to a first course in logic design of digital systems are described in
Roth, C.H., Continuing Effectiveness of Personalized Self-Paced Instruction in Digital Systems
Engineering, Engineering Education, Vol. 63, No. 6, March 1973.
The instructor in charge of a self-paced course will serve as course manager in addition to
his role in the classroom. For a small class, he may spend a good part of his time acting as proctor
in the classroom, but as class size increases he will have to devote more of his time to supervision
of course activities and less time to individual interaction with students. In his managerial role, the
instructor is responsible for organizing the course, selection and training of proctors, supervision
of proctors, and monitoring of student progress. The proctors play an important role in the success
of a self-paced course, and therefore their selection, training, and supervision is very important.
After an initial session to discuss proper ways of grading readiness tests and interacting with
students, weekly proctor meetings to discuss course procedures and problems may be appropriate.
A progress chart showing the units completed by each student is very helpful in
monitoring student progress through the course. The instructor may wish to have individual
conferences with students who fall too far behind. The instructor needs to be available in the
classroom to answer individual student questions and to assist with grading of readiness tests
as needed. He should make a special point to speak with the weak or slow students and give
them a word of encouragement. From time to time he may need to settle differences which
arise between proctors and students.
Various strategies for organizing a PSI course are described in the Keller Plan
Handbook. The procedures previously used for operating the self-paced digital logic course
at the University of Texas are described in “Unit 0”, which is available from Prof. Charles H.
Roth, .croth@austin.rr.com. At the first class meeting, we handed out a copy of Unit 0. The
students were asked to read through Unit 0 and take a short test on the course procedures.
This test was immediately evaluated so that the student could complete Unit 0 before the
end of the first class period. In this way, the student was exposed to the basic way the course
operated and was ready to proceed immediately with Unit 1 in the textbook.
During a typical class period, some of the students spent their time studying but most
of the students came prepared to take a unit test. At the beginning of the period, the instructor
or a proctor was available to answer student questions on an individual basis. Later in the
3
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period, most of the time was spent evaluating unit tests. We found that a standard 50 minute
class period was not long enough for a PSI session. We usually scheduled sessions of 1½ or
2 hours or longer depending on class size. This allowed adequate time for students to have
their questions answered, take a unit test, and have their tests graded. Interactive grading of
the tests with the student present is an important part of the PSI system and adequate time
must be allowed for this activity. If you have a large number of students and proctors, you
may wish to prepare a manual for guidance of your proctors. The procedures that we used for
evaluating unit tests are described in a Proctor’s Manual, which can be obtained by writing
to Professor Charles H. Roth.
1.4. Use of Computer Software
Three software packages are included on the CD that accompanies the textbook. The first
is a logic simulator program called SimUaid, the second is a basic computer-aided logic design
program called LogicAid, and the third is a VHDL Simulator called DirectVHDL. In addition, we
use the Xilinx ISE software for synthesizing VHDL code and downloading to CPLD or FPGA circuit
boards. The Xilinx ISE software is available at nominal cost through the Xilinx University Program
(for information, go to www.xilinx.com/university/index.htm). A “Webpack” version of the Xilinx
software is also available for downloading from the Xilinx.com website.
SimUaid provides an easy way for students to test their logic designs by simulating them.
We first introduce SimUaid in Unit 4, where we ask the students to design a simple logic circuit such
as problem 4.13 or 4.14, and simulate it. SimUaid is easy to learn, and it is highly interactive so that
students can flip a simulated switch and immediately observe the result. In Unit 8, students design a
multiple-output combinational logic circuit using NAND and NOR gates and test its operation using
SimUaid. Students can use the simulator to help them understand the operation of latches and flip-flops
in Unit 11. In Unit 12, we ask them to design a counter and simulate it (one part of problem 12.10). In
Unit 16, students use SimUaid to test their sequential circuit designs. They can also generate VHDL
code from their SimUaid circuit, synthesize it, and download it to a circuit board for hardware testing.
In Unit 18, students can use the advanced features of SimUaid to simulate a multiplier or divider
controlled by a state machine.
LogicAid provides an easy way to introduce students to the use of the computer in the logic
design process. It enables them to solve larger, more practical design problems than they could by
hand. They can also use LogicAid to verify solutions that they have worked out by hand. Instructors
can use the program for grading homework and quizzes. We first introduce LogicAid in Unit 5. The
program has a Karnaugh Map Tutorial mode that is very useful in teaching students to solve Karnaugh
map problems. This tutorial mode helps students learn to derive minimum solutions from a Karnaugh
map by informing them at each step whether that step is correct or not. It also forces them to choose
essential prime implicants first. When in the KMap tutor mode, LogicAid prints “KMT” at the top of
each output page, so you can check to see if the problems were actually solved in the tutorial mode.
Students can use LogicAid to help them solve design problems in Units 8, 16, 18, 19 and other
units. For designing sequential circuits, they can input a state graph, convert it to a state table, reduce
the state table, make a state assignment, and derive minimized logic equations for outputs and flip-flop
inputs.
The LogicAid State Table Checker is useful for Units 14 and 16, and for other units in which
students construct state tables. It allows students to check their solutions without revealing the correct
4
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answers. If the solution is wrong, the program displays a short input sequence for which the student’s
table fails. The LogicAid folder on the CD contains encoded copies of solutions for most of the state
graph problems in Fundamentals of Logic Design, 7th Ed. If you wish to create a password-protected
solution file for other state table problems, enter the state table into LogicAid, syntax check it, and
then hold down the Ctrl key while you select Save As on the file menu. The Partial Graph Checker
serves as a state graph tutor that allows a student to check his work at each step while constructing
a state graph. If the student makes a mistake, it provides feedback so that the student can correct his
answer. The partial graph checker works with any state graph problem for which an encoded state table
solution file is provided.
The DirectVHDL simulator helps students learn VHDL syntax because it provides immediate
visual feedback when they make mistakes. Our students use it for simulating VHDL code in Units 10,
17, and 20. Students can simulate and debug their code at home and then bring the code into lab for
synthesis and hardware testing.
1.5. Suggested Equipment for Laboratory Exercises
Many types of logic lab equipment are available that are adequate to perform the lab
exercises. Since most logic design is done today using programmable logic instead of individual
ICs, we now recommend use of CPLDs or FPGAs for hardware implementation of logic circuit
designs. At the University of Texas, we are presently using the XILINX Spartan-3 FPGA boards,
which are available from Digilent. The Spartan-3 FPGA has more than an adequate number of
logic cells to implement the lab exercises in the text. The board has 8 switches, 4 pushbuttons, 8
single LEDs, and four 7-segment LEDs.. Information about this board and other CPLD and FPGA
boards made by Digilent can be found on their website, www.digilentinc.com. We use the board
in conjunction with the Xiliinx ISE software mentioned earlier.
5
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6
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 1 Solutions
II. SOLUTIONS TO HOMEWORK PROBLEMS
Unit 1 Problem Solutions
1.1 (a)
757.2510
1.1 (b)
16 | 7570.25
16 | 47 r5
16
16 | 2 r15=F16(4).00
0 r2
∴ 757.2510 = 2F5.4016
=
0010 1111 0101.0100 00002
2
F
5
4
0
1.1 (c)
16 | 3560.89
16 | 22 r4
16
16 | 1 r6(14).24
0 r1
16
(3).84
16
(13).44
16
(7).04
1.1 (d)
1063.510
16 | 10630.5
16 | 66 r7
16
16 | 4 r2(8).00
0 r4
∴1063.510 = 427.816
=
0100 0010 0111.10002
4
2
7
8
EB1.616 = E × 162 + B × 161 + 1 × 160 + 6 × 16–1
= 14 × 256 + 11 × 16 + 1 + 6/16 = 3761.37510
1110 1011 0001.011(0)2
E
B
1
6
1.2 (b)
59D.C16 = 5 × 162 + 9 × 161 + D × 160 + C × 16–1
= 5 × 256 + 9 × 16 + 13 + 12/16 =
1437.7510
0101 1001 1101.110016
5
9
D
C
2635.68 = 2 × 83 + 6 × 82 + 3 × 81 + 5 × 80 + 6 × 8–1
= 2 × 512 + 6 × 64 + 3 × 8 + 5 + 6/8 =
1437.7510
010 110 011 101.1108
2 6 3 5 6
1.4 (b)
1457.1110
7261.38 = 7 × 83 + 2 × 82 + 6 × 81 + 1 + 3 × 8–1
= 7 × 512 + 2 × 64 + 6 × 8 + 1 + 3/8 = 3761.37510
111 010 110 001.0118
7 2 6 1 3
1.3
16 | 1230.17
16 | 7 r11
16
0 r7(2).72
16
(11).52
16
(8).32
∴123.1710 = 7B.2B16
=
0111 1011.0010 10112
7
B
2
B
356.8910
∴ 356.8910 = 164.E316
=
0001 0110 0100.1110 00112
1
6
4
E
3
1.2 (a)
123.1710
3BA.2514 = 3 × 142 + 11 × 141 + 10 × 140 + 2 × 14–1
+ 5 ×14–2
= 588 + 154 + 10 + 0.1684 = 752.168410
6 | 7520.1684
6 | 125 r2
6
6 | 20 r5
(1).0104
6 | 3 r2
6
0 r3(0).0624
6
(0).3744
6
(2).2464
6
(1).4784
16 | 14570.11
16 | 91 r1
16
16 | 5 r11=B16(1).76
0 r5
16
(12).16
∴ 1457.1110 = 5B1.1C16
5
B 1
1 C
5B1.1C16 = 010110110001.000111002=2661.0708
2 6 6 1 0 7 0
∴ 3BA.2514 = 752.168410 = 3252.10026
7
1.4 (c)
5B1.1C16 = 11 23 01.01 304
5 B 1 1 C
1.4 (d)
DEC.A16 = D × 162 + E × 161 + C × 160 + A× 16–1
= 3328 + 224 + 12 + 0.625 =3564.62510
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 1 Solutions
1.5 (a)
1111 (Multiply)
1 11
1111 (Add) ×1010
+1010
0000
11001
1111
11110
1111 (Sub)
0000
−1010
011110
0101
1111
10010110
1.5 (b, c) See FLD p. 730 for solutions.
1.6, 1.7, See FLD p. 730 for solutions.
1.8, 1.9
1.10 (a) 1305.37510
16 | 111
6 r15 = F16
0.33
16
(5).28
16
(4).48
1.10 (c) 301.1210
r12
r6
0.375
16
(6).000
0.12
16
(1).92
16
(14).72
∴ 301.1210 = 12D.1E16
= 0001 0010 1101.0001 11102
1
2 D
1
E
∴ 111.3310 = 6F.5416
= 0110 1111.0101 01002
6
F
5
4
16 | 1644
16 | 102
6
r9
r1
∴ 1305.37510 = 519.60016
=
0101 0001 1001.0110 0000 00002
5
1
9
6
0
0
1.10 (b) 11.3310
1.10 (d) 1644.87510
16 | 1305
16 | 81
5
1.11 (a)
0.875
16
(14).000
∴ 1644.87510 = 66C.E0016
= 0110 0110 1100.1110 0000 00002
6
6
C
E
0
0
16 | 301
16 | 18
1
r13
r2
101 111 010 100.101 2 = 5724.58
= 5 × 83 + 7 × 82 + 2 × 81 + 4 × 80 + 5 × 8–1
= 5 × 512 + 7 × 64 + 2 × 8 + 4 + 5/8
= 3028.62510
1011 1101 0100.10102 = BD4.A16
B × 162 + D × 161 + 4 × 160 + A × 16–1
11 × 256 + 13 × 16 + 4 + 10/16
= 3028.62510
1.11 (b) 100 001 101 111.0102 = 4157.28
= 4 × 83 + 1 × 82 5 × 81 + 7 × 80 + 2 × 8–1
= 4 × 512 + 1 × 64 + 5 × 8 + 7 + 2/8
= 2159.2510
1000 0110 1111.01002 = 86F.416
= 8 × 162 + 6 × 161 + F × 160 × 4 × 16–1
= 8 × 256 + 6 × 16 + 15 + 4/16
= 2159.2510
1.12 (b) 384.7410
1.12 (a) 375.548 = 3 × 64+ 7 × 8 + 5 + 5/8 + 4/64
= 253.687510
3 | 2530.69
3 | 84 r1
3
3 | 28 r0(2).07
3 | 9 r1
3
3 | 3 r0(0).21
3 | 1 r0 3
0 r1(0).63
3
(1).89
∴ 375.548 = 100101.20013
1.12 (c) A52.A411 = 10 × 121 + 5 × 11 + 2 + 10/11 + 4/121
= 1267.9410
4 | 3840.74
4 | 96 r0
4
4 | 24 r0(2).96
4 | 6 r0
4
4 | 1 r2(3).84
0 r1 4
(3).36
∴ 384.7410 = 12000.2331134...
9 | 12670.94
9 | 140 r7
9
9 | 15 r5(8).46
9 | 1 r6
9
0 r1(4).14
∴ A52.A411 = 1267.9410 = 1657.84279...
8
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Unit 1 Solutions
1.13
544.19 = 5 × 92 + 4 × 91 + 4 × 90 + 1 × 9–1
= 5 × 81 + 4 × 9 + 4 + 1/9
= 445 1/910
16 | 4451/9
16 | 27 r13
16
16 | 1 r11(1)7/9
0 r1
16
(12)4/9
16
(7)1/9
∴ 544.19 = 1BD.1C716
= 1 1011 1101.0001 1100 01112...
1.14 (a), (c)
(b), (c)
1.14 (d)
3 | 97 .7
3 |32 r1
3
3 |10 r2(2).1
3 |3 r1
3
3 |1 r0
(0).3
0 r1 3
(0).9
3
(2).7
∴ 97.710 = 10121.2002....3
1.15
1.14 (e)
16 | 97 .7
16 | 6 r1
16
0 r6(11).2
16
(3).2
∴ 97.710 = 61.B3333....16
(a) 61.B3333..16
= 110 0001.1011 0011 0011 0011 0011... 2
(b) 1 100 001.101 100 110 011 001 100 11... 2
= 141.5 4631 4631.... 8
1110212.202113
01 11 02 12.20 21 10 = 1425.6739
Base 3
00
01
02
10
11
12
20
21
22
5 | 97 .7
5 |19 r2
5
5 |3 r4(3).5
0 r3
5
(2).5
∴ 97.710 = 342.322..5
1.16 (b)
1.16 (a) 2983 63/6410 =
8 | 29830.984
8 | 372 r7
8
8 | 46 r4
(7).872
9 | 5 r6
8
0 r5(6).976
Base 9
0
1
2
3
4
5
6
7
8
93.7010
8 | 930.70
8 | 11 r5
8
8 | 1 r3(5).60
0 r1
8
(4).80
∴ 93.7010 = 135.548 = 001 011 101.101 1002
∴ 2983 63/6410 = 5647.768 (or 5647.778)
= 101 110 100 111.111 1102
(or 101 110 100 111.111 1112)
1.16 (c) 1900 31/3210
8 | 19000.969
8 | 273 r4
8
8 | 29 r5
(7).752
9 | 3 r5
8
0 r3(6).016
1.16 (d)
∴ 1900 31/3210 = 3554.768
= 011 101 101 100.111 1102
109.3010
8 | 1090.30
8 | 13 r5
8
8 | 1 r5(2).40
0 r1
8
(3).20
∴ 109.3010 = 155.238
= 001 101 101.010 0112
9
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 1 Solutions
1.17 (a)
1 1 1
1.17 (b)
111
1111 (Add) 1111 (Subtract)
1001
1001
11000
0110
1111 (Multiply)
1001
1111
0000
01111
0000
001111
1111
10000111
1.17(c)
1
11 1
1 11
11
1101001(Add) 1101001 (Sub)
110110
110110
10011111
110011
1101001 (Mult)
110110
0000000
1101001
11010010
1101001
1001110110
0000000
1001110110
1101001
100100000110
1101001
1011000100110
1
1.18
110010 (Add)
110010 (Sub)
11101
11101
1001111 10101
110010 (Mult)
11101
110010
000000
0110010
110010
11111010
110010
1010001010
110010
10110101010
1
1
1
(a)
10100100
01110011
0110001
1
1
(b) 10010011
01011001
00111010
11
(c)
11110011
10011110
01010101
1.19(a)
101110 Quotient
101 )11101001
101
1001
101
1000
101
110
101
11 Remainder
1.19(b)
11011 Quotient
1110 )110000001
1110
10100
1110
11000
1110
10101
1110
111 Remainder
1.19(c)
1.20(a)
10111 Quotient
110 )10001101
110
1011
110
1010
110
1001
110
11 Remainder
1100 Quotient
1001 )1110010
1001
1010
1001
110 Remainder
10
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 1 Solutions
1.20(b)
100011 Quotient
1011 )110000011
1011
10001
1011
1101
1011
10 Remainder
1.20(c)
1011 Quotient
1010 )1110100
1010
10010
1010
10000
1010
110 Remainder
1.21
(a) 4 + 3 is 10 in base 7, i.e., the sum digit is
0 with a carry of 1 to the next column. 1 + 5 +
4 is 10 in base 7. 1 + 6 + 0 is 10 in base 7. This
overflows since the correct sum is 10007.
(b) 4 + 3 + 3 + 3 = 13 in base 10 and 23 in base
5. Try base 10. 1 + 2 + 4 + 1 + 3 = 11 in base 10 so
base 10 does not produce a sum digit of 2. Try base
5. 2 + 2 + 4 + 1 + 3 = 22 in base 5 so base 5 works.
(c) 4 + 3 + 3 + 3 = 31 in base 4, 21 in base 6,
and 11 in base 12. Try base 12. 1 + 2 + 4 + 1 + 3 =
B in base 12 so base 12 does not work. Try base 4.
3 + 2 + 4 + 1 + 3 = 31 in base 4 so base 4 does not
work. Try base 6. 2 + 2 + 4 + 1 + 3 = 20 so base 6
is correct.
1.22
If the binary number has n bits (to the right of the
radix point), then its precision is (1/2n+1). So to
have the same precision, n must satisfy
(1/2n+1) < (1/2)(1/104) or n > 4/(log 2) = 13.28 so n
must be 14.
1.23
1.24 (a) Expand the base b number into a power series
N = d3k-1b3k-1 + d3k-2b3k-2 + d3k-3b3k-3 + …. +
d5b5 + d4b4 + d3b3 + d2b2 + d1b1 + d0b0 + d-1b-1 +
d-2b-2 + d-3b-3 + …. + d-3m+2b-3m+2 + d-3m+1b-3m+1
+ d-3mb-3m where each di has a value from 0 to
(b-1). (Note that 0’s can be appended to the number
so that it has a multiple of 3 digits to the left and
right of the radix point.) Factor b3 from each group
of 3 consecutive digits of the number to obtain
N = (d3k-1b2 + d3k-2b1 + d3k-3b0)(b3)(k-1) + ….
1.24 (b)
+ (d5b2 + d4b1 + d3b0)(b3)1 + (d2b2 + d1b1 +
d0b0 )(b3)0 + (d-1b2 + d-2b1 + d-3b0)(b3)-1 + …. +
(d-3m+2b2 + d-3m+1b1 + d-3mb0)(b3)-m
Each (d3i-1b2 + d3i-2b1 + d3i-3b0) has a value from
0 to [(b-1)b2 + (b-1)b1 + (b-1)b0]
= (b-1)( b2 + b1 + b0) = (b3-1)
so it is a valid digit in a base b3 number.
Consequently, the last expression is the power
series expansion for a base b3 number.
.363636....
= (36/102)(1 + 1/102 + 1/104 + 1/106 + …)
= (36/102)[1/(1 – 1/102)] = (36/102)[102/99]
= 36/99 = 4/11
8(4/11) = 2 + 10/11
8(10/11) = 7 + 3/11
8(3/11) = 2 + 2/11
8(2/11) = 1 + 5/11
8(5/11) =3 + 7/11
8(7/11) = 5+ 1/11
8(1/11) = 0 + 8/11
8(8/11) = 5 + 9/11
8(9/11) = 6 + 6/11
8(6/11) = 4 + 4/11
8(4/11) = 2 + 10/11
Repeats: .27213505642…….
Expand the base b3 number into a power series
N = dk(b3)k + dk-1(b3)k-1 + … + d1(b3)1 + d0(b3)0
+ d-1(b3)-1 + …. + d-m(b3)-m
where each di has a value from 0 to (b3 -1).
Consequently, di can be represented as a base b
number in the form
(e3i-1b2 + e3i-2b1 + e3i-3b0)
Where each ej has a value from 0 to (b-1).
Substituting these expressions for the di produces a
power series expansion for a base b number.
1.25(a)
(5 - 1) = 45, (52 - 1) = 445 and (53 - 1) = 4445
1.26(a)
(b + 1)2 = b2 + 2b + 1 so (11b)2 = 121b if b > 2.
1.25(b)
(bn-1) = (b - 1)(bn-1) + bn-1
= (b - 1)bn-1 + (b - 1)bn-2 + bn-2
= (b - 1)bn-1 + (b - 1)bn-2 + …
+ (b - 1)b + (b - 1)
This expression is the polynomial expansion for the
base b number with n digits (b - 1)(b - 1) … (b - 1)
1.26(b)
(b2 + b + 1)2 = b4 + 2b3 + 3b2 + 2b + 1 so
(111b)2 = 12321b if b > 3.
2
(b + 2b + 1)2 = b4 + 4b3 + 6b2 + 4b + 1 so
(121b)2 = 14641b if b > 6.
3
(b + b2 + b + 1)2 = b6 + 2b5 + 3b4 + 4b3 + 3b2 +
2b + 1 so (1111b)2 = 1234321b if b > 4.
11
1.26(c)
1.26(d)
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 1 Solutions
1.27(a)
1.27(b)
1.27(c)
1.27(d)
1.30
1.28
(0.12)3 = (1/3 + 2/9)10 = (2/6 + 8/36)10
= (3/6 + 2/36)10 = (0.32)6
(0.375)10 = (3/8)10 = (0.3)8
0
1
2
3
4
5
6
7
8
9
(a-1R-1 + a-2R-2 + ... + a-mR-m)Sn will be an
integer for every N only if Rm divides Sn for
some n. Hence, each factor of R must be a factor
of S, not necessarily the same number of times.
For a specific number N, (a-1R-1 + a-2R-2 + ...
+ a-mR-m)Sn will be an integer if each factor of
Rm is a factor of either Sn or
(a-1Rm-1 + a-2Rm-2 + ... + a-m)
5-4-1-1 is not possible, because there is no way to
represent 3 or 8. 6-3-2-1 is possible:
0
1
2
3
4
5
6
7
8
9
6321
0000
0001
0010
0100
0101
0110
1000
1001
1010
1100
3
0
0
0
1
0
0
0
1
1
1
2
0
0
1
0
0
0
1
0
0
1
1
0
1
0
0
0
1
0
0
1
0
9154 =
1110 0001 1001 1000
53
00
00
00
01
01
10
10
10
11
11
0
1
2
3
4
5
6
7
8
9
1
0
0
1
0
0
0
0
1
0
0
1
0
1
1
0
1
0
1
1
0
1
(0010)
(0110)
(1010)
(1110)
1.32
Alternate
Solutions:
1.31
1.33
0
1
2
3
4
5
6
7
8
9
Alternate
Solutions:
73
0 00
1 00
2 00
3 01
4 01
5 01
6 01
7 10
8 10
9 10
A 11
B 11
4
0
0
0
0
1
1
1
1
1
1
1.29
5-3-1-1 is possible, but
6-4-1-1 is not, because
there is no way to
represent 3 or 9.
Alternate
Solutions:
21
00
01
10
00
01
10
11
00
01
10
00
01
(0011)
62
00
00
00
00
01
01
10
10
10
10
21
00
01
10
11
10
11
00
01
10
11
(0100)
(0101)
(1100)
(1101)
1100 0011 = 83
1.34
(a)
0
1
2
3
4
5
6
7
8
9
(1011)
B4A9 = 1101 0101 1100 1010
Alt.: = "
" 1011 "
12
8 4 -2-1
00 00
01 11
01 10
01 01
01 00
10 11
10 10
10 01
10 00
11 11
Alternate
Solutions:
0
1
2
3
4
5
6
7
8
9
52 2 1
00 0 0
00 0 1
00 1 0
00 1 1
01 1 0
10 0 0
10 0 1
10 1 0
10 1 1
11 1 0
1110 0110 = 94
(b)
The 9’s
complement
of a decimal
number
represented
with this
weighted code
can be obtained
by replacing
0's with 1's
and 1's with
0's (bit-by-bit
complement).
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
(0100)
(0101)
(1100)
(1101)
Unit 1 Solutions
1.35 (a) 222.2210
0.22
r14
16
r13
(3).52
16
(8).32
∴ 222.2210 = DE.3816
= 1000100 1000101 0101110 0110011 0111000
D
E
.
3
8
1.36 (a)
16 | 222
16 | 13
0
In 2’s complement
In 1’s complement
(–10) + (–11)
(–10) + (–11)
110110
110101
110101
110100
(1)101011 (–21)
(1)101001
1
101010 (–21)
1.35 (b) 183.8110
16 | 183
16 | 11
0
0.81
16
(12).96
16
(15).36
∴ 183.8110 = B7.CF16
= 1000010 0110111 0101110 1000011 1000110
B
7
.
C
F
r7
r11
1.36 (b)
In 2’s complement
In 1’s complement
(–10) + (–6) (–10) + (–6)
110110 110101
111010 111001
(1)110000 (–16)
(1)101110
1
101111 (–16)
1.36 (c) In 2’s complement In 1’s complement
(–8) + (–11) (–8) + (–11)
111000110111
110101
110100
(1)101101 (–19)
(1)101011
1
101100 (–19)
1.36(d)
In 2’s complement In 1’s complement
11 + 9 11 + 9
001011001011
001001
001001
010100 (20) 010100 (20)
1.36 (e)
In 2’s complement In 1’s complement
(–11) + (–4) (–11) + (–4)
110101 110100
111100 111011
(1)110001 (–15) (1)101111
1
110000 (–15)
1.37 (a)
01001-11010
In 2’s complement
01001
+ 00110
01111
In 1’s complement
01001
+ 00101
01110
1.37 (b)
In 2’s complement
11010
+ 00111
(1)00001
In 1’s complement
11010
+ 00110
(1)00000
1
00001
1.37 (c)
In 2’s complement
10110
+ 10011
(1)01001
overflow
In 1’s complement
10110
+ 10010
(1)01000
1
01001
overflow
1.37 (d)
In 2’s complement
11011
+ 11001
(1)10100
In 1’s complement
11011
+ 11000
(1)10011
1
10100
1.37 (e) In 2’s complement
11100
+ 01011
(1)00111
1.38 (a)
In 2’s complement
11010
+ 01100
(1)00110
In 1’s complement
11010
+ 01011
(1)00101
1
00110
1.38 (b)
13
In 2’s complement
01011
+ 01000
10011
In 1’s complement
11100
+ 01010
(1)00110
1
00111
In 1’s complement
01011
+ 00111
10010
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 1 Solutions
1.38 (c) In 2’s complement
10001
+ 10110
(1)00111
overflow
1.39
1.41
In 1’s complement
10001
+ 10101
(1)00110
1
00111
overflow
1.38 (d) In 2’s complement
10101
+ 00110
11011
add subt
101010 101010
+ 011101
- 011101
(1)000111001101
1 overflow
001000
(b)
add subt
101010 101010
+ 011101
- 011101
(1)000111001101
overflow
1.40
(a) (16)(4) = 64, add 2 0’s to get 6400
(10)(2) = 20, add 1 0 to get 200
(7)(1) = 7
6400 + 200 + 7 = 6607
1.42
(a)
(b)
(b) (dn-1dn-2 … d1d0)20 = dn-1(20)n-1 +
dn-2(20)n-2 + … + d1(20)1 + d0(20)0 =
dn-1(2)n-1(10)n-1 + dn-2(2)n-2(10)n-2 + …
+ d1(2)1(10)1 + d0(2)0(10)0 = The general term
in the expansion is di(2)i(10)i. The multiplication
by (10)i adds i 0’s on the right of di(2)i.
14
00000000 (0)
00000010 (2)
11001101 (-51)
10000000 (-128)
(a) If A + B < 2n-1 - 1, then the sign bit of A + B is
0 indicating a positive number with magnitude
A + B. If A + B > 2n-1 - 1, then the sign bit
of A + B is 1 indicating a negative number with
magnitude 2n - (A + B).
(c) After ignoring the carry from the sign position,
(2n - A) + (2n - B) = 2n - (A + B). If (A + B) <
2n-1, 2n - (A + B) > 2n - 2n-1 = 2n-1 so the sign
bit of 2n - (A + B) is 1 indicating a negative
number with magnitude (A + B). If (A + B) >
2n-1, 2n - (A + B) < 2n - 2n-1 = 2n-1 so the sign
bit of 2n - (A + B) is 0 indicating a positive
number with magnitude 2n - (A + B).
(d) 15/2 = 7.5 shifted right 1 place is 0.75
10/4 = 2.5 shifted right 2 places is 0.025
7/8 = 0.875 shifted right 3 places is 0.000875
0.75 + 0.025 + 0.000875 = 0.775875
A and B positive: Overflow does not occur if
A + B < 2n - 1 - 1 in which case A + B has a sign
bit of 0 and has a magnitude of A + B.
A positive and B negative and A > |B|: A + 2n 1 - B = 2n - 1 + (A - B) > 2n - 1 so there is a carry
from the sign position and, after the end-around
carry, the result is (A - B).
A positive and B negative and A < |B|: A + 2n 1 - B = 2n - 1 - (B - A) < 2n - 1 so there is no carry
from the sign position and the sign bit is 1 so the
result represents a negative number with magnitude
(B - A).
i) 00000000 (0)
ii) 11111110 (-2)
iii) 00110011 (51)
iv) 10000000 (-128)
complement
11111111 (-0)
00000001 (1)
11001100 (-51)
01111111 (127)
(b) If A > B, then A + (-B) = A + (2n - B) = 2n
+ (A - B) is > 2n so there is a carry from the sign
position that is ignored and the sum is (A - B). If
A < B, then A + (-B) = A + (2n - B) = 2n (B - A) is < 2n and > 2n-1 so there is no carry
from the sign position and the sign bit is 1.
2n - (B - A) represents a negative number of
magnitude (B - A).
(c) The algorithm would be divide d-i by 2i and
shift the result i places to the right, then add all
terms.
1.43
(a)
i) 00000000 (0)
ii) 11111110 (-1)
iii) 00110011 (51)
iv) 10000000 (-127)
In 1’s complement
10101
+ 00101
11010
1.43
cont.
A and B negative: (2n - 1 - A) + (2n - 1 - B) =
n
2 - 1 - (A + B) after the end-around carry. There
is no overflow if A + B < 2n - 1 - 1 in which case
2n - 1 - (A + B) > 2n - 1 so the sign bit is 1 and the
result represents a negative number with magnitude
(A + B).
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 1 Solutions
1.44
1.45
Two positive numbers
No overflow: 0x…x + 0x…x = 0x…x
carry in = 0 = carry out
Overflow: 0x…x + 0x…x = 1x…x
carry in = 1, carry out = 0
Two negative numbers
No overflow: 1x…x + 1x…x = 1x…x
carry in = 1 = carry out
Overflow: 1x…x + 1x…x = 0x…x
carry in = 0, carry out = 1
No overflow
10101
+ 11010
(1)01111
1
10000
A positive and a negative number
No overflow: 0x…x + 1x…x = 0x…x
carry in = 1 = carry out
No overflow: 0x…x + 1x…x = 1x…x
carry in = 0 = carry out
1.46
There is no overflow if the carry into the sign
position equals the carry out of the sign position.
There is overflow if the carry into the sign position
does not equal the carry out of the sign position
unless an end around carry causes a carry into the
sign position.
Overflow
11001
+ 10101
(1)01110
1
01111
If bn-1 = 0, then bn-22n-2 + bn-32n-3 + … + b12
+ b0 is the value of the positive number. If bn-1 =
1, then
- 2n-1 + bn-22n-2 + bn-32n-3 + … + b12 + b0
= - (2n-2 + 2n-3 + … + 2 + 1 + 1) +
bn-22n-2 + bn-32n-3 + … + b12 + b0
= - [(1 - bn-2)2n-2 + (1 - bn-3)2n-3 + …
+ (1 - b1)2 + (1 - b0) + 1].
The expression in brackets has each bit
complemented and 1 added to the result.
15
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 1 Solutions
16
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 2 Solutions
Unit 2 Problem Solutions
2.1
See FLD p. 731 for solution.
2.2 (a)
In both cases, if X = 0, the transmission is 0, and if
X = 1, the transmission is 1.
X
X
2.2 (b)
In both cases, if X = 0, the transmission is YZ, and
if X = 1, the transmission is 1.
X
X
Y
Y
Z
X
X
Y
Z
2.3
Answer is in FLD p. 731
2.4 (a)
F = [(A·1) + (A·1)] + E + BCD = A + E + BCD
2.4 (b)
Y = (AB' + (AB + B)) B + A = (AB' + B) B + A
= (A + B) B + A = AB + B + A = A + B
2.5 (a)
(A + B) (C + B) (D' + B) (ACD' + E)
= (AC + B) (D' + B) (ACD' + E) By Dist. Law
= (ACD' + B) (ACD' + E) By Dist. Law
= ACD' + BE By Dist. Law
2.5 (b)
(A' + B + C') (A' + C' + D) (B' + D')
= (A' + C' + BD) (B' + D')
{By Distributive Law with X = A' + C'}
= A'B' + B'C' + B'BD + A'D' + C'D' + BDD'
= A'B' + A'D' + C'B' + C'D'
2.6 (a)
AB + C'D' = (AB + C') (AB + D')
= (A + C') (B + C') (A + D') (B + D')
2.6 (b)
WX + WY'X + ZYX = X(W + WY' + ZY)
= X(W + ZY)
{By Absorption}
= X(W +Z) (W + Y)
2.6 (c)
A'BC + EF + DEF' = A'BC + E(F +DF')
= A'BC + E(F +D) = (A'BC + E) (A'BC + F + D)
= (A' + E) (B + E) (C + E) (A' + F + D)
(B + F + D) (C + F + D)
2.6 (d)
XYZ + W'Z + XQ'Z = Z(XY + W' + XQ')
= Z[W' + X(Y + Q')]
= Z(W' + X) (W' + Y + Q') By Distributive Law
2.6 (e)
ACD' + C'D' + A'C = D' (AC + C') + A'C
= D' (A + C') + A'C By Elimination Theorem
= (D' + A'C) (A + C' + A'C)
= (D' + A') (D' + C) (A + C' + A')
By Distributive Law and Elimination Theorem
= (A' + D') (C + D')
(A + B + C + D) (A + B + C + E) (A + B + C + F)
= A + B + C + DEF
Apply second Distributive Law twice
2.6 (f)
A + BC + DE
= (A + BC + D)( A + BC + E)
= (A + B + D)(A + C + D)(A + B + E)(A + C + E)
2.7 (b)
WXYZ + VXYZ + UXYZ = XYZ (W + V + U)
By first Distributive Law
2.7 (a)
D
E
F
2.8 (a)
2.8 (c)
2.9 (a)
A
B
U
V
W
C
X
Y
Z
[(AB)' + C'D]' = AB(C'D)' = AB(C + D')
= ABC + ABD'
((A + B') C)' (A + B) (C + A)'
= (A'B + C') (A + B)C'A' = (A'B + C')A'BC'
= A'BC'
2.8 (b)
[A + B (C' + D)]' = A'(B(C' + D))'
= A'(B' + (C' + D)') = A'(B' + CD')
= A'B' + A'CD'
F = [(A + B)' + (A + (A + B)')'] (A + (A + B)')'
= (A + (A + B)')'
By Elimination Theorem with
X=(A+(A+B)')' = A'(A + B) = A'B
2.9 (b)
G = {[(R + S + T)' PT(R + S)']' T}'
= (R + S + T)' PT(R + S)' + T'
= T' + (R'S'T') P(R'S')T = T' + PR'S'T'T = T'
17
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 2 Solutions
2.10 (a)
X
Y
2.10 (c)
X
X
Y'
X'
2.10 (e)
X
X
Y
X
Z
X
Y
X
2.10 (d)
Y'
A
Y
2.10 (f)
B
X
X
Y
C
A
B
A
Z
X
Y
Z
Y
2.11 (a) (A' + B' + C)(A' + B' + C)' = 0 By
Complementarity Law
2.11 (c) AB + (C' + D)(AB)' = AB + C' + D
By Elimination Theorem
2.10 (b)
C'
X
B
X
Y
2.11 (b) AB(C' + D) + B(C' + D) = B(C' + D) By
Absorption
2.11 (d) (A'BF + CD')(A'BF + CEG) = A'BF + CD'EG
By Distributive Law
Z
2.11 (e) [AB' + (C + D)' +E'F](C + D)
= AB'(C + D) + E'F(C + D) Distributive Law
2.11 (f)
2.12 (a) (X + Y'Z) + (X + Y'Z)' = 1 By Complementarity
Law
2.12 (b) [W + X'(Y +Z)][W' + X' (Y + Z)] = X'(Y + Z)
By Uniting Theorem
2.12 (c) (V'W + UX)' (UX + Y + Z + V'W) = (V'W + UX)'
(Y + Z) By Elimination Theorem
2.12 (d) (UV' + W'X)(UV' + W'X + Y'Z) = UV' + W'X
By Absorption Theorem
2.12 (e) (W' + X)(Y + Z') + (W' + X)'(Y + Z')
= (Y + Z') By Uniting Theorem
2.12 (f) (V' + U + W)[(W + X) + Y + UZ'] + [(W + X) +
UZ' + Y] = (W + X) + UZ' + Y By Absorption
2.13 (a) F1 = A'A + B + (B + B) = 0 + B + B = B
2.13 (b) F2 = A'A' + AB' = A' + AB' = A' + B'
2.13 (c) F3 = [(AB + C)'D][(AB + C) + D]
= (AB + C)'D (AB + C) + (AB + C)' D
= (AB + C)' D By Absorption
2.13 (d) Z = [(A + B)C]' + (A + B)CD = [(A + B)C]' + D
By Elimination with X = [(A + B) C]'
= A'B' + C' + D'
2.14 (a) ACF(B + E + D)
2.14 (b) W + Y + Z + VUX
2.15 (a) f ' = {[A + (BCD)'][(AD)' + B(C' + A)]}'
= [A + (BCD)']' + [(AD)' + B(C' + A)]'
= A'(BCD)'' + (AD)''[B(C' + A)]'
= A'BCD + AD[B' + (C' + A)']
= A'BCD + AD[B' + C''A']
= A'BCD + AD[B' + CA']
2.15(b)
2.16 (a) f D = [A + (BCD)'][(AD)' + B(C' + A)]D
= [A (B + C + D)'] + [(A + D)'(B + C'A)]
2.16 (b) f D = [AB'C + (A' + B + D)(ABD' + B')]D
= (A + B' + C)[A'BD + (A + B + D' )B')
2.17 (a) f = [(A' + B)C] + [A(B + C')]
= A'C + B'C + AB + AC'
= A'C + B'C + AB + AC' + BC
= A'C + C + AB + AC' = C + AB + A = C + A
2.17 (c) f = (A' + B' + A)(A + C)(A' + B' + C' + B)
(B + C + C') = (A + C)
2.17 (b) f = A'C + B'C + AB + AC' = A + C
18
A'(B + C)(D'E + F)' + (D'E + F)
= A'(B + C) + D'E + F By Elimination
f ' = [AB'C + (A' + B + D)(ABD' + B')]'
= (AB'C)'[(A' + B + D)(ABD' + B']'
= (A' + B'' + C')[(A' + B + D)' + (ABD')'B'']
= (A' + B + C')[A''B'D' + (A' + B' + D'')B]
= (A' + B + C')[AB'D' + (A' + B' + D)B]
2.18 (a) product term, sum-of-products, product-of-sums)
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 2 Solutions
2.18 (b) sum-of-products
2.18 (c) none apply
2.18 (d) sum term, sum-of-products, product-of-sums
2.18 (e) product-of-sums
2.19
2.20 (a) F = D[(A' + B' )C + AC' ]
W
Z
Z
+
X
2.20 (b) F = D[(A' + B' )C + AC' ]
= A' CD + B' CD +AC' D
+
X
Y
F
W
+
Y
2.20 (c) F = D[(A' + B' )C + AC' ]
= D(A' + B' + AC' )(C + AC' )
= D(A' + B' + C' )(C + A)
A'
D
B'
C'
2.21
C
A
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
A'
C
D
B'
C
D
A
C'
D
C
0
1
0
1
0
1
0
1
H
0
1
1
1
0
1
0
1
F
0
1
0
1
0
0
0
1
G
0
x
1
x
0
1
0
x
2.22 (a) A'B' + A'CD + A'DE'
= A'(B' + CD + DE')
= A'[B' + D(C + E')]
= A'(B' + D)(B' + C + E')
2.22 (d) A'B' + (CD' + E) = A'B' + (C + E)(D' + E)
= (A'B' + C + E)(A'B' + D' + E)
= (A' + C + E)(B' + C + E)
(A' + D' + E)(B' + D' + E)
2.22 (b) H'I' + JK
= (H'I' + J)(H'I' + K)
= (H' + J)(I' + J)(H' + K)(I' + K)
2.22 (e) A'B'C + B'CD' + EF' = A'B'C + B'CD' + EF'
= B'C (A' + D') + EF'
= (B'C + EF')(A' + D' + EF')
= (B' + E)(B' + F')(C + E)(C + F' )
(A' + D' + E)(A' + D' + F')
2.22 (c) A'BC + AB'C + CD'
= C(A'B + AB' + D')
= C[(A + B)(A' + B') + D']
= C(A + B + D')(A' + B' + D')
2.22 (f) WX'Y + W'X' + W'Y' = X'(WY + W') + W'Y'
= X'(W' + Y) + W'Y'
= (X' + W')(X' + Y')(W' + Y + W')(W' + Y + Y')
= (X' + W')(X' + Y')(W' + Y)
2.23 (a) W + U'YV = (W + U')(W + Y)(W + V)
2.23 (b) TW + UY' + V
= (T+U+Z)(T+Y'+V)(W+U+V)(W+Y'+V)
2.23 (c) A'B'C + B'CD' + B'E' = B'(A'C + CD' + E')
= B'[E' + C(A' + D')]
= B'(E' + C)(E' + A' + D')
2.23 (d) ABC + ADE' + ABF' = A(BC + DE' + BF')
= A[DE' + B(C + F')]
= A(DE' + B)(DE' + C + F')
= A(B + D)(B + E')(C + F' + D)(C + F' + E')
19
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 2 Solutions
2.24 (a)
[(XY')' + (X' + Y)'Z] = X' + Y + (X' + Y)'Z
= X' + Y'+ Z By Elimination Theorem with X
= (X' + Y)
2.24 (c)
[(A' + B')' + (A'B'C)' + C'D]'
= (A' + B')A'B'C(C + D') = A'B'C
2.25 (a)
F(P, Q, R, S)' = [(R' + PQ)S]' = R(P' + Q') + S'
= RP' + RQ' + S'
2.25 (c)
F(A, B, C, D)' = [A' + B' + ACD]'
= [A' + B' + CD]' = AB(C' + D')
2.26 (a)
F = [(A' + B)'B]'C + B = [A' + B + B']C + B
=C+B
2.26 (c)
H = [W'X'(Y' + Z')]' = W + X + YZ
2.24 (b)
(X + (Y'(Z + W)')')' = X'Y'(Z + W)' = X'Y'Z'W'
2.24 (d)
(A + B)CD + (A + B)' = CD + (A + B)'
{By Elimination Theorem with X = (A + B)'}
= CD + A'B'
2.25 (b) F(W, X, Y, Z)' = [X + YZ(W + X')]'
= [X + X'YZ + WYZ]'
= [X + YZ + WYZ]' = [X + YZ]'
= X'Y' + X'Z'
2.26 (b) G = [(AB)'(B + C)]'C = (AB + B'C')C = ABC
2.27
F = (V + X + W) (V + X + Y) (V + Z)
= (V + X + WY)(V + Z) = V + Z (X + WY)
By Distributive Law with X = V
W
Y
2.28 (a)
X
+
Z
+
V
F
2.28 (b) Beginning with the answer to (a):
F = ABC + A'BC + AB'C + ABC'
= BC + AB'C + ABC' (By Uniting Theorem)
= C (B + AB') + ABC' = C (A+ B) + ABC'
(By Elimination Theorem)
= AC + BC + ABC' = AC + B (C + AC')
= AC + B (A + C) = AC + AB + BC
F = A (B + C) + BC
B
C
B
C
A
+
+
B
C
F
Alternate solutions:
F = AB + C(A + B)
A
C
+
F = AC + B(A + C)
F
A
B
2.29 (a)
XYZ
X+Y
X'+Z
000
001
010
011
100
101
110
111
0
0
1
1
1
1
1
1
1
1
1
1
0
1
0
1
(X+Y)
(X'+Z)
0
0
1
1
0
1
0
1
XZ
X'Y
XZ+X'Y
0
0
0
0
0
1
0
1
0
0
1
1
0
0
0
0
0
0
1
1
0
1
0
1
20
2.29 (b)
XYZ
X+Y
Y+Z
X'+Z
000
001
010
011
100
101
110
111
0
0
1
1
1
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
0
1
0
1
(X+Y)
(Y+Z)
(X'+Z)
0
0
1
1
0
1
0
1
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
(X+Y)
(X'+Z)
0
0
1
1
0
1
0
1
Unit 2 Solutions
2-29 (c)
2.29 (e)
2.30
XYZ
000
001
010
011
100
101
110
111
WXYZ
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
XY
0
0
0
0
0
0
1
1
YZ
0
0
0
1
0
0
0
1
W'XY
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
X'Z
0
1
0
1
0
0
0
0
WZ
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
XY+YZ+X'Z
0
1
0
1
0
0
1
1
W'XY+WZ
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
1
2.29 (d) A B C
XY+X'Z
0
1
0
1
0
0
1
1
W'+Z
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
000
001
010
011
100
101
110
111
W+XY
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
A+C
AB+C'
0
1
0
1
1
1
1
1
1
0
1
0
1
0
1
1
(A+C)
(AB+C')
0
0
0
0
1
0
1
1
AB
AC'
0
0
0
0
0
0
1
1
0
0
0
0
1
0
1
0
(W'+Z)(W+XY)
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
1
F = (X+Y')Z + X'YZ' (from the circuit)
= (X+Y'+ X'YZ')( Z+X'YZ') (Distributive Law)
= (X+Y'+X')(X+Y'+Y)(X+Y'+Z')(Z+X')(Z+Y)(Z+Z')
(Distributive Law)
= (1+Y')(X+1)(X+Y'+Z')(Z+X')(Z+Y)(1) (Complementation Laws)
= (1)(1)(X+Y'+Z')(Z+X')(Z+Y)(1) (Operations with 0 and 1)
= (X+Y'+Z')(Z+X')(Z+Y) (Operations with 0 and 1)
G = (X +Y' + Z' )(X' + Z)(Y + Z) 21
(from the circuit)
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
AB
+AC'
0
0
0
0
1
0
1
1
Unit 2 Solutions
22
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 3 Solutions
Unit 3 Problem Solutions
3.6 (a) (W + X' + Z') (W' + Y') (W' + X + Z') (W + X') (W + Y + Z)
= (W + X') (W' + Y') (W' + X + Z') (W + Y + Z)
= (W + X') [W' + Y' (X + Z')] (W + Y + Z )
= [W + X' (Y + Z)] [W' + Y'(X + Z')] = WY' (X + Z') + W'X' (Y + Z) {Using (X + Y) (X' + Z) = X'Y +XZ with X = W}
= WY'X + WY'Z' + W'X'Y + W'X'Z
3.6 (b)
(A + B + C + D) (A' + B' + C + D') (A' + C) (A + D) (B + C + D)
= (B + C + D) (A' + C) (A + D) = (B + C + D) (A'D + AC) {Using (X + Y) (X' + Z) = X'Y + XZ with X = A}
= A'DB + A'DC + A'D + ABC + AC + ACD = A'D + AC
3.7 (a)
BCD + C'D' + B'C'D + CD
3.7 (b)
= CD + C'(D' + B'D) = (C' + D) [C + (D' + B'D)] {Using (X + Y) (X' + Z) = X'Y + XZ with X = C}
= (C' + D) [C + (D' + B') (D' + D)] = (C' + D) (C + D' + B')
A'C'D' + ABD' + A'CD + B'D
= D' (A'C' + AB) + D (A'C + B')
= D' [(A' + B) (A + C')] + D [(B' + A') (B' + C)] {Using XY + X'Z = (X' + Y) (X + Z) twice inside the brackets}
= [D + (A' + B) (A + C')] [D' + (B' + A') (B' + C)] {Using XY + X'Z = (X' + Y) (X + Z) with X = D}
= (D + A' + B) (D + A + C') (D' + B' + A') ( D' + B' + C) {Using the Distributive Law}
3.8
3.9
F = AB ⊕ [(A ≡ D) + D] = AB ⊕ (AD + A'D' + D) = AB ⊕ (A'D' + D) = AB ⊕ (A' + D)
= (AB)' (A' + D) + AB(A' + D)' = (A' + B') (A' + D) + AB(AD')
= A' + B'D + ABD' {Using (X + Y) (X + Z) = X + YZ} = A' + BD' + B'D {Using X + X'Y = X + Y}
A ⊕ BC = (A ⊕ B) (A ⊕ C) is not a valid distributive law. PROOF: Let A = 1, B = 1, C = 0.
LHS: A ⊕ BC = 1⊕ 1 · 0 = 1 ⊕ 0 = 1. RHS: (A⊕ B) (A ⊕ C) = (1 ⊕ 1) (1 ⊕ 0) = 0 · 1 = 0.
3.10 (a) (X + W) (Y ⊕ Z) + XW'
= (X + W) (YZ' + Y'Z) + XW'
3.10 (b) (A ⊕ BC) + BD + ACD = A'BC + A(BC)' + BD +
ACD
= A'BC + A (B' + C') + BD + ACD
= A'BC + AB' + AC' + BD + ACD
= XYZ' + XY'Z + WYZ' + WY'Z + XW'
= A'BC + AB' + AC' + AD + BD + ACD
(Add consensus term AD, eliminate ACD)
= A'BC + AB' + AC' + BD
(Remove consensus term AD)
Using Consensus Theorem
WYZ' + WY'Z + XW'
3.10 (c)
(A' + C' + D') (A' + B + C') (A + B + D) (A + C + D)
= (A' + C' + D') (B + C' + D) (A' + B + C') (A + B + D) (A + C + D) Add consensus term
= (A' + B + C') (A + B + D)
= (A' + C' + D') (B + C' + D) (A + C + D) Removing consensus terms
23
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 3 Solutions
3.11
(A + B' + C + E') (A + B' + D' + E) (B' + C' + D' + E') = [A + B' + (C + E') (D' + E)] (B' + C' + D' + E')
= (A + B' + D'E' + CE) (B' + C' + D' + E') = B' + (A + D'E' + CE) (C' + D' + E')
CD' {Add consensus term}
= B' + AC' + AD' + AE' + C'D'E' + D'E' + D'E' + CD'E = B' + AC' + AD' + AE' + CD' +CD'E + D'E'
= B' + AC' + AE' + CD' + D'E'
3.12
A'CD'E + A'B'D' + ABCE + ABD = A'B'D' + ABD + BCD'E
Proof: LHS: A'CD'E + BCD'E + A'B'D' + ABCE + ABD Add consensus term to left-hand side and use it to
eliminate two consensus terms
= BCD'E + A'B'D' + ABD
This yields the right-hand side.
∴ LHS = RHS
3.13 (a) KLMN' + K'L'MN + MN' = K'L'MN + MN' = M(K'L'N + N') = M(N' + K'L') {Elimination with X = N'} = MN' + K'L'M
3.13 (b) KL'M' + MN' + LM'N' = KL'M' + N'(M + LM') = KL'M' + N'(M + L) = KL'M' + MN' + LN'
3.13 (c) (K + L') (K' + L' + N) (L' + M + N') = L' + K (K' + N) (M + N') = L' + KN (M + N') = L' + KMN
3.13 (d) (K' + L + M' + N) (K' + M' + N + R) (K' +M' + N + R') KM
= [K' + M' + (L + N) (N + R) (N + R')] KM {Distributive Law twice with X = K' + M'} = [K' + M' + (L + N)N] KM
= [K' + M' + N] KM = KMN
3.14 (a) K'L'M + KM'N + KLM + LM'N' = M' (KN + LN') + M (K'L' + KL)
= M' [(K + N') (L + N)] + M [(K' + L) (K + L')] {Multiplying out and factoring twice with X = N and X = L}
= [M + (K + N') (L + N) ] [M' + (K' + L) (K + L')] {Multiplying out and factoring with X = M}
= (M + K + N') (M + L + N) (M' + K' + L) (M' + K + L') {Distributive Law}
3.14 (b) KL + K'L' + L'M'N' + LMN' = L' (K' + M'N') + L (K + MN')
= (L + K' + M'N') (L' + K + MN') {Multiplying out and factoring with X = L}
= (L + K' + M') (L + K' + N') (L' + K + M) (L' + K + N')
3.14 (c) KL + K'L'M + L'M'N + LM'N' = L' [K'M + M'N] + L [K + M'N'] = L' [(M + N) (M' + K')] + L [(K + M') (K + N')]
= [L + (M + N) (M' + K')][L' + (K + M') (K + N')] = (L + M + N) (L + M' + K') (L' + K + M') (L' + K + N')
3.14 (d) K'M'N + KL'N' + K'MN' + LN = N (K'M' + L) + N' (KL' + K'M) = N ( L + K') (L + M') + N' (L' + K') (K + M)
= [N' + (L + K') (L + M')] [N + (L' + K') (K + M)] = (N' + L + K') (N' + L + M') (N + L' + K') (N + K + M)
3.14 (e) WXY + WX'Y + WYZ + XYZ' = WY (X + X' + Z) + XYZ' = WY + XYZ' = Y (W + XZ') = Y (W + X) (W + Z')
3.15 (a) (K' + M' + N) (K' + M) (L + M' + N') (K' + L + M) (M + N)
= (M' + NL + K'N') (M + K'N) = M (LN + K'N') + (M'K'N) {Using XY + X'Z = (X + Z)(X' + Y) with X = M}
= MLN + MK'N' + M'K'N
3.15 (b) (K' + L' + M') (K + M + N') (K + L) (K' + N) (K' + M + N)
= [K' + N (L' + M')] [K + L ( M + N')] = KN (L' + M') + K'L (M + N') = KNL' + KNM' + K'LM + K'LN'
3.15 (c) (K' + L' + M) (K + N') (K' + L + N') (K + L) (K + M + N')
= [K' + (L' + M) ( L + N')] (K + LN') = (K' + LM + L'N') (K + LN') {Multiplying out and factoring with X = L}
= K (LM + L'N') + K'LN' {Multiplying out and factoring with X = K}
= KLM + KL'N' + K'LN'
24
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 3 Solutions
3.15 (d) (K + L + M) (K' + L' + N') (K' + L' + M') (K + L + N) = ( K + L + MN) (K' + L' + M'N')
= K ( L' + M'N') + K'( L + MN) {Multiplying out and factoring with X = K} = KL' + KM'N' + K'L + K'MN
3.15 (e) (K + L + M) (K + M + N) (K' + L' + M') (K' + M' + N') = (K + M + LN) (K' + M' + L'N')
= K(M' + L'N') + K'(M + LN) = KM' + KL'N' + K'M + K'LN
Alt. soln's: KM' + K'M + L'MN' + LM'N (or) KM' + K'M + K'LN + L'MN' (or) KM' + K'M + KL'N' + LM'N
3.16 (a) (KL ⊕ M) + M'N' = (KL)'M + KLM' + M'N' = (K' + L') M + KLM' + M'N' = M(K' + L') + M'(KL + N')
= (M' + K' + L') ( M + N' + KL) = (M' + K' + L') (M + N' + K) (M + N' + L)
3.16 (b) M'(K ⊕ N') + MN + K'N = M' [K'N' + KN] + MN + K'N = K'M'N' + KM'N + MN + K'N
= K'M'N' + N(M + KM' + K')
= K'M'N' + N(M + K' + M') = K'M'N' + N = N + K'M' = (K' + N)(M' + N)
3.17
(a)
(b)
(c)
(d)
(e)
(f)
3.18
(a)
(b)
(c)
(d)
(e)
(f)
3.19
(a) x ⊕ y ⊕ xy = x ⊕ [y(xy)' + y'(xy)] = x ⊕ [yx'] = x(yx')' + x'(yx') = x(y'+x) +x'y = x + x'y = x + y
(b) x ≡ y ≡ xy = (xy + x'y') ≡ xy = (xy + x'y')xy + (xy + x'y')'(xy)' = xy + (xy' +x'y)(x' + y') = xy + x'y + xy'
=x+y
3.20
(a)
(b)
(c)
(d)
x ≡ 0 = x(0) + x'(0)' = x'
x ≡ 1 = x(1) + x'(1)' = x
x ≡ x = x(x) + x'(x)' = x + x' = 1
x ≡ x' = x(x') + x'(x')' = 0
x ≡ y = xy + x'y' = yx + y'x' = y ≡ x
(x ≡ y) ≡ z = (xy + x'y') ≡ z = (xy + x'y')z + (xy' + x'y)z' = xyz + x'y'z + xy'z' + x'yz'
= x(yz + y'z') + x'(y'z + yz') = x(yz + y'z') + x'(yz + yz)' = x ≡ (yz + y'z') = x ≡ (y ≡ z)
(g) (x ≡ y)' = (xy + x'y')' = (x' + y')(x + y) = x'y + xy' = x' ≡ y = xy' + x'y = x ≡ y'
x ⊕ 0 = x(0)' + x'(0) = x
x ⊕ 1 = x(1)' + x'(1)' = x'
x ⊕ x = x(x)' + x'(x) = 0
x ⊕ x' = x(x')' + x'(x') = x + x' = 1
x ⊕ y = xy' + x'y = y'x + yx' = y ⊕ x
(x ⊕ y) ⊕ z = (xy' + x'y) ⊕ z = (xy' + x'y)z' + (xy' + x'y)'z = xy'z' + x'yz' + xyz + x'y'z
= x(yz + y'z') + x'(yz' + y'z) = x(yz' + yz')' + x'(yz' + y'z) = x ⊕ (yz + y'z') = x ⊕ (y ⊕ z)
(g) (x ⊕ y)' = (xy' + x'y)' = (x' + y)(x + y') = x'y' + xy = x' ⊕ y = xy + x'y' = x ⊕ y'
xy ⊕ xz = xy(x' + z') + (x' + y')xz = xyz' + xyz = x(yz' + yz') = x(y ⊕ z)
For y = 1, the left hand side is x + z' but the right hand side is x'z' which are not equal.
For y = 0, the left hand side is xz' but the right hand side is x' + z' which are not equal.
(x + y) ≡ (x + z) = (x + y)(x + z) + (x + y)'(x + z)' = x + yz + (x'y')(x'z') = x + yz + x'y'z' = x + yz + y'z'
= x + (y ≡ z)
3.21 (a) BC'D' + ABC' + AC'D + AB'D + A'BD' = BC'D' + ABC' + AB'D + A'BD' = ABC' + AB'D + A'BD'
3.21 (b) W'Y' + WYZ + XY'Z + WX'Y + WXZ = W'Y' + WYZ + XY'Z + WX'Y + WXZ = W'Y' + WYZ + WX'Y + WXZ
= W'Y' + WX'Y + WXZ
3.21 (c) (B + C + D) (A + B + C) (A' + C + D) (B' + C' + D') = (A + B + C) (A' + C + D) (B' + C' + D')
3.21 (d) W'XY + WXZ + WY'Z + W'Z' = W'XY + WXZ + WY'Z +W'Z' + XYZ = WY'Z + W'Z' + XYZ
XYZ (add consensus term)
25
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 3 Solutions
3.21 (e) A'BC' + BC'D' + A'CD + B'CD + A'BD = BC'D' + B'CD + A'BD
3.21 (f)
(A + B + C) (B + C' + D) (A + B + D) (A' + B' + D') = (A + B + C) (B + C' + D) (A' + B' + D')
3.22
Z = ABC + DE + ACF + AD' + AB'E' = A (BC + CF + D' + B'E') + DE
= (A + DE) (DE + BC + CF + D' + B'E') {By Distributive Law with X = DE}
= (A + D) (A + E) (BC + CF + D' + E + B'E')
= (A + D) (A + E) (D' + E + B' + BC + CF) {Since E + B'E' = E + B'}
= (A + D) (A + E) (D' + E + B' + C + CF) {Since B' + BC = B' + C}
= (A + D) (A + E) (D' + E + B' +C) {Since C + CF = C}
= (A + DE) (D' + E + B' + C)
= AD' + AE + AB' + AC + DE + DEB' + DEC {eliminate consensus term AE; use X + XY = X where X = DE}
= AD' + AB' + AC + DE
3.23
F = A'B + AC + BC'D' + BEF + BDF = (A + B) (A' + C) + B (C'D' + EF + DF)
= [(A + B) (A' + C) + B] [(A + B) (A' + C) + C'D' + EF + DF]
= (A + B) (A' + C + B) (A + B + C'D' + EF + DF) (A' + C + C'D' + EF + DF)
B+C
C + D'
= (A + B) (A' + C + B) (C + B) (A + B + C'D' + EF + DF) (A' + C + D' + EF + DF)
= (A + B) ( B + C) (A' + C + D' + FE + DF) = (A + B) (B + C) (A' + C + D' + F + FE)
= (A + B) (B + C) (A' + C + D' + F)
= (B + AC) (A' + C + D' + F)
= (A'B + BC + BD' + BF + AC + ACD' + ACF = A'B + BD' + BF + AC
use consensus, X + XY = X where X = AC
3.24
X'Y'Z' + XYZ = (X + Y'Z') (X' + YZ) = (X + Y') (X + Z') (X' + Y) (X' + Z) (Y + Z')
= (X + Y') (X + Z') (X' + Y) (X' + Z) (Y + Z') = (X + Y') (X + Z') (X' + Z) (Y + Z')
= (X + Y') (X' + Z) (Y + Z')
Alt.: (X' + Y) (Y' + Z) (X + Z') by adding (Y' + Z) as consensus in 3rd step
3.25 (a) xy + x'yz' + yz = y (x + x'z') + yz = xy + yz' + yz
3.25 (b) (xy' + z) (x + y') z = (xy' + xz + y'z) z
= xy + y = y
= xy'z + xz + y'z = xz + y'z
Alternate Solution: xy + x'yz' + yz = y (x + x'z' + z)
Alternate Solution: (xy' + z) (x+y') z = z ( x + y')
= y (x + z' + z) = y (x + 1) = y
= zx + zy'
3.25 (c) xy' + z + (x' + y) z'
= x'y + (x' + y) {Elimnation with Y = z}
= xy' + x' + y = x + x' + y = 1 + y = 1
Alt.: xy' + z + (x' + y) z' = (xy' + z) + (xy' + z)' = 1
3.25 (e) w'x' + x'y' + yz + w'z' + x'z Add redundant term
= w'x' + x'y' + yz + w'z' + x'z
3.25 (d) a'd (b' + c) + a'd' (b + c') +(b' + c) (b + c')
= a'b'd + a'cd + a'bd' + a'c'd' + b'c' + bc
= a'b'd + a'bd' + b'c' + bc'
Other Solutions: b'c' + bc + a'c'd' + a'b'd
b'c' + bc + a'c'd' + a'cd
b'c' + bc + a'bd' + a'cd
= x'y' + yz + w'z' + x'z Remove redundant term
= x'y' + yz + w'z'
26
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 3 Solutions
3.25 (f)
A'BCD + A'BC'D+ B'EF+ CDE'G+A'DEF+A'B'EF
= A'BD + B'EF + CDE'G + A'DEF (consensus)
c'd
b'd'
= abd + a'b'd' + b'd' + c'd = abd + b'd' + c'd
= A'BD + B'EF + CDE'G
3.26 (b) A'B'C' + ABD + A'C + A'CD' + AC'D + AB'C'
3.26 (a) A'C'D' + AC' + BCD + A'CD' + A'BC + AB'C'
= A'D' + AC' + BCD + A'BC consensus
= B'C' + ABD + A'C + AC'D
= A'D' + AC' + BCD
3.27
3.25 (g) [(a' + d' + b'c) (b + d + ac')]' + b'c'd' + a'c'd
= ad (b + c') + b'd' (a' + c) +b'c'd' + a'c'd
= abd + ac'd+ a'b'd' + b'cd' + b'c'd' + a'c'd
= B'C' + ABD + A'C
WXY' + (W'Y' ≡ X) + (Y ⊕ WZ)
= WXY' + W'Y'X + (W'Y')' X' + Y (WZ)' + Y'WZ
= WXY' + W'XY' + (W + Y) X' + Y (W' + Z') + Y'WZ
= XY' + WX' + X'Y + W'Y + YZ' + WY'Z + WY'
= XY' + WX' + X'Y + W'Y + YZ' + WY'Z + WY'
= XY' + WX' + W'Y + YZ' + WY'
= XY'+ WX' + W'Y + YZ'
Alternate Solutions: F = W'Y + WX' + WZ' + XY'
F = YZ' + W'X + XY' + WY'
F = W'X + X'Y + XZ' + WY'
F = W'X + XY' + WZ' + WY'
3.28 (a) VALID: a'b + b'c + c'a
= a'b (c + c') + (a + a') b'c + (b + b') ac'
= a'bc + a'bc' + ab'c + a'b'c + abc' + ab'c'
= a'c +
bc' +
ab'
Alternate Solution: a'b + b'c + c'a
Add all consensus terms: ab', bc', ca'
∴ We get = a'b + b'c + c'a + ab' + bc' + ca'
= ab' + bc' + ca'
3.28 (b) NOT VALID. Counterexample: a = 0, b = 1, c = 0.
LHS = 0, RHS = 1. ∴ This equation is not always
valid.
In fact, the two sides of the equation are
complements: [(a + b) (b + c) (c + a)]'
= [(b + ac) (a + c)]' = [ab + ac + bc]'
= (a' + b') (a' + c') (b' + c')
3.28 (c) VALID. Starting with the right side, add consensus
terms
RHS = abc + ab'c' + b'cd + bc'd + acd + ac'd
3.28 (d) VALID: LHS = xy' + x'z + yz'
3.28 (e) NOT VALID. Counterexample: x = 0, y = 1, z = 0,
then LHS = 0, RHS = 1. ∴ This equation is not
always valid. In fact, the two sides of the equations
are complements.
LHS = (x + y) (y + z) (x + z)
= [(x + y)' + (y + z)' + (x + z)']'
= (x'y' + y'z' + x'z')' = [x' (y' + z') + y'z']'
= [(x' + y'z') (y' + z' + y'z')]'
= [(x' + y') (x' + z') (y' + z')]'
≠ (x' + y') (y' + z') (x' + z')
consensus terms:y'z, xz', x'y
= xy' + x'z + yz' + y'z + xz' + x'y
= y'z + xz' + x'y = RHS
3.28 (f) VALID: LHS = abc' + ab'c + b'c'd + bcd
consensus terms:
ab'd, abd
= abc' + ab'c + b'c'd + bcd + ab'd + abd
ad
abc' + ab'c + ad + bcd + b'c'd = RHS
27
= abc + ab'c' + b'cd + bc'd + acd + ac'd
= abc + ab'c' + b'cd + bc'd + ad = LHS
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 3 Solutions
3.29
SUM = (X ⊕ Y) ⊕ Ci = (XY' + X'Y) ⊕ Ci
= (XY' + X'Y)Ci' + (XY' + X'Y)'Ci
= XY'Ci' + X'YCi' + X'Y'Ci + XYCi
Co = (X ⊕ Y)Ci + XY
= XY'Ci + X'YCi + XY
= XCi + YCi + XY
3.30
A B C F
0 0 0
0
0 0 1
0
0 1 0
0
0 1 1
1
1 0 0
0
1 0 1
1
1 1 0
1
1 1 1
1
F = AB + AC + BC
X Y Ci SUM Co
0 0 0
0 0
0 0 1
1 0
0 1 0
1 0
0 1 1
0 1
1 0 0
1 0
1 0 1
0 1
1 1 0
0 1
1 1 1
1 1
3.31 (a) VALID:
LHS = (X' + Y') (X ⊕ Z) + (X + Y) (X ⊕ Z)
= (X' + Y') (X'Z' + XZ) + (X + Y) (X'Z + XZ')
= X'Z' + X'YZ' + XY'Z + X'YZ + XZ' + XYZ'
= X'Z' + (XY' + X'Y)Z + XZ'
= Z' + Z(X ⊕ Y) = Z' + (X ⊕ Y) = RHS
3.31 (b) LHS = (W' + X + Y') (W + X' + Y) (W + Y' + Z) = (W' + X + Y') (W + (X' + Y) (Y' + Z))
= (W' + X + Y') (W + (X'Y' + YZ)) = (W' (X'Y' + YZ) + W (X + Y ')) = W'X'Y' + W'YZ + WX + WY'
consensus terms:
X'Y'
XYZ
= W'X'Y' + W'YZ + WX + WY' + XYZ + X'Y' = W'X'Y' + W'X'Z + W'YZ + XYZ + WX + WY' + X'Y'
= W'X'Z + W'YZ + XYZ + WX + X'Y' = W'YZ + XYZ + WX + X'Y'
3.31 (c) LHS = ABC + A'C'D' + A'BD' + ACD = AC (B + D) + A'D' (B + C') = (A + D' (B + C')) (A' + C(B + D))
= (A + D') (A + B + C') (A' + C) (A' + B + D) = (A + D') (A + B + C') (A' + C) (A' + B + D) (B + C' + D)
consensus:
B + C' + D
= (A + D') (A + B + C') (A' + C) (B + C' + D) = (A + D') (A' + C) (B + C' + D) = RHS
3.32 (a) VALID. [A + B = C] ⇒ [D' (A + B) = D'(C)]
[A + B = C] ⇒ [AD' + BD' = CD']
3.32 (b) NOT VALID. Counterexample: A = 1, B = C = 0
and D = 1 then LHS = (0)(0) + (0)(0) = 0
RHS = (0)(1) = 0 = LHS
but B + C = 0 + 0 = 0; D = 1 ≠ B + C
∴ The statement is false.
3.32 (c) VALID. [A + B = C] ⇒ [(A + B) + D = (C) + D]
[A + B = C] ⇒ [A + B + D = C + D]
3.32 (d) NOT VALID. Counterexample: C = 1, A = B = 0
and D = 1 then LHS = 0 + 0 + 1 = 1
RHS = 1 + 1 = 1 = LHS
but A + B = 0 + 0 = 0 ≠ D
∴ The statement is false.
28
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 3 Solutions
3.33 (a) A'C' + BC + AB' + A'BD + B'C'D' + ACD'
Consensus terms: (1) B'C' using A'C' + AB'
(2) A'B using A'C' + BC (3) AC using AB' + BC (4)
AB'D' using B'C'D' + ACD'
Using 1, 2, 3: A'C' + BC + AB' + A'BD + B'C'D'
+ ACD' + B'C' + A'B + AC = A'C' + BC + AB'
(Using the consensus theorem to remove the added
terms since the terms that generated them are still
present.)
3.33 (b) A'C'D' + BC'D + AB'C' + A'BC
Consensus terms:
(1) A'BC' using A'C'D' + BC'D
(2) AC'D using AB'C' + BC'D
(3) B'C'D' using A'C'D' + AB'C'
(4) A'BD' using A'C'D' + A'BC
(5) A'BD using BC'D + A'BC
Using 1: A'C'D' + BC'D + AB'C' + A'BC + A'B,
which is the minimum solution.
3.34
abd'f' + b'cegh' + abd'f + acd'e + b'ce
= (abd'f' + abd'f) + (b'cegh' + b'ce) + acd'e
= abd' + b'ce + acd'e
= abd' + b'ce (consensus)
= (b + ce)(b' + ad')
= (b + c)(b + e)(b' + a)(b' + d')
3.35
(a + c)(b'+ d)(a + c'+ d')(b'+ c'+ d')
= (a + cd')(b' + c'd)
= ab'+ ac'd + b'cd'
3.36
abc' + d'e + ace + b'c'd'
= (d' + abc' + ace + b'c'd')(e + abc' + ace + b'c'd')
= (d' + abc' + ace)(e + abc' + b'c'd')
= [d' + a(bc' + ce)][e + c'(ab + b'd')]
= [d' + a(b + c)(c' + e)][e + c'(a + b')(b + d')]
= (d' + a)(d' + b + c)(d' + c' + e)(e + c')
(e + a + b')(e + b + d')
= (d' + a)(d' + b + c)(e + c')
(e + a + b')(e + b + d')
= (d' + a)(d' + b + c)(e + c')(e + a + b')
(consensus)
3.37
(a) (x ≡ y)' = (xy + x'y')' = (x' + y')(x + y)
= x'y + xy' = x ⊕ y
(b) a'b'c' + a'bc + ab'c + abc'
= a'(b'c' + bc) + a(b'c + bc')
= a'(b ≡ c) + a (b ≡ c)'
= a' ≡ (b ≡ c)
3.38
(a) x(y + a′) = x(y + b′) implies that
0 = x(y + a′) ⊕ x(y + b′) = x(y + a′)(x′ + y′b) +
(x′ + y′a)x(y + b′) = xy′b(y + a′) + xy′a(y + b′) =
xy′a′b + xy′ab′ = xy′(a′b + ab′) = xy′(a ⊕ b)
which implies that a = b.
3.39
Let A = [(a + b) + c][a + (b + c)]
= a[(a + b) + c] + (b +c) [(a + b) + c]
= [(a + ab) + ac] + [(a + b)(b +c) + c(b +c)]
= a + [(a + b)(b + c) + c]
= a + [{(a + b)b + (a + b)c} + c]
= a + [{b + (ac + bc)} + c]
= a + [{(b + ac)(b + bc)} + c]
= a + [{(b + ac)b} + c]
= a + [(b + bac) + c]
= a + [b + c]
Also,
A = [(a + b) + c][a + (b + c)]
= (a + b)[a + (b + c)] + c[a + (b + c)]
= [(a + b)a + (a + b)(b + c)] + [ac + c(b + c)]
= [a + {(a + b)b + (a + b)c}] + [ac + c]
= [a + {b + (ac + bc)}] + c
= [a + {(b + ac)(b + bc)}] + c
= [a + (b + ac)b] + c
= [a + b] + c
So A = a + [b + c] = [a + b] + c
(b) a′b + ab′ = a′c + ac′ implies that
0 = (a′b + ab′) ⊕ (a′c + ac′)
= (a′b + ab′)(ac + a′c′) + (ab + a′b′)(a′c + ac′)
= a′bc′ + ab′c + abc′ + a′b′c
= a′(bc′ + b′c) + a(bc′ + b′c) = bc′ + b′c = b ⊕ c
which implies that b = c.
29
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 3 Solutions
30
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 4 Solutions
4.1
4.2
See FLD p. 733 for solution.
AB C D E
0
1
1
1
1
1
4.3
Unit 4 Problem Solutions
0
0
1
1
1
1
0
0
0
1
1
1
0
0
0
0
1
1
0
0
0
0
0
1
y
(less than 10 gpm)
(at least 10 gpm)
(at least 20 gpm)
(at least 30 gpm)
(at least 40 gpm)
(at least 50 gpm)
z
+
+
+
4.2 (a)
Y = A'B'C'D'E' + AB'C'D'E' + ABC'D'E'
4.2 (b)
Z = ABC'D'E' + ABCD'E' + ABCDE'
+
+
+
F1 = ∑ m(0, 4, 5, 6); F2 = ∑ m(0, 3, 4, 6, 7); F1 + F2 = ∑ m(0, 3, 4, 5, 6, 7)
General rule: F1 + F2 is the sum of all minterms that are present in either F1 or F2.
n
2 –1
n
2 –1
Proof: Let F1 =
S a m ; F =Sb m ; F
i
i=0
i
2
j=0
j
j
1
n
2 –1
n
2 –1
S a m +S b m = a m
+ F2 =
i=0
i
i
j=0
j
j
0
0
+ a1m1 + a2m2 + ...
+ b0m0 + b1m1 + b2m2 + ... = (a0 + b0 ) m0 + (a1 + b1 ) m1 + (a2 + b2 ) m2 + ... =
4.4 (a)
S (a + b ) m
i=0
i
i i
n
22 = 222 = 24 = 16
x
0
0
1
1
y
0
1
0
1
z0
0
0
0
0
z1
1
0
0
0
z2
0
1
0
0
z3
1
1
0
0
z4
0
0
1
0
z5
1
0
1
0
z6
0
1
1
0
z7
1
1
1
0
z8
0
0
0
1
z9
1
0
0
1
z10 z11 z12
0 1 0
1 1 0
0 0 1
1 1 1
z13 z14 z15
1 0 1
0 1 1
1 1 1
1 1 1
0
x'y'
x'y
x'
xy'
y'
x'y+xy'
x'+y'
xy
x'y'+xy
y
x'+y
x
x+y'
x +y
1
4.4 (b)
n
2 –1
4.5
Alternate
Solutions
ABC D E F
0 0 0 1 1 X3
0 0 1 X2 X2 1
0 1 0 X1 X1 X1
0 1 1 X X 1
1 0 0 X4 0 0
1 0 1 X2 X2 1
2
2
Z
1
ABC D E F
Z
1
X
1
0 1 1 1
1 X3 1
0
1
1 1 0 X1 X1 X1 X
1 1 1 X4 0 0 0
1 1 1 0 X4 0 0
These truth table entries were made don't cares because
ABC = 110 and ABC = 010 can never occur
2
These truth table entries were made don't cares because
when F is 1, the output Z of the OR gate will be 1 regardless
of its other input. So changing D and E cannot affect Z.
3
These truth table entries were made don't cares because
when D and E are both 1, the output Z of the OR gate will
be 1 regardless of the value of F.
4
These truth table entries were made don't cares because
when one input of the AND gate is 0, the output will be 0
regardless of the value of its other input.
1
4.6 (a)
Of the four possible combinations of d1 & d5, d1 = 1 and d5 = 0 gives the best solution:
F = A'B'C' + A'B'C + ABC' + ABC = A'B' + AB
4.6 (b)
By inspection, G = C when both don’t cares are set to 0.
31
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 4 Solutions
4.7 (a)
Exactly one variable not complemented: F = A'B'C
+ A'BC' + AB'C' = ∑ m(1, 2, 4)
4.8 (a)
F(A, B, C, D) = ∑ m(0, 1, 2, 3, 4, 5, 6, 8, 9, 12)
Refer to FLD p. 733 for full term expansion
4.7 (b)
Remaining terms are maxterms:
F = ∏ M(0, 3, 5, 6, 7) = (A + B + C) (A + B' + C')
(A' + B + C') (A' + B' + C) (A' + B' + C')
4.8 (b)
F(A, B, C, D) = ∏ M(7, 10, 11, 13, 14, 15)
Refer to FLD p. 733 for full term expansion
4.9 (a)
F = abc' + b' (a + a') (c + c') = abc' + ab'c + ab'c' +
a'b'c + a'b'c'; F = ∑ m(0, 1, 4, 5, 6)
4.9 (b)
Remaining terms are maxterms: F = ∏ M(2, 3, 7)
4.9 (c)
Maxterms of F are minterms of F':
F' = ∑ m(2, 3, 7)
4.9 (d)
Minterms of F are maxterms of F':
F' = ∏ M(0, 1, 4, 5, 6)
4.8
AB CD
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
0×0=0≤2
0×1=0≤2
0×2=0≤2
0×3=0≤2
1×0=0≤2
1×1=1≤2
1×2=2≤2
1×3=3>2
2×0=0≤2
2×1=2≤2
2×2=4>2
2×3=6>2
3×0=0≤2
3×1=3>2
3×2=6>2
3×3=9>2
4.10
F
1
1
1
1
1
1
1
0
1
1
0
0
1
0
0
0
F(a, b, c, d) = (a + b + d) (a' + c) (a' + b' + c') (a + b + c' + d')
= (a + b + c + d) (a + b + c' + d) (a' + c + bb' + dd') (a' + b' + c' + d) (a' + b' + c' + d') (a + b + c' + d')
= (a + b + c + d) (a + b + c' + d) (a' + b + c + d) (a' + b + c + d') (a' + b' + c + d) (a' + b' + c + d')
(a' + b' + c' + d) (a' + b' + c' + d') (a + b + c' + d')
4.10 (a) F = ∑ m(1, 4, 5, 6, 7, 10, 11)
4.10 (b) F = ∏ M(0, 2, 3, 8, 9, 12, 13, 14, 15)
4.10 (c) F' = ∑ m(0, 2, 3, 8, 9, 12, 13, 14, 15)
4.10 (d) F' = ∏ M(1, 4, 5, 6, 7, 10, 11)
4.11 (a) difference, di = xi ⊕ yi ⊕ bi; bi+1 = bi xi' + xi'yi + bi yi
4.11 (b) di = si; bi+1 is the same as ci+1 with xi replaced by xi'
xi yi bi
00 0
00 1
01 0
01 1
10 0
10 1
11 0
11 1
bi+1 di
00
11
11
10
01
00
00
11
4.12
32
See FLD p. 734 for solution.
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 4 Solutions
4.13
AB CD
00 0 0
00 0 1
00 1 0
00 1 1
01 0 0
01 0 1
01 1 0
01 1 1
10 0 0
10 0 1
10 1 0
10 1 1
11 0 0
11 0 1
11 1 0
11 1 1
Z
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
Z = A'B'C'D' + A'B'C'D + AB'C'D'
+ ABCD' + ABCD + A'BCD
= A'B'C' + ABC + AB'C'D' +
A'BCD
= A'B'C' + ABC + AB'C'D' +
A'BCD + BCD + B'C'D'
(Added consensus terms)
∴ Z = A'B'C' + ABC + BCD +
B'C'D'
A'
B'
C'
A
B
C
B
C
D
B'
C'
D'
4.14
Z
AB CD
00 0 0
00 0 1
00 1 0
00 1 1
01 0 0
01 0 1
01 1 0
01 1 1
10 0 0
10 0 1
10 1 0
10 1 1
11 0 0
11 0 1
11 1 0
11 1 1
Z = A'BC'D + A'BCD' + A'BCD +
AB'C'D' + AB'C'D + AB'CD'
+ AB'CD
= A'BD + AB'C' + AB'C + A'BCD'
= AB' + A'BD + A'BCD' + A'BC
(Added consensus terms)
∴ Z = AB' + A'BD + A'BC
Z
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
A'
B
C
A'
B
D
Z
A
B'
4.15
(a) Prime digits are 1, 3, 5, and 7 represented as 0010, 0111, 1011 and 1110. The minterms are A'B'CD', A'BCD,
AB'CD and ABCD'. The don't care minterms are A'B'C'D', A'B'CD, A'BC'D, A'BCD', AB'C'D, AB'CD', ABC'D'
and ABCD.
(b) Nonprime digits are 0, 2, 4, and 6 represented as 0001, 0100, 1000 and 1101. The maxterms are A + B + C + D',
A + B'+ C + D, A'+ B + C + D and A'+ B'+ C + D'. The don't care maxterms are A + B + C + D, A + B + C'+D',
A + B'+ C + D', A + B'+ C' + D, A'+ B + C + D', A'+ B + C' + D, A'+ B'+ C + D and A'+ B'+ C' + D'.
4.16
Truth Table
x3x2x1 x0
00 0 0
00 0 1
00 1 0
00 1 1
01 0 0
01 0 1
01 1 0
01 1 1
10 0 0
10 0 1
10 1 0
10 1 1
11 0 0
11 0 1
11 1 0
11 1 1
z y1 y0
0 x x
1 0 0
1 0 1
1 0 1
1 1 0
1 1 0
1 1 0
1 1 0
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
(a)
minterms of z: 1, 2, 3, 4, 5, 6,
7, 8, 9, 10, 11, 12, 13, 14, 15
minterms of y1: 4, 5, 6, 7, 8, 9,
10, 11, 12, 13, 14, 15
don't care minterm: 0
minterms of y0: 2, 3, 8, 9, 10,
11, 12, 13, 14, 15
don't care minterm: 0
(b)
maxterms of z: 0
maxterms of y1: 1, 2, 3
don't care maxterm: 0
maxterms of y0: 1, 4, 5, 6, 7
don't care maxterm: 0
33
4.17
Truth Table
AB CD
00 0 0
00 0 1
00 1 0
00 1 1
01 0 0
01 0 1
01 1 0
01 1 1
10 0 0
10 0 1
10 1 0
10 1 1
WX
1 0
1 0
0 1
0 1
0 1
0 1
0 0
0 0
0 0
0 0
x x
x x
Y
0
0
1
1
0
0
1
1
0
0
x
x
Z
1
0
1
0
1
0
1
0
1
0
x
x
1
1
1
1
x
x
x
x
x
x
x
x
x
x
x
x
1
1
1
1
0
0
1
1
0
1
0
1
x
x
x
x
(a)
minterms of w: 0, 1
minterms of x: 2, 3, 4, 5
minterms of y: 2, 3, 6, 7
minterms of z: 0, 2, 4, 6, 8
don't care minterms: 10, 11,
12, 13, 14, 15
(b)
maxterms of w: 2, 3, 4, 5, 6,
7, 8, 9
maxterms of x: 0, 1, 6, 7, 8, 9
maxterms of y: 0, 1, 4, 5, 8, 9
maxterms of z: 1, 3, 5, 7, 9
don't care maxterms: 10, 11,
12, 13, 14, 15
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 4 Solutions
4.18 (a), Truth Table
(b)
AB CD
00 0 0
00 0 1
00 1 0
00 1 1
01 0 0
01 0 1
01 1 0
01 1 1
10 0 0
10 0 1
10 1 0
10 1 1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
WX
1 1
1 1
1 1
1 1
x x
x x
1 0
x x
x x
0 1
x x
x x
0
0
0
0
0
0
0
0
Y
1
1
0
0
x
x
0
x
x
1
x
x
Z
1
0
1
0
x
x
1
x
x
0
x
x
(a)
minterms of W: 0, 1, 2, 3, 6
minterms of X: 0, 1, 2, 3, 9
minterms of Y: 0, 1, 9, 12, 13
minterms of Z: 0, 2, 6, 12,14
don't care minterms: 4, 5, 7,
8, 10, 11
(b)
maxterms of W: 9, 12, 13,
14, 15
maxterms of X: 6, 12, 13, 14,
15
maxterms of Y: 2, 3, 6, 14,
15
maxterms of Z: 1, 3, 9, 13,
15
1 1
don't care maxterms: 4, 5, 7,
1 0 8, 10, 11
0 1
0 0
4.18 (a), Alternative Truth Table
(b)
(a)
A B C D WX Y Z
minterms of W: 0, 1, 2, 3, 7
00 0 0 1 1 1 1
minterms of X: 0, 1, 2, 3, 8
0 0 0 1 1 1 1 0 minterms of Y: 0, 1, 9, 12, 13
0 0 1 0 1 1 0 1 minterms of Z: 0, 2, 8, 12, 14
0 0 1 1 1 1 0 0 don't care minterms: 4, 5, 6,
9, 10, 11
01 0 0 x x x x
01 0 1 x x x x
(b)
0 1 1 0 x x x x maxterms of W: 8, 12, 13,
14, 15
01 1 1 1 0 0 0
maxterms of X: 7, 12, 13,
10 0 0 0 1 1 1
14,15
1 0 0 1 x x x x maxterms of Y: 2, 3, 7, 14,
1 0 1 0 x x x x 15
1 0 1 1 x x x x maxterms of Z: 1, 3, 7, 13,
15
11 0 0 0 0 1 1
don't care maxterms: 4, 5, 6,
11 0 1 0 0 1 0
9, 10, 11
11 1 0 0 0 0 1
11 1 1 0 0 0 0
4.19 (a) The buzzer will sound if the key is in the ignition switch and the car door is open, or the seat belts are not fastened.
B
K
D
S'
∴ The two possible interpretations are: B = KD + S' and B = K(D + S')
4.19 (b) You will gain weight if you eat too much, or you do not exercise enough and your metabolism rate is too low.
W
F
E'
M
∴ The two possible interpretations are: W = (F + E') M and W = F + E'M
4.19 (c) The speaker will be damaged if the volume is set too high and loud music is played or the stereo is too powerful.
D
V
M
S
∴ The two possible interpretations are: D = VM + S and D = V (M + S)
4.19 (d) The roads will be very slippery if it snows or it rains and there is oil on the road.
V
S
R
O
∴ The two possible interpretations are: V = (S + R) O and V = S + RO
4.20
4.21
Z = AB + AC + BC
4.22 (a) 1310 = D16 = 0001101; ∴ X = A'B'C'DEF'G
Z = (ABCDE + A'B'C'D'E')'; Y = A'B'CD'E
4.22 (b) 1010 = 0001010; ∴ Y = A'B'C'DE'FG'
4.22 (c) 010 = 00000002; 6410 = 10000002; 3110 = 00111112; 12710 = 11111112; 3210 = 01000002; ∴ Z = (A'B')' = A + B
4.23
F1F2 = ∏ M(0, 4, 5, 6, 7). General rule: F1F2 is the product of all maxterms that are present in either F1 or F2.
Proof:
Let F1 = ∏ (ai + Mi); F2 = ∏ (bj + Mj); F1F2 = ∏ (ai + Mi) ∏ (bj + Mj)
= (a0 + M0) (b0 + M0) (a1 + M1) (b1 + M1) (a2 + M2) (b2 + M2) ... = (a0b0 + M0) (a1b1 + M1) (a2b2 + M2) ...
= ∏ (aibi + Mi)
Maxterm Mi is present in F1F2 iff aibi = 0, i.e., if either ai = 0 or bi = 0. Maxterm Mi is present in F1 iff ai =0.
Maxterm Mi is present in F2 iff bi = 0. Therefore, maxterm Mi is present in F1F2 iff it is present in F1 or F2.
34
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 4 Solutions
4.24
F1 + F2 = ∏ M(0, 4). General rule: F1 + F2 is the product of all maxterms that are present in both F1 and F2.
Proof:
Let F1 =
n
2 –1
S
i=0
(ai mi); F2 =
n
2 –1
S
i=0
(bjmj); F1 + F2 =
n
2 –1
n
2 –1
S (a m ) + S (b m )
i=0
i
i
j
j
i=0
= a0m0 + b0m0 + a1m1 + b1m1 + a2m2 + b2m2) ... = (a0 + b0)m0 + (a1 + b1)m1 + (a2 + b2)m2 + ...
n
2 –1
S
= (ai + bi)mi
i=0
Minterm mi is present in F1 + F2 iff ai + bi = 1, i.e., if either ai = 1 or bi = 1 so maxterm Mi is present in F1 + F2 if ai =
0 and bi = 0. Therefore, maxterm Mi is present in F1 + F2 iff it is present in both F1 and F2.
4.25
4.27
AB CD
00 0 0
00 0 1
00 1 0
00 1 1
01 0 0
01 0 1
01 1 0
01 1 1
10 0 0
10 0 1
10 1 0
10 1 1
11 0 0
11 0 1
11 1 0
11 1 1
FG H J
01 0 0
00 0 0
01 0 0
00 0 0
01 0 1
10 0 0
11 0 0
10 1 0
00 0 1
00 0 0
10 0 0
10 1 0
00 0 1
10 1 1
10 1 1
10 1 0
(a) F(A, B, C, D) =
∑ m(5, 6, 7, 10, 11, 13, 14, 15)
= ∏ M(0, 1, 2, 3, 4, 8, 9, 12)
(b) G (A, B, C, D) =
∑ m(0, 2, 4, 6)
= ∏ M(1, 3, 5, 7, 8, 9, 10, 11,
12, 13, 14, 15)
(c) H (A, B, C, D) =
∑ m(7, 11, 13, 14, 15)
= ∏ M(0, 1, 2, 3, 4, 5, 6, 8, 9,
10, 12)
(d) J (A, B, C, D) =
∑ m(4, 8, 12, 13, 14)
= ∏ M(0, 1, 2, 3, 5, 6, 7, 9, 10,
11, 15)
You can also work this problem using a truth table,
as in problem 4.28.
f(a, b, c) = a(b + c') = ab + ac' = ab (c + c') +
a(b + b') c' = abc + abc' + abc' + ab'c'
m7
m6
m6
m4
f = ∑ m(4, 6, 7)
4.26
f = ∏ M(0, 1, 2, 3, 5)
f ' = ∑ m(0, 1, 2, 3, 5) f ' = ∏ M(4, 6, 7)
35
4.28
AB CD
00 0 0
00 0 1
00 1 0
00 1 1
01 0 0
01 0 1
01 1 0
01 1 1
10 0 0
10 0 1
10 1 0
10 1 1
11 0 0
11 0 1
11 1 0
11 1 1
FG H J
01 0 0
01 0 0
01 0 0
00 0 0
01 0 1
10 0 0
00 0 0
10 1 0
01 0 1
00 0 0
10 0 0
10 1 0
00 0 1
10 1 1
10 1 1
10 1 0
a
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
f
0
1
1
0
1
1
1
0
0
0
0
1
1
0
1
1
b
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
c
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
d
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(a) F(A, B, C, D) =
∑ m(5, 7, 10, 11, 13, 14, 15)
= ∏ M(0, 1, 2, 3, 4, 6, 8, 9,
12)
(b) G (A, B, C, D) =
∑ m(0, 1, 2, 4, 8)
= ∏ M(3, 5, 6, 7, 9, 10, 11, 12,
13, 14, 15)
(c) H (A, B, C, D) =
∑ m(7, 11, 13, 14, 15)
= ∏ M(0, 1, 2, 3, 4, 5, 6, 8, 9,
10, 12)
(d) J (A, B, C, D) =
∑ m(4, 8, 12, 13, 14)
= ∏ M(0, 1, 2, 3, 5, 6, 7, 9, 10,
11, 15)
(a) f = ∑ m(1, 2, 4, 5, 6, 11, 12,
14, 15)
(b) f = ∏ M(0, 3, 7, 8, 9, 10, 13)
(c) f ' = ∑ m(0, 3, 7, 8, 9, 10, 13)
(d) f '= ∏ M(1, 2, 4, 5, 6, 11, 12,
14, 15)
You can also work this problem
algebraically, as in problem 4.27.
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 4 Solutions
4.29 (a) f(A,B,C,D) = AB+ A'CD = ABC'D' + ABC'D
+ ABCD' + ABCD + A'B'CD + A'BCD
= (A+A'CD)(B+A'CD) = (A+C)(A+D)(A'+B)
(B+C)(B+D)
f(A,B,C,D) = (A+B'+C+D')(A+B'+C+D)
(A+B+C+D')(A+B+C+D)(A+B'+C'+D)
(A+B'+C+D)(A+B+C'+D)(A+B+C+D)
(A'+B+C'+D')(A'+B+C'+D)(A'+B+C+D')
(A'+B+C+D)(A'+B+C+D')(A'+B+C+D)
(A+B+C+D')(A+B+C+D)(A'+B+C'+D)
(A'+B+C+D)(A+B+C'+D)(A+B+C+D)
= (A+B'+C+D')(A+B+C+D')(A+B'+C'+D)
(A+B'+C+D)(A+B+C'+D) (A+B+C+D)
(A'+B+C'+D')(A'+B+C'+D)(A'+B+C+D')
(A'+B+C+D)
Note: Consensus could have been applied twice to
write f = (A+C)(A+D)(A'+B) and save some work.
4.29 (b) f(A,B,C,D) = (A+B+D')(A'+C)(C+D)
= (A+B+D')(A'D+C) = AC+A'BD+BC+CD'
= AC(B+B')(D+D')+A'BD(C+C')
+BC(A+A')(D+D')+(A+A')(B+B')CD'
= ABCD+ABCD'+AB'CD+AB'CD'+A'BCD
+A'BC'D+ABCD+ABCD'+ABCD+A'BCD'
+ABCD'+AB'CD'+A'BCD'+A'B'CD'
= ABCD+ABCD'+AB'CD+AB'CD'+A'BCD
+A'BC'D+A'BCD'+A'B'CD'
f(A,B,C,D) = (A+B+CC'+D')(A'+BB'+C+DD')
(AA'+BB'+C+D)
= (A+B+C+D')(A+B+C'+D')(A'+B+C+D)
(A'+B+C+D')(A'+B'+C+D)(A'+B'+C+D')
(A+B+C+D) (A+B'+C+D)(A'+B+C+D)
(A'+B'+C+D)
= (A+B+C+D')(A+B+C'+D')(A'+B+C+D)
(A'+B+C+D')(A'+B'+C+D)(A'+B'+C+D')
(A+B+C+D)(A+B'+C+D)
4.30 (a) F(A, B, C, D) = ∑ m(3, 4, 5, 8, 9, 10, 11, 12, 14)
F = A'B'CD + A'BC'D' + A'BC'D + AB'C'D' +
AB'C'D + AB'CD' + AB'CD + ABC'D' + ABCD'
4.30 (b) F(A, B, C, D) = ∏ M(0, 1, 2, 6, 7, 13, 15)
F = (A + B + C + D)(A + B + C + D')
(A + B + C' + D)(A + B' + C' + D)
(A + B' + C' + D')(A' + B' + C + D')
(A' + B' + C' + D')
4.31 (a) F(A, B, C, D) = ∑ m(0, 3, 4, 7, 8, 9, 11, 12, 13, 14) = A'B'C'D' + A'B'CD + A'BC'D' + A'BCD + AB'C'D' + AB'C'D
m0
m3
m4
m7
m8
m9
+ AB'CD + ABC'D' + ABC'D + ABCD'
m11
m12
m13
m14
4.31 (b) F(A, B, C, D) = ∏ M(1, 2, 5, 6, 10, 15) = (A + B + C + D') (A + B + C' + D) (A + B' + C + D') (A + B' + C' + D)
M1
M2
M5
M6
(A' + B + C' + D) (A' + B' + C' + D')
M10
M15
4.32 (a) If don't cares are changed to (1, 1), respectively,
F1 = A'B'C' + ABC + A'B'C + AB'C
= A'B' + AC
4.32 (b) If don't cares are changed to (1, 0), respectively
F2 = A'B'C'+ A'BC' + AB'C' + ABC' = C'
4.32 (c) If don't cares are changed to (1, 1), respectively
F3 = (A + B + C) (A + B + C') = A + B
4.32 (d) If don't cares are changed to (0, 1), respectively
F4 = A'B'C' + A'BC + AB'C' + ABC
= B'C' + BC
4.33
ABC D E F
0 0 0 1 1 X2
0 0 1 0 1 X2
0 1 0 0 X2 1
Z
0
1
1
0 1 1 X X X X
1 0 0 0 1 X2 1
1 0 1 0 X2 1 1
1
1
1
1 1 0 X1 X1 X1 X
1 1 1 1 X2 1 0
These truth table entries
were made don't cares
because ABC = 110 and
ABC = 011 can never
occur.
2
These truth table entries
were made don't cares
because when one input
of the OR gate is 1, the
output will be 1 regardless
of the value of its other
input.
1
4.34 (a) G1(A, B, C) = ∑ m(0, 7) = ∏ M(1, 2, 3, 4, 5, 6)
36
4.34 (b) G2(A, B, C) = ∑ m(0, 1, 6, 7) = ∏ M(2, 3, 4, 5)
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 4 Solutions
4.35 (a)
AB CD
00 0 0
00 0 1
00 1 0
00 1 1
01 0 0
01 0 1
01 1 0
01 1 1
10 0 0
10 0 1
10 1 0
10 1 1
11 0 0
11 0 1
11 1 0
11 1 1
1's
0
1
1
2
1
2
2
3
1
2
2
3
2
3
3
4
XY
00
00
00
01
00
01
01
01
00
01
01
01
01
01
01
10
Z
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
X = ABCD
4.36 (a)
Y = A'B'CD + A'BC'D +
A'BCD' + A'BCD +
AB'C'D + AB'CD' +
AB'CD + ABC'D' +
ABC'D + ABCD'
Z = A'B'C'D + A'B'CD' +
A'BC'D' + A'BCD +
AB'C'D' + AB'CD +
ABC'D + ABCD'
4.35 (b) Y = (A + B + C + D) (A + B + C + D')
(A + B + C' + D) (A + B' + C + D)
(A' + B + C + D) (A' + B' + C' + D')
AB CD
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
0 × 5 = 00
1 × 5 = 05
2 × 5 = 10
3 × 5 = 15
4 × 5 = 20
5 × 5 = 25
6 × 5 = 30
7 × 5 = 35
8 × 5 = 40
9 × 5 =45
STUV
00 0 0
00 0 0
00 0 1
00 0 1
00 1 0
00 1 0
00 1 1
00 1 1
01 0 0
01 0 0
WX
00
01
00
01
00
01
00
01
00
01
X = A'B'C'D + A'B'CD'
+ A'B'CD + A'BC'D'
+ A'BC'D + A'BCD'
+ A'BCD + AB'C'D'
+ AB'C'D + AB'CD'
+ AB'CD + ABC'D'
+ ABC'D + ABCD'
+ ABCD
Y = A'B'C'D' + A'BCD +
ABC'D + ABCD' +
ABCD
Z = A'B'C'D' + A'B'CD +
A'BC'D + A'BCD' +
AB'C'D + AB'CD' +
AB'CD + ABC'D' +
ABCD
4.36 (b) Y = (A + B + C + D') (A + B + C' + D)
(A + B + C' + D') (A + B' + C + D)
(A + B' + C + D') (A + B' + C' + D)
(A' + B + C + D) (A' + B + C + D')
(A' + B + C' + D) (A' + B + C' + D')
(A' + B' + C + D)
Z = (A + B + C + D) (A + B' + C + D')
(A + B' + C' + D) (A' + B + C + D')
(A' + B + C' + D) (A' + B' + C + D)
(A' + B' + C' + D')
4.37
A B C D WX Y Z
00 0 0 00 1 1
00 0 1 01 0 0
00 1 0 01 0 0
00 1 1 01 0 1
01 0 0 01 0 0
01 0 1 01 0 1
01 1 0 01 0 1
01 1 1 01 1 0
10 0 0 01 0 0
10 0 1 01 0 1
10 1 0 01 0 1
10 1 1 01 1 0
11 0 0 01 0 1
11 0 1 01 1 0
11 1 0 01 1 0
11 1 1 01 1 1
Z = (A + B + C + D') (A + B + C' + D)
(A + B' + C + D) (A + B' + C' + D)
(A' + B + C + D) (A' + B' + C + D')
(A' + B' + C' + D)
Y
0
0
0
0
0
0
0
0
0
0
4.38
Z
0
1
0
1
0
1
0
1
0
1
AB CD
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
0 × 4 + 1 = 01
1 × 4 + 1 = 05
2 × 4 + 1 = 09
3 × 4 + 1 = 13
4 × 4 + 1 = 17
5 × 4 + 1 = 21
6 × 4 + 1 = 25
7 × 4 + 1 = 29
8 × 4 + 1 = 33
9 × 4 + 1 =37
STUV
00 0 0
00 0 0
00 0 0
00 0 1
00 0 1
00 1 0
00 1 0
00 1 0
00 1 1
00 1 1
WX
00
01
10
00
01
00
01
10
00
01
Y
0
0
0
1
1
0
0
0
1
1
Note: Rows 1010 through 1111 have don't care
outputs.
Note: Rows 1010 through 1111 have don't care
outputs.
S = 0, T = A, U = B, V = C, W = 0, X = D, Y = 0, Z
=D
S = 0, T = 0, U = BD + BC + A,
V = B'CD + BC'D' + A, W = B'CD' + BCD,
X = B'C'D + BD', Y = B'CD + BC'D' + A, Z = 1
37
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Z
1
1
1
1
1
1
1
1
1
1
Unit 4 Solutions
4.39
Notice that the sign bit X3 of the 4-bit number is
extended to the leftmost full adder as well.
S4
S3
C3
F.A.
C4
F.A.
S2
C2
Y3
Y4
C1
F.A.
Y2
S1
X2
F.A.
Y1
X1
S0
C0
F.A.
Y0
0
X0
X3
4.40
XY
00
01
10
11
Sum Cout
0
0
1
1
0
4.41 (a), (a)
(b), (c) f = x(y+y')+y(x+x') = xy+xy'+x'y
Sum
(sum-of-minterms)
f = x+y already in product-of-maxterms form
X
0
0
1
Y
S3
C out
S2
C2
H.A.
S1
C1
H.A.
H.A.
(b)
f = ax+by = ax(y+y')+by(x+x')
= axy+axy'+bxy+bx'y = (a+b)xy+axy'+bx'y
= xy+axy'+bx'y
S0
C0
(c)
f ' = (a'+x')(b'+y') = (b+x')(a+y')
= ab+ax'+by'+x'y' = ax'(y+y')+by'(x+x')+x'y'
= ax'y+ax'y'+by'x+by'x'+x'y'
= ax'y+by'x+x'y'(a+b+1) = ax'y+by'x+x'y' so
f = (a'+x+y')(b'+x'+y)(x+y)
= (b+x+y')(a+x'+y)(x+y)
Alternatively,
f = ax+by = (a+by)(x+by) = (a+b)(a+y)(x+b)(x+y)
= (a+xx'+y)(b+yy'+x)(x+y)
= (a+x+y)(a+x'+y)(b+x+y)(b+x+y')(x+y)
= [(a+x+y)(b+x+y)(x+y)](a+x'+y)(b+x+y')
= (ab+x+y)(a+x'+y)(b+x+y')
= (x+y)(a+x'+y)(b+x+y')
H.A.
1
X3
4.41 (d), (d)
xy
(e)
00
01
0a
0b
10
11
1a
1b
X2
f
0
b
0
b
a
1
a
1
xy
a0
a1
aa
ab
b0
b1
ba
bb
X1
f
a
1
a
1
0
b
0
b
X0
(e)
f(x,y) is completely
specified by the
coefficients of the
minterms in the sum of
minterms expression.
These coefficients are
determined by the value
of the function for xy =
00, 01, 10 and 11.
38
4.42
(a) m1 + m2 = m1(m2' + m2) + (m1' + m1)m2
= m1m2' + m1m2 + m1'm2
But m1m2 = 0, so m1 + m2 = m1m2' + m1'm2
= m1 ⊕ m2.
(b) Using part (a), any function can be written as
the exclusive-or sum of its minterms. However, if
a product contains a complemented literal, it can
be written as the exclusive-or sum of two products
without a complemented literal by using
x'p = (x ⊕ 1)p = xp ⊕ p.
By repeated application of the preceding
relationship, all complemented literals can be
removed from the products.
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 4 Solutions
4.43
(a) Sum = X ⊕ Y ⊕ Cin and
Cout = X′YCin + XY′Cin + XYC′in + XYCin
= (X′Y + XY′)Cin + XY(C′in + Cin)
= (X ⊕ Y)Cin + XY
Cin
X
4.44
bi+1 = (xi + yi + bi)(xi′ + yi + bi)
(xi′ + yi + bi′)(xi′ + yi′ + bi)
= [(xi + yi)(xi′ + yi′) + bi](xi′ + yi)
= [(xi ⊕ yi) + bi](xi′ + yi)
bi
xi
Sum
yi
Y
Cin
bi
Cout
X
xi
(b) Cin to Cout is two gate delays so they are the
same.
E1
0
E0
0
si
si = ai ⊕ bi ⊕ ci
0
1
si = ai ⊕ bi ⊕ ci
1
0
si = ai ⊕ bi
1
1
si = ai ⊕ bi ⊕
aibi
ci+1
ci+1 = aibi + aici
+ bici
ci+1 = ai′bi +
ai′ci + bici
ci+1 = aibi + aici
+ bici
ci+1 = ai′bi +
ai′ci + bici
(b)
4.48
4.46
Same answer as Problem 4.45. This result can be
obtained by using gate conversions; the inverters at
the outputs of the NANDs can be moved forward
through the XOR’s where they cancel.
4.47
(a) si = ai ⊕ bi ⊕ E1ci ⊕ E1′E0′ai′bi′ and
ci+1 = (E0 ⊕ ai)bi + (E0 ⊕ ai)ci + bici
(a) si = ai ⊕ bi ⊕ E1′ci ⊕ E1E0aibi and
ci+1 = (E0 ⊕ ai)bi + (E0 ⊕ ai)ci + bici
E1
0
0
1
E0
0
1
0
1
1
bi+1
yi
Y
4.45
di
Function
Add (A + B)
Subt (A - B)
(a) si = ai ⊕ bi ⊕ (E1′ + ci′) ⊕ (E1 + E0 + ai + bi)
and ci+1 = (E0 ⊕ ai)bi + (E0 ⊕ ai)ci + bici
E0
0
si
si = ai′ + bi′
0
1
si = ai ⊕ bi
1
0
si = ai ⊕ bi ⊕ ci
1
1
si = ai ⊕ bi ⊕ ci
E1
0
0
E0
0
1
Function
NAND (A′ + B′)
1
1
0
1
E0
0
si
si = ai′ + bi′
0
1
si = ai ⊕ bi
1
0
si = ai ⊕ bi ⊕ ci
1
1
si = ai ⊕ bi ⊕ ci
E1
0
0
E0
0
1
Function
NAND (A′ + B′)
1
1
0
1
ci+1
ci+1 = aibi + aici
+ bici
ci+1 = ai′bi +
ai′ci + bici
ci+1 = aibi + aici
+ bici
ci+1 = ai′bi +
ai′ci + bici
(b)
XOR (A ⊕ B)
OR (A + B)
E1
0
E1
0
XOR (A ⊕ B)
Add (A + B)
Subt (A - B)
ci+1
ci+1 = aibi + aici
+ bici
ci+1 = ai′bi +
ai′ci + bici
ci+1 = aibi + aici
+ bici
ci+1 = ai′bi +
ai′ci + bici
(b)
XOR (A ⊕ B)
Add (A + B)
Subt (A - B)
39
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 4 Solutions
40
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 5 Solutions
5.3 (a)
bc
a
00
Unit 5 Problem Solutions
5.3 (b)
0
d
ef
1
1
01
1
1
CD
00
1
1
01
1
10
1
f1 = a'c' + a b'c + b c'
5.4 (a)
1
5.3 (c)
AB
1
5.4 (b)
01
11
10
1
1
1
1
00
01
CD
11
1
10
1
1
AB
cd
ab
1
1
01
1
0
11
1
11
1
1
10
1
10
1
1
1
01
10
1
1
1
1
1
01
1
1
10
1
1
01
1
1
11
1
1
11
1
*
1
01
11
10
00
0
0
1
0
01
1
1
0
0
11
1
0
1
1
10
1
1
0
0
1
*
*
1
f = a'b'c' + a'd + b'cd + abd' + bcd'
Alt: f = a'b'c' + a'd + b'cd + abd' + a'bc
00
01
11
10
00
1
1
1
1
01
0
0
1
0
1
11
1
0
1
1
1
1
10
1
1
1
1
F = (A + B'+ D')(B + C + D')
Z = C1'X1'X2 + C1'X1X2' + C1C2X1'X2' + C1X1X2 + C1'C2'X2
Alt:
Z = C1'X1'X2 + C1'X1X2' + C1C2X1'X2' + C1X1X2 + C1'C2'X1
Z = C1'X1'X2 + C1'X1X2' + C1C2X1'X2' + C1X1X2 + C2'X1X2
cd
*
AB
CD
F = D' + B'C + A B
10
1
f4 = x'z + y + x z'
1
5.6 (b)
00
1
1
11
C1 C2
00
yz
5.4 (c)
11
1
X1 X2
00
10
0
1
01
1
5.5 (b)
See FLD p. 735
for solution.
5.6 (a)
00
00
00
01
F = BD' + B'CD + ABC + ABC'D + B'D'
5.5 (a)
1
1
f3 = r' + t'
00
1
x
0
0
f2 = d'e' + d'f ' + e'f '
00
5.3 (d)
r
st
11
11
10
0
ab
00
01
11
00
1
1
0
01
0
1
1
11
1
1
1
0
10
1
1
0
1
*
10
1*
*
0
F = a'c + b'd' + bd + a'd'
Alt: F = a'c + b'd' + bd + a'b
(*) Indicates a minterm that makes the
corresponding prime implicant essential.
(*) Indicates a minterm that makes the
corresponding prime implicant essential.
a'd →m5; a'b'c'→m0; b'cd→m11;abd'→m12
bd→m13 or m15; a'c→m3; b'd'→m8 or m10
41
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 5 Solutions
5.6 (c)
cd
ab
5.7 (a)
ab
00
01
11
10
00
1
1
1
1
00
01
X
0
0
X
01
11
X
0
0
1
10
X
1
0
1*
*
*
cd
*
F = a'd' + b' + c'd'
00
01
1
1
11
1
1
10
1
11
10
1
1
f = a'c'd' + a'cd + b'c'd' + abcd' + a'b'd'
Alt: f = a'c'd' + a'cd + b'c'd' + abcd' + a'b'c
(*) Indicates a minterm that makes the
corresponding prime implicant essential.
c'd'→m12; a'd'→m6; b'→m10 or m11
5.7 (b)
cd
ab
5.7 (c)
00
01
00
X
1
01
1
11
X
10
1
11
10
cd
ab
10
00
0
0
X
0
0
01
X
1
1
X
0
1
11
1
1
X
1
1
1
10
0
0
1
1
10
00
1
0
1
1
01
0
1
1
1
11
0
1
X
10
0
1
f = b'c'd' + ab'c + a'bc + bc'd + ad'
cd
ab
F=D+AC
01
11
10
00
01
11
10
00
0
1
0
0
00
0
1
0
0
01
0
1
1
1
01
0
1
1
1
11
X
X
X
0
11
X
X
X
0
10
1
0
X
1
10
1
0
X
1
f = (c'+ d')(b'+ c')(a + b + c)(a'+ c + d)
cd
11
11
00
cd
5.8 (b)
01
01
CD
ab
00
01
11
10
00
0
1
X
X
01
1
0
0
11
1
X
10
X
0
AB
00
00
f = a'b' + a'c'd' + abc
5.8 (a)
5.7 (d)
ab
f = a'bc' + ac'd + b'cd'
cd
ab
00
01
11
10
00
0
1
X
X
0
01
1
0
0
0
X
1
11
1
X
X
1
X
0
10
X
0
X
0
f = a'b'd + bc'd' + cd
f = (a'+ c)(b'+ d')(b + d)(c'+ d)
Alt: f = (a'+ c)(b'+ d')(b + d)(b'+ c')
42
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 5 Solutions
5.9 (a)
BC
DE
00
A 01
1
0
11
10
00
01
1
11
1
1
0
0
X
1
1
X
1
X
0
0
1
0
1
1
1
1
1
1
0
0
BC
DE
1
1
0
1
1
0
1
10
0
1
X
0
1
1
1
0
0
0
0
0
0
1
0
1
0
1
1
1
0
X
1
1
0
1
0
0
0
11
11
1
1
1
1
X
1
1
1
0
X
1
X
0
0
1
0
10
0
1
X
10
1
01
0
1
A 01
0
1
0
0
X
00
1
00
1
X
BC
DE
0
X
0
F = A'C'E + A'C'D + A'D E + A B'C D' + C'D E
+ A B C D E' + B'C'E' + A'B'D
Alt: F = A'C'E + A'C'D + A'D E + A B'C D' + C'D E
+ A B C D E' + B'C'E' + A'B'E'
10
0
1
X
11
11
0
0
A 01
0
01
1
00
1
00
0
0
1
1
10
0
X
1
X
10
1
11
0
X
0
11
X
F = (A'+ B'+ C + E )(A'+ B + C'+ D')(A + B'+ C'+ E )
(B'+ D + E )(A + C'+ D)(A'+ C + D + E')(A'+ B'+ C'+ E')
5.9 (b)
0
01
1
1
A 01
1
00
1
00
0
0
0
BC
DE
0
0
0
X
10
0
0
1
0
0
0
0
1
1
F = A'C D' + A'B E' + C D E + A B'C'D' + A B'D E' + B'C E
F = A'C D' + A'B E' + C D E + A B'C'E' + A B'C D + B'D'E
F = (A'+ B'+ E )(A'+ C'+ D + E )(C + D'+ E')
(A + B + D'+ E )(A + B + C )(B'+ D + E')
Alt:
F = A'C D' + A'B E' + C D E + A B'C'D' + A B'D E' + B'D'E
F = A'C D' + A'B E' + C D E + A B'C'E' + A B'D E' + B'D'E
5.10 (a)
bc
de
00
a
1
0
00
01
10
5.10 (b)
10
1
1
1
1
1
1
1
00
1
1
1
a
1
1
1
1
1
bc
de
1
01
11
11
0
01
11
11
10
1
1
1
1
01
10
1
00
1
1
1
1
1
1
1
1
1
1
1
1
Prime implicants: a'b'de, a'd'e', cd'e, a'ce', ace,
a'b'c, b'ce, c'd'e', a'cd'
Essential prime implicants: c'd'e' (m16 , m24 ),
a'ce' (m14 ), ace (m31 ), a'b'de (m3 )
43
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 5 Solutions
5.11
5.12 (a)
bc
de
00
1
00
a
1
0
01
0
1
1
X
1
11
1
0
0
1
1
0
1
0
0
X
1
1
0
0
0
10
0
1
0
0
1
AB
CD
10
1
0
01
11
01
11
10
0
1
0
1
01
0
1
0
0
11
1
1
1
1
10
1
1
0
1
0
F = A B'D' + A'B + A'C + C D
F = ∏ M(0, 1, 9, 12, 13, 14) = (A + B + C + D)
(A + B + C + D') (A' + B' + C + D)
(A' + B' + C + D') (A' + B' + C' + D)
(A' + B + C + D')
0
1
00
00
1
f = (a'+ b + c') (a'+ d'+ e) (a + b'+ e') (a + c + e')
(a + b + c + d) (a'+b'+ c + d) (c + d + e')
Alt: f = (a'+ b + c') (a'+ d'+ e) (a + b'+ e') (a + c + e')
(a + b + c + d) (a'+b'+ c + e ) (c + d + e')
5.12 (b)
AB
CD
5.13
01
11
10
CD
00
01
00
1
0
1
0
00
1
1
01
1
0
1
1
01
1
1
11
0
0
0
0
11
1
10
0
0
1
0
10
1
F' = A'B'C' + A B D' + A C'D
5.12 (c)
CD
AB
00
AB
00
01
11
10
00
0
1
0
1
01
0
1
0
0
11
1
1
1
1
10
1
1
0
1
11
10
1
1
1
1
F = A C D' + B C'D + B'C + A'C'
Minterms m0, m1, m2, m3, m4, m10, and m11 can be
made don’t cares, individually, without changing
the given expression. However, if m13 or m14 is
made a don’t care, the term BC'D or the term ACD'
(respectively) is not needed in the expression.
F = (A'+ B'+ D )(A + B + C )(A'+ C + D')
5.14 (a)
BC
A
5.14 (b)
0
1
00
01
d
5.14 (c)
0
1
1
st
r
00
1
1
00
1
01
1
1
01
01
1
11
1
11
10
1
10
1
f1 = B'C + A'BC' + AC
f2 = e'f + d e
44
1
1
f3 = s' + t'
bc
a
1
1
1
5.14 (d)
0
00
11
10
ef
0
1
1
11
1
10
1
1
f4 = a'c' + bc
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 5 Solutions
5.14 (e)
pq
5.14 (f)
n
0
1
00
01
1
11
1
1
00
1
01
10
st
5.15 (d)
r
0
bc
1
01
A
0
1
1
01
11
1
11
1
10
1
0
10
5.16 (c)
st
0
0
0
10
0
x
yz
1
0
1
00
0
01
0
0
11
0
10
r
0
0
f6 = (x + y + z')(x'+ y'+ z')
5.16 (d)
a
bc
0
1
1
1
00
00
1
01
1
01
1
11
1
11
1
10
1
5.17 (a)
& (b)
0
1
1
1
1
1
f1 = bc + ac'
f3 = t' + r
CD
AB
00
00
1
1
00
1
1
01
1
1
01
1
1
11
0
1
11
1
10
1
0
10
1
45
0
11
1
f4 = y' + x'z' + xz
1
0
f2 = (e + f )(d + e')
5.15 (f)
0
10
x
0
01
f5 = (n + q )(n'+ p')
1
1
00
1
f2 = n'p + nq
yz
0
d
ef
0
1
00
11
01
f2 = e'f + de' + df
5.16 (f)
01
0
10
f1 = A'C + AC'
n
00
0
1
0
pq
0
00
1
0
11
d
ef
1
f1 = (A'+ C)(A + B'+ C')(B + C)
1
0
5.15 (b)
0
10
1
5.15 (e)
0
01
n
11
f4 = (b + c')(a'+ c )
5.16 (b)
10
pq
01
10
00
5.16 (e)
1
11
0
f3 = (s'+ t')
BC
00
1
01
10
5.16 (a)
1
10
00
0
1
1
00
11
1
11
a
A
BC
0
f6 = z' + x'y + xy'
f5 = n'q + np'
5.15 (c)
5.15 (a)
x
yz
01
11
10
1
1
1
1
F = A'B' + CD' + ABC
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 5 Solutions
5.17 (c)
CD
5.18 (c)
5.18 (a) & (b)
AB
00
01
11
10
00
1
0
0
0
01
1
0
0
11
1
0
10
1
1
C D
A B
00
01
11
10
A B
00
C D
01
11
10
00
1
1
0
0
00
1
1
0
0
0
01
1
1
1
1
01
1
1
1
1
1
0
11
1
1
0
0
11
1
1
0
0
1
1
10
1
1
0
1
10
1
1
0
1
F = (B'+ C )(A + B'+ D')(A'+ C )(A'+ B + D')
F = (A'+ C + D ) (A'+ C'+ D') (A'+ B'+ D )
F = A' + C'D + B'C D'
Alt: F = (A'+ C + D ) (A'+ C'+ D') (A'+ B'+ C')
5.19 (a)
C1 C2 X1 X2
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
5.19 (b)
Z
0
0
0
1
0
1
1
0
1
1
0
1
1
0
0
1
X1X 2
C1C 2
00
01
11
10
00
0
0
1
1
01
0
1
0
1
11
1
0
1
1
10
0
1
0
0
{
(C1' + C2' + X1 + X2')(C1'+ X1' + X2) (C1 + C2 +X2)
5.20 (a)
bc
a
5.20 (b)
0
00
1
01
1
10
1
1
ef
d
0
1
00
X
1
1
01
1
1
11
1
10
F = a'c' + b'c + ab or
= a'b' + bc' + ac
qr
p
5.20 (d)
0
00
1
01
1
11
1
10
1
tu
s
5.20 (e)
0
00
X
01
1
1
11
1
1
10
1
1
F = p'r + q'r' + pq or
or
(C2 + X1'+X2)
11
5.20 (c)
}
F = (C1 + C2 + X1)(C1 + X1 + X2)(C1 + C2' + X1' + X2')
1
bc
a
D
0
1
01
1
11
1
11
X
10
1
10
X
01
1
X
46
EF
X
1
= p'q' + pr' + qr
1
00
00
F = s'
1
X
g = d'e' + f '
5.20 (f)
0
X
f = a'b' + a b + b'c or
= a'b' + a b + a c
1
X
1
G = D E F' + D'E'
G = D E F' + D'F
G = D E F' + E'F
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 5 Solutions
5.21
ab
cd
5.22 (a)
00
00
1
01
1
01
11
1
10
00
00
01
1
11
X
1
X
1
01
X
1
X
01
1
1
11
X
1
11
1
1
10
X
X
10
11
1
10
1
CD
X
10
CD
AB
00
01
11
10
X
01
X
X
11
X
10
X
X
1
11
X
1
10
5.23 (a)
X
1
X
00
0
X
01
X
X
X
01
0
X
X
11
11
0
X
X
10
10
0
X
X
10
X
CD
AB
00
01
00
0
0
X
00
01
0
X
X
01
11
0
X
PIs: (B'+ C'+ D'), (A + C ), (A + D ),
(B + D), (B + C), (A + B')
f = (B'+ C'+ D') (A + D ) (B + C ) or
= (B'+ C'+ D') (A + C ) (B + D ) or
= (B'+ C'+ D') (A + C ) (A + D )
X
CD
1
X
X
PIs: B C D, A'C', A'D', A'B, B'D', B'C'
f = B C D + A'B or
f = B C D + A'D' or
f = B C D + A'C'
5.23 (c)
10
X
10
AB
00
11
11
10
01
0
0
X
X
AB
10
0
X
00
0
X
01
0
X
0
11
0
X
X
10
0
X
0
PIs: (B + C + D ), (C'+ D'), (A'+ C + D ),
(A' + B), (A + B' + D'), (A + B' + C')
f = (B + C + D ) (C'+ D') (A'+ C + D )
47
00
11
X
X
01
11
10
X
X
0
X
PIs: (B'+ C'+ D'), (A + B ),
(A + D'), (A + C')
f = (B'+ C'+ D') (A + B )
5.23 (d)
00
1
PIs: C D, A'B, A B'
f = C D + A'B
01
X
CD
1
X
PIs: A'B, B C D, A B'C', A B'D'
f = A'B + B C D
AB
X
00
X
X
1
X
01
0
X
01
X
10
1
X
X
X
X
X
1
11
1
1
00
11
X
00
PIs: A'B, B C', B D', A C', A D', A B'
f = B D'
f = B C'
f = A'B
CD
1
X
10
AB
11
X
X
11
X
01
10
1
X
5.22 (e)
00
11
1
01
5.23 (b)
CD
AB
01
PIs: B'C D, A C', A D', A B', B C'D,
B C D', A'C D, A'B D, A'B C
f = B'C D + A C' + A D'
PIs: A B', B C', A D', B D', A C', A' B
f = A B' + B D' + A C' or
= A B' + B C' + B D' or
= A B' + B C' + A D'
5.22 (g)
00
1
00
00
PIs: C'D, C D', A'B, A B'C', A B'D'
f = C'D + C D' + A'B
AB
AB
CD
00
X
10
10
X
1
01
11
1
5.22 (d)
CD
01
1
5.22 (c)
AB
00
00
F = a'b'c' + a'c'd + bcd +abc + a b'
= (a'b'c' + ab') + a'c'd + bcd + (abc + a b')
= (a'c' + a)b' + (a'c'd + bcd) + a(bc + b')
= (c' + a)b' + (a'c'd + bcd +a'bd) + a(c + b')
= (b'c' + a'bd + a'c'd) + (bcd + a'bd + ac) + ab'
= (b'c' + ac + ab') + a'bd
= b'c' + ac + a'bd
5.22 (f)
CD
5.22 (b)
1
1
11
10
AB
CD
00
01
11
10
0
X
0
X
0
0
X
PIs: (B ), (A'+ C ), (A'+ D ), (C + D'),
(C' + D), (A + D'), (B + D'), (A + C')
f = (B ) (C + D') (A'+ D ) or
= (B ) (A'+ C ) (C'+ D ) or
= (B ) (A'+ C ) (A'+ D )
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 5 Solutions
5.23 (e)
CD
AB
5.23 (f)
00
00
0
01
0
11
10
01
X
X
10
0
X
00
0
0
X
01
0
11
10
CD
0
X
PIs: (C + D'), (A'+ D ), (B + D ), (A' + C),
(B + C), (C' + D), (A + B' + D'), (A + B'+ C')
f = (A'+ C ) (B + C ) (C'+ D ) or
= (C + D') (A'+ D ) (B + D )
5.24 (a)
C D
5.23 (g)
11
X
0
AB
00
01
10
X
X
00
X
X
X
X
01
X
X
0
X
0
X
11
0
X
0
X
X
X
10
X
X
00
01
1
01
1
11
1
1
10
1
1
11
10
= (B ) (D')
1
00
1
01
1
01
X
11
C D
10
1
X
10
1
X
Alt: F = A B C' + B'C D + A'C + A'B'D' + B C'D
Alt: F = A'C'D' + B'C'D' + A'B'C
yz
5.24 (e)
00
01
00
1
01
X
1
11
1
1
10
X
10
1
0
X
0
X
11
10
X
1
F = A'C'D + A'B + B C'D
5.25 (a)
cd
ab
0
X
1
1
00
1
01
0
0
X
0
01
1
X
11
1
0
1
0
11
1
1
10
0
1
1
X
10
1
X
F = A'B'C D + BD' + AD' + AB
00
01
11
10
1
1
1
1
1
1
f = a'd + a'bc' + c'd + bd
f = x'y' + wy' + w'z + wz'
f = x'y' + wy' + w'z + wx'
5.25 (b)
cd
1
00
f = x'y' + w'z + y'z + wz'
Alt:
11
10
1
10
0
0
1
11
1
CD
1
01
10
11
X
00
11
X
AB
01
00
1
F = A'C'D' + B'C'D' + A'B'D'
wx
A B
00
01
11
01
5.24
F (c)
A B
00
C D
00
PIs: (B)(A'+ D)(A'+ C)(A + C')
(C'+ D)(C + D')(A + D')
f = (B)(A'+ C)(C'+ D) or
= (B)(A'+ D)(C+ D') or
= (B)(A'+ D)(A'+ C)
F = A B C' + B'C D + A'C + A'B'D' + A'B D
5.24 (d)
CD
PIs: (B), (D'), (A'), (C')
f = (B ) (A') or
= (B ) (C') or
5.24 (b)
A B
00
AB
11
ab
5.25 (c)
ab
5.25 (d)
00
01
11
10
00
0
1
1
0
00
01
1
0
1
1
01
11
0
1
1
0
11
X
10
1
1
1
1
10
1
cd
f= b'c'd + cd' + bd' + bc + ab
00
01
11
1
1
1
1
f = b'd' + cd' + ac'd
48
10
cd
ab
00
01
11
10
X
00
0
1
0
1
1
01
X
X
0
0
11
X
0
1
1
10
0
0
1
1
X
f = a'bc' + ab'd' + ac
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 5 Solutions
5.26 (a)
AB
CD
00
5.26 (b)
00
01
0
0
01
11
10
0
11
10
0
0
0
A B
00
C D
01
11
10
00
0
0
X
1
0
01
1
0
0
1
X
11
1
X
1
0
X
10
0
X
0
0
F = (C'+ D ) (A'+ B + D') (A + B'+ C ) (A + D )
F = (B'+ C ) (A'+ B + C') (A + D ) (C'+ D )
Alt: F = (B'+ C ) (A'+ B + C') (A + D ) (B'+ D )
5.27 (a)
CD
AB
00
01
11
10
00
0
1
0
1
01
1
X
1
11
1
X
10
0
1
00
01
11
10
00
0
1
0
1
1
01
1
X
1
1
0
0
11
1
X
0
0
0
0
10
0
1
0
0
f = (A'+ B'+ D)(A'+ C')(A + B + D)
5.27 (b)
wx
yz
f = C'D + AB'C' + A'B + A'D
wx
00
01
11
10
yz
00
01
11
10
00
1
0
1
1
00
1
0
1
1
01
X
1
1
1
01
X
1
1
1
11
1
1
0
X
11
1
1
0
X
10
0
X
X
1
10
0
X
X
1
f = x'y' + w'z + y'z + wz'
Alt:
5.28
cd
ab
f = (w + x'+ z)(w + y'+ z)(w'+ y'+ z')
f = (w + x'+ z)(w + y'+ z)(w'+ x'+ y')
Alt:
f = x'y' + wy' + w'z + wz'
f = x'y' + wy' + w'z + wx'
5.29 (a)
00
AB
CD
01
11
00
1
01
1
X
1
11
1
1
X
10
1
10
CD
AB
5.29 (b)
00
01
11
10
CD
AB
00
01
11
10
1
00
0
1
0
1
00
1
0
1
0
1
01
0
1
0
0
01
1
0
1
1
11
1
1
1
1
11
0
0
0
0
10
1
1
0
1
10
0
0
1
0
1
F = b'd' + a'd + c'd
Notice that abcd = 0101 and 1111
never occur, so minterms 5 and 15
are don’t cares.
F = A B'D' + A'B + A'C + C D
F '= ABD' + A'B'C' + AC'D
F = ∏ M(0, 1, 9, 12, 13, 14)
= (A + B + C + D)(A + B + C + D')
(A' + B + C + D' )(A' + B' + C + D)
(A' + B' + C + D')(A' + B' + C' + D)
49
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 5 Solutions
5.29 (c)
AB
CD
5.30
AB
CD
00
01
11
10
01
1
X
1
X
1
11
1
1
1
X
1
10
00
01
11
10
00
0
1
0
1
00
01
0
1
0
0
11
1
1
1
10
1
1
0
1
F = D + AB C
F = (A'+ B'+ D )(A + B + C )(A'+ C + D')
5.31
For F: b'c'de', a'ce, ab'e', ac'd', abc'e, c'd'e, a'd'e
5.32
Prime implicants for f ': abc'e, ac'd', ab'e', a'ce,
b'c'de', c'd'e, a'd'e
For G: ab'ce, a'bcd, a'bde', cde, b'de, a'b'c'd, a'c'e'
Prime implicants for f: a'd'e', ace, a'ce', bde', abc,
bce', b'c'de, a'c'de, a'bc'd, ab'de
5.33
5-variable mirror image map
de
5-variable diagonal map
abc
000 001 011 010 110 111 101 100
00
1
01
1
11
1
10
1
1
1
1
1
1
1
1
1
00
a 01
1
1
1
Essential PIs: ab'c'e', a'bc'e, a'b'cd
f = a'b'cd + a'bc'e + ab'c'e' + a'bcd' + ab'ce + ac'd'e + acd'e'
cd
ab
00
00
01
11
X
1
X
01
X
10
5.34 (b)
& (c)
ab
cd
00
00
01
11
X
1
X
1
X
1
X
1
X
PIs: bd', a'b, a'd', c, ab'd
f = b d' + c or
= a'b + c or
= a'd' + c
50
1
1
1
1
1
1
11
1
1
1
5.34 (d)
& (e)
1
cd
ab
00
X
10
X
1
11
1
1
1
0
X
10
1
10
01
1
1
11
X
X
X
1
01
X
11
1
00
00
01
X
X
10
X
11
0
10
Other PIs: ab'd', b cd'e', bc'd'e, a'bd'e, b'cde
5.34 (a)
b c
d e
10
01
X
11
10
X
0
0
X
X
X
X
PIs: (c + d'), (a'+ c), (b + c ), (a + b +d'),
(a + b'+c'+d), (a'+b'+d'), (a'+b+d )
f = (c + d')(a'+ c ) or
= (b + c )(c + d') or
= (b + c )(a'+ c )
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 5 Solutions
5.35 (a), 5-variable mirror image map
(b) &
ABC
(c)
DE
000 001 011 010
00
X
01
1
11
X
10
5-variable diagonal map
110 111 101 100
X
1
X
X
X
1
X
1
X
X
X
X
X
1
X
X
X
X
1
X
X
X
X
X
X
00
A 01
1
0
PIs: A, C'D', B'E, C E, B D', D'E, B C'E', B'C D
F= A + B'E + BD' or
= A + C'D' + CE
X
01
11
10
X
0
X
X
X
X
0
0
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
01
X
X
1
11
X
1
X
10
X
X
1
X
A 01
X
1
X
0
110 111 101 100
X
X
X
X
X
01
X
X
11
X
10
X
X
1
X
1
X
X
X
X
X
X
X
X
00
01
11
X
X
X
10
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
0
X
0
X
1
X
X
X
X
1
X
X
1
X
00
00
X
A 01
1
0
11
10
01
11
X
X
10
X
X
X
X
X
X
X
1
X
X
X
X
X
1
1
X
1
1
X
X
X
X
X
X
1
X
5-variable diagonal map
X
X
X
X
0
X
1
X
X
X
X
B C
D E
X
ABC
000 001 011 010 110 111 101 100
X
X
1
X
10
X
5-variable diagonal map
5.36 (d), 5-variable mirror image map
(e)
00
11
X
X
1
11
10
PIs: A B, A D, A C'E, B C, B D'E, C D, D E', C E',
A'C, B'D, C'D'E,A'D'E, B'C'E, A'B'
F = A'C + B'D + AB or
= B'D + AB + BC or
= A'C + AB + AD
DE
X
00
X
F = (B'+D')(A + B + E) or
= (C'+ E)(A + C + D')
00
01
X
X
B C
D E
PIs: (A'+ B'), (A'+ C'), (A'+D + E'), (B'+D'), (B'+ C + E'),
(C'+ E), (D'+E), (B + C'+ D), (A + C + D'), (A + B + E)
5.36 (a), 5-variable mirror image map
(b) &
ABC
(c)
DE
000 001 011 010
00
1
5-variable diagonal map
000 001 011 010 110 111 101 100
00
11
10
5.35 (d), 5-variable mirror image map
& (e)
ABC
DE
B C
D E
X
X
0
X
0
X
X
0
X
X
X
X
X
B C
D E
00
A 01
1
X
PIs: (A'+ B'+ C'), (A'+B'+D'), (A'+ B'+ E), (A'+ C'+ E'),
(A'+C'+ D), (B'+ D'+ E'), (B'+ C+ D'), (D + E),
(A + B + E), (A + C ), (B + D ), (C + E)
F = (A + C )(B + D )
51
0
00
11
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
10
X
0
X
11
10
01
0
X
0
X
X
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 5 Solutions
5.37 (a),
(b) &
(c)
BC
DE
11
X
1
X
1
1
X
X
1
X
X
00
1
0
11
1
00
a
01
10
01
1*
1 *
10
1
1
1
00
a
0
00
1
10
11
1
1
1
1
1
1
1
1
1
X
1
0
0
01
X
11
10
1
1
1
1
1
1
1
1
1
1
1
1
1
bc
01
a
X
1
1
00
1
00
1
X
X
X
1
de
1
1
1
0
0
1
a'b'd', cd'e', bc'd'e, b'cd', ac'de', ab'ce', ab'de', a'c'd'e,
a'bc'e, a'bc'd, bc'de', a'bde', a'bce'
10
1
1
01
11
01
X
X
0
5.39 (b)
bc
de
X
10
a'b'd'→m1; cd'e'→m28; bc'd'e→m25; b'cd'→m21
5.39 (a)
0
11
1
(*) Indicates a minterm that makes the
corresponding prime implicant essential.
1
0
1
1
X
01
a
1
11
0
X
X
00
1
X
X
X
bc
de
1
1*
10
X
F = (A'+ D + E')(C'+ E )(D'+ E )(B'+ D') or
= (A + B + E )(B'+ D')(A'+ B')(A'+ C') or
= (A + C + D')(C'+ E )(A'+ B')(A'+ C') or
= (B + C'+ D )(D'+ E )(B'+ D')(A'+ B') or
= (B'+ C + E')(C'+ E )(D'+ E )(A'+ C')
1
1 *
1
0
0
11
5.38 (b)
bc
de
11
0
PIs: (B'+ C + E'), (C'+ E ), (D'+ E ), (A'+D +E'),
(A'+ C'), (B'+D'), (A'+B'), (A + C+D'), (A + B + E)
A'B'E + A'B D' + A B'C' or
A'C'D' + A'C E + A B'C' or
A'D'E + B'D E + C'D'E' or
A'B D' + B'C'D' + B'D E or
A'C E + B'C'E + C'D'E'
5.38 (a)
X
10
X
PIs: A B C D E', B C D'E, A C'D E, A B'D'E', A B'C',
A'B C'E', A'B D', A'B'C D, A'D'E, A'C E, B'D E, A'B'E,
B'C'E, C'D'E', A'C'D', B'C'D'
F =
=
=
=
=
0
01
X
X
A 01
X
X
10
00
00
1
X
X
BC
DE
X
1
11
5.37 (d),
& (e)
10
X
X
X
A 01
0
01
X
1
00
1
00
0
11
00
01
1
11
1
10
1
1
1
1
1
1
1
1
1
1
1
10
1
f = a'b'c + a'bc' + ab'c'd + c'd'e' + abd' + bcde + a'c'e
Alt: f = a'b'c + a'bc' + ab'c'd + c'd'e' + abd' + bcde + a'b'e
alt:
52
f = a'b'c'e + a'bc'd' + bcde + ab'd'e' + abde + acd'e' +
a'b'd'e + ab'ce
f = a'b'c'e + a'bc'd' + bcde + ab'd'e' + abde + acd'e' +
b'cd'e + ab'ce
f = a'b'c'e + a'bc'd' + bcde + ab'd'e' + abde + acd'e' +
b'cd'e + acde
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 5 Solutions
5.40
01
0
1
1
A 01
0
00
0
00
1
5.41
BC
DE
1
1
1
1
1
0
00
X
00
0
X
1
1
1
1
0
1
0
1
0
0
1
X
1
0
00
a
1
0
01
11
10
00
01
0
0
0
0
1
1
0
1
0
1
0
0
0
1
1
1
0
1
1
a
1
1
0
0
1
0
F = (c + d + e)(a'+ b)(a + b')(a + c'+ d'+ e')
1
1
1
0
0
0
0
1
X
bc
0
01
11
10
0
1
0
1
0
0
0
1
0
1
10
0
1
1
X
00
0
11
1
1
X
de
0
0
01
0
1
0
0
1
F = (X + Y + Z) (V + Y' + Z') (V + X' + Z')
(V + X' + Y') (V' + W + Z)
0
0
1
1
10
00
0
11
1
11
1
1
X
X
5.43 (b)
bc
de
X
X
1
10
F = V'XY'Z' + X'Y'Z + VZ + WX'YZ' + VWX
5.43 (a)
0
0
1
0
1
1
V 01
1
1
0
1
00
0
1
0
0
10
0
1
1
WX
YZ
10
1
X
11
11
0
0
V 01
1
01
1
F = AB'CD'E' + BC'D' + ABDE'
+ A'B'C'E' + A'C'DE + A'CD'E
5.42 (b)
WX
YZ
10
X
1
10
0
11
1
11
1
F = A'B'C'D' + BC'DE + BCD' + B'CDE' + ABC'D
+ A'B'CE + AD'E
5.42 (a)
0
1
0
0
0
0
01
1
A 01
1
0
00
00
0
1
1
0
10
1
1
0
BC
DE
0
0
1
0
10
1
1
0
11
11
00
01
1
11
0
X
1
X
1
1
0
0
1
0
0
0
1
1
0
0
X
1
1
1
X
10
0
0
0
0
1
0
0
0
1
0
F = (c + d')(a + d'+ e')(b'+ c + e')(a'+ b'+ c'+ d)
(a + c + e) (b + c'+ e)
Alt: F = (c + d + e)(a'+ b )(a + b')(b + c'+ d'+ e')
Alt: F = (c + d')(a + d'+ e')(a + b'+ c)(b'+ c + e')
(a'+ b'+ c'+ d)(b + c'+ e)
53
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 5 Solutions
5.44 (a)
1
5.45 (a)
1
1
1
0
1
1
00
01
00
1
1
01
1
1
11
1
10
1
11
0
0
1
0
a
0
0
1
0
1
1
0
0
YZ
1
11
1
10
00
V 01
1
0
01
1
X
1
X
1
1
1
1
0
X
0
0
0
00
01
11
10
1
1
1
1
1
1
1
1
1
ab
00
01
11
10
00
1
1
1
1
01
1
1
1
11
1
1
1
10
1
1
1
X
f
cd
1
X
1
X
Changing m1 to a don't care removes C'D from the
solution.
10
1
0
0
F = C'D + BD + AB'
1
11
10
11
0
X
0
AB
01
5.47 (a)
00
0
0
11
CD
1
m4, m13, or m14 change the minimum
sum of products, removing A'C', BC'D,
or ACD', respectively.
WX
0
00
1
10
0
F = (c + d + e) (a' + c' + d') (a' + b + c + d)
(a + c' + d) (b + d' + e) (a + c + e)
5.45 (b)
10
11
0
10
0
01
X
01
F = ACD' + BC'D + B'C + A'C'
5.46 (a)
00
0
00
1
0
0
0
0
1
bc
de
F = (v'+ w'+ x'+ y + z')(w + y'+ z')(v + y')(w + x + y)
(v'+ x + y + z) (w'+ x + y')
F = (v'+ w'+ x'+ y + z')(w + y'+ z')(v + y')(w + x + y)
(v'+ w'+ x + z )(w'+ x + y')
F = (v'+ w'+ x'+ y + z')(w + y'+ z')(v + y')(w + x + y)
(v'+ w'+ x + z)(x + y'+ z')
AB
CD
1
0
10
1
1
0
11
11
1
0
10
Alt:
01
0
01
0
00
0
00
v
5.44 (b)
wx
yz
1
1
1
F = V'XY' + V'WZ' + XYZ + VW'X'Y' + VW'Y Z' + W'XZ
m4
m8
m31
1
F = V'XY' + V'WZ' + XYZ + VW'X'Z' + VW'XY + W'Y'Z
F = V'XY' + V'WZ' + XYZ + VW'X'Y' + VW'Y Z' + W'Y'Z
F = V'XY' + V'WZ' + XYZ + VW'X'Z' + VW'Y Z' + W'Y'Z
5.46 (b) V'WZ'→m8; XYZ→m31; V'XY'→m4
5.47 (b) Essential: a′b′, ab, c′d′, cd,
Nonessential: a′c′, a′d, bc′, bd
5.47 (c) f = a′b′ + ab + c′d′ + cd + a′d
f = a′b′ + ab + c′d′ + cd + bd
f = a′b′ + ab + c′d′ + cd + bc′
f = a′b′ + ab + c′d′ + cd + a′c′
54
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 5 Solutions
5.48 (a)
f
cd
5.49 (a)
ab
00
01
11
10
00
1
1
1
1
01
1
1
1
1
11
1
1
1
10
1
1
f
ab
cd
1
f(a, b, c, d) = ∑m(0, 1, 2, 3, 4, 5, 7, 8, 9, 10, 12, 13,
14, 15)
5.48 (b) Essential: c'
Nonessential: a'b', a'd, b'd', bd, ab, ad'
00
01
11
10
00
1
1
1
1
01
1
1
1
1
11
1
1
10
1
1
1
1
f(a, b, c, d) = ∑m(0, 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12,
13, 14)
5.49 (b) Essential: b', c', a'd, ad'
5.49 (c) f = b' + c' + a'd + ad'
5.48 (c) f = c' + a'd + b'd' + ab
f = c' + a'b' + ad' + bd
Another solution to 5.49
5.49 (a)
f
cd
ab
5.50 (a)
00
01
11
10
00
1
1
1
1
01
1
1
11
1
10
1
1
f
cd
ab
00
01
11
10
00
1
1
1
X
1
01
1
1
0
X
1
1
11
X
X
0
0
1
1
10
0
0
X
X
f(a, b, c, d) = ∑m(0, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12,
14, 15)
f(a, b, c, d) = ∑m(0, 1, 4, 5, 12)
+ ∑d(3, 7, 8, 9, 10, 14)
5.49 (b) Essential: b', a'c', d', ac
5.50 (b) Nonessential: a'd, c'd', a'c', b'c', ad'
5.49 (c) f = b' + a'c' + d' + ac
5.50 (c) f = a'd + c'd'
f = a'c' + c'd'
f = a'c' + ad'
'
55
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 5 Solutions
5.50 (d)
f
cd
ab
00
01
11
10
00
1
1
1
X
01
1
1
0
X
11
X
X
0
0
10
0
0
X
X
Essential: c', a' + d'
Nonessential: a' + b
'
5.50 (e) f = (c')(a' + d')
56
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 6 Solutions
6.2 (a)
1
5
9
12
7
11
14
15
Unit 6 Problem Solutions
0001
0101
1001
1100
0111
1011
1110
1111
0-01
-001
01-1
10-1
11-0
-111
1-11
111-
1, 5
1, 9
5, 7
9, 11
12, 14
7, 15
11, 15
14, 15
6.2 (b)
a'c'd
b'c'd
a'bd
ab'd
abd'
bcd
acd
abc
0, 1
000- a'b'c' 1, 3, 5, 7
0, 8
-000 b'c'd' 1, 5, 3, 7
1, 3
6, 7, 14, 15
00-1
1, 5
6, 14, 7, 15
0-01
8, 10 10-0 ab'd'
3, 7
0-11
5, 7
01-1
6, 7
011-
6, 14 -110
10, 14 1-10 acd'
7, 15 -111
14, 15 111-
Prime implicants: a'b'c', b'c'd', ab'd', acd', a'd, bc
0
1
8
3
5
6
10
7
14
15
Prime implicants: a'c'd, b'c'd, a'bd, ab'd,
abd', bcd, acd, abc
6.3 (a)
1
1, 5
1, 9
5, 7
9, 11
12, 14
7, 15
11, 15
14, 15
a'c'd
b'c'd
a'bd
ab'd
abd'
bcd
acd
abc
5
0--1 a'd
0--1
-11- bc
-11-
9 11 12 14 15
× ×
×
×
× ×
× ×
f = abd' + a'c'd + ab'd + bcd
f = abd' + b'c'd + a'bd + acd
× ×
×
×
×
× ×
×
6.3 (b)
0
1, 3, 5, 7
6, 7, 14, 15
0, 1
0, 8
8, 10
10, 14
7
0000
0001
1000
0011
0101
0110
1010
0111
1110
1111
a'd
bc
a'b'c'
b'c'd'
ab'd'
acd'
1
3
5
× × ×
× ×
×
6
7
8
×
× ×
10 14 15
× ×
f = a'd + bc + a'b'c' + ab'd'
f = a'd + bc + b'c'd' + ab'd'
f = a'd + bc + b'c'd' + acd'
×
× ×
× ×
57
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 6 Solutions
6.4
1
2
4
3
5
6
9
10
12
7
13
15
0001
0010
0100
0011
0101
0110
1001
1010
1100
0111
1101
1111
1, 3
1, 5
1, 9
2, 3
2, 6
2, 10
4, 5
4, 6
4, 12
3, 7
5, 7
5, 13
6, 7
9, 13
12, 13
7, 15
13, 15
13, 15
00-1
0-01
-001
001-
0-10
-010 b'cd'
010-
01-0
-100
0-11
01-1
-101
011-
1-01
110-
-111
11-1
11-1
1
6.5
1, 3, 5, 7
1, 5, 9, 13
2, 3, 6, 7
4, 5, 6, 7
4, 5, 12, 13
5, 7, 13, 15
2, 10
a'd
c'd
a'c
a'b
bc'
bd
b'cd'
1
4
8
5
9
12
7
11
13
14
15
1, 5
1, 9
4, 5
4, 12
8, 9
8, 12
5, 7
5, 13
9, 11
9, 13
12, 13
12, 14
7, 15
11, 15
13, 15
14, 15
0001
0100
1000
0101
1001
1100
0111
1011
1101
1110
1111
3
× ×
×
×
4
1, 3, 5, 7
1, 5, 3, 7
1, 5, 9, 13
1, 9, 5, 13
2, 3, 6, 7
2, 6, 3, 7
4, 5, 6, 7
4, 5, 12, 13
4, 6, 5, 7
4, 12, 5, 13
5, 7, 13, 15
5, 13, 7, 15
5
6
7
×
×
0--1
0--1
--01
--01
0-10-101--1001--10-1-1
-1-1
a'd
c'd
a'c
a'b
bc'
Prime implicants: b'cd', a'd, c'd, a'c, a'b, bc',
bd
bd
10 12 13
×
×
× ×
× × × ×
× ×
×
×
× ×
×
f = bc' + b'cd' + a'd + a'b
f = bc' + b'cd' + c'd + a'c
f = bc' + b'cd' + a'c + a'd
×
0-01
-001
010-
-100
100-
1-00
01-1
-101
10-1
1-01
110-
11-0
-111
1-11
11-1
111-
1, 5, 9, 13
1, 9, 5, 13
4, 5, 12, 13
4, 12, 5, 13
5, 7, 13, 15
5, 13, 7, 15
8, 9, 12, 13
8, 12, 9, 13
9, 11, 13, 15
9, 13, 11, 15
12, 13, 14, 15
12, 14, 13, 15
Prime implicants: C'D, BC', BD, AC', AD, AB
58
--01
--01
-10-10-1-1
-1-1
1-01-01--1
1--1
11-11--
C'D
BC'
BD
AC'
AD
AB
9 12 13 15
P1
P2
P3
P4
P5
P6
(1, 5, 9, 13)
(4, 5, 12, 13)
(5, 7, 13, 15)
(8, 9, 12, 13)
(9, 11, 13, 15)
(12, 13, 14, 15)
C'D
BC'
BD
AC'
AD
AB
×
×
× ×
× ×
× × ×
×
× ×
× × ×
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 6 Solutions
6.5
(cont.)
(P1 + P4 + P5) (P2 + P4 + P6) (P1 + P2 + P3 + P4 + P5 + P6) (P3 + P5 + P6)
= (P4 + P1P2 + P1P6 + P2P5 + P5P6) (P3 + P5 + P6)
= P3P4 + P4P5 + P4P6 + P1P2P3 + P1P2P5 + P1P2P6 + P1P3P6
+ P1P5P6 + P1P6 + P2P3P5 + P2P5 + P2P5P6 + P3P5P6 + P5P6 = 1
F = (AC' + BD) or (AD + BC') or (AD + AC') or (AB + AD) or (AB + AC') or (AB + C'D)
P4
6.6 (a)
C D
P3
A B
00
P5
01
00
1
1
01
E
1
11
1
10
X
11
P2
10
P5
C D
A B
00
A B
00
C D
00
E
C D
A B
00
00
X
X
1
X
11
1
X
11
X
10
X
10
X
C D
G
1
X
01
X
1
X
1
11
1
X
E
X
10
X
1
X
C D
E = 1; F = G = 0
A B
00 01 11 10
X
01
X
1
11
X
X
X
X
10
X
1
X
X
MS0 = A'B' + A B D
10
X
00
1
X
11
MS1 = A'C' + ACD
MS1 = A'C' + BCD
MS0 = A'C'D' + A'B + A B'D
E=F=G=0
A B
00 01 11 10
P1
E=1
01
X
1
10
10
01
00
11
11
P6
1
E
X
E=0
01
P4
1
10
01
P6
01
F
1
P5
1
11
00
01
1
P6
1
F = MS0 + EMS1 = A'B + A'C'D' +
AB'D + E (A'C' + ACD)
or E (A'C' + BCD)
6.6 (b)
P4
1
X
X
MS1 = B'C' + A'C
MS1 = B'C' + B C
C D
6.7 (a)
0
4
3
5
9
7
11
13
A B
00
F = 1; E = G = 0
01
11
11
10
X
01
X
1
X
X
11
X
X
X
X
10
X
1
01
X
X
11
X
10
X
0000
0100
0011
0101
1001
0111
1011
1101
01
X
X
MS2 = A B
C D
G = 1; E = F = 0
00
00
X
10
A B
00
0, 4
4, 5
3, 7
3, 11
5, 7
5, 13
9, 11
9, 13
X
Z = A'B' + ABD + E (B'C' + A'C) +
F (AB) + G (A'D)
X
MS3 = A'D or C'D or BD
0-00
0100-11
-011
01-1
-101
10-1
1-01
a'c'd'
a'bc'
a'cd
b'cd
a'bd
bc'd
ab'd
ac'd
Prime implicants: a'c'd', a'bc', a'cd,
b'cd, a'bd, bc'd, ab'd, ac'd
59
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 6 Solutions
6.7 (b)
2
4
5
6
9
10
12
11
13
15
6.8 (a)
0010
0100
0101
0110
1001
1010
1100
1011
1101
1111
0-10 a'cd'
-010 b'cd'
010-
01-0 a'bd'
-100
-101
10-1
1-01
101- ab'c
110-
1-11
11-1
2, 6
2, 10
4, 5
4, 6
4, 12
5, 13
9, 11
9, 13
10, 11
12, 13
11, 15
13, 15
-10- bc'
-101--1 ad
1--1
4, 5, 12, 13
4, 12, 5, 13
9, 11, 13, 15
9, 13, 11, 15
2
2, 6
2, 10
4, 6
10, 11
4, 5, 12, 13
9, 11, 13, 15
6.9 (a)
1
2
4
3
9
10
12
7
11
13
14
15
a'cd'
b'cd'
a'bd'
ab'c
bc'
ad
0001
0010
0100
0011
1001
1010
1100
0111
1011
1101
1110
1111
1, 3
1, 9
2, 3
2, 10
4, 12
3, 7
3, 11
9, 11
9, 13
10, 11
10, 14
12, 13
12, 14
7, 15
11, 15
13, 15
14, 15
4
bc'd'
b'd
b'c
cd
ad
ac
ab
6
×
5
7
9
11 13
×
× ×
×
×
×
×
× ×
×
×
× ×
×
×
f = bc' + ad + a'cd' + b'cd'
f = bc' + ad + a'cd' + ab'c
f = bc' + ad + a'bd' + b'cd'
×
×
a'c'd'
a'bc'
a'cd
b'cd
a'bd
bc'd
ab'd
ac'd
4
9 10 11 12 13 15
×
×
× ×
× ×
×
00-1
-001
001-
-010
-100 bc'd'
0-11
-011
10-1
1-01
101-
1-10
110-
11-0
-111
1-11
11-1
111-
2
4, 12
1, 3, 9, 11
2, 3, 10, 11
3, 7, 11, 15
9, 11, 13, 15
10, 11, 14, 15
12, 13, 14, 15
5
×
×
0, 4
4, 5
3, 7
3, 11
5, 7
5, 13
9, 11
9, 13
3
f = a'c'd' + a'cd + ab'd + bc'd
f = a'c'd' + ac'd + a'bd + b'cd
Prime implicants: ad, bc', a'cd', b'cd', a'bd', ab'c
6.8 (b)
0
3
4
×
1, 3, 9, 11
1, 9, 3, 11
2, 3, 10, 11
2, 10, 3, 11
3, 7, 11, 15
3, 11, 7, 15
9, 11, 13, 15
9, 13, 11, 15
10, 11, 14, 15
10, 14, 11, 15
12, 13, 14, 15
12, 14, 13, 15
7
-0-1
-0-1
-01-01--11
--11
1--1
1--1
1-11-111-11--
b'd
b'c
cd
ad
Prime implicants: bc'd', b'd, b'c, cd, ad, ac, ab
ac
ab
9 11 12 13 14
×
×
× ×
×
× ×
× ×
×
× ×
×
×
×
× ×
×
60
f = b'c + bc'd' + cd + b'd + ab
f = b'c + bc'd' + cd + ad + ab
f = b'c + bc'd' + cd + ad + ac
×
×
× × ×
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 6 Solutions
6.9 (b)
0
1
8
5
6
9
10
12
7
11
13
0000
0001
1000
0101
0110
1001
1010
1100
0111
1011
1101
0, 1
0, 8
1, 5
1, 9
8, 9
8, 10
8, 12
5, 7
5, 13
6, 7
9, 11
9, 13
10, 11
12, 13
0
5, 7
6, 7
0, 1, 8, 9
1, 5, 9, 13
8, 9, 10, 11
8, 9, 12, 13
6.9 (c)
6.11
a'bd
a'bc
b'c'
c'd
ab'
ac'
1
5
00000
00010
00100
01000
10000
00110
01001
01010
01100
10010
00111
01011
01101
01110
10011
10101
11101
11110
0, 2
0, 4
0, 8
0, 16
2, 6
2, 10
2, 18
4, 6
4, 12
8, 9
8, 10
8, 12
16, 18
6, 7
6, 14
9, 11
9, 13
10, 11
10, 14
12, 13
12, 14
18, 19
13, 29
14, 30
21, 29
6
8
9
-00-00--01
--01
10-10-1-01-0-
b'c'
c'd
ab'
Prime implicants: a'bd, a'bc, b'c', c'd, ab', ac'
ac'
11 13
×
f = a'bc + b'c' + ab' + c'd
×
× ×
× ×
f = a'b + bc + ab'c' + bd + cd
f = a'b + bc + ab'c' + ad + cd
f = a'b + bc + ab'c' + ad + a'c
0
2
4
8
16
6
9
10
12
18
7
11
13
14
19
21
29
30
0, 1, 8, 9
0, 8, 1, 9
1, 5, 9, 13
1, 9, 5, 13
8, 9, 10, 11
8, 10, 9, 11
8, 9, 12, 13
8, 12, 9, 13
000-
-000
0-01
-001
100-
10-0
1-00
01-1 a'bd
-101
011- a'bc
10-1
1-01
101-
110-
000-0
00-00
0-000
-0000
00-10
0-010
-0010
001-0
0-100
0100-
010-0
01-00
100-0
0011- A'B'CD
0-110
010-1
01-01
0101-
01-10
0110-
011-0
1001- AB'C'D
-1101 BCD'E
-1110 BCDE'
1-101 ACD'E
× ×
×
×
× × ×
× ×
×
6.10
Prime implicants: abc', bc'd, a'bd, b'cd, a'c, a'b'd'
f = abc' + b'cd + a'c + a'b'd' + a'bd
f = abc' + b'cd + a'c + a'b'd' + bc'd
0, 2, 4, 6
0, 2, 8, 10
0, 2, 16, 18
0, 4, 2, 6
0, 4, 8, 12
0, 8, 2, 10
0, 8, 4, 12
0, 16, 2, 18
2, 6, 10, 14
2, 10, 6, 14
4, 6, 12, 14
4, 12, 6, 14
8, 9, 10, 11
8, 9, 12, 13
8, 10, 9, 11
8, 10, 12, 14
8, 12, 9, 13
8, 12, 10, 14
61
0, 2, 4, 6, 8, 10, 12, 14 0---0 A'E'
00--0
0, 2, 8, 10, 4, 6, 12, 14 0---0
0-0-0
-00-0 B'C'E' 0, 4, 8, 12, 2, 6, 10, 14 0---0
00--0
0--00
0-0-0
0--00
-00-0
0--10
0--10
0-1-0
0-1-0
010-- A'BC'
01-0- A'BD'
010-01--0
01-001--0
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 6 Solutions
6.11
cont.
0
6, 7
18, 19
13, 29
14, 30
21, 29
0, 2, 16, 18
8, 9, 10, 11
8, 9, 12, 13
0, 2, 4, 6, 8, 10, 12, 14
A'B'CD
AB'C'D
BCD'E
BCDE'
ACD'E
B'C'E'
A'BC'
A'BD'
A'E'
2
6
7
8 10 11 12 13 14 16 18 19 29 30
× ×
× ×
×
×
×
×
×
× ×
× ×
× × ×
× × ×
×
× ×
× ×
×
×
F = BCDE' + AB'C'D + B'C'E' + A'BC' + A'B'CD + BCD'E + A'E'
6.12 (a)
0
1
2
4
8
3
9
10
11
19
21
22
28
23
27
29
30
00000
00001
00010
00100
01000
00011
01001
01010
01011
10011
10101
10110
11100
10111
11011
11101
11110
0, 1
0, 2
0, 4
0, 8
1, 3
1, 9
2, 3
2, 10
8, 9
8, 10
3, 11
3, 19
9, 11
10, 11
11, 27
19, 23
19, 27
21, 23
21, 29
22, 23
22, 30
28, 29
28, 30
0000-
000-0
00-00*
0-000
000-1
0-001
0001-
0-010
0100-
010-0
0-011
-0011
010-1
0101-
-1011
10-11*
1-011
101-1*
1-101*
1011-*
1-110*
1110-*
111-0*
0, 1, 2, 3
0, 1, 8, 9
0, 2, 8, 10
1, 3, 9, 11
2, 3, 10, 11
8, 9, 10, 11
3, 11, 19, 27
000--
0-00-
0-0-0
0-0-1
0-01-
010--
--011*
0, 1, 2, 3, 8, 9, 10, 11
0-0--*
Prime Implicants: A'B'D'E', AB'DE, AB'CE,
ACD'E, AB'CD, ACDE', ABCD'. ABCE',
C'DE, A'C'
1
2
4
5
6
7
9
12 13 15 17 20 22 25 28 30
(0,4)
A'B'D'E'
(19, 23)
AB'DE
(21, 23)
AB'CE
X
(21, 29)
ACD'E
X
(22,23)
AB'CD
X
(22, 30)
ACDE'
X
(28, 29)
ABCD'
X
(28, 30)
ABCE'
X
(3, 11, 19, 27)
C'DE
(0, 1, 2, 3, 8, 9, 10, 11) A'C'
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
f = A'C' + C'DE + A'B'D'E' + AB'CE + ACDE' + ABCD'
f = A'C' + C'DE + A'B'D'E' + ACD'E + AB'CD + ABCE'
62
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
X
X
Unit 6 Solutions
6.12 (b)
0
1
2
4
8
17
18
20
11
13
14
21
26
15
27
30
31
00000
00001
00010
00100
01000
10001
10010
10100
01011
01101
10110
10101
11010
01111
11011
11110
11111
0, 1
0, 2
0, 4
0, 8
1, 17
2, 18
4, 20
17, 21
18, 26
20, 21
11, 15
11, 27
13, 15
14, 15
14, 30
26, 27
26, 30
15, 31
27, 31
30, 31
0000-*
000-0*
00-00*
0-000*
-0001*
-0010*
-0100*
10-01*
1-010*
1010-*
01-11
-1011
011-1*
0111-
-1110
1101-
11-10
-1111
11-11
1111-
11, 15, 27, 31
14, 15, 30, 31
26, 27, 30, 31
Prime Implicants: A'B'D'E', AB'DE, AB'CE,
ACD'E, AB'CD, ACDE', ABCD'. ABCE',
C'DE, A'C'
-1-11*
-111-*
11-1-*
0
1
Q (0, 1)
A'B'C'D'
R (0, 2)
A'B'C'E'
X
S
A'B'D'E'
X
(0, 8)
A'C'D'E'
X
(1, 17)
B'C'D'E
U (2, 18)
B'C'DE'
V (4, 20)
B'CD'E'
W (17, 21)
AB'D'E
X (18,26)
AC'DE'
Y
(20,21)
AB'CD'
(13, 15)
A'BCE
T
(0, 4)
(11, 15, 27, 31)
BDE
(14, 15, 30, 31)
BCD
Z (26, 27, 30, 31)
ABD
2
4
8
11 13 14 15 17 18 20 21 26 27 30 31
X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Essential prime implicants: A'C'D'E', BDE, A'BCE, BCD
Petrick’s Method for remaining minterms: (Q+T)(R+U)(S+V)(T+W)(U+X)(V+Y)(W+Y)(X+Z)
= (QW+T)(RX+U)(SY+V)(W+Y)(X+Z) = (QW+TW+TY)(RX+UX+UZ)(SY+V)
= (QSWY+STY+QVW+TVW+TVY)(RX+UX+UZ) There are four minimal choices from the first parenthesis. In the
second parenthesis only UZ is minimal since Z has fewer literals than the other two PI’s. The minimal solutions are
(STY+QVW+TVW+TVY)(UZ)
6.12 (b) f = BCD + A'BCE + BDE + A'C'D'E' + ABD + B'C'DE' + AB'CD' + B'C'D'E + A'B'D'E'
(cont.) f = BCD + A'BCE + BDE + A'C'D'E' + ABD + B'C'D E' + AB'D'E + B'CD'E' + A'B'C'D'
f = BCD + A'BCE + BDE + A'C'D'E' + ABD + B'C'D E' + AB'D'E + B'CD'E' + B'C'D'E
f = BCD + A'BCE + BDE + A'C'D'E' + ABD + B'C'D E' + AB'C D' + B'CD'E' + B'C'D'E
6.13 (a)
16
5
6
12
17
18
20
24
7
13
14
25
26
15
31
10000
00101
00110
01100
10001
10010
10100
11000
00111
01101
01110
11001
11010
01111
11111
16, 17
16, 18
16, 20
16, 24
5, 7
5, 13
6, 7
6, 14
12, 13
12, 14
17, 25
18, 26
24, 25
24, 26
7, 15
13, 15
14, 15
15, 31
1000-
100-0
10-00*
1-000
001-0
0-101
0011-
0-110
0110-
011-0
1-001
1-010
1100-
110-0
0-111
011-1
0111-
-1111*
16, 17, 24, 25
16, 18, 24, 26
5, 7, 13, 15
6, 7 14, 15
12, 13, 14, 15
1-00-*
1-0-0*
0-1-1*
0-11-*
011--*
Prime implicants of f ': AB'D'E', BCDE, AC'D',
AC'E', A'CE, A'CD, A'BC
5
(16, 20)
7
12 13 14 15 16 17 18 20 24 25 26 31
BCDE
(16, 17, 24, 25)
AC'D'
(16, 18, 24, 26)
AC'E'
(5, 7, 13, 15)
A'CE
(6, 7, 14, 15)
A'CD
A'BC
X
X
AB'D'E'
(15, 31)
(12, 13, 14, 15)
6
X
X
X
X
X
X
X
X
X
X
X X
X
X
X
X
X
X
X
X X
X
f'(A, B, C, D, E)= AB'D'E' + BCDE + AC'D' + AC'E' + A'CE + A'CD + A'BC
f(A, B, C, D, E)= (A' + B + D + E)(B' + C' + D' + E')(A' + C + D)(A' + C + E)(A + C' + E')(A + C' + D')(A + B' + C')
63
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 6 Solutions
6.13 (b)
16
3
5
6
9
10
12
24
7
19
22
25
28
23
29
10000
00011
00101
00110
01001
01010*
01100
11000
00111
10011
10110
11001
11100
10111
11101
16, 24
3, 7
3, 19
5, 7
6, 7
6, 22
9, 25
12, 28
24, 25
24, 28
7, 23
19, 23
22, 23
25, 29
28, 29
1-000*
00-11
-0011
001-1*
0011-
-0110
-1001*
-1100*
1100-
11-00
-0111
10-11
1011-
11-01
1110-
3, 7, 19, 23
6, 7, 22, 23
24, 25, 28, 29
Prime implicants of f ': A'BC'DE', AC'D'E', A'B'CE,
BC'D'E, BCD'E', B'DE, B'CD, ABD'
-0-11*
-011-*
11-0-*
3
(10)
A'BC'DE'
(16, 24)
AC'D'E'
(5, 7)
A'B'CE
(9, 25)
BC'D'E
(12, 28)
BCD'E'
(3, 7, 19, 23)
B'DE
(6, 7, 22, 23)
B'CD
5
6
7
9
10 12 16 19 22 23 24 25 28 29
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(24, 25, 28, 29) ABD'
X
X
X
X
f' = A'BC'DE' + AC'D'E' + A'B'CE + BC'D'E + BCD'E' + B'DE + B'CD + ABD'
f = (A'+B'+D)(A'+C + D+E )(B'+C'+D+E )(B'+C+D+ E')(B+C'+D')(A+B+C'+E')(B+D'+ E')(A+B'+C+D'+E)
6.14 (a)
6.14 (b)
1
4
8
3
5
6
9
10
12
13
14
15
0001
0100
1000
0011
0101
0110
1001
1010
1100
1101
1110
1111
1, 3
1, 5
1, 9
4, 5
4, 6
4, 12
8, 9
8, 10
8, 12
5, 13
6, 14
9, 13
10, 14
12, 13
12, 14
13, 15
14, 15
00-1*
0-01
-001
010-
01-0
-100
100-
10-0
1-00
-101
-110
1-01
1-10
110-
11-0
11-1
111-
1, 5, 9, 13
4, 5, 12, 13
4, 6, 12, 14
8, 9, 12, 13
8, 10, 12, 14
12, 13, 14, 15
--01*
-10-*
-1-0*
1-0-*
1--0*
11--*
Prime implicants: A'B'D, A B, A C', C'D, A D',
B D', B C'
1
(1, 3)
3
A'B'D
X X
(1, 5, 9, 13)
C'D
X
(4, 5, 12, 13)
BC'
(4, 6, 12, 14)
BD'
5
6
8
12 14 15
X
X
X
X
X
X
(8, 9, 12, 13)
AC'
X
(8, 10, 12, 14)
AD'
X
(12, 13, 14, 15)
9
X
X
X
AB
X
X
X
X
X
Essential Prime Implicants: AB, BD', A'B'D
f = A B + B D' + A'B'D + C'D + A D'
f = A B + B D' + A'B'D + A C' + C'D
f = A B + B D' + A'B'D + A C' + B C'
0 0000
0, 2
00-0*
2 0010
0, 4
0-00*
4 0100
2, 10
-010*
10 1010
10, 11 101-*
7 0111*
11 1011
13 1101*
Prime Implicants of f ': A'BCD, A'B'D', ABC'D,
AB'C, B'CD', A'C'D'
0
(7)
2
7
11
8
9
12 14 15
X
A'BCD
(13)
ABC'D
(0, 2)
A'B'D'
X
(0, 4)
A'C'D'
X
(2, 10)
B'CD'
(10, 11)
AB'C
X
X
X
Essential Prime Implicants: AB'C, A'BCD
f ' = AB'C + A'BCD + A'B'D'
64
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 6 Solutions
6.15 (a)
6.15 (b)
1
2
4
5
6
9
12
17
20
7
13
22
25
28
15
30
0
8
16
3
10
18
24
11
14
19
21
26
23
27
29
31
00001
00010
00100
00101
00110
01001
01100
10001
10100
00111
01101
10110
11001
11100
01111
11110
00000
01000
10000
00011
01010
10010
11000
01011
01110
10011
10101
11010
10111
11011
11101
11111
1, 5
1, 9
1, 17
2, 6
4, 5
4, 6
4, 12
4, 20
5, 7
5, 13
6, 7
6, 22
9, 13
9, 25
12, 13
12, 28
17, 25
20, 22
20, 28
7, 15
13, 15
22, 30
28, 30
00-01
0-001
-0001
00-10*
0010-
001-0
0-100
-0100
001-1
0-101
0011-
-0110
01-01
-1001
0110-
-1100
1-001
101-0
1-100
0-111
011-1
1-110
111-0
1, 5, 9, 13
1, 9, 17, 25
4, 5, 6, 7
4, 5, 12, 13
4, 6, 20, 22
4, 12, 20, 28
5, 7, 13, 15
20, 22, 28, 30
0, 8
0,16
8, 10
8, 24
16, 18
16, 24
3, 11
3, 19
10, 11
10, 14
10, 26
18, 19
18, 26
24, 26
11, 27
19, 23
19, 27
21, 23
21, 29
26, 27
23, 31
27, 31
29, 31
0-000
-0000
010-0
-1000
100-0
1-000
0-011
-0011
0101-
01-10*
-1010
1001-
1-010
110-0
-1011
10-11
1-011
101-1
1-101
1101-
1-111
11-11
111-1
0, 8, 16, 24
8, 10, 24, 26
16, 18, 24, 26
3, 11, 19, 27
10, 11, 26, 27
18, 19, 26, 27
19, 23, 27, 31
21, 23, 29, 31
Prime Implicants: a c e', a'c e, c d'e', a'c d', a'b'c,
b'c e', a'b'd e', c'd'e, a'd'e
0--01*
--001*
001--*
0-10-*
-01-0*
--100*
0-1-1*
1-1-0*
1
2
4
5
6
(2, 6)
a'b'de'
(1, 5, 9, 13)
a'd'e
X
(1, 9, 17, 25)
c'd'e
X
(4, 5, 6, 7)
a'b'c
X
X X
(4, 5, 12, 13)
a'cd'
X
X
(4, 6, 20, 22)
b'ce'
X
(4, 12, 20, 28)
cd'e'
X
(5, 7, 13, 15)
a'ce
(20, 22, 28, 30)
ace'
X
7
9
12 13 15 17 20 22 25 28 30
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X X
Essential Prime Implicants: a c e', c'd'e, a'c e, a'b'd e'
f = a c e' + c'd'e + a'c e + a'b'd e' + a'c d'
f = a c e' + c'd'e + a'c e + a'b'd e' + c d'e'
Prime Implicants of f ': ace, ade, ac'd, ac'e', bc'd,
a'bde', bc'e', c'de, c'd'e'
--000*
-10-0*
1-0-0*
--011*
-101-*
1-01-*
1--11*
1-1-1*
0
(10, 14)
a'bde'
(0, 8, 16, 24)
c'd'e'
(8, 10, 24, 26)
bc'e'
(16, 18, 24, 26)
ac'e'
(3, 11, 19, 27)
c'de
(10, 11, 26, 27)
bc'd
(18, 19, 26, 27)
ac'd
(19, 23, 27, 31)
ade
(21, 23, 29, 31)
ace
3
8
10 11 14 16 18 19 21 23 24 26 27 29 31
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X X
X
X
X
X
X
X
X
X
X
X
Essential Prime Implicants: ace, a'bde', c'de, c'd'e'
f ' = ace + a'bde' + c'de + c'd'e' + ac'e'
f ' = ace + a'bde' + c'de + c'd'e' + ac'd
65
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
X
X X
Unit 6 Solutions
6.16
1
2
16
32
3
17
18
48
19
26
28
15
29
30
39
63
000001
000010
010000
100000
000011
010001
010010
110000
010011
011010
011100
001111 A'B'CDEF
011101
011110
100111 AB'C'DEF
111111 ABCDEF
1, 3
1, 17
2, 3
2, 18
16, 17
16, 18
16, 48
32, 48
3, 19
17, 19
18, 19
18, 26
26, 30
28, 29
28, 30
1
15
39
63
16, 48
32, 48
18, 26
26, 30
28, 29
28, 30
1, 3, 17, 19
2, 3, 18, 19
16, 17, 18, 19
A'B'CDEF
AB'C'DEF
ABCDEF
BC'D'E'F'
AC'D'E'F'
A'BD'EF'
A'BCEF'
A'BCDE'
A'BCDF'
A'C'D'F
A'C'D'E
A'BC'D'
0000-1
0-0001
00001-
0-0010
01000-
0100-0
-10000 BC'D'E'F'
1-0000 AC'D'E'F'
0-0011
0100-1
01001-
01-010 A'BD'EF'
011-10 A'BCEF'
01110- A'BCDE'
0111-0 A'BCDF'
2
1, 3, 17, 19
1, 17, 3, 19
2, 3, 18, 19
2, 18, 3, 19
16, 17, 18, 19
16, 18, 17, 19
0-00-1 A'C'D'F
0-00-1
0-001- A'C'D'E
0-0010100-- A'BC'D'
0100--
3 16 17 18 19 26 32 39 48 63
×
×
×
×
×
×
×
× ×
×
×
×
×
×
×
× ×
× × × ×
6.16 (a) G = AB'C'DEF + ABCDEF + A'C'D'F + A'C'D'E
+ AC'D'E'F' + A'BC'D' + A'BD'EF'
G = AB'C'DEF + ABCDEF + A'C'D'F + A'C'D'E
+ AC'D'E'F' + A'BC'D' + A'BCEF'
6.16 (b)
6.16 (c) Essential prime implicants are underlined in 6.16 (a).
If there were no don't cares, prime implicants 15,
(26, 30), (28, 29), and (28, 30) are omitted. There
is only one minimum solution. Same as (a),
except delete the second equation.
6.17 (a)
1 000001
12 001100*
33 100001
7 000111
11 001011
35 100011
50 110010
15 001111
30 011110*
43 101011
54 110110
58 111010
60 111100*
47 101111
59 111011
1, 33
33, 35
7, 15
11, 15
11, 43
35, 43
50, 54
50, 58
15, 47
43, 47
43, 59
58, 59
-00001*
1000-1*
00-111*
001-11
-01011
10-011*
110-10*
11-010*
-01111
101-11
1-1011*
11101-*
11, 15, 43, 47
-01-11*
Prime Implicants: A'B'CDE'F', A'BCDEF', ABCDE'F',
B'C'D'E'F, AB'C'D'F, A'B'DEF, AB'D'EF, ABC'EF',
ABD'EF', ACD'EF, ABCD'E, B'CEF
66
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 6 Solutions
6.17 (a)
(cont.)
1
(12)
A'B'CDE'F'
(30)
A'BCDEF'
(60)
ABCDE'F'
(1, 33)
B'C'D'E'F
(33, 35)
AB'C'D'F
(7, 15)
A'B'DEF
(35, 43)
AB'D'EF
(50, 54)
ABC'EF'
(50, 58)
ABD'EF'
(43, 59)
ACD'EF
(58, 59)
ABCD'E
11 12 15 33 35 43 47 59 60
7
X
X
X
X
X
X
X
X
X
X
X
X
X
6.17 (b) Prime Implicants of G': AB'CE', AB'DE', AB'F',
BDF, BE'F, BD'E', CE'F, CD'E', DE'F, C'DE',
A'C'D'E, AC'D, D'F', C'F', BC', A'B, EF', BDE
Essential Prime Implicants of G': BC', AC'D, A'B,
EF', A'C'D'E
G' = BC' + AC'D + A'B + EF' + A'C'D'E + AB'F'
+ BDF + CD'E' + DE'F + C'F'
G' = BC' + AC'D + A'B + EF' + A'C'D'E + AB'F'
+ BDF + CE'F + C'DE' + D'F'
G' = BC' + AC'D + A'B + EF' + A'C'D'E + AB'F'
+ CD'E' + DE'F + C'F' + BDE
G' = BC' + AC'D + A'B + EF' + A'C'D'E + AB'F'
+ CE'F + C'DE' + D'F' + BDE
1
1
X
6
X
X
X
X
X
X
X
X
X
X
X
X
6.18
(a) -0-1 = (1, 3, 9, 11), -01- = (2, 3, 10, 11),
--11 = (3, 7, 11, 15), 1--1 = (9, 11, 13, 15)
(b) maxterms = 0, 4, 5, 6, 8, 12, 14
(c) don't cares = 1, 10, 15
(d) B'C, CD, AD
Using Petrick’s method:
(C1 + C3)(C2 + C3 + C5)(C1 + C4)(C1 + C5)
(C2 + C3)(C2 + C3 + C4)(C3 + C4)
= (C1C2 + C1C5 + C3)(C1 + C4C5)(C2C4 + C3)
= (C1C2 + C1C5 + C1C3 + C3C4C5)(C2C4 + C3)
= C1C2C4 + C1C3 + C3C4C5
7
X
4
5
Package
3 4 5
X
X
2
Cart 3
2
G = A'B'CDE'F' + ABCDE'F' + B'C'D'E'F +
A'B'DEF + B'CEF + ACD'EF + AB'C'D'F
G = A'B'CDE'F' + ABCDE'F' + B'C'D'E'F +
A'B'DEF + B'CEF + ACD'EF + AB'D'EF
G = A'B'CDE'F' + ABCDE'F' + B'C'D'E'F +
A'B'DEF + B'CEF + ABCD'E + AB'C'D'F
G = A'B'CDE'F' + ABCDE'F' + B'C'D'E'F +
A'B'DEF + B'CEF + ABCD'E + AB'D'EF
X
X
(11, 15, 43, 47) B'CEF
6.19
X
Essential Prime Implicants: A'B'CDE'F',
ABCDE'F', B'C'D'E'F, A'B'DEF, B'CEF
Each product term specifies a nonredundant
combination of carts that can be used to deliver the
packages. The minimal cart solution, using carts C1
and C3, costs $6. However, using the three carts C1,
C2 and C4 costs only $5 so it is the minimal cost
solution desired by the stockroom manager.
X
67
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 6 Solutions
6.20
24
28
70
88
39
86
92
102
105
47
118
0011000
0011100
1000110
1011000
0100111
1010110
1011100
1100110
1101001*
0101111
1110110
24, 28
24, 88
28, 92
70, 86
70, 102
88, 92
39, 47
86, 118
102, 118
0011-00 24, 28, 88, 92*
-011000 70, 86, 102, 118*
-011100
10-0110
1-00110
1011-00
010-111*
1-10110
11-0110
-011-00*
1--0110*
(105) = (1101001) = ABC'DE'F'G
(39, 47) = (010-111) = A'BC'EFG
(24, 28, 88, 92) = (-011-00) = B'CDF'G'
(70, 86, 102, 118) = (1--0110) = AD'EFG'
6.21
(a) r = ∏ M(1, 2, 3, 12) = (w + x + y + z′)(w + x + y′ + z)(w + x + y′ + z′)(w′ + x′ + y + z).
(b) prime implicant A: (0, 4) = w′y′z′
prime implicant C: (6, 7, 14, 15) = xy
prime implicant D: (8, 9, 10, 11) = wx′
(c) Using Petrick’s method
(A + G)(A + H)(B + H)(C + H)(B + C + H)(D + G)(D + F)(D + E)(D + E + F)(B + F)
(C + E)(B + C + E + F) = (A + G)(ABC + H)(D + EFG)(B + F)(C + E)
= (ABC + AH + GH)(BD + DF + EFG)(C + E)
= (ABC + AH + GH)(BCD + CDF + BDE + DEF + EFG)
= (ABCD + EFGH + other products with more than 4 literals)
6.22
(a) A minimum solution must cover (have an X in) the covered column, but then the minimum solution must cover
the covering column.
(b) If there is a minimal solution containing the covered row (P1 in this case), then it can be replaced by the covering
row (P3 in this case) since the covering row covers all of the columns covered by the covered row. The new
solution will be minimum provided the covering row has the same number (or fewer) of literals as the covered
row. Hence, a covered row can be removed if the covering row has the same number or fewer literals as the
covered row.
(c) After removing row P1 column 1 is only covered by row P3 so it must be included in the solution; P3 has become
(secondarily) essential.
6.23
Prime implicants: AC, AD', AB, CD, BD, A'D
Minimum solutions: (AD' + CD); (AD' + BD);
(AB + BD); (AB + CD); (AB + A'D)
6.24 (a)
CD
AB
6.24 (b)
00
01
11
00
1
1
E
01
E
1
10
CD
X
11
10
X
1
1
AB
00
01
11
00
G
X
E
01
X
1
X
11
X
10
1
10
1
E
1
X
F
Z = C'D + A'CD' + E (BC' + B'D) + F(CD') + G (A'C')
MS0
MS1
MS2
MS3
F = AC'D + BCD' + A'D' + E (A'B'C' + BD')
MS0
MS1
68
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 6 Solutions
6.25 (b) Prime implicants: A'C'D', A'B, AB'D, A'C'E, ACDE,
BCDE, B'C'DE
6.25 (a) Each minterm of the four variables A, B, C, D
expands to two minterms of the five variables
A, B, C, D, E. For example,
m4(A,B,C,D) = A'BC'D'
= A'BC'D'E' + A'BC'D'E
= m8(A,B,C,D,E) + m9(A,B,C,D,E)
BC
DE
00
00
0
11
10
11
1
A 01
1
01
1
X
1
1
6.26
10
X
1
F = A'C'D' + A'B + AB'D + A'C'E + ACDE
F = A'C'D' + A'B + AB'D + A'C'E + BCDE
1
X
1
1
1
1
1
EF
CD
00
00
A
01
1
11
1
10
X
A
01
11
10
A
1
B
1
1
A
* This square contains 1 + B, which reduces to 1.
G = C'E'F + DEF + A (D'F') + B (DF)
MS0
MS1
MS2
F = A'C'D' + A'B + A B'D + A'C'E + B C D E
F = A'C'D' + A'B + A B'D + A'C'E + A C D E
69
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 6 Solutions
70
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 7 Solutions
7.1 (a)
c d
Unit 7 Problem Solutions
a b
00
01
11
10
a b
00
01
11
10
00
0
1
0
1
1
01
0
0
0
1
0
0
11
0
1
0
0
0
1
10
0
1
0
1
00
0
1
0
1
01
0
0
0
11
0
1
10
0
1
c d
f = (a'+ b') (a + b ) (a + c + d') (b + c'+ d')
f = a b'd' + a b'c' + a'b c + a'b d'
Sum of products solution requires 5
gates, 16 inputs
f = (a'+ b') (a + b ) (b + c'+ d') (b'+ c + d')
f = (a'+ b') (a + b ) (a + c + d') (a'+ c'+ d')
f = (a'+ b') (a + b ) (b'+ c + d') (a'+ c'+ d')
Product of sums solution requires 5 gates,
14 inputs, so product of sums solution is
minimum.
7.1 (b)
Beginning with the minimum sum of products
solution, we can get
f = (a + b) (a' + b') (d' + ac' + a'c))
f = a'b (c + d') + ab' (c' + d')
3
2
5 gates, 12 inputs
3
Beginning with a minimum product of sums
solution, we can get
2
2
2
2
2
2
3
3
6 gates, 14 inputs
So sum of products solution is minimum.
7.2 (a)
7.2 (b)
AC'D + ADE' + BE' + BC' + A'D'E'
= E' (AD + B) + A'D'E' + C' (AD + B)
F = (E + FG) [A + B (C + D)]
F = (AD + B) (E' + C') + A'D'E'
2
2
2
AE + BDE + BCE + BCFG + BDFG + AFG
= AE + AFG + BE (C + D) + BFG (C + D)
3
2
2
2
2
2
2
2
2
4 levels, 6 gates, 13 inputs
4 levels, 6 gates, 12 inputs
71
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 7 Solutions
7.3
F (a, b, c, d)n = a'bd + ac'd or d (a'b + ac') = d (a + b) (a' + c')
You can obtain this equation in the product of sums form using a Karnaugh map, as shown below:
AND-OR
a'
b
d
a
c'
d
F
F = a'bd+ac'd
(F')' = [(a'bd+ac'd)']'
F
a
b'
d'
a'
c
d'
F
a'
b'
F
AB
CD
01
11
10
00
01
11
10
00
0
0
0
0
00
0
0
0
0
01
0
1
1
1
01
0
1
1
1
11
0
1
0
0
11
0
1
0
0
10
0
0
0
0
10
0
0
0
0
F = AC'D + A'BD
7.4
AB
AB
a
c
NAND-AND
a'
b'
F
F
d
(F')'=d(a'b')'(ac)'
F = (A + B)(D)(A'+ C')
F (A, B, C, D) = ∑ m(5, 10, 11, 12, 13)
CD
(F')' = (a+b'+d')'+(a'+c+d')'
(F')' = [d'+a'b'+ac]'
00
F
a'
c
d'
d'
d'
F = d(a+b)(a'+c')
(F')' = [d'+(a+b)'+(a'+c')']'
(F')' = [d(a+b)(a'+c'))']'
CD
F
AND-NOR
a
c
a
b
d
NOR-OR
a
b'
d'
(F')' = [(a+b'+d')(a'+c+d')]'
NOR-NOR
a'
c'
a
b
OR-NAND
(F')' = [(a'bd)'(ac'd)']'
OR-AND
a'
c'
NAND-NAND
a'
b
d
a
c'
d
00
01
11
10
00
0
0
1
0
01
0
1
1
0
11
0
0
0
1
10
0
0
0
1
F = ABC' + BC'D + AB'C = BC' (A + D) + AB'C
F = BC' (A + D) + AB'C
2
3
3
2
4 gates, 10 inputs
A'
D'
F = BC'D + AB'C + ABC'
72
B
C'
A
B'
C
F
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 7 Solutions
7.5
AB
CD
00
01
11
10
00
0
0
0
1
01
1
1
0
0
11
1
1
0
0
10
1
1
0
0
7.6
Z = ABC + AD + C'D'
= A (BC + D) + C'D'
B
C
D'
A
Z
C'
D'
Z = (A + C + D)(A'+ D')(A'+ C')(A'+ B')
Z = (A + C + D) (A' + B'C'D')
3
2
7.8
7.7
Z = AE + BDE + BCEF
= E (A + BD + BCF)
= E [A + B (D + CF)]
2
4 gates, 10 inputs
B
C
D
3
C'
F'
A'
A
C
D
D
Z
For the solution to 7.8, see
FLD p. 738.
7.9
ab
cd
00
01
11
B'
A
cd
10
00
cd
00
01
00
1
1
1
1
1
01
1
11
1
1
1
11
1
1
1
10
1
f1 = acd' + ad + a'b'd
7.10
ab
01
10
Z
E'
1
11
10
1
1
f2 = a'd' + a'b'd + acd'
6 gates
f1 (A, B, C, D) = ∑ m(3, 4, 6, 9, 11)
f2 (A, B, C, D) = ∑ m(2, 4, 8, 10, 11, 12)
f3 (A, B, C, D) = ∑ m(3, 6, 7, 10, 11)
ab
00
01
11
01
10
ab
cd
1
00
11
10
1
00
1
01
1
11
10
1
f1 = ab'd + b'cd + a'bd'
00
01
11
10
1
1
1
cd
ab
00
01
11
1
1
1
1
1
00
01
1
1
11
1
10
f2 = ab'c + b'cd' + bc'd' + ac'd'
f3 = ab'c + b'cd + a'bc
f2 = ab'c + b'cd' + bc'd' + ab'd'
11 gates
73
10
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 7 Solutions
7.11
cd
ab
ab
00
01
11
10
00
01
11
10
00
0
0
0
1
00
1
0
0
1
01
0
0
0
1
01
1
1
0
1
11
1
0
1
0
11
0
0
1
0
10
1
0
1
0
10
0
0
1
0
cd
F1 = (a + c)(a + b')(a'+b'+c)(a'+b+c')
F2 = (b'+c+d)(a'+b'+c)(a+c')(a'+b+c')
F2 = (a+b'+d)(a'+b'+c)(a+c')(a'+b+c')
8 gates
7.12
CD
AB
00
01
11
10
00
0
0
0
1
01
0
1
1
11
1
1
10
1
0
AB
CD
01
11
10
00
0
0
0
1
0
01
0
0
1
1
1
1
11
0
1
1
0
1
1
10
0
1
1
0
01
11
10
00
0
0
0
0
1
01
0
1
0
1
1
11
1
1
0
1
10
1
1
CD
f3 = (B'+C+D)(A+C)(B+C')
f2 = (A+B+C)(B'+C+D)(A'+C)
f1 = (A+B+C)(B'+D)
AB
00
00
9 gates
7.13 (a) Using F = (F')' from Equations (7-23(b)), p. 206:
f1 = [(A'BD)' (ABD)' (AB'C')' (B'C)']'; f2 = [C' (A'BD)']'; f3 = [(BC)' (AB'C')' (ABD)']'
A'
B
D
A
B
D
A
B'
C'
B'
C
f1
A'
B
D
C'
A
B'
C'
A
B
D
B
C
f2
f3
7.13 (b) Using F = (F')' from Equations derived in problem 7.12:
f1 = [(A + B + C)' + (B' + D)']'
f2 = [(A + B + C)' + (B' + C + D)' + (A' + C)']'
f3 = [(B' + C + D)' + (A + C)' + (B + C')']'
A
B
C
B'
D
f1
A
B
C
B'
C
D
A'
C
f2
B'
C
D
A
C
B
C'
74
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
f3
Unit 7 Solutions
7.14 (a)
f
a b
00
c d
01
11
10
00
0
1
1
1
01
0
1
0
1
11
0
1
0
1
10
1
1
0
1
7.14 (b) Beginning with the sum of products solution, we
get
f = a'b + ab' + d' (a'c + ac')
= a'b + ab' + d' (a' + c') (a + c) — 6 gates,
14 inputs
But, beginning with the product of sums solution
above, we get
f = (a + b + cd') (a' + b' + c'd') — 5 gates, 12
inputs, which is minimum
f = (a + b + c )(a + b + d')(a'+ b'+ d')(a'+ b'+ c')
f = a c'd + a'c d + a'b + a b'
a
5 gates, 16 inputs
c'
and f = a'b + ab' + b'cd' + ac'd' d'
f = a'b + ab' + a'cd' + bc'd' a'
(two other minimun solutions)c
d'
5 gates, 14 inputs minimal
c
d'
f
a'
b
a
c'
d'
a'
c
d'
a'
b
a
b'
c
d'
f
c
d
a'
b'
7.15 (b) From K-maps:
F = cd + ac + b'c' — 4 gates, 9 inputs
F = (b' + c) (a + c' + d) — 3 gates, 7 inputs,
minimal
a
b
c
c
d
F
F
a'
c'
a'
c'
7.15 (c) From K-maps:
F = ad + a'cd' + bcd
= ad + a'cd' + a'bc — 4 gates, 11 inputs
F = (a + c) ( a' + d) (a + b + d') — 4 gates, 10
inputs, minimal
a
c
a'
d
a
b
d'
F
a'
b
a
c
a
c
a'
d
a
b
d'
b
d'
a'
b'
f
7.15 (a) From K-maps:
F = a'c + bc'd + ac'd — 4 gates, 11 inputs
F = (a + b + c) (c + d) (a' + c') — 4 gates, 10
inputs, minimal
a
b
c
f
a
b
c'
d'
a
b'
c'
d'
a
b
b'
c
a
c'
d
F
7.15 (d) From K-maps:
F = a'b + ac + bd' — 4 gates, 9 inputs, minimal
F = (a + b) (a' + c + d') (a' + b + c)
= (a + b) (a' + c + d') (b + c + d) — 4 gates, 11
inputs
a'
b
F
F
a
c
F
b
d'
75
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 7 Solutions
7.16 (b) Too many variables to use a K-map; use algebra.
Add ACE by consensus, then use X + XY = X
7.16 (a) In this case, multi-level circuits do not improve the
solution. From K-maps:
F = ABC' + ACD + A'BC + A'C'D — 5 gates, 16
inputs, minimal
F = (A' + B + C) (A + C + D) (A' + C' + D)
(A + B + C') — 5 gates, 16 inputs, also
minimal
Either answer is correct.
ABCE + ABEF + ACD' + ABEG + ACDE + ACE
= ABEF + ACD' + ABEG + ACE
F = ABE (F + G) + AC (D' + E)
A
B
C'
4
F
A'
B
C
2
5 gates, 13 inputs, minimal
A
B
C'
F
A
C
D
A'
C'
D
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
3
2
A
C
D
7.17 (a)
2
G
AB CD
00 0 0
00 0 1
00 1 0
00 1 1
01 0 0
01 0 1
01 1 0
01 1 1
10 0 0
10 0 1
10 1 0
10 1 1
11 0 0
11 0 1
11 1 0
11 1 1
F
0
0
0
1
0
1
1
1
0
1
1
1
1
1
1
1
E
F
A'
B
C
E
B
A
A
C
D'
A'
C'
D
7.17 (b)
CD
AB
00
01
11
10
00
0
0
1
0
01
0
1
1
1
11
1
1
1
1
10
0
1
1
1
F = (A + C + D) (A + B + C)
(A + B + D) (B + C + D)
= (A + D + BC)(B + C + AD) or
= (A + C + BD)(B + D + AC) or
= (C + D + AB)(A + B + CD)
This solution has 5 gates, 12 inputs.
Beginning with the sum of products
requires 6 gates.
C
F = ∏ M(0, 1, 2, 4, 8)
D
B
A
76
A
B
C
D
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
F
Unit 7 Solutions
7.18 (a) F (w, x, y, z) = (x + y' + z) (x' + y + z) w
x
y'
z
x'
y
z
OR-AND
F
w
x
y'
z
x'
y
z
NOR-NOR
x'
y
z'
x
y'
z'
F
w'
AND-NOR
x'
y
z'
x
y'
z'
F
w'
NAND-AND
F
w
From Karnaugh map: F = wxy + wx'y' + wz
AND-OR
w
x
y
w
x'
y'
NAND-NAND
F
w
z
w
x
y
w
x'
y'
F
OR-NAND
w'
x'
y'
w'
x
y
w
z
F
w'
z'
NOR-OR
w'
x'
y'
w'
x
y
F
w'
z'
7.18 (b) F(a, b, c, d) = ∑ m(4, 5, 8, 9, 13)
From Kmap:
F = a'bc' + ab'c' + bc'd
F = a'bc' + ab'c' + ac'd
F = c' (a + b) (a' + b' + d)
AND-OR
a'
b
c'
a
b'
c'
b
c'
d
NAND-NAND
F
a'
b
c'
a
b'
c'
b
c'
d
F
c'
a
b
a'
b'
d
a
b'
c
a'
b
c
b'
c
d'
F
AND-NOR
NOR-NOR
OR-AND
a
b
a'
b'
d
F
NOR-OR
OR-NAND
a
b'
c
a'
b
c
b'
c
d'
a'
b'
F
c
77
a
b
d'
F
c
F
a'
b'
a
b
d'
NAND-AND
F
c'
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 7 Solutions
yz
x
0
1
00
1
1
01
1
0
11
1
1
10
0
From Kmap:
F = (y' + z) (x' + y + z')
y
z'
0
x
0
1
00
1
1
01
1
0
11
1
1
10
0
0
x'
z
( )
yz
or
z'
f
x
y'
z
f = (y'+ z)(x'+ y + z')
7.19 (b)
y
x'
y'
x'
z
y'
z'
f
x
y'
z
( )
7.19 (a)
or
y'
z'
f
y
z
f = yz + y'z' + x'y'
x'
y'
f
y
z
f = yz + y'z' + x'z
7.20 (a) Using OR and NOR gates:
cd
ab
00
01
11
10
00
0
1
0
0
01
0
1
0
0
11
1
1
1
1
10
0
1
0
0
a
b'
a
b'
f
c'
d'
f
c'
d'
f = a'b + cd
7.20 (b) Using NOR gates only:
cd
ab
00
01
11
10
00
0
1
0
0
01
0
1
0
0
11
1
1
1
1
10
0
1
0
0
f = (b + c)(b + d )(a' + c)(a' + d)
b
c
b
c
a'
c
a'
c
f
b
d
a'
d
b
d
a'
d
7.21 (a) NAND gates:
F = D' + B'C + A'B
7.21 (b) NAND gates:
f = a'bc' + ac'd' + b'cd
NOR gates:
F = (A' + B' + D') (B + C + D')
NOR gates:
f = (b' + c') (c' + d) (a + b + c) (a' + c + d')
78
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
f
Unit 7 Solutions
7.21 (c) NAND gates:
f = a'b'd' + bc'd + cd'
7.21 (d) NAND gates:
F = A'B'CD' + AC'E + C'DE + ADE + A'BCDE' +
AC'D + B'C'E' + AB'D
F = A'B'CD' + AC'E + C'DE + ADE + A'BCDE' +
AC'D + B'C'E' + AB'E'
NOR gates:
f = (b + d') (b' + d) (a' + c) (b' + c')
f = (b + d') (b' + d) (a' + c) (c' + d')
7.21 (e) NAND gates:
F=ACD'+ABE'+CDE+A'B'C'D'+B'D'E+A'B'DE'
F=ACD'+ABE'+CDE+A'B'C'E'+A'B'CD+B'D'E
F=ACD'+ABE'+CDE+A'B'DE'+A'B'C'E'+B'D'E
F=ACD'+ABE'+CDE+A'B'DE'+A'B'C'D'+B'CE
NOR gates:
F = (B' + D + E) (A' + C' + D) (A + B + C' + D')
(A + B' + C + E ) (A' + B' + C' + E)
(A + C + D + E') (A + B' + C' + E')
7.21 (f)
NOR gates:
F = (A + C' + D + E) (C + D' + E') (A + B' + E)
(A' + B + D' + E) (A' + B + C) (B' + D + E')
NOR gates:
f = (a + b + d')(a' + b' + d')(a' + c')
7.22
7.21 (g) NAND gates:
f = x'y' + wy' + w'z'+ wz
f = x'y' + wy' + wx' + w'z'
f = x'y' + wy' + y'z'+ wz
NOR gates:
f = (w + x' + z') (w + y' + z') (w' + y' + z)
f = (w + x' + z') (w + y' + z') (w' + x' + y')
NAND gates:
f = c'd' + a'b + a'd' + ab'c'
(a) F is 0 if any 3 (or 4) of the inputs are 1 so
F = (A + B' + C' + D') (A' + B' + C + D')
(A' + B' + C' + D')(A' + B' + C' + D)
(A' + B + C' + D')
= (A' + B' + C')(A' + B' + D')(A' + C' + D')
(B' + C' + D')
(b) F = (A' + B' + C'D')(A'B' + C' + D') or
F = (A' + C' + B'D')(A'C' + B' + D')
A'
B'
C'
D'
7.23 (a)
cd
ab
C'
D'
F
A'
B'
b'
c'
00
01
11
10
00
0
1
0
0
01
0
1
0
0
11
1
1
1
1
a
10
0
1
0
0
c'
b'
d'
F
a
f = (b + c)(b + d)(a' + c)(a' + d)
d'
79
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 7 Solutions
7.23 (b)
cd
ab
7.23 (c)
01
11
10
00
0
1
0
0
1
01
0
1
0
0
0
0
11
1
1
1
1
1
1
10
0
1
0
0
01
11
10
00
1
0
1
1
01
1
0
1
11
0
0
10
1
0
cd
ab
00
00
f = a'b + cd
f ' = (a + b')(c' + d')
a
a'
b
b'
c'
f
d'
c
d
7.24 (a)
7.24 (c) f = A(B' + C') + A'BC + B'C'
A
f
B
f
C
C
B
A
7.24 (b) f = A(AB)' + (AB)'[AB + B' + C]B +
[AB + B' + C]C'
= AB' + (A' + B')[AB + BC] + AC' + B'C'
= AB' + A'BC + AC' + B'C'
7.25 (a)
7.25 (c) f = [A + B + C'][A + C + B'][A' + B' + C']
= [A + (B + C')(B' + C ][A' + B' + C']
= [A + BC + B'C'][A' + B' + C']
A
B
f
C
A
B
C
7.25 (b) f = A(B' + C') + A'BC + B'C'
= [A + A'BC + B'C'][B' + C' + A'BC + B'C']
= [A + BC + B'C'][A' + B' + C']
= [A + B + B'C'][A + C + B'C'][A' + B' + C']
= [A + B + C'][A + C + B'][A' + B' + C']
80
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
f
Unit 7 Solutions
7.26
A
H
I
B
C'
W
J
D
E
G'
F'
7.27 (a)
7.27 (c) Remove the inverter from the output NAND so
the new output is f'. Then, ‘push the inverters at
the NAND outputs forward to the inputs of the
following gates’. An AND with inverters on the
inputs is a NOR
A
B
C
D
f
A
B
7.27 (b) f = (A' + B)(C' + CD)(D' + CD) + B'( C' + D')C
= (A' + B)(C' + D)(D' + C) + B'CD'
= (A' + B)(C'D' + CD) + B'CD'
= A'C'D' + A'CD + BC'D' + BCD + B'CD'
7.28 (a)
1
0
01
0
0
1
1
1
1
1
0
1
0
1
10
1
0
e
d'
0
1
0
0
1
a'
e'
1
1
0
1
10
1
0
1
11
11
0
0
01
a
00
1
00
f'
7.28 (b) f = (b' + d' + ae) (b + c' + de') (a + c + d)
bc
de
C
D
0
0
0
0
b'
d'
b
c'
a
c
d
F
f = (b + c' + d) (b + c' + e') (b' + d' + e)
(a + c + d) (a + b' + d')
7.29
cd
ab
00
00
01
11
10
1
0
0
0
01
1
0
1
0
11
1
0
1
1
10
1
0
0
0
b'
d'
a'
c'
d'
a
b'
f = (a' + d) (a' + b + c) (a + b')
= (a + b') [a' + d (b + c)]
= (a + b') (a' + bd + cd)
81
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
f
Unit 7 Solutions
7.30 (b) Z= (a' + b +e + f)(c' + a' + b)(d' + a' + b)(g+h)
= [a' + b + c'd' (e + f)] (g + h)
7.30 (a) Z = abe'f + c'e'f + d'e'f + gh
= e'f (ab + c' + d') + gh
g
g
h
c
d
a
z
e'
f
e
b
7.31
h
c
d
z
a'
b
f
7.32
F = abde' + a'b' + c
= (a + b') (a' + bde') + c
= (a + b' + c) (a' + c + bde')
a
b'
c
b'
d'
e
f = x'yz + xvy'w' + xvy'z'
= x'yz + xvy' (z' + w')
x'
y
z
w
z
F
f
x
v
y'
a'
c
Alternate: F = (a' + b + c) (b' + c + ade')
7.33 (a)
CD
AB
00
7.33 (b)
00
01
11
10
CD
1
01
1
11
1
10
1
1
1
1
F = B C'D + B'CD + A'B'D' + A'CD
7.33 (c) F = B (A'D + C'D) + B' (A'D' + CD)
B'
11
10
00
1
0
0
0
01
0
1
1
0
11
1
1
0
1
10
1
0
0
0
Alternative:
F = A' (B'D' + BD) + D (B'C + BC')
= D (A'B + BC') + B' (A'D' + CD)
= A' (B'D' + CD) + D (B'C + BC')
=D (A'C + BC') + B' (A'D' + CD)
A'
D
A'
D'
01
Draw OR-AND circuit and replace all gates with
NORs.
Draw AND-OR circuit and replace all gates with
NANDs.
B
00
F = (B + C + D')(B'+ D)(A'+ D)(A'+ B'+ C')
F = B C'D + B'CD + A'B'D' + A'BD
C'
D
AB
F
C
D
82
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 7 Solutions
7.34 (a)
CD
AB
00
7.34 (b)
00
01
11
1
CD
1
1
01
11
10
1
1
1
10
AB
00
01
11
10
00
1
0
1
0
01
0
0
0
1
11
1
0
1
0
10
0
1
0
0
F = (A + C + D')(B + C' + D)(A + B' + C)
(A + B' + D')(A' + B + D)(A' + B + C')
(B' + C + D')(A' + C' + D)
F = ABCD + ABC'D' + AB'C'D + A'BCD' +
A'B'CD + A'B'C'D'
7.34 (c) Many solutions exist. Here is one, drawn with alternate gate symbols.
F = A' (B'C'D' + B'CD + BCD') + A (B'C'D + BC'D' + BCD)
= A' (B'(C'D' + CD) + BCD') + A (B(C'D' + CD) + B'C'D)
C'
D
A'
B'
B
C
D
F
C'
D'
B'
A
B
C
D'
7.35 (a) F = A'BC' + BD + AC + B'CD'
= B (D + A'C') + C (A + B'D')
CD
A'
C'
D'
B
F
B'
D'
C
AB
00
01
11
10
00
0
1
0
0
01
0
1
1
0
11
0
1
1
1
10
1
0
1
1
00
01
11
10
00
0
1
0
0
01
0
1
1
0
11
0
1
1
1
10
1
0
1
1
A'
Many NOR solutions exist. Here is one.
F = (B + C) (A' + C + D) (A + B + D') (A + B' + C' + D)
= (B + C) [A + (B + D') (B' + C' + D)] (A' + C + D)
= (B + C) [A (C + D) + A' (B + D') (B' + C' + D)]
= (B + C) [A (C + D) + A' (B(C' + D) + B'D')]
C'
D
B
D
B'
C
D
A'
A
CD
AB
F
B
C
83
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 7 Solutions
7.35 (b)
CD
AB
00
01
11
10
00
0
0
1
0
01
0
0
0
1
11
1
1
1
0
10
0
1
1
0
A'
D
AB
00
01
11
10
00
0
0
1
0
01
0
0
0
1
11
1
1
1
0
10
0
1
1
0
B
D
CD
AB
00
01
11
10
00
1
1
01
1
1
1
1
11
1
1
1
1
10
1
F
A
F = C (B + A'D) + A (B'C'D + BD')
= C (B + A'D) + A[(B' + D') (B + C'D)]
B'
D'
C
A'
F
D'
A'
C'
B
F = (B' + C + D') (A' + B + C') (B + D) (A + C)
= (C + A (B' + D')) (B + D (A' + C'))
F = (A + C)(B + D)(A'+ B + C')(B'+ C + D')
7.36
C
B'
F = A'CD + BC + AB'C'D + ABD'
CD
B'
C'
D
F = ∑ m(0, 1, 2, 3, 4, 5, 7, 9, 11, 13, 14, 15)
F = D + A'B' + A'C' + ABC
= D + A' (B' + C') + ABC
Alternate solution:
F = D + (A' + BC) (A + B' + C')
1
F = A'B' + A'C' + D + ABC
7.36 (a)
7.36 (b)
A
B
B'
C'
A
B
C
A'
D
C
A'
F
B'
C'
A
B
F
D
C
A'
D'
B
C
84
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
F
Unit 7 Solutions
7.36 (c)
A
B
C
A'
B'
C'
A'
B'
C'
A
Z = A [BC' + D + E(F' + GH)]
G
H
F'
E
D
B
C'
G'
H'
F'
Z
A
E'
D
B'
C
7.38
F
D
B'
C'
7.37
F
D
Z
A'
The minimal product-of-sums expression for F is
F = (A + E)(B′ + C′ + E)(A + B + D′)(A + C + D′)
This expression can be multiplied out to give
F = [A(B′ + C′) + E](A + D′ + BC)
A'
B'
C'
E
F
A
D'
85
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 7 Solutions
7.39 (a) The minimal product-of-sums expression for F is
F = (A + B)(A + C)(B + C)(A′ + B′ + C′)
A
7.39 (b) F can be multiplied out as follows:
F = (A + B)(A + C)(B + C)(A′ + B′ + C′)
= (A + B)(B + C)(A + B′ + C)(A′ + B′ + C′)
= (AC + B)[B′ + (A + C)(A′ + C′)]
B
B
A'
A
C'
C
F
B
F
A
C
B'
C
A'
B'
C'
7.39 (c) The minimal sum-of-products expression for F is
F = ABC′ + AB′C + A′BC
7.39 (d) One factorization of F is
F = A(BC′ + B′C) + C(A′B + AB′)
A
B
C'
B
C
A
B'
C
A
B
F
A
F
C
A'
B
C
7.40 (a) An inverter on the output of an XOR can be moved
to one of its inputs.
B
C
B'
C'
A
A'
7.40 (b) F = (A ⊕ BC) + (A′ ⊕ B′C′) = A′BC + AB′ + AC′
+ AB′C′ + A′B + A′C
= AB′ + AC′ + A′B + A′C
= A(B′ + C′) + A′(B + C)
= (A + B + C)(A′ + B′ + C′)
F
A
B
C
A'
B'
C'
7.40 (c) F = A(B′ + C′) + A′(B + C)
B
C
B'
C'
7.41
A
F
A'
86
F
(a) No—NOR-AND is equivalent to NOT-ANDAND.
(b) Yes—NOR-OR is equivalent to OR-AND-NOT.
(c) No—NOR-NAND is equivalent to OR-OR.
(d) Yes—NOR-XOR is equivalent to NOT-ANDXOR.
(e) Yes—NAND-AND is equivalent to NOT-ORAND.
(f) No—NAND-OR is equivalent to NOT-OR-OR..
(g) No—NAND-NOR is equivalent to AND-AND.
(h) Yes—NAND-XOR is equivalent to AND-XOR
or AND-XOR-NOT.
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 7 Solutions
7.42
f1
c d
f2
a b
00
00
01
11
10
X
1
X
01
f3
a b
00
c d
00
1
01
X
11
1
1
11
10
X
1
10
11
10
c d
01
11
1
X
1
00
1
X
1
01
X
1
X
11
1
1
10
1
X
f 1 = b c'd' + a c
a b
00
01
10
f 3 = a b + a d + b c'd'
f 2 = b'c' + b c'd'
8 gates
7.43
c d
a b
00
01
11
00
10
a b
00
c d
1
01
01
00
1
1
01
1
1
11
1
1
10
1
11
1
1
10
1
1
1
f 1 = a'c + a'b d + a b'd'
11
10
1
1
f 2 = a'b' + a'b d + a b'd'
6 gates
7.44
x
yz
0
1
yz
x
0
1
00
01
1
01
1
1
1
11
10
1
10
f1 = x'yz + x'yz' + xy'
x
0
1
01
1
1
00
00
11
yz
1
1
1
1
1
11
10
1
f2 = y'z + x'yz + xyz'
f3 = xy' + y'z + x'yz' + xyz'
8 gates
7.45 (a)
cd
ab
00
01
11
10
00
1
0
0
0
01
1
1
1
11
1
0
10
1
0
cd
ab
00
01
11
10
00
1
1
1
0
1
01
0
1
1
0
0
1
11
0
0
0
0
0
0
10
1
1
1
0
f2
f1
f1 = (a' + b + d) (b' + c' + d') (b' + d) — 6 gates
f2 = (a' + b + d) (b' + c' + d') (b + d')
87
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 7 Solutions
7.45 (b)
ab
ab
00
01
11
10
00
01
11
10
00
1
0
0
0
00
1
1
1
0
01
1
1
1
1
01
0
1
1
0
11
1
0
0
1
11
0
0
0
0
10
1
0
0
0
10
1
1
1
0
cd
cd
f2
f1
Circle 1's to get sum-of-products expressions:
f1 = bc'd + a'b'd' + b'd — 6 gates
f2 = bc'd + a'b'd' + bd'
Then convert directly to NAND gates.
7.46 (a) Circle 0’s
a b
00
c d
01
11
10
a b
00
c d
01
11
10
00
0
0
1
1
00
0
0
0
0
01
1
1
1
1
01
1
1
0
0
11
1
0
0
1
11
1
1
0
1
10
0
0
0
0
10
1
1
1
1
f1 = (a + c + d)(b'+ c')(c'+ d)
7 gates
f2 = (a + c + d)(a' + c)(a' + b' + d')
7.46 (b) Circle 1's to get sum-of-products expressions:
ab
cd
00
01
11
10
00
0
0
1
1
01
1
1
1
1
11
1
0
0
1
10
0
0
0
0
f1 = ac' + c'd + b'cd
7.47 (a)
c d
a b
00
01
f2
cd
7 gates
11
10
00
10
00
01
11
10
00
0
0
0
0
01
1
1
0
0
11
1
1
0
1
10
1
1
1
1
f2 = a'd + cd' + b'cd
c d
a b
00
00
01
11
ab
Then convert directly to NAND gates
1
1
1
1
1
1
01
11
1
1
01
1
f1 = b c + b'c d + a b c'd
11
10
10
1
1
1
1
1
f2 = b d' + b'c d + a b c'd
88
b
c
b'
c
d
a
b
c'
d
b
d'
f1
f2
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 7 Solutions
7.47 (b)
c d
a b
00
cd
00
11
10
0
0
00
0
0
01
0
00
0
0
01
0
0
01
0
f1 = (b + d)(c + d)(b + c)(a + c + d')
c
d
10
0
0
0
b
d
0
a
c
d'
0
0
10
0
11
0
11
11
10
ab
01
f2 = (b + d)(b + c)(a + c + d')(b'+c'+d')
f1
f2
b
c
b'
c'
d'
7.48 (a)
cd
ab
ab
00
01
11
10
00
1
1
0
0
0
01
1
1
0
0
0
0
11
0
1
0
0
1
1
10
0
0
1
1
00
01
11
10
00
1
1
0
0
01
0
0
0
11
0
1
10
1
1
cd
cd
ab
a
c
d'
a'
b
c
d
a'
c'
f2 = a'c' + a'bcd+ acd'
f1 = a'd' + a'bcd+ acd'
7.48 (b)
a'
d'
ab
00
01
11
10
00
1
1
0
0
0
01
1
1
0
0
0
0
11
0
1
0
0
1
1
10
0
0
1
1
00
01
11
10
00
1
1
0
0
01
0
0
0
11
0
1
10
1
1
f1 = (a'+ c)(a'+ d')(c + d')(b + c'+ d')
cd
f2 = (a'+ c)(a'+ d')(b + c'+ d')(a + c' + d )
f1
f2
c
d'
a'
c
b
c'
d'
a'
d'
a
c'
d
89
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
f1
f2
Unit 7 Solutions
7.49 (a) The circuit consisting of levels 2, 3, and 4 has OR
gate outputs. Convert this circuit to NAND gates
in the usual way, leaving the AND gates at level 1
unchanged. The result is:
c
a'
b
d'
F1
e
f'
h
F2
g
7.49 (b) One solution would be to replace the
two AND gates in (a) with NAND
gates, and then add inverters at the
output. However, the following solution
avoids adding inverters at the outputs:
F1 = [(a + b') c + d] (e' + f)
= ace' + b'ce' + de' + acf + b'cf + df
= ce' (a + b') + d (e' + f) + cf (a + b')
a'
b
c
e'
F1
c
f
e
f'
F2 = [(a + b') c + g'] (e' + f) h
= h (ace' + b'ce' + acf + b'cf) + g'h (e' + f)
= h [ce' (a + b') + cf (a + b')] + g'h (e' + f)
g'
h
h
d
90
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
F2
Unit 8 Solutions
8.1
Unit 8 Problem Solutions
8.2 (a)
W
C D
X
A B
00
00
Y
01
1
01
V
Z
0
5
10
15
20
25
30
35
40 t (ns)
11
10
1
1
1
11
1
1
10
1
1
F = A'C'D' + A C + B C'D
Static 1-hazards: 1101↔1111 and 0100↔0101
8.2 (a)
(cont.)
C D
A B
00
8.2 (b)
01
00
01
0
11
0
0
10
0
0
11
10
0
0
C D
00
0
A B
00
8.3 (a)
01
00
01
0
11
0
0
10
0
0
11
10
0
0
A B
00
01
1
1
1
10
1
1
C
G
1
1
10
1
1
3
4
5
6
7
8.4
A = 1; B = Z; C = 1 ⋅ Z = X; D = 1 + Z = 1;
E = X' = X; F = 1' = 0; G = X ⋅ 0 = 0;
H=X+0=X
See FLD Table 8-1, p. 241.
8.5
A = B = 0, C = D = 1
So F = AB'D + BC'D' + BCD = 0
10
1
11
2
t (ns)
Glitch
(static '1' hazard)
00
01
1
1
11
1
11
10
F
0
Modified circuit (to avoid hazards)
C D
11
1
E
Ft = (A + C') (A' + C + D) (B + C + D')
(A' + B + C) (A + B + D')
8.3 (b)
01
Ft = A'C'D' + A C + B C'D + A'BC' + ABD
Static 0-hazards are: 0001↔0011 and 1000↔1001
C D
1
01
F = (A + C') (A'+ C + D ) (B + C + D')
8.2 (c)
A B
00
But in the figure, gate 4 outputs F = 1, indicating
something is wrong. For the last NAND gate,
F = 0 only when all its inputs are 1. But the
output of gate 3 is 0. Therefore, gate 4 is working
properly, but gate 3 is connected incorrectly or is
malfunctioning.
G = A'C'D + B C + A'BD
91
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Solutions
8.6 (a)
8.6 (b)
C
F
A
G
H
1
2
3
4
5
6
7
t (ns)
D
Glitch
(static '0' hazard)
C
B
The circuit has three static 0-hazards:
0001↔0011, 1001↔1011 and 1000↔1010. Two
sum terms are needed to eliminate the hazards:
(A' + B) (B + D')
8.7 (a)
cd
ab
8.7 (b)
00
00
01
11
0
0
0
0
11
0
0
0
0
0
0
b'
d
c'
d'
f = (a+d')(b'+c+d)(a'+c'+d')(b'+c'+d)
The static-0 hazards are 0100↔0101,
0100↔0110, 0111↔0110, 1100↔1110,
1111↔1110, 0011↔1011 and 0111↔1111.
8.8 (a)
CD
AB
00
00
01
11
1
01
1
1
1
1
1
10
1
1
b'
c'
B
D
10
A'
C
1
A
B'
C'
Static-1 Hazards: 0000↔0010, 1101↔1001
CD
AB
00
00
01
11
1
01
Hazard-free AND-OR circuit function:
f(A, B, C, D) = BD + A'C + AC'D + B'C'D' +
A'B'D' + AB'C'
10
1
1
1
1
11
1
1
10
1
1
F
B'
C'
D'
F = B D + A'C + A B'C' + B'C'D' .
8.8 (a)
cont.
f
a
b'
1
11
The minimal POS expression for f is f(a,b,c,d)
= (a + d')(b' + d)(c' + d') but (a + b') and (b' + c')
must be added to eliminate the static-0 hazards.
a
d'
01
10
10
H
1
B
D
A'
C
F = B D + A'C + A B'C' + A'B'D' .
A
B'
C'
Static-1 Hazards: 0000↔1000, 1101↔1001
F
A'
B'
D'
92
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Solutions
8.8 (a)
cont.
CD
AB
00
00
01
11
1
01
B
D
10
1
1
1
1
11
1
1
10
1
1
A'
C
1
F
A
C'
D
B'
C'
D'
F = B D + A'C + A C'D + B'C'D' .
Static-1 Hazards: 0000↔0010, 1000↔1001
8.8 (a)
cont.
8.8 (b)
A
B'
C'
CD
01
A'
01
11
0
0
F
A
C'
D
10
10
0
11
C
0
0
0
F = (A + B + C + D')(B'+ C + D )
(A'+ B + C')(A'+ B'+ D )
B'
C'
D'
Static-0 Hazard: 1110↔1010
A'
B'
D'
CD
00
00
B
D
8.8 (b)
cont.
AB
A
B
C
D'
AB
00
00
01
01
11
0
0
10
A'
B
C'
0
11
10
B'
C
D
A'
B'
D
0
0
F
0
F = (A + B + C + D')(B'+ C + D )
(A'+ B + C')(A'+ C'+ D )
Static-0 Hazard: 1100↔1110
Hazard-free OR-AND circuit function:
f(A, B, C, D) = (A + B + C + D')(B'+ C + D)
(A'+ B + C') (A'+ B'+ D) (A'+ C'+ D)
A
B
C
D'
B'
C
D
A'
B
C'
BA
D' C
F
B'
C
D
A'
C'
D
A'
B
C'
A'
B'
D
A'
C'
D
93
F
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Solutions
8.9 (a)
AB
CD
00
01
00
01
1
11
1
11
10
1
1
1
1
f = (A'B'+AC')(A+D) = AA'B' + AC' + A'B'D +
AC'D) = AA'B' + AC' + A'B'D
static-1 hazard: 0001↔1001
static-0 hazard: 0010↔1010
potential dynamic hazards:
0000↔1000 and 0011↔1011
dynamic hazard: 0000↔1000
(Note the 0011↔1011 change only propagates
over one path in the circuit and is not a dynamic
hazard.)
10
f = AC' + A'B'D
8.9 (b)
f can be multiplied out as f = (A'B'D+C')(A+B'D).
When this expression is expanded to a POS, it does
not contain any sum of the form (X + X' + ß) so the
corresponding circuit is free of hazards. The three
level NOR circuit is.
Since a circuit with NOR gates is desired, start with
POS expressions for f that corresponds to a hazardfree OR-AND (NOR-NOR) circuit. From the Karnaugh map, all prime implicants are required,
f = (A'+C')(A+B')(A+D)(C'+D)(B'+C').
AB
CD
00
00
01
0
0
11
A
B
01
0
11
0
0
0
0
0
0
0
10
C
10
D
It is possible to start with a SOP that is free of hazards, namely, f = AC' + A'B'D + B'C'D, and then
factor it, e.g., the same result as above is obtained
by f = (A+B'D)C'+A'B'D = (A'B'D+C')(A+B'D).
f = (A + D)(A + B')(A'+ C')(C'+ D)(B'+ C')
8.10
W
X
Y
V
Z
0
8.11 (a)
cont.
CD
5
AB
00
10
00
f
8.11 (a) f = (A + B)(B'C' + BD')
= AB'C' + ABD' + BB'C' + BD'
= (A + B)(B' + B)(B' + D')(B + C')(C' + D')
From the Karnaugh map and the BB'C' term
static-1 hazard: 1100↔1000
static-0 hazard: 0001↔0101
potential dynamic hazards:
0000↔0100 and 1101↔1001
15 20 25 30 35 40 45 50 55 t (ns) The circuit shows that only 0000↔0100 propagates
over three paths.
01
11
10
1
1
1
A
B
1
01
C
11
10
1
1
D
f = A B'C' + A B D' + B D' .
94
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
f
Unit 8 Solutions
8.11 (a) From the Karnaugh map for f, it is seen that a hazard-free POS expression for f requires all prime implicants.
cont.
f = (A + B)(B' + D')(B + C')(C' + D')(A + D')
f can be multiplied out as f = (A + B)(B' + D')(B + C')(C' + D')(A + D') = (AC' + B)(AB'C' + D')
CD
AB
D
00
01
11
00
0
01
0
0
0
11
0
0
0
10
0
10
B
C
f
A
0
0
f = (A + B)(B + C')(B'+ D')(C'+ D')(A + D')
8.13
AB
CD
8.12
01
00
W
01
X
11
1
10
1
Y
V
11
10
1
1
1
1
Z = A'C D + A C'D' + B'C D'
Z
0
8.14
00
5
15 20 25 30 35 40 t (ns)
10
Static 1-hazards lie between 1000↔1010 and
0010↔0011. Without hazards: Z t = AC'D' + A'CD
+ B'CD' + A'B'C + AB'D'
8.15
A = Z; B = 0; C = Z' = X; D = Z ⋅ 0 = 0;
E = Z; F = 0 + 0 + X = X; G = (0 ⋅ Z)' = 0' = 1;
H = (X + 1)' = 1' = 0
A = B = C = 1, so F = (A + B' + C') (A' + B +
C') (A' + B' + C) = 1. But, in the figure, gate 4
outputs F = 0, indicating something is wrong. For
the last NOR gate, F = 1 only when all its inputs
are 0. But the output of gate 1 is 1. Therefore,
gate 4 is working properly, but gate 1 is connected
incorrectly or is malfunctioning.
8.16 (a) F (A, B, C, D) = ∑ m(0, 2, 5, 6, 7, 8, 9, 12, 13, 15)
There are 3 different minimum AND-OR solutions to this problem. The problem asks for any two of these.
CD
AB
00
00
01
1
10
1
1
00
1
01
11
01
1
1
11
1
1
10
1
AB
CD
11
1
10
00
01
10
1
1
00
1
1
1
01
1
1
11
1
1
1
F = B D + A C' + A'C D' + B'C'D'
F = B D + A C' + A'B'D' + A'B C
Solution 1: 1-hazards are between
0000↔0010 and 0111↔0110
Solution 2: 1-hazards are between
0010↔0110 and 0000↔1000
95
AB
11
CD
10
00
01
11
10
1
1
1
1
1
1
1
1
1
1
F = B D + A C' + A'B'D' + A'C D'
Solution 3: 1-hazards are between
0111↔0110 and 0000↔1000
Without hazards: F t = BD + AC' +
B'C'D' + A'CD' + A'B'D' + A'BC
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Solutions
8.16 (b)
CD
AB
00
00
11
10
CD
0
01
0
11
0
10
01
AB
00
00
0
11
10
0
01
0
0
11
0
0
10
F = (A + B + D') (A + B' + C + D) (A' + C' + D)
(A' + B + C')
0-hazard is between 1011↔0011
01
0
0
0
F = (A + B + D') (A + B' + C + D) (A' + C' + D)
(B + C' + D')
0-hazard is between 1011↔1010
Either way, without hazard:
F t = (A + B + D') (A + B' + C + D) (A' + C' + D)
(B + C' + D') (A' + B + C')
96
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 9 Solutions
Unit 9 Problem Solutions
9.1
See FLD p. 741 for solution.
9.2
See FLD p. 741 for solution.
9.3
See FLD p. 742 for solution.
9.4
See FLD p. 742 and Figure 4-4 on FLD p.109.
9.5
y0 y1 y2 y3
00 0 0
10 0 0
b
0
0
1
c
0
1
1
y0 y1
00
X1 0 0
a
0
0
0
XX 1 0
10 1
11
1
1
1
1
XX X 1
11 1
11
1
1
1
1
11
1
1
1
1
10
1
1
1
1
10
0
0
0
0
10
1
1
1
1
y2 y3
01
11
10
00
0
0
0
0
01
1
1
1
y2 y3
y0 y1
00
01
11
10
y0 y1
00
01
11
10
00
0
1
1
1
1
01
1
1
1
1
00
0
1
1
0
1
01
1
1
1
a = y3 + y2
y2 y3
b = y3 + y2' y1
c = y3+ y2+ y1+ y0
9.6
See FLD p. 743 for solution.
9.7
See FLD p. 743 for solution.
9.8
See FLD p. 743-744 for solution.
9.9
9.10
Note: A6 = A4' and A5 = A4. Equations for A4
through A0 can be found using Karnaugh maps. See
FLD p. 745-746 for answers.
The equations derived from Table 4-6 on FLD p.
111 are:
D = x'y'bin + x'ybin' + xy'bin' + xybin
bout = x'bin + x'y + ybin
See FLD p. 744 for PAL diagram.
9.11 (a) F = C'D' + BC' + A'C → Use 3 AND gates
F' = [C'D' + BC' + A'C]' = [C' (B +D') + CA']'
= [(C + B + D') (A' + C')]'
= B'C'D + AC → Use 2 AND gates
9.11 (b) F = A'B' + C'D' → Use 2 AND gates
F' = (A'B' + C'D')'
= (A + B)(C + D)
= AC + AD +BC +BD → Use 4 AND gates
9.12 (a) See FLD p. 746, use the answer for 9.12 (b), but
leave off all connections to 1 and 1'.
9.12 (b) See FLD p. 746 for solution.
9.13
Using Shannon’s expansion theorem:
F = ab'cde' + bc'd'e + a'cd'e + ac'de'
= b' (acde' + a'cd'e + ac'de') + b (c'd'e + a'cd'e + ac'de')
= b' [ade' (c + c') + a'cd'e] + b [(c' + a'c) d'e + ac'de']
= b' (ade' + a'cd'e) + b (c'd'e + a'd'e + ac'de')
The same result can be obtained by splitting a Karnaugh map, as
shown to the right.
B C
D E
00
1
A 01
0
11
10
00
0
01
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
1
0
1
0
10
0
0
1
B=0
97
11
0
0
1
0
B=1
0
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 9 Solutions
9.14 (a) R = ab'h' + bch' + eg'h + fgh
= (ab' + bc)h'+ (eg' + fg)h
= [(a)b' + (c)b]h' + [(e)g' + (f)g]h
a
0
2-to-1
MUX
1
c
b
e
0
2-to-1
MUX
1
f
9.14 (b)
a
b
c
h
0
2-to-1
MUX
1
R
e
g
R
f
h
g
9.15
There are many solutions. For example:
J0
J1
J2
J3
I0
I1
I2
I3
I4
I5
I6
I7
I0
I1
I2
I3
I4
I5
I6
I7
J0
J1
F
J2
J3
I0
I2
I4
I6
I8
I10
I12
I14
I16
I18
I20
I22
I24
I26
I28
I30
I0
2-to-1
Z
Mux
I1
S
I0 S
I1 3 S2
S1
I2
S0
I3
I4
I5
I6
I7 16-to-1
Z
I8
Mux
I9
I10
I11
I12
I13
I14
I15
I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
I11
I12
I13
I14
I15
I0
I1
I2
I3
I4
I5
I6
I7 16-to-1
Z
I8
Mux
I9
I10
I11
I12
S
S1 0
I13
I14 S S2
I15 3
I0
2-to-1
Z
Mux
I1
S
S3
S2
S1
S0
I16
I17
I18
I19
I20
I21
I22
I23
I24
I25
I26
I27
I28
I29
I30
I31
I0
I1
I2
I3
I4
I5
I6
I7 16-to-1
Z
I8
Mux
I9
I10
I11
I12
S
S1 0
I13
I14 S S2
I15 3
S4
S3
S2
S1
I1
I3
I5
I7
I9
I11
I13
I15
I17
I19
I21
I23
I25
I27
I29
I31
F
A 1 B
0 A B
9.16
cont.
9.16
I0 S
I1 3 S2
S1
I2
S0
I3
I4
I5
I6
I7 16-to-1
Z
I8
Mux
I9
I10
I11
I12
I13
I14
I15
Y
S4
Y
S0
98
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 9 Solutions
9.17 (a)
9.17 (b)
S1
I0
I1
I0 E
2-to-1
Z
Mux
I1
S
I3
9.18
S1
I0 E
2-to-1
Z
Mux
I1
S
I0
I1
S0
I2
9.17 (c)
S1
Y
I0 E
2-to-1
Z
Mux
I1
S
I0 E
2-to-1
Z
Mux
I1
S
B
s2
C
s1
D
s0
m0
m1
m2
4 - to - 10 m3
line
m4
decoder m
5
m6
m7
m8
m9
I2
I3
9.19
Since the decoder outputs are negative, NAND
gates are required. The excess-3 outputs are
Σ m(5,6,7,8,9), Σ m(1,2,3,4,9), Σ m(0,3,4,7,8), and
Σ m(0,2,4,6,8) so four 5-input NAND gates are
needed with inputs corresponding to the minterms
of the excess-3 outputs.
f
Y
I0 E
2-to-1
Z
Mux
I1
S
Using S1 = w and S0 = z, I0 = x, I1 = 1, I2 = y and
I3 = 0 which does not require any gates.
x
1
y
0
f
I0 E
2-to-1
Z
Mux
I1
S
S0
Y
I3
s3
I1
S0
I2
A
I0
F
w z
Other answers: Using S1 = w and S0 = y, I0 = x, I1
= z, I2 = 0 and I3 = z' which requires one inverter.
Using S1 = w and S0 = x, I0 = z, I1 = 1, I2 = yz'
and I3 = y which requires one inverter and one
AND gate.
f
E3
9.20
f (a, b, c, d, e) = a'b'cde' + a'b'cde + a'bc'd'e +
a'bc'de + a'bcd'e' + a'bcd'e + ab'c'd'e' + ab'c'd'e +
ab'c'de' + ab'cd'e' + ab'cd'e + ab'cde + abc'd'e +
abcd'e'
= a(b'c'd'e') + a(b'c'd'e) + a(b'c'de') + a(b'cd'e')
+ a(b'cd'e) + a'(b'cde') + [a'(b'cde) + a(b'cde)] +
[a'(bc'd'e) + a(bc'd'e)] + a'(bc'de) + [a'(bcd'e') +
a(bcd'e')] + a'(bcd'e)
I0 = a, I1 = a, I2 = a, I3 = 0, I4 = a, I5 = a, I6 = a',
I7 = 1, I8 = 0, I9 = 1, I10 = 0, I11 = a', I12 = 1, I13
= a', I14 = 0, I15 = 0
a
a
a
0
a
a
a'
1
0
1
0
a'
1
a'
0
0
I0
I1
I2
I3
I4
I5
I6
I7 16-to-1
Z
I8
Mux
I9
I10
I11
I12
S
S1 0
I13
I14 S S2
I15 3
b c d e
99
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 9 Solutions
9.21 (a)
x
0
0
0
0
1
1
1
1
y cin
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
Sum Cout
0
0
1
0
1
0
0
1
1
0
0
1
0
1
1
1
0
1
1
0
1
0
0
1
0
0
0
1
Sum 0
1
1
1
X Y Cin
X Y Cin
9.21 (b)
C in
Cout
9.21(c)
0
C'in
Sum
C in
Cout
X
X'
X'
X
Y Cin
1
x
0
0
0
0
1
1
1
1
y bin
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
Diff
0
1
1
0
1
0
0
1
Bout
0
1
1
1
0
0
0
1
0
1
1
0
1
0
0
1
Diff
Y Cin
0
1
1
1
0
0
0
1
Bout
X Y B in
X Y B in
9.22 (c)
9.22 (b)
B in
Cout
X Y
X Y
9.22 (a)
Sum
0
X
X
1
B'in
Diff
X Y
B in
1
B out
0
B in
X
X'
X'
X
Diff
Y Bin
X Y
100
0
X'
X'
1
Bout
Y Bin
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 9 Solutions
9.23
For a positive number A, |A| = A and for a negative
number A, |A| = −A. Therefore, if the number is
negative, that is A[3] is 1, then the output should be
the 2's complement (that is, invert and add 1) of the
input A.
A3
0
A2
0
A1
0
A0
1
A3
F.A.
A2 A3
F.A.
A1 A3
F.A.
A0 A3
F.A.
0
9.24
A3
I0
I0
I1
A
Z
I2
I3
B
m0
m1
2-to-4
m2
decoder
m3
A B
9.25
output
Z
I2
I3
9.26 (a)
I0
I1
I2
I3
I4
I5
I6
I7
I1
D
x
y
B C
A
3-to-8
Decoder
B in
Z
Bout
D = ∑ m(1, 2, 4, 7); Bout = ∑ m(1, 2, 3, 7)
9.26 (b)
x
y
B C
B in
D
3-to-8
Decoder
Bout
D = ∏ M(0, 3, 5, 6); Bout = ∏ M(0, 4, 5, 6)
101
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 9 Solutions
9.27
a
b
a
1
4-to-2 b
priority c1
encoder 1
y0
y
1
y2
y3
y4
y
5
y6
y7
a
2
b
2
c
4-to-2
priority
encoder
c
2
If any of the inputs y0 through y7 is 1, then d of the
8-to-3 decoder should be 1. But in that case, c1
or c2 of one of the 4-to-2 decoders will be 1. So
d = c1 + c2.
If one of the inputs y4, y5, y6, and y7 is 1, then
a should be 1, and b and c should correspond
to a2 and b2, respectively. Otherwise, a should
be 0, and b and c should corresond to a1 and
b1, respectively. So a = c2, b = c2a2 + c2'a1, and
c = c2b2 + c2'b1.
d
9.28
a
b
c
d
N1
RS
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
ROM
e
f
g
h
N2
9.29 (a)
28 x 5
TU
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
S3
S2
S1
S0
a b c d e f g h
0 0 0 0 0 0 0 0
0 0 1 1 0 0 1 1
0 1 0 1 0 1 1 0
1 0 1 0 0 1 1 1
S3 S2 S1 S0 Cout
X
0
1
0
X
0
0
1
X
1
0
0
X
1
0
0
X
0
0
1
Meaning
(0000 is a not valid input)
(0 + 0 = 0)
(2 + 3 = 5)
(7 + 4 = 11)
Cout
VW Y
0 0 0
0 0 0
0 0 1
0 1 0
0 1 0
0 1 1
1 0 0
1 0 0
1 0 1
1 1 0
Z
0
1
0
0
1
0
0
1
0
0
9.29 (b)
R
4
S
2 x4
T
ROM
V
T U
R S
00
01
11
10
W
00
X
1
Y
01
X
1
Z
11
1
X
X
10
1
X
X
U
V = ST+R
T U
R S
00
01
11
10
00
0
1
X
0
XXXX
01
0
1
X
1
1 0 1 1
XXXX
1 1 0 0
XXXX
11
1
0
X
X
1 1 0 1
XXXX
10
0
0
X
X
1 1 1 0
XXXX
1 1 1 1
XXXX
W = S'T U + S T' U + R U + S T' U'
102
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 9 Solutions
9.29 (b)
(cont.) T U
R S
00
01
11
10
00
0
0
X
1
01
0
1
X
0
11
0
0
X
X
10
1
0
X
X
Y = S'T U' + S T'U + R U'
T U
R S
00
01
11
10
00
0
1
X
0
01
1
0
X
0
11
0
1
X
X
10
0
0
X
X
Z = R'S'T'U + S T 'U' + S T U
9.29 (c)
RS
-1
10
11-0
-1
-1
-0
00
-1
TU
1 0 - 0
- 1
1 1
0 1
0 0
1 0
0 1
1 1
VW Y
10 0
10 0
00 1
01 0
01 0
01 1
01 0
00 1
00 0
00 0
S
T
V
R'
R
U
S'
T
U
S
T'
U
R
W
Y
U'
S
T'
U'
S'
T
U'
R'
S'
T'
U
S
T
U
Z
9.30 (a)
Z
0
0
0
0
0
0
1
0
1
1
RS
0 0
0 0
0 0
0 0
0 1
TU
0 0
0 1
1 0
1 1
0 0
0 1 0 1
0 1 1 0
0 1 1 1
1
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
1 1 0 1
1 1 1 0
1 1 1 1
103
VW Y
0 0 0
0 0 0
0 1 0
0 0 1
Z
0
1
0
0
XXXX
XXXX
0 1 0 1
XXXX
1 1 0 0
1 0 1 0
1 0 0 0
1 0 0 1
XXXX
XXXX
0 1 1 0
XXXX
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 9 Solutions
9.30 (b)
T U
R S
00
01
11
10
R S
00
T U
RS
10
-1
0111
0101
01-
9.31 (a)
(cont.) C D
10
0
X
X
1
00
0
X
X
1
01
0
X
X
1
01
0
X
X
0
11
0
X
X
1
11
0
X
X
0
10
0
0
0
1
10
1
1
1
0
R S
00
01
11
10
T U
R S
00
01
11
10
00
0
X
X
0
00
0
X
X
0
01
0
X
X
1
01
1
X
X
0
11
1
X
X
0
11
0
X
X
1
10
0
0
1
0
10
0
1
0
0
TU
- - 1 0
0 0
- 1 1
0 1
- 0 1
1 1
VW Y
10 0
01 0
01 0
01 0
00 1
00 1
00 1
00 0
00 0
00 0
A B
00
R
S'
R'
T
U'
R
T'
U'
R
S
R'
T
U
R
T'
U
R'
T'
U
R
T
U
R'
S
W = R'T U' + R T'U' + S
Y = R'T U + R T'U + R S
9.30 (c)
11
00
V = R S'
T U
01
Z
0
0
0
0
0
0
0
1
1
1
or
01
11
10
00
0
1
1
1
01
0
0
0
0
11
0
0
1
1
10
1
1
1
1
RS
10
01
11
010101-
Z = R'T'U + R'S + R T U
TU
- - - 1 0
0 0
1 1
0 1
0 1
1 1
VW Y
10 0
01 0
01 1
01 0
01 0
00 1
00 1
00 0
00 0
Z
0
1
0
0
0
0
0
1
1
9.31 (a)
W
S'
Y
Z
A B
00
01
11
10
00
0
1
1
1
01
1
1
0
0
11
0
0
0
0
10
1
1
1
1
F1 = (A + B + C + D)(A'+ C + D')(C' + D')
c'
d'
a'
c
d
a
b
c
d
a
d
F2 = (A + B + C + D)(A' + C + D')(A + D')
C D
V
F1
F2
Alternate solution:
F1 = (a + b + c + d) (a + c' + d') (a' + d')
F2 = (a + b + c + d) (a + b' + d') (c + d')
104
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 9 Solutions
9.31 (b)
a
(cd')
(bd')
1
(ad')
1
(ac)
(a'c'd) 0
b
1
-
c
1
1
0
d
0
0
0
1
F1F2
11
11
11
01
10
a
x
x
b
c
d
x
x
x
x
x
x
x
x
x
x
x
x
x
cd'
bd'
ad'
ac
a'c'd
x
x
x
x
F1 F2
9.32 (a)
AB CD
00 0 0
00 0 1
00 1 0
00 1 1
01 0 0
01 0 1
01 1 0
01 1 1
10 0 0
10 0 1
CD
WX
01
10
10
11
11
10
11
11
10
01
AB
Y
1
0
0
0
1
1
0
1
1
0
Z
1
0
1
0
0
0
1
1
1
1
CD
AB
00
01
11
CD
10
AB
00
01
11
10
1
1
X
0
00
0
1
X
1
00
01
1
1
X
0
01
0
0
X
1
11
1
1
X
X
11
1
1
X
X
10
1
1
X
X
10
0
1
X
X
X = A'C'D' + C D + A D + B C
W = A'D + C + B + AD'
CD
AB
00
01
11
10
00
1
1
X
1
00
01
0
1
X
0
01
11
0
1
X
X
11
10
0
0
X
X
10
00
01
11
10
X
1
X
1
1
X
X
1
X
X
1
1
Z = A D + B C + B'D'
Y = A D' + B D + A'C'D'
Alt:
Z = A + B C + B'D'
105
A'
D
A
D'
A'
C'
D'
C
D
B
C
A
D
B
D
B'
D'
B'
C'
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
W
X
Y
Z
Unit 9 Solutions
9.32 (b)
a
0
1
0
1
-
b
1
1
1
0
c
1
0
1
1
-
d
1
0
0
1
1
1
0
WX
1 0
1 0
1 0
1 0
0 1
0 1
0 1
0 1
0 0
0 0
Y
0
0
0
1
1
0
0
0
1
0
9.32 (c)
Z
0
0
0
0
0
0
1
1
0
1
a
b
c
x
x
x
d
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
W X
b
c
a'd
ad'
a'c'd'
cd
x ad
x bc
bd
x b'd'
x
x
x
Y
Z
9.33 (a) See solution for 7.10
a
1
0
1
1
0
b
0
0
1
0
0
1
1
c
1
1
1
0
0
1
d
1
1
0
0
0
0
-
f1
1
1
1
0
0
0
0
0
f2
0
0
0
1
1
1
1
0
f3
0
1
0
1
0
0
0
1
a
b
x
x
x
x x
x
c
d
x
x x
x
x
x x
x x
x x
x
9.33 (b) See solution for 7.41
x
0
0
1
1
y
1
1
0
0
1
x
x
x
z
1
0
1
0
f1
1
1
1
0
0
f2
1
0
0
1
1
x
x
x
x
x
x
x
x x
x x
x
x
x x
x
x
f1 f 2 f 3
a
1
0
-
z
ab'd
b'cd
a'bd'
ab'c
b'cd'
bc'd'
ac'd'
a'bc
x
9.33 (c) Because a PLA works with a sum-of-products
expression, see solution for 7.43(b), not (a).
f3
0
1
1
1
1
y
x
x
x
x
x
x
x
b
0
-
c
0
0
1
1
d
1
1
1
0
a
x
x
x
x
x
x
x
x
x
x
x
x
x'yz
x'yz'
xy'
y'z
xyz'
f1 f 2 f 3
106
f1
1
1
1
0
0
b
x
x
f2
0
0
1
1
1
c
d
x
x x
x
x x
x
x
x
ac'
c'd
x b'cd
x a'd
x cd'
f1 f 2
x
x
x
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 9 Solutions
9.34
Z = I0A'B'C' + I1A'B'C + I2A'BC' + I3A'BC + I4AB'C' + I5AB'C + I6ABC' + I7ABC
= X1A' + X2A where X1 = I0B'C' + I1B'C + I2BC' + I3BC and X2 = I4B'C' + I5B'C + I6BC' + I7BC
Note: Unused inputs, outputs, and
wires have been omitted from this
diagram.
A
B
C
I0
I1
I2
I3
I4
I5
I6
I7
x
x
x
x
x x xx
x xx
x
xx
x
x
xx x
x
x x
x
xx
x
x
x
x
x x
x
X1
X2
x
x
9.35
Z
For an 8-to-3 encoder, using the truth table given in
FLD Figure 9-16, we get
a = y4 + y5 + y6 + y7
b = y2 y3' y4' y5' y6' y7' + y3 y4' y5' y6' y7' + y6 y7' + y7
c = y1y2' y3' y4' y5' y6' y7' + y3 y4' y5' y6' y7' + y5 y6' y7' + y7
d = a + b + c + y0
Alternative solution for simplified expressions:
b = y2 y4' y5' + y3 y4' y5' + y6 + y7
c = y1 y2' y4' y6' + y3 y4' y6' + y5 y6' + y7
107
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 9 Solutions
9.35
(cont.)
Note: Unused inputs, outputs,
and wires have been omitted
from this diagram.
y0
y1
y2
y3
y4
y5
y6
y7
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
9.36
a
x
x
x
x
x
b
x
x
x
c
x
F = CD'E + CDE + A'D'E + A'B'DE' + BCD
9.36 (a) F = A'B'(CD'E + CDE + D'E + DE') +
A'B (CD'E + CDE + D'E + CD) +
AB' (CD'E + CDE) + AB (CD'E + CDE + CD)
9.36 (b) F = B'C' (A'D'E + A'DE') +
B'C (D'E +DE + A'D'E + A'DE') +
BC' (A'D'E) + BC (D'E + DE + A'D'E + D)
9.36 (c) F = A'C' (D'E + B'DE') +
A'C (D'E + DE + D'E + B'DE' + BD) +
AC'(0) + AC(D'E + DE + BD)
x
d
x
9.36 (d) Use the expansion about A and C
F = A'C'(F0 ) + A'C(F1 ) + AC(F3 )
where F0, F1, F3 are implemented in lookup tables:
B
D
E
B
D
E
F0
LUT 0
F1
LUT 1
F
0
B
D
E
108
LUT 3
F3 A C
BD E
00 0
00 1
01 0
01 1
10 0
10 1
11 0
11 1
F0 F1 F3
0 0 0
1 1 1
1 1 0
0 1 1
0 0 0
1 1 1
0 1 1
0 1 1
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 9 Solutions
9.37
F = B'D'E' + AB'C + C'DE' + A'BC'D
9.37 (a) F = A'B' (D'E' + C'DE') + A'B (C'DE' + C'D) + AB' (D'E' + C + C'D) + AB (C'DE')
9.37 (b) F = B'C' (D'E' + DE') + B'C (D'E' + A) + BC' (DE' + A'D) + BC (0)
9.37 (c) F = A'C' (B'D'E' + DE' + BD) + A'C (B'D'E') + AC' (B'D'E' + DE') + AC (B'D'E' + B')
In this case, use the expansion about B and C to implement the function in 3 LUTs:
F = B'C'(F0 ) + B'C(F1 ) + BC'(F2 ) + BC(0)
Here we use the LUTs to implement F0, F1, F2 which are functions of A, D, E
A
D
E
A
D
E
A
D
E
LUT 0
LUT 1
F0
F1
F
F2
LUT 2
B C
0
9.38
AD E
00 0
00 1
01 0
01 1
10 0
10 1
11 0
11 1
F0 F1 F2
1 1 0
0 0 0
1 0 1
0 0 1
1 1 0
0 1 0
1 1 1
0 1 0
For a 4-to-1 MUX:
Y = A'B'I0 + A'BI1 + AB'I2 + ABI3
= A' (B'I0 + BI1 ) + A(B'I2 + BI3 )
= A'G + AF, where G = B'I0 + BI1; F = B'I2 + BI3
Set programmable MUX so that Y is the output of
MUX H.
9.39 (a)
9.39 (b)
0
1
1
B'
B
0
0
0
1
I0
I1
E
0
B
I2
I 3 8-to-1
I 4 MUX
I5
I6
I7
1
0
B'
f
1
1
1
0
LUT 0
F 4= 0
F 3= B
F 2= I2
F 1= I3
LUT 1
G
H
F
9.39 (c)
I0
I1
I 3 8-to-1
I 4 MUX
B
D
I5
I6
f
Y
H1 = A
0
E
I2
1
I0 E
0
I 1 4-to-1
I 2 MUX
S
I 3 S1 0
D
A C
I7
A C D
A C D
9.40
G4 = 0
G3 = B
G2 = I0
G1 = I1
Same answer as 9.39 except connect E to the enable
input in parts (a) and (c) and E’ in part (b).
109
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f
Unit 9 Solutions
9.41 (a) F = a’ + ac’d’ + b’cd’ + ad
= d’(a’ + ac’ + b’c) + d(a’ + a)
= d’(a’ + ac’ + b’c) + d(1)
= d’(e) + d(g)
9.41 (b)
a
e
b
LUT 0
c
0
a
1
b
LUT 1
g
9.41 (c)
a
0
0
0
0
1
1
1
1
b
0
0
1
1
0
0
1
1
c
0
1
0
1
0
1
0
1
e
1
1
1
1
1
1
1
0
g
1
1
1
1
1
1
1
1
9.42 (c)
a
0
0
0
0
1
1
1
1
b
0
0
1
1
0
0
1
1
c
0
1
0
1
0
1
0
1
e
0
1
1
1
1
1
1
1
g
0
1
1
0
0
0
1
0
9.43 (c)
a
0
0
0
0
1
1
1
1
b
0
0
1
1
0
0
1
1
c
0
1
0
1
0
1
0
1
e
1
1
1
1
0
0
1
0
g
0
0
1
1
1
0
1
1
F
d
c
9.42 (a) F = cd’ + ad’ + a’b’cd’+ bc’
= d’(c + a + bc’ ) + d(a’ b’c+ bc’)
= d’(e) + d(g)
9.42 (b) Same as 9.41 (b).
9.43 (a) F = bd + bc’ + ac’ d+ a’d’
= d’(bc’ + a’ ) + d(b + bc’+ ac’)
= d’(bc’ + a’ ) + d(b + ac’)
= d’(e) + d(g)
9.43 (b) Same as 9.41 (b).
9.44 (a)
9.44 (b)
f = b′(ac′ + ac + a′c′). b′ must be connected to
w. If s = a, t = c, then connect y0, y2 and y3 to a
3-input OR-gate. If s = c, t = a, then connect y0, y1
and y3 to a 3-input OR-gate.
No. The outputs are y0 = s′t′w, y1 = s′tw, y2 =
st′w and y3 = stw so any function realized by ORing
some of M’s outputs has the form (minterms of s
and t)w; hence, only functions that can be factored
in this form can be realized. For example, a′bc +
ab′c + abc′ cannot be realized in this way. (Another
possible answer: The outputs of M are only half
of the minterms of the three variables so only
functions containing a subset of those minterms can
be realized.).
110
9.44 (c)
If a NOR-gate is connected to some of outputs of
M and it realizes the function f, then f′ is the OR of
the minterms from M. For the function of Part (a),
f′ = (a′ + b)(b + c) = b + a′c = a′bc′ + a′bc + abc′ +
abc + a′b′c. f′ contains five minterms and, hence,
cannot be realized.
9.44 (d)
NAND or AND (When selected the four outputs
are y0 = s′t′w′, y1 = s′tw′, y2 = st′w′, and y3 = stw′;
unselected outputs are 1.)
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 9 Solutions
9.45
Z3 = A, Z2 = A′B, Z1 = A′B′C and Z0 = A′B′C′D
9.46 (b)
The decoder outputs are minterms of A and B
active low: Y0 = A′B′, Y1 = A′B, Y2 = AB′, Y3 = AB.
The mux output is selected by select inputs S1 = C
and S0 = D: f = I0′C′D′ + I1′C′D + I2′CD′ + I3′CD
and the mux inputs are I0 = Y0′, I1 = Y1′, I2 =
Y2′and I3 = Y3′. So f(A,B,C,D)
= Y0′C′D′ + Y1′C′D + Y2′CD′+ Y3′CD
= A′B′C′D′ + A′BC′D + AB′CD′ + ABCD.
This can be made easier by moving the inversion on
the output of the mux to all inputs of the mux, and
noticing that the two inversions in series between
the decoder and mux cancel.
9.47 (a)
Let c0 = 0 and ci = 0(1) indicate that A > B (A <
B) in bits 0, …, i, then ci+1 = ciai′ + cibi + ai′bi.
Let c0 = 1 and ci = 1(0) indicate that A > B (A < B)
in bits 0, …, i, then ci+1 = cibi′ + ciai + aibi′.
9.47 (b)
For c0 = 1, the ci are the carries between adder
stages for A + (-B).
9.48 (a) Sum = (X ⊕ Y) ⊕ Cin and
Cout = X′YCin + XY′Cin + XYC′in + XYCin
= (X′Y + XY′)Cin + XY
= (X ⊕ Y)Cin + (X ⊕ Y)′XY
= (X ⊕ Y)Cin + (X ⊕ Y)′X
or = (X ⊕ Y)Cin + (X ⊕ Y)′Y
9.46 (a)
The decoder outputs are Y0 = A′B′, Y1 = A′B, Y2 =
AB′, Y3 = AB. The mux outputs are
f = I0′C′D′ + I1′C′D + I2′CD′ + I3′CD. So
f(A,B,C,D) = Y0′C′D′ + Y1′C′D + Y2′CD′+ Y3′CD
= (A + B)C′D′ + (A + B′)C′D + (A′ + B)CD′
+ (A′ + B′)CD
= AC′D′ + BC′D′ + AC′D + B′C′D + A′CD′ ′
+ BCD′ + A′CD + B′CD
= AC′ + BD′ + B′D + A′C.
9.47 (c)
It is not possible to determine the output of Mi
when ai = 0 and bi.= 1 and the input to Mi indicates
that A > B in bits i+1, …, 3. If A > B in bits i+1, …,
3, then the output of Mi should still indicate A > B,
but if A = B in bits i+1, … , 3, then the output of Mi
should indicate A < B. It is necessary to distinguish
between the three cases, A > B, A = B and A < B so
there must be a second line between the modules.
X
Cin
Sum
Y
I1 S
Z
9.48 (b)
9.49 (a) di = (xi ⊕ yi) ⊕ bi and
bi+1 = xi′yi′bi + xi′yibi′ + xi′yibi + xiyibi
= (xi′yi′ + xiyi)bi + xi′yi
= (xi ⊕ yi)′bi + (xi′yi + xiyi′)xi′yi
= (xi ⊕ yi)′bi + (xi ⊕ yi)xi′
or = (xi ⊕ yi)′bi + (xi ⊕ yi)yi
9.49 (b)
X or Y
In CMOS logic a multiplexer can be
implemented using transmission transistors which
is faster than a regular gate implementation; hence,
the full adder of part (a) would be faster.
xi
yi
I0
bi
di
I0 S
In CMOS logic a multiplexer can be
implemented using transmission transistors which
is faster than a regular gate implementation; hence,
the full subtracter of part (a) would be faster.
111
x′i or yi
Cout
Z
b i+1
I1
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 9 Solutions
112
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 10 Solutions
10.1
10.3
10.5
Unit 10 Problem Solutions
See FLD p. 747 for solution.
See FLD p. 748 for solution
10.2
See FLD p. 747 for solution.
10.4
See FLD p. 748 for solution.
See FLD p. 748 for solution.
Notes: The function vec2int is found in bit_pack, which is in the library bitlib, so the following declarations are
needed to use vec2int:
library bitlib;
use bitlib.bit_pack.all;
If std_logic is used instead of bits, then the index can be computed as:
index <= conv_integer(A&B&Cin); where A, B, and Cin are std_logic.
conv_integer is found in the std_logic_arith package.
10.6
See FLD p. 748 for solution.
10.8
See FLD p. 749 for solution.
10.9
See FLD p. 749 for solution.
10.10
The circuit represented by the given code is:
P
Q
L
N
10.7
M
See FLD p. 749 for solution.
Notes: In line 8, "00"&a converts a to a 18-bit
std_logic_vector. The overloaded “+” operators
automatically extend b, c, and d to 18 bits so that
the sum is 18 bits. In line 9, sum(17 downto 2)
drops the lower 2 bits of sum, which effectively
divides by 4 to give the average. Adding sum(1)
rounds up the value of f if sum(1) = 1.
R
(1) Statement (a) will execute as soon as either P or Q change. Hence, it will execute at 4 ns.
(2) Since the NAND gate has a delay of 10 ns, L will be updated at 14 ns.
(3) Statement (c) will execute when the value M changes. It will execute at 19 ns.
(4) R will be updated at 19 + Δ ns, since Δ is the default delay time when no delay is explicitly specified.
10.11 (a) H <= not A nand B nor not D nand E;
10.11(b)
(Note: not happens first, then it proceeds from left to
right)
113
AN <= not A after 5 ns;
C <= AN nand B after 10ns;
F <= not D after 5ns;
G <= C nor F after 15ns;
H <= G nand E after 10ns;
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 10 Solutions
10.12
R
S
10.13
F
P
Q
S
P
Q
R
U
V
T
10.14 (a) The expression can be rewritten as:
F <= (((not E) & "011") or "000100") and (not D);
Evaluating in this order, we get:
F = 000110
10.15
L = X (Since 1 and 0 in the resolution function
yields X)
M=0
N = 1 (1 overrides Z in the resolution function)
10.14 (b) LHS: not("101" & "011") = "010100"
RHS: ("100" & "101" and "010" & "101") = "000101"
Since LHS > RHS, the expression evaluates to
FALSE
10.16 (a) databus <= membus when mRead = '1'
library bitlib;
use bitlib.bit_pack.all;
else "ZZZZZZZZ";
databus <= probus when mWrite = '1'
else "ZZZZZZZZ";
entity myrom is
port (A, B, C, D: in bit; W, X, Y: out bit);
end myrom;
architecture table of myrom is
type ROM16_3 is array(0 to 15)of bit_vector(0 to 2);
constant ROM1: ROM16_3 := ("010", "111", "100",
"110", "011", "110", "001", "000", "000", "111",
"100", "010", "001", "100", "101", "000");
signal index: integer range 0 to 15;
signal temp: bit_vector(0 to 2);
begin
index <= vec2int(A&B&C&D);
temp <= ROM1(index);
W <= temp(0);
X <= temp(1);
Y <= temp(2);
end table;
10.17 (a) with C&D select
10.16 (b) The value will be determined by the
std_logic resolution function. For example, if
membus = "01010101" and probus = "00001111",
then databus = "0X0XX1X1"
10.17 (b) F <= not A after 15ns when C&D = "00"
F <= not A after 15ns when "00",
B after 15ns when "01",
not B after 15ns when "10",
'0' after 15ns when "11";
else B after 15ns when C&D = "01"
else not B after 15ns when C&D = "10"
else '0' after 15ns;
10.18 (b) entity main is
port(A, B, C, D: in bit; F: out bit);
end main;
10.18 (a) entity mynand is
port(X, Y: in bit; Z: out bit);
end mynand;
architecture eqn of main is
component mynand is
port(X, Y: in bit; Z: out bit);
end component;
architecture eqn of mynand is
begin
Z <= X nand Y after 4 ns;
end eqn;
signal E, G: bit;
begin
n1: mynand port map(A, B, E);
n2: mynand port map(C, D, G);
n3: mynand port map(E, G, F);
end eqn;
114
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Unit 10 Solutions
10.19(a)
10.19(b)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity hazard_circuit is
port (a, b, c : in std_logic;
f : out std_logic);
end hazard_circuit;
architecture hazarddf of hazard_circuit is
signal d, e, g : std_logic;
begin
d <= not b after 10ns;
e <= a and b after 10ns;
g <= c and d after 10ns;
f <= e or g after 10ns;
end hazarddf;
Si gnal Cur r ent 0ns
a
b
c
f
d
e
g
' 1'
' 0'
' 1'
' 1'
' 1'
' 0'
' 1'
10ns
20ns
30ns
10ns
20ns
30ns
10.19(c)
change the assignment statement for d to
d <= not b after 5 ns;
10.19(e)
change the assignment statement for f to
f <= transport e or g after 10 ns;
10.19(g)
When the output gate has a 10ns inertial delay,
the 5ns glitch caused by the static-1 hazard is not
passed through the gate; however, with a transport
delay the glitch does pass through. Note: The
initial values of d, e, f and g are 'U' becasue std_
logic type is used. These initial values are '0' when
bit type is used.
40ns
50ns
60ns
70ns
80ns
90ns
U
U
U
U
10.19(d)
Si gnal
a
b
c
f
d
e
g
0ns
Cur r ent
' 1'
' 0'
' 1'
' 1'
' 1'
' 0'
' 1'
40ns
50ns
60ns
70ns
80ns
U
U
U
U
10.19 (f)
Si gnal
a
b
c
f
d
e
g
Cur r ent
' 1'
' 0'
' 1'
' 1'
' 1'
' 0'
' 1'
0ns
10ns
20ns
30ns
40ns
50ns
60ns
70ns
U
U
U
U
115
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Unit 10 Solutions
10.20(a)
10.20(b)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dynhaz_circuit is
port (a, b, c, d : in std_logic;
f : out std_logic);
end dynhaz_circuit;
architecture hazarddf of dynhaz_circuit is
signal e, g, h, i, j : std_logic;
begin
e <= not b after 10ns;
g <= a and b after 10ns;
h <= c and e after 10ns;
i <= b or d after 40ns;
j <= g or h after 10ns;
f <= i and j after 10ns;
end hazarddf;
Signal Current 0ns
a
'1'
b
'0'
c
'1'
d
'0'
U
f
'0'
U
e
'1'
U
g
'0'
U
h
'1'
U
i
'0'
j
10.20(d)
15ns
30ns
45ns
10.20(c)
change the assignment statement for e to
e <= not b after 5 ns;
10.20(e)
change the assignment statements for j and f to
j <= transport g orh after 10 ns;
f <= transport i or j after 10 ns;
10.20(g)
When the gate 4 has a 10ns inertial delay, the 5ns
glitch caused by the static-1 hazard for gate 4 is not
passed through gate 4 ; however, with a transport
delays for gates 4 and 5, the static-1 hazard glitch
at gate 4 does passes through gate 4 and gate 5.
In addition, the 5ns glitch caused by the delay
through gate 3 also passes through gate 5. The
three changes in f illustrate the dynamic hazard that
exists in the circuit.
60ns
75ns
90ns
105ns
U
'1'
Signal Current 0ns
a
'1'
b
'0'
c
'1'
d
'0'
U
f
'0'
e
'1'
g
h
'0'
'1'
i
j
'0'
'1'
15ns
30ns
45ns
60ns
75ns
90ns
105ns
U
U
U
U
U
116
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Unit 10 Solutions
10.20(f)
10.21(a)
10.21(c)
10.21(b)
& (d)
Signal Current 0ns
a
'1'
b
'0'
c
'1'
d
'0'
U
f
'0'
U
e
'1'
U
g
'0'
U
h
'1'
U
i
'0'
U
j
'1'
15ns
30ns
45ns
60ns
75ns
90ns
105ns
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bcd_to_2421 is
port (x : in std_logic_vector(3 downto 0);
y : out std_logic_vector(3 downto 0));
end bcd_to_2421;
architecture behavioral1 of bcd_to_2421 is
begin
y <= "0000" when x = "0000"
else "0001" when x = "0001"
else "0010" when x = "0010"
else "0011" when x = "0011"
else "0100" when x = "0100"
else "1011" when x = "0101"
else "1100" when x = "0110"
else "1101" when x = "0111"
else "1110" when x = "1000"
else "1111" when x = "1001"
else "XXXX";
end behavioral1;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bcd_to_2421 is
port (x : in std_logic_vector(3 downto 0);
y : out std_logic_vector(3 downto 0));
end bcd_to_2421;
architecture behavioral2 of bcd_to_2421 is
begin
with x select
y <= "0000" when "0000",
"0001" when "0001",
"0010" when "0010",
"0011" when "0011",
"0100" when "0100",
"1011" when "0101",
"1100" when "0110",
"1101" when "0111",
"1110" when "1000",
"1111" when "1001",
"XXXX" when others;
end behavioral2;
Time
0 ns
5 ns
10 ns
15 ns
x
0100
0101
1001
1010
y
0100
1011
1111
XXXX
117
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Unit 10 Solutions
10.22(a)
10.22(b)
10.22(c)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity c8421_to_excess3 is
port (x : in std_logic_vector(3 downto 0);
y : out std_logic_vector(3 downto 0));
end c8421_to_excess3;
architecture behavioral1 of c8421_to_excess3 is
begin
y <= "0011" when x = "0000"
else "0100" when x = "0111"
else "0101" when x = "0110"
else "0110" when x = "0101"
else "0111" when x = "0100"
else "1000" when x = "1011"
else "1001" when x = "1010"
else "1010" when x = "1001"
else "1011" when x = "1000"
else "1100" when x = "1111"
else "XXXX";
end behavioral1;
Time
0 ns
5 ns
10 ns
15 ns
x
0011
0100
1001
1010
10.22(d)
y
XXXX
0111
1010
1001
118
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity c8421_to_excess3 is
port (x : in std_logic_vector(3 downto 0);
y : out std_logic_vector(3 downto 0));
end c8421_to_excess3;
architecture behavioral2 of c8421_to_excess3 is
begin
with x select
y <= "0011" when "0000",
"0100" when "0111",
"0101" when "0110",
"0110" when "0101",
"0111" when "0100",
"1000" when "1011",
"1001" when "1010",
"1010" when "1001",
"1011" when "1000",
"1100" when "1111",
"XXXX" when others;
end behavioral2;
Time
0 ns
5 ns
10 ns
15 ns
x
0100
0101
1001
1010
y
0111
0110
1010
1001
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 11 Solutions
Unit 11 Problem Solutions
11.1
Z responds to X and to Y after 10 ns; Y responds to
Z after 5 ns. See FLD p. 751 for answer.
11.3
P and Q will oscillate. See FLD p. 751 for timing
chart.
11.4
11.5
11.2
See FLD p. 751 for solution. For part (b), also use
the following Karnaugh map. Don’t cares come
from the restriction in part (a).
H Q
See FLD p. 752 for solution.
See FLD p. 752 for solution.
R
0
1
00
0
X
01
0
X
11
1
1
10
0
1
Q+ = R + H Q
11.6 (a)
S R Q Q+
00 0 0
00 1 1
01 0 0
01 1 0
10 0 1
10 1 1
11 0 0
11 1 0
R Q
S
11.6 (b) See FLD p. 752 for solution.
0
1
00
0
1
01
1
1
11
0
0
10
0
0
Q+ = R'Q + S R'
11.11
11.7
See FLD p. 752 for solution.
11.8
See FLD p. 752 for solution.
11.9
See FLD p. 753 for solution.
11.10
See FLD p. 753 for solution.
11.12
For every input/state combination with the
condition SR = 0 holding, each circuit obeys the
next-state equation Q+ = S + R'Q. When S = R = 1,
in (a), both outputs are 1, and in (b), the latch holds
its state.
S
R
Q
11.13 (a)
Present
State
Q
0
1
AB
00
0
0
Next State Q+
AB
AB
01
11
0
1
1
1
11.13 (b)
AB
10
0
1
A
B
P
Q+ = AB + QA + QB
Q+ = AB + Q(A + B)
11.13 (c) A change between AB = 01 and 10 can cause Q to
change depending on the inverter delays.
11.13 (d) P = Q' + A'B' equals Q' in all stable states.
119
Q
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 11 Solutions
11.13 (e)
A
B
Q
11.13 (e) A change between AB = 01 and 10 can cause Q to
change depending on the inverter delays.
P = Q'(A' + B') equals Q' in all stable states.
P
Q+ = (AB + Q)(A + B)
11.14 (a)
Present
State
Q
0
1
00
0
0
Next State Q+
A B
01
11
0
0
0
1
10
1
1
11.14 b) Q+ = A(B' + Q)
& (c)
This is a reset dominant latch where A´ acts a reset
and B´ acts as a set.
11.15 (a) Q+ = (M + N + G)[Q + (M + N+ G)N'G']
= (M +N + G)[Q + N'G']
= (M + N + G)Q + MN'G'
11.15 (b)
Q
0
1
000
0
0
001
0
1
011
0
1
GMN
010
100
1
0
1
1
101
0
1
111
0
1
110
0
1
The stable states are in bold.
11.15 (c) When G = 1, the circuit is always stable. When G = 0, M and N determine the state; N = 1 makes the state stable and
with N = 0 the state becomes the value of M. There would be a restriction on M and N if they could cause both inputs
to the output latch to be 1 when G = 0. This is not possible so there is no restriction.
11.15 (d) P = Q'[N + G + M'N'G'] = Q'[N + G + M']
For every stable state, P = Q' so P is usable as the complement of Q..
11.16 (a) Q+ = AB + QB
11.16 (b)
11.16 (c) AB = 01 is a hold input combination, AB = 00 and
10 are reset input combinations, and AB = 11 is a
set input combination. This is reset dominant latch
where S = A and R = B'. P = Q' + B'. In each
stable state P = Q' even for the input combination
AB = 10 (SR = 11) so P is usable as Q'. Allowing
the input combination AB = 10 (SR = 11) would
result in unreliable operation if both A and B could
change at the same time, i.e., change to AB = 01
(SR = 00), because the latch could end up in either
state 0 or 1 depending upon the delays in the circuit.
120
Present
State
Q
0
1
00
0
0
Next State Q+
A B
01
11
0
1
1
1
The stable states are in bold.
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
10
0
0
Unit 11 Solutions
11.17
11.18
(a) Q+ = R'(S + Q) if SR = 0
(b) Q+ = (G + Q)(G' + D)
(c) Q+ = D
(d) Q+ = (Q + CE)(CE' + D)
(e) Q+ = (J + Q)(K' + Q')
(f) Q+ = (T + Q)(T' + Q')
D
G
Q
S
R
11.19
11.20 (a)
Clock
SRQ
00 0
00 1
01 0
01 1
10 0
10 1
11 0
11 1
D
Q
P
11.20 (b) A set-dominant FF from an S-R FF—The
arrangement will ensure that when S = R = 1, S1 = 1,
R1 = 0, and Q+ = 1.
S
S1
Q
R1
Q'
11.21
CK
R
Q+
0
1
0
0
1
1
1
1
R Q
S
0
1
00
0
1
01
1
1
11
0
1
10
0
1
Q+ = S + R'Q
Clock
S
R
Q
11.22 (a)
Clock
& (b)
J
K
(a) Q
(b) Q
121
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Unit 11 Solutions
11.23 (a)
Clock
& (b)
Q
(a) D
(b) T
11.24
Clock
Q0
Q1
Q2
5
11.25
10
15
20
25
30
35
40
45
50 t (ns)
Clock
PreN
T
Q
11.26
11.27 (a)
Clock
D
ClrN
S
Q
R
Q'
CK
D
Q1
When D = 0, then S = 0, and R = 1, so Q+ = 0.
When D = 1, then S = 1, and R = 0, so Q+ = 1.
Q2
11.27 (b) R will not be ready until D goes through the
inverter, so we must add the delay of the inverter to
the setup time:
Setup time = 1.5 + 1 = 2.5 ns
Propagation delay for the DFF:
2.5 ns (same as for the S-R flip-flop, since the
propagation delay is measured with respect to the
clock)
11.28
+V
S
Q
+V
R
122
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Unit 11 Solutions
11.29 (a)
D
G
11.29 (c)
Q
D
G
Q
11.29 (b) Static-1 hazard: (G, D, Q) = ( 0, 1, 1) ↔ (1, 1, 1)
11.29 (d) P = Q′
11.30 (a)
11.30 (b) Q+ = GD + Q(G′ + D) = GD + QG′ + QD Each
pair of adjacent 1’s is covered by one of the
products, so no static-1 hazards. There is no product
containing both an X and an X′ so no static-0 or
dynamic hazards.
D
Q
G
P
11.30 (c) Q+ = GD + Q(G′ + D) = GD + QG′ + QD
= GD + QG′ by consensus.
11.31 (a)
11.31 (b) Q+ = (G′ + R′)(Q + SG)
R'
Q
11.31 (c) Q+ = (G′ + R′)(Q + S)(Q + G) Static-0 hazard:
(G, S, R, Q) = (0, 1, 1, 0) ↔ (1, 1, 1, 0)
G'
11.31 (d) If S = R = 1, then Q = P = 0 when G = 1, so P is not
equal to Q′ in this state. When G changes to 0, both
Q and P attempt to change to 1; theoretically, they
oscillate; this is indicated by the static-0 hazard.
The resulting next-state of Q depends upon the
propagation delays of the gates.
P
S'
11.32 (a) P+ = x′P + xQ + PQ = (x′ + Q)P+ xQ
Q+ = x′P′ + xQ + P′Q = (x′ + Q)P′+ xQ
11.32 (b) If the initial state is PQ = 01, then the U and V
outputs are as shown in the table below.
P
x
Q
Present
State
PQ
00
01
11
10
Next State
P+Q+
x=0
01
01
10
10
x=1
00
11
11
00
UV
11
00
01
10
Then U = Q′ and V = (P ⊕ Q)′. If the initial state is
PQ = 10, then U = Q and V = (P ⊕ Q)′.
123
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Unit 11 Solutions
11.33
(x, y, P, Q)
(0, 0, 0, 0) → (1, 1, 0, 1) Correct change
→ (1, 0, 0, 0) → (1, 1, 0, 0) x first, correct, no glitch
→ (0, 1, 0, 0) → (1, 1, 0, 0) y first, correct, no glitch
(0, 1, 0, 0) → (1, 0, 0, 0) Correct change
→ (1, 1, 0, 1) → (1, 0, 1, 1) x first, incorrect
→ (0, 0, 0, 0) → (1, 0, 0, 0) y first, correct, no glitch
(1, 0, 0, 0) → (0, 1, 0, 0) Correct change
→ (0, 0, 0, 0) → (0, 1, 0, 0) x first, correct, no glitch
→ (1, 1, 0, 1) → (0, 1, 0, 0) y first, correct, glitch in Q
(1, 1, 0, 1) → (0, 0, 1, 1) Correct change
→ (0, 1, 0, 0) → (0, 0, 0, 0) x first, incorrect
→ (1, 0, 1, 1) → (0, 0, 1, 1) y first, correct, no glitch
(0, 0, 1, 1) → (1, 1, 1, 1) Correct change
→ (1, 0, 1, 1) → (1, 1, 1, 1) x first, correct, no glitch
→ (0, 1, 1, 0) → (1, 1, 1, 1) y first, correct, glitch in Q
(1, 1, 1 ,1) → (0, 0, 1, 1) Correct change
→ (0, 1, 1, 0) → (0, 0, 0, 0) x first, incorrect
→ (1, 0, 1, 1) → (0, 0, 1, 1) y first, correct, no glitch
(1, 0, 1, 1) → (0, 1, 1, 0) Correct change
→ (0, 0, 1, 1) → (0, 1, 1, 0) x first, correct, no glitch
→ (1, 1, 1, 1) → (0, 1, 1, 0) y first, correct, no glitch
(0, 1, 1, 0) → (1, 0, 0, 0) Correct change
→ (1, 1, 1, 1) → (1, 0, 1, 1) x first, incorrect
→ (0, 0, 0, 0) → (1, 0, 0, 0) y first, correct, no glitch
11.34
a
000
b
111
c
001
d
100
e
010
f
101
g
011
h
110
There is one race for x changing 1 to 0 starting in state
f = (111). The correct next state is g = (011). If P
changes first, then the sequence of states is f = (101) →
c = (001) → g = (101) which is correct. If Q changes
first, then the sequence of states is f = (101) → b =
(111) → g = (101) which is correct. The race is not
critical
124
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Unit 12 Solutions
Unit 12 Problem Solutions
12.1
Consider 3 × Y = Y + Y + Y, that is, we need to add Y to itself 3 times. First, clear the accumulator before the first
rising clock edge so that the X-register is 000000. Let the Ad pulse be 1 for 3 rising clock edges and let the Y register
contain the desired number (y5 y4 y3 y2 y1 y0 ) which is to be added three times. The timing diagram is on FLD p. 755.
Note: ClrN should go to 0 and back to 1 before the first rising clock edge. Ad should be 1 before the same clock
edge. However, it does not matter in what order, that is, Ad could go to 1 before ClrN returns to 1, or even before it
goes to 0.
12.2
Serial input connected to D0 for left shift.
Sh = 0, L = 1 causes a left shift.
Sh = 1, L = 1 or 0 causes a right shift
12.3
See FLD Appendix E for solution.
Serial Out Q
3 Q2 Q1 Q0
SI
4-bit Parallel In
SH
Parallel Out
L
Shift Register
Clock
D3 D2 D1 D0
12.4 (a)
Present
State
DC B A
00 0 0
00 0 1
00 1 0
00 1 1
01 0 0
01 0 1
01 1 0
01 1 1
10 0 0
10 0 1
10 1 0
10 1 1
11 0 0
11 0 1
11 1 0
11 1 1
Next State
D+C+B+A+
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
0 0 0 0
Flip-Flop
Inputs
TDTCTBTA
0 0 0 1
0 0 1 1
0 0 0 1
0 1 1 1
0 0 0 1
0 0 1 1
0 0 0 1
1 1 1 1
0 0 0 1
0 0 1 1
0 0 0 1
0 1 1 1
0 0 0 1
0 0 1 1
0 0 0 1
1 1 1 1
D'
D
TD
C'
C
TC
B'
B
TB
A'
A
TA
1
Clock
As explained in Section 12.3, it can be seen that A changes on every
rising clock edge: TA = 1
B changes only when A = 1: TB = A
C changes only when both B and A = 1: TC = AB
D changes only when A, B, and C = 1: TD = ABC
125
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Unit 12 Solutions
12.4 (b) The binary counter using D flip-flops is obtained
by converting each T flip-flop to a D flip-flop by
adding an XOR gate.
12.5
Equations for C, B, and A are from Equations (122) on FLD p. 383. Beginning with (b) of Problem
12.4 solutions,
D+ = D ⊕ CBA = D'CBA + D(CBA)'
= D'CBA + D(C' + B' + A')
= D'CBA + DC' + DB' + DA'
See FLD p. 755 and Figure 12-15 on FLD p. 386.
12.6
In the following state graph, the first flip-flop (C)
A+
takes on the required sequence 0, 0, 1, 0, 1, 1,
(repeat).
B A
000
110
001
101
100
010
12.7 (a)
CB A
00 0
C+B+A+
C
0
0
0
0
B
0
0
1
1
A
0
1
0
1
1
1
1
1
0
0
1
1
0
1
0
1
C+.B+ A+
0 0 1
1 0 0
1 0 1
X
0
1
0
X
1
1
0
X
0
0
0
+
B
C
0
1
00
1
0
01
0
11
10
TC
B A
C
0
1
00
X
1
01
0
11
10
0
1
01
1
1
X
X
11
X
X
0
0
10
1
0
1
0
01
0
X
X
11
1
0
10
+
B+ = C B'
C + = A + C'B
X X X
C
TA
0
1
00
X
0
0
01
1
0
0
11
1
0
10
TC = C'A' + B'A'
0
0
B+
B A
00
00
B A
C
1
1
A = C'A'
C+
TB
B A
0
0
A+
C
C
XXX
B A
0
1
B A
0
1
00 1 01 1
00 X
0
00 X
0
01 0 11 0
01 1
0
01 0
1
01 1 01 0
11 1
0
11 0
1
10 0 00 1
10 1 10 0
10 1
1
10 1
1
11 0 11 1
+
B = C' + B A'
C + = C A + B A'
11 1 10 1
For D flip-flop: 000 goes to 011 because DCDBDA = 011
12.7 (b)
C+
C
0
1
00
X
1
01
1
0
11
0
1
10
0
1
+
A = C'B' + C B + B'A'
+
A = C'B' + C B + C A'
C
0
1
00
X
1
0
01
0
1
0
1
11
1
0
0
0
10
0
1
TB = C'B' + C B A
B A
C
B A
TA = C'B A + C B' + C A'
For T flip-flop: 000 goes to 110 because TATBTC = 110
126
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Unit 12 Solutions
12.8 (a)
CB A
00 0
0
0
0
1
1
1
1
JC
B A
C
0
1
1
0
0
1
1
1
0
1
0
1
0
1
C+B+A+
XXX
01 1
11 0
01 0
00 1
10 0
11 1
10 1
KC
0
1
00
X
X
01
0
11
10
C+
B A
C
B A
C
1
00
X
1
X
01
X
0
X
11
1
X
10
A+
C
1
0
1
00
X
0
00
X
1
1
01
1
0
01
1
0
0
1
11
1
0
11
0
1
1
1
10
1
1
10
0
1
1
00
X
0
01
0
11
10
B A
B A
C
0
0
JB
0
JC = A'
B+
C
KB
00
X
1
X
01
X
0
1
11
0
0
10
X
X
0
01
X
X
X
11
X
X
10
X
0
0
01
1
X
0
11
X
0
10
B A
B A
C
0
1
00
X
X
X
01
0
1
X
X
11
1
0
0
1
10
X
X
JA = C
KB = C A
JB = C'
KA
1
00
00
C
0
1
1
B A
JA
0
0
KC = B'A'
C
B A
K A = C'B + C B'
In state 000,
JC = A' = 1, KC = B'A' = 1, C+ = C' = 1
JB = C' = 1, KB = CA = 0, B+ = 1
JA = C = 0, KA = CB' + C'B = 0, A+ = A = 0
So the next state is C+B+A+ = 110
12.8 (b)
SC
B A
C
RC
0
1
00
X
0
01
0
11
10
SB
B A
C
RB
0
1
B A
C
SA
0
1
B A
C
1 B A
00
X
0
1
1
X
0
X
0
01
0
1
11
0
X
11
1
0
10
0
1
10
X
0
00
X
1
00
X
0
00
X
X
X
01
X
0
01
1
0
01
0
X
01
0
X
11
X
0
11
X
0
11
0
1
1
X
10
0
0
10
X
X
10
0
0
S B = C'
RB = C A
C
00
1
R C = B'A'
RA
0
0
S C = B A'
B A
C
S A = C A'
R A = C'B + C B'A
S C = C'A'
In state 000,
SC = BA' = 0, RC = B'A' = 1, C+ = 0
SB = C' = 1, RB = CA = 0, B+ = 1
SA = CA' = 0, RA = C'B + C'BA = 0, A+ = A = 0
So the next state is C+B+A+ = 010
127
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Unit 12 Solutions
12.9 (a)
12.9 (b)
Q Q+ M N
}
1 0
1X
1 1}
1 0
X0
0 0}
0 1
X1
1 1}
0 0
0X
01
00
01
10
11
C+
B A
C
MC
0
1
00
0
0
01
0
11
10
B A
C
B A
X
0
0
X
01
X
1
11
1
X
11
X
1
10
X
X
10
X
X
0
1
01
1
1
X
X
MB
NB
C
00
X
X
0
01
X
X
X
X
11
1
0
X
X
10
X
X
00
0
0
0
01
1
1
0
11
X
X
10
0
0
01
1
11
10
C
1
1
00
B A
0
0
1
B A
0
1
00
1
0
01
1
0
11
1
1
10
X
X
B A
C
1
1
1
0
0
NB = C'
MB = C'A
MA
1
1
0
0
0
NC = A
MC = B
NA
0
1
00
1
0
01
X
11
10
B A
C
0
1
00
X
X
X
01
1
0
X
X
11
1
1
X
X
10
X
X
MA = C'
12.10
C
B A
1
1
1
1
0
1
00
A+
0
1
1
1
0
0
1
1
0
0
X
1
0
C
0
0
1
1
1
0
0
B+
A+
C+B+A+
00 1
00
B A
C+
B+
NC
C
CB A
00 0
NA = C' + B
See Lab Solutions for Unit 12 in this manual.
128
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Unit 12 Solutions
12.11
The flip-flops change state only when Ld or Sh = 1. So CE = Sh + Ld. Now only a 2-to-1 MUX is required to select
the input to the D flip-flop.
SI
1
0
D3
Sh
Ld
1
D Q3
0
D2
CE
1
D Q2
CE
0
D1
1
D Q1
CE
0
D0
D Q0
CE
Clk
12.12 (a) When ShLd = 00, the MUX for flip-flop i selects Qi to hold its state
When ShLd = 01, the MUX for flip-flop i selects Di to load.
When ShLd = 10 or 11, the MUX for flip-flop i selects Qi-1 to shift left.
Q3 D
Q1 D
Q2 D
D3
D2
Q0 D
SI
D1
D0
Sh
Ld
Clk
12.12 (b) Q3+ = Ld'Sh'Q3 + LdSh'D3 + ShQ2; Q2+ = Ld'Sh'Q2 + LdSh'D2 + ShQ1; Q1+ = Ld'Sh'Q1 + LdSh'D1 + ShQ0
Q0+ = Ld'Sh'Q0 + LdSh'D0 + ShSI
12.13
Notice that Sh overrides Ld when Sh = Ld = 1
Clock
Sh
Ld
QA
QB
SI = QC
QD
12.14 (a) Similar to problem 12.4 (a),
TE = ABCD. TD, TC, TB and TA
remain unchanged.
E'
E
TE
12.14 (b) Similar to problem 12.4 (b),
DE = E ⊕ DBCA.
DD, DC, DB and DA remain
unchanged.
E'
E
DE
Clk
Clk
A BCD
E
A BCD
129
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 12 Solutions
12.15
4-bit Johnson counter using J-K flip-flops:
J4
Q4
J3
Q3
J2
Q2
J1
Q1
K4
Q'4
K3
Q'3
K2
Q'2
K1
Q'1
CLK
Starting in 0000: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, (repeat) 0000, ...
Starting in 0110: 0110, 1011, 0101, 0010, 1001, 0100, 1010, 1101, (repeat) 0110, ...
12.16
When U = 1, D = 0, add 001. When U = 0, D = 1, subtract 1: add 111.
When U = 0, D = 0, no change: add 000.
U = 1, D = 1, can never occur.
So add the contents of the register to X2 X1 X0, where X2 = X1 = D and
X0 = D + U. (Note: to save the OR gate, let X0 = D and Cin = U.)
Q2 Q1 Q0
D2 D1 D0
Clk
S2 S 1 S0
3-BIT ADDER Cin
Y2 Y1 Y 0 X2 X1 X0
D D
D U
12.17 (a)
A B C D A+B+C+D+
00 0 0 0 0 0 1
00 0 1 0 0 1 0
00 1 0 0 0 1 1
00 1 1 0 1 0 0
01 0 0 0 1 0 1
01 0 1 0 1 1 0
01 1 0 0 1 1 1
01 1 1 1 0 0 0
10 0 0 1 0 0 1
10 0 1 0 0 0 0
10 1 0 XXXX
10 1 1 XXXX
11 0 0
XXXX
11 0 1
XXXX
11 1 0
XXXX
11 1 1
XXXX
DA
C D
A B
00
DB
11
10
00
X
1
01
X
11
01
1
10
A B
00
C D
01
11
00
1
X
01
1
X
X
X
11
X
X
10
C D
A B
00
DD
01
00
01
1
1
11
10
1
1
11
10
1
X
X
X
X
DB = B'C D + B C' + B D'
DA = B C D + A D'
DC
1
10
C D
A B
00
01
11
10
1
1
X
1
X
00
X
01
X
X
X
X
X
X
X
11
X
X
10
DC = A'C'D + C D'
130
1
1
DD = D'
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
0
Unit 12 Solutions
12.17 (b) See Table 12-7 (c) on FLD p. 398.
01
11
10
00
0
0
X
0
0
01
1
1
X
X
X
11
X
X
X
X
10
X
X
01
11
10
00
0
X
X
0
X
01
0
X
X
X
X
11
1
X
X
X
10
0
X
01
11
10
00
0
0
X
X
01
0
0
X
11
0
1
10
0
0
C D
JA = B C D
C D
01
11
10
00
X
X
X
0
01
X
X
X
11
X
X
10
X
X
11
10
00
1
1
X
1
0
01
X
X
X
X
X
X
11
X
X
X
X
X
X
10
1
1
X
X
JD = 1
01
11
10
00
X
X
X
X
X
01
X
X
X
X
X
11
1
1
X
X
10
0
0
01
11
10
00
X
0
X
X
1
01
X
0
X
X
X
11
X
1
X
X
10
X
0
KA = D
01
A B
00
A B
00
C D
A B
00
C D
JC = A'D
JB = C D
A B
00
C D
A B
00
A B
00
A B
00
C D
C D
A B
00
01
11
10
00
X
X
X
X
X
01
1
1
X
1
X
X
11
1
1
X
X
X
X
10
X
X
X
X
C D
KD = 1
KC = D
KB = C D
12.17 (c) See Table 12-5 (c) on FLD p. 395.
SA
C D
A B
00
SB
11
10
00
X
X
01
X
11
01
1
10
C D
A B
00
01
11
00
X
X
01
X
X
X
X
11
X
X
10
1
X
C D
A B
00
RB
01
11
C D
10
C D
A B
00
01
X
X
11
X
X
10
11
10
C D
X
X
1
01
X
X
X
01
X
X
11
X
X
11
X
X
10
X
X
10
X
X
01
X
X
X
11
X
10
X
RA = C'D
1
1
X
1
X
X
A B
00
X
X
01
11
10
C D
A B
00
RB = B C D
00
X
1
11
10
1
X
1
00
X
01
X
X
X
X
X
11
10
X
X
11
X
X
10
1
01
X
1
1
SD = D'
SC = A'C'D
RC
01
SD
00
00
00
X
10
A B
00
SB = B'C D
SA = B C D
RA
SC
RD
A B
00
01
11
10
X
X
X
X
X
01
1
1
X
1
X
X
11
1
1
X
X
X
X
10
X
X
1
RC = C D
C D
01
00
X
RD = D
RA = A D
RA = B'D
131
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 12 Solutions
12.17 (d) See Table 12-4 on FLD p. 391.
TA
C D
A B
00
TB
01
11
00
X
01
X
11
1
10
10
C D
A B
00
TC
01
11
00
X
1
01
X
X
X
11
X
X
10
TA = B C D + A D
1
1
10
TD
A B
00
C D
01
00
11
10
11 0 0
XXXX
11 0 1
XXXX
11 1 0
XXXX
11 1 1
XXXX
01
11
10
X
00
1
1
X
1
01
1
1
X
1
1
1
X
1
1
X
X
11
1
1
X
X
X
X
10
1
1
X
X
X
X
11
X
X
10
TB = C D
TD = 1
TC = A'D
1110
1000
0111
1111
1001
0000
0001
0110
0101
0100
1010
A B C D A+B+C+D+
00 0 0 1 0 0 1
00 0 1 0 0 0 0
00 1 0 0 0 0 1
00 1 1 0 0 1 0
01 0 0 0 0 1 1
01 0 1 0 1 0 0
01 1 0 0 1 0 1
01 1 1 0 1 1 0
10 0 0 0 1 1 1
10 0 1 1 0 0 0
10 1 0 XXXX
10 1 1 XXXX
A B
00
01
12.17 (e) Use equations to find next states for unused states.
State 1101:
JA = BCD = 0, KA = D = 1, A+ = 0
JB = CD = 0, KB = CD = 0, B+ = B = 1
JC = A'D = 0, KC = D = 1, C+ = 0
JD = 1, KD = 1, D+ = D' = 0
So the next state is 0100. Other next states can be found
in a similar way.
12.18
C D
1011
0010
0011
1101
1100
12.18 (a) DA = A'B'C'D' + AD;
DB= BD + BC + AD';
DC = CD + BC'D' + AD';
DD = D'
12.18 (b) JA = B'C'D', KA = D';
JB = AD', KB = C'D';
JC = BD' + AD', KC = D';
JD = 1, KD = 1
12.18 (c) SA = A'B'C'D', RA = AD';
SB = AD', RB = BC'D' or A'C'D';
SC = BD'C' + AD', RC = CD',
SD = D', RD = D
12.18 (d) TA = B'C'D';
TB = BC'D' + AC'D';
TC = CD' + BD' + AD';
TD = 1
12.18 (e)
0010
1101
132
1100
0011
1011
1010
1111
1110
0001
0000
1001
0100
0101
0110
1000
0111
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 12 Solutions
12.19 (a)
Since J0 = K0 = 1, Q0 toggles when Clk
changes 1 to 0.
Q1 clears if Q3 = 1 and toggles if Q3 = 0 when
Q0 changes 1 to 0.
Since J2 = K2 = 1, Q2 toggles when Q1
changes 1 to 0.
Q3 clears if Q1 = 0 or Q2 = 0 and toggles if Q1
= Q2 = 1 when Q0 changes 1 to 0.
12.19 (b)
0000
0001
0111
0101
0001
1001
0110
0100
0011
1000
0111
0101
0010
1001
0011
0111
0011
0000
0001
12.19 (b)
cont.
1000
0100
0101
0000
0100
0110
1001
0010
0000
0111
1000
0011
0010
0110
1100
Q3
Q2 Q1
00
0
1
0-
01
Q3
Clk
0
1
--
1-
-1
--
--
01
0-
--
11
-1
--
11
0-
--
10
--
1-
10
0-
--
0
1
1-
--
-1
--
01
11
-1
--
10
1-
--
J
Q
Clk
K
Q0
J3 = Q2′Q1′
K3 = 1
J2 = K2 = 1
J
Q
Q1
J
K
Q
Clk
Clk
Q'
Q3
Q2 Q1
00
Q2 Q0
00
J1 = Q3 + Q2
K1 = 1
1
Q0 must toggle when Clk changes 1 to 0.
Q1 clears if Q3 = Q2 = 0 and toggles if Q3 = 1
or Q2 = 1 when Q0 changes 0 to 1.
Q2 toggles when Q1 changes 0 to 1.
Q3 clears if Q1 = 1 or Q2 = 1 and toggles if Q1
= Q2 = 0 when Q0 changes 1 to 0.
These results can be derived by constructing
Karnaugh maps for the J and K inputs; see below.
K
Q'
133
Q2
J
Q
Q3
Clk
Q'
K
Q'
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 12 Solutions
12.20
A B C A+B+C+
00 0 X XX
00 1 1 0 0
01 0 0 1 1
01 1 0 0 1
10 0 1 0 1
10 1 1 1 1
11 0 0 1 0
11 1 1 1 0
12.21(a) ABCD
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
DADBDCDD
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
1 0 1 1
x x x x
x x x x
x x x x
x x x x
x x x x
x x x x
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
0 0 0 0
12.20 (a) DA = B' + AC; DB = AC + BC'; DC = A'B + AB'
12.20 (b) JA = B', KA = BC'; JB = AC, KB = A'C; JC = A' + B', KC = A'B' + AB
12.20 (c) TA = A'B' + ABC'; TB = A'BC + AB'C; TC = A'B' + A'C' + B'C' + ABC
12.20 (d) SA = B', RA = BC'; SB = AC, RB = A'C; SC = A'B + AB', RC = A'B' + AB
12.20 (e) State 000 goes to 100, because DADBDC = 100.
DA = AB' + A D' + BC' or
= AB' + B D' + BC' or
= AB' + AC' + BD'
DB = B'CD + A D' + AC'
DC = C'D + CD' + A'B
DD = D'
134
12.21(b) ABCD
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
JAKA, JBKB, JCKC, JDKD
0x, 0x, 0x, 1x
0x, 0x, 1x, x1
0x, 0x, x0, 1x
0x, 1x, x1, x1
1x, x1, 1x, 1x
xx, xx, xx, xx
xx, xx, xx, xx
xx, xx, xx, xx
xx, xx, xx, xx
xx, xx, xx, xx
xx, xx, xx, xx
x0, 1x, x1, x1
x0, x0, 0x, 1x
x0, x0, 1x , x1
x0, x0, x0, 1x
x1, x1, x1, x1
JA = B
KA = BCD
JB = CD
KB = A' + CD
JC = D + A'B
KC = D
JD = 1
KD = 1
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 12 Solutions
12.21(c)
ABCD
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
12.22(a) DA =
DB =
=
=
DC =
DD =
TA TB TC TD
0 0 0 1
0 0 1 1
0 0 0 1
0 1 1 1
1 1 1 1
x x x x
x x x x
x x x x
x x x x
x x x x
x x x x
0 1 1 1
0 0 0 1
0 0 1 1
0 0 0 1
1 1 1 1
TA =
TB =
TC =
TD =
12.21(d) ABCD
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
A'B + BCD
CD + A'B
D + A'B
1
SARA, SBRB, SCRC, SDRD
0x, 0x, 0x, 10
0x, 0x, 10, 01
0x,
0x, x0, 10
0x, 10, 01, 01
10, 01, 10, 10
xx, xx, xx, xx
xx, xx, xx, xx
xx, xx, xx, xx
xx, xx, xx, xx
xx, xx, xx, xx
xx, xx, xx, xx
x0, 10, 01, 01
x0, x0, 0x, 10
x0, x0, 10, 01
x0, x0, x0, 10
01, 01, 01, 01
SA = A'B or
= BC' or
= BD'
RA = BCD
SB = B'CD
RB = BCD + A'C' or
= BCD + A'D' or
= BCD + A'B
SC = C'D + A'B
RC = CD
SD = D'
RD = D
12.22(b) JA = (B)
KA = (B)(C)(D )
JB = (C )(D)
KB = (A'+ D)(A'+ C) or
= (A'+ C)(C'+ D) or
= (A'+ D)(C + D')
JC = (B + D)(A'+ D)
KC = (D)
JD = (1)
KD = (1)
(B'+ C'+ D')(A + B)
(B'+ C'+ D')(A + D)(A + C) or
(B'+ C'+ D')(B + D)(A + C) or
(B'+ C'+ D')(B + C)(A + D)
(B + C + D)(C'+ D')(A'+ C + D)
(D')
12.22(c) TA = (B)(A'+ D)(A'+ C) or
= (B)(A'+ C)(C'+ D) or
= (B)(A'+ D)(C + D')
TB = (A'+ D)(B + D)(C + D')
or = (B + C)(A'+ C)(C'+ D)
TB = (B + D)(A'+ D)
TB = (1)
12.22(d) SA = (B)(D') or
= (B)(C') or
= (B)(A')
RA = (B)(C)(D )
SB = (C)(D)(B')
RB = (B )(A'+ D)(A'+ C) or
= (B )(A'+ C)(C'+ D) or
= (B )(A'+ D)(C + D')
SC = (B + D )(C')(A'+ D)
RC = (C)(D)
SD = (D')
RD = (D)
135
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 12 Solutions
12.23(a)
ABCD
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
DADBDCDD
x x x x
x x x x
x x x x
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
0 0 1 1
x x x x
x x x x
x x x x
DA =
DB =
DC =
DD =
BCD + AB'
B'CD + A'D' + A'C'
C'D + CD' + AB
D'
12.23(c)
ABCD
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
TA TB TC TD
x x x x
x x x x
x x x x
0 1 1 1
0 0 0 1
0 0 1 1
0 0 0 1
1 1 1 1
0 0 0 1
0 0 1 1
0 0 0 1
0 1 1 1
1 1 1 1
x x x x
x x x x
x x x x
TA =
TB =
TC =
TD =
AB + B C D
CD + AB
D + AB
1
12.23(b) ABCD
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
12.23(d) ABCD
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
136
JAKA, JBKB, JCKC, JDKD
xx, xx, xx, xx
xx, xx, xx, xx
xx, xx, xx, xx
0x, 1x, x1, x1
0x, x0, 0x, 1x
0x, x0, 1x, x1
0x, x0, x0, 1x
1x, x1, x1, x1
x0, 0x, 0x, 1x
x0, 0x, 1x, x1
x0, 0x, x0, 1x
x0, 1x, x1, x1
x1, x1, 1x, 1x
xx, xx, xx, xx
xx, xx, xx, xx
xx, xx, xx, xx
SARA, SBRB, SCRC, SDRD
xx, xx, xx, xx
xx, xx, xx, xx
xx, xx, xx, xx
0x, 10, 01, 01
0x, x0, 0x, 10
0x, x0, 10, 01
0x, x0, x0, 10
10, 01, 01, 01
x0, 0x, 0x, 10
x0, 0x, 10, 01
x0, 0x, x0, 10
x0, 10, 01, 01
01, 01, 10, 10
xx, xx, xx, xx
xx, xx, xx, xx
xx, xx, xx, xx
JA = BCD
KA = B
JB = CD
KB = A + CD
JC = D + AB
KC = D
JD = 1
KD = 1
SA =
RA =
=
=
SB =
RB =
=
=
SC =
RC =
SD =
RD =
BCD
BC' or
BD' or
AB
B'CD
BCD + AC' or
BCD + AD' or
BCD + AB
C'D + AB
CD
D'
D
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 12 Solutions
12.24(a) DA = (A + B)(B'+ D)(A + C) or
= (A + B)(B'+ C)(A + D) or
= (A + B)(B'+ D)(B'+ C)
DB = (B'+ C'+ D')(A'+ D)(B + C) or
= (B'+ C'+ D')(A'+ C)(B + D) or
= (B'+ C'+ D')(A'+ D)(A'+ C)
DC = (A + C + D)(C'+ D')(B + C + D)
DD = (D')
12.24(b) JA = (B)(C)(D)
KA = (B)
JB = (C)(D)
KB = (C'+ D)(A + C) or
= (A + D)(A + C) or
= (C + D')(A + D)
JC = (A + D)(B + D)
KC = (D)
JD = (1)
KD = (1)
12.24(c) TA = (B)(C'+ D)(A + C) or
= (B)(A + D )(A + C) or
= (B)(C + D')(A + D)
TB = (C + D')(B + D)(A + D) or
= (C'+ D )(A + C)(B + C)
TB = (A + D)(B + D)
TB = (1)
12.26
12.24(d) SA = (B)(C)(D)
SC = (A + D)(C')(B + D)
RA = (B)(A) or
RC = (C)(D)
= (B)(D') or
SD = (D')
= (B)(C')
RD = (D)
SB = (B')(C)(D)
RB = (B)(C'+ D)(A + C) or
= (B)(A + D)(A + C) or
= (B)(C + D')(A + D)
12.25
(a) The counter must clear on the next clock edge
when the count is 1011 so ClrN = (Q3Q1Q0)'.
(b) The counter must clear when the count reaches
1100 so ClrN = (Q3Q2)'.
137
Q3Q2Q1Q0 ClrN Ld
0000
1 0
0001
1 0
0010
1 0
0011
1 0
0100
1 1
0101
x x
0110
x x
0111
x x
1000
x x
1001
x x
1010
x x
1011
1 0
1100
1 0
1101
1 0
1110
1 0
1111
1 0
The transition from state 1111 to state 0000 can be
effected using Clear, Parallel Load or increment.
The latter gives the simplest equations. Then ClrN
= 1, Ld = Q3'Q2, and P3P2P1P0 = 1011.
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 12 Solutions
12.27
(a)
(b) There are two answers:
Sin = Q2 ⊕ Q3 or
Sin = Q0 ⊕ Q3.
001
011
100
000
111
110
12.28
010
(c) The state 0000 can
only occur between states
0001 and 1000. The
resulting Karnaugh map
for the Sin = Q2 ⊕ Q3 case
is shown below.
12.27 (c) S
in
(cont.)
Q0Q1
00
Q2Q3
01
11
10
00
1
0
0
0
01
0
1
1
1
11
0
0
0
0
10
1
1
1
1
Sin = Q2Q3' + Q0Q2'Q3 + Q1Q2'Q3 + Q0'Q1'Q3'.
If the circuit for Sin = Q0 ⊕ Q3 is modified, then
Sin = Q0Q3' + Q0'Q1Q3 + Q0'Q2Q3 + Q1'Q2'Q3'.
101
12.29 (a) Skips all 1’s: Dn = Q2′Q1′
(a) 000, 100, 110, 111, 011, 001
010, 101.
(b)Skips all 0’s:
Dn = Q2′ + Q1′
(b) 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001
0010, 1001, 0100, 1010, 1101, 0110, 1011, 0101.
(c) 00000, 10000, 11000, 11100, 11110, 11111, 01111, 00111, 00011, 00001
01010, 10101
00010, 10001, 01000, 10100, 11010, 11101, 01110, 10111, 01011, 00101
00100, 10010, 11001, 01100, 10110, 11011, 01101, 00110, 10011, 01001
12.30
(a) The changed transition is (QnQn-1 ... Q2Q1) = (11 ... 10) → (01 ... 11): Jn = Q1′, Kn = Q2
(b) The changed transition is (QnQn-1 ... Q2Q1) = (00 ... 01) → (10 ... 00): Jn = Q2′, Kn = Q1
12.31 (a) All stages toggle the same as for a binary counter
except when the count becomes 1001, in which
case stages Q0, Q1 and Q2 respond the same as
for a binary counter, but Q3 must toggle (reset).
Taking into account the don’t cares, the equations
become
J0 = K0 = 1
J1 = K1 = Q0
J2 = K2 = Q0Q1
J3 = Q0Q1Q2
K3 = Q0Q1Q2 + Q0Q3
12.31 (c) To create a design that can be cascaded, we need
to add a count enable input, CE, which is ANDed
with the above equations, and terminal count
output, TE, such as TE = CE(Q2Q3). TE would be
connected to CE of the next counter.
138
12.31 (b) All stages toggle the same as for a binary counter
for counts 0011 through 1011. For count 1100
stages 3 and 2 must reset and stage 1 must set
while stage 0 toggles as it does it does for a binary
counter. Taking into account the don’t cares, the
equations become
J0 = K0 = 1
J1 = Q0 + Q2Q3
K1 = Q0
J2 = Q0Q1
K2 = Q0Q1 + Q2Q3
J3 = Q0Q1Q2
K3 = Q0Q1Q2 + Q2Q3
K3 can be further simplified to K3 = Q2Q3.
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 12 Solutions
12.32 (a) UABC
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
SARA
10
0x, x1
0x, x1
0x, x1
x1
x0
x0
x0
0x, x1
0x, x1
0x, x1
10
x0
x0
x0
x1
SBRB
10
0x, x1
x1
x0
10
0x, x1
x1
x0
0x, x1
10
x0
x1
0x, x1
10
x0
x1
SCRC
10
x1
10
x1
10
x1
10
x1
10
x1
10
x1
10
x1
10
x1
SA
BC
RA
BC
UA
00
01
11
10
00
1
X
X
X
01
X
X
X
X
11
X
X
X
1
10
0
X
X
0
00
01
11
10
00
0
1
0
1
01
1
0
0
1
11
1
0
1
0
10
X
0
0
X
UA
SA = B' + C
RA = UABC
+ U'AB'C'
+ U'A'C
+ UA'B'
Another solution for the A FF:
SA = B + C'
RA = UABC + U'AB'C' + U'A'B + UA'C'
SB
BC
SC
BC
UA
RB
00
01
11
10
00
1
1
X
X
01
X
X
1
1
11
X
X
X
X
10
X
X
X
X
UA
BC
SB = 1
RC
UA
00
01
11
10
00
0
0
1
1
01
1
1
0
0
11
0
0
1
1
10
1
1
0
0
00
01
11
10
UA
00
01
11
10
00
1
1
1
1
00
0
0
0
0
01
X
X
X
X
01
1
1
1
1
11
X
X
X
X
11
1
1
1
1
10
1
1
1
1
10
0
0
0
0
BC
SC = 1
139
RB = U'B'C
+ U'BC'
+ UB'C'
+ UBC
RC = C
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 12 Solutions
12.32 (b) UABC
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
CEADA
11
0x, 10
0x, 10
0x, 10
10
0x, 11
0x, 11
0x, 11
0x, 10
0x, 10
0x, 10
11
0x, 11
0x, 11
0x, 11
10
CEBDB
11
0x, 10
10
0x, 11
11
0x, 10
10
0x, 11
0x, 10
11
0x, 11
10
0x, 10
11
0x, 11
10
CECDC
11
10
11
10
11
10
11
10
11
10
11
10
11
10
11
10
CEA
BC
DA
BC
UA
00
01
11
10
00
1
1
0
0
01
0
0
0
0
11
0
0
1
1
10
0
0
0
0
CEA = UBC + U'B'C'
UA
00
01
11
10
00
1
0
X
X
01
X
X
X
X
11
X
X
0
1
10
X
X
X
X
DA = A'
CEB
DB
01
11
10
00
1
1
X
X
1
01
X
X
1
1
1
1
11
X
X
0
0
0
0
10
0
0
X
X
01
11
10
00
1
1
0
0
01
0
0
1
11
0
0
10
1
1
CEC
BC
CEB = U'C' + UC
UA
UA
00
00
BC
BC
UA
DC
00
01
11
10
00
1
1
1
1
01
1
1
1
11
1
1
10
1
1
BC
DB = B'
UA
00
01
11
10
00
1
1
1
1
1
01
0
0
0
0
1
1
11
0
0
0
0
1
1
10
1
1
1
1
CEC = 1
DC = C'
140
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 12 Solutions
12.33 (a)
Present
State
AB
00
Next State
Present
State
01
01
11
xx
10
10
01
10
00
10
xx
11
00
xx
xx
xx
10
11
xx
01
00
Present
State
MN =
00
JB KB
11
10
1x
1x
xx
0x
01
x1
x1
x1
xx
11
x1
xx
xx
xx
10
1x
xx
JB = M' + N KB = 1
1x
0x
MN =
00
JA KA
01
11
10
0x
0x
xx
1x
01
1x
0x
1x
xx
11
x1
xx
xx
xx
x1
x1
AB
00
10
x0
xx
JA = M + N'B KA = M + B
12.33 (b)
01
AB
00
12.34
MN =
00
01
Present
State
AB
00
O0 O1
MN =
00
01
11
10
00
00
01
10
01
01
01
10
00
11
11
01
10
00
01
10
10
10
00
O1 = M'N'A + MNB + MN'B'
O0 = M'B + MNB'
Since the FFs are changing on the negative edge of the clock, the pulses must be concident with positive portions
of the clock. Assuming the clock is symmetrical, the FFs’ propagation delay must be less than half of the clock
period.
(a) The ring counter requires 8 stages: Q0, Q1, …, Q7 and Ti = (Clk)Qi for i = 0, 1, …, 7.
(b) The Johnson counter requires 4 stages: Q0, Q1, Q2, Q3. The count sequence will be 0000, 1000, 1100, 1110,
1111, 0111, 0011, 0001. Then T0 = (Clk)Q0'Q3', T1 = (Clk)Q0Q1', T2 = (Clk)Q1Q2', T3 = (Clk)Q2Q3',
T4 = (Clk)Q0Q3, T5 = (Clk)Q0'Q3, T6 = (Clk)Q1'Q3, T7 = (Clk)Q2'Q3.
(c) The binary counter requires 3 stages: Q0, Q1, Q2. The count sequence will be 000, 001, 010, 011, 100, 101,
110, 111. Then T0 = (Clk)Q0'Q1'Q2', T1 = (Clk)Q0'Q1'Q2, T2 = (Clk)Q0'Q1Q2', T3 = (Clk)Q0'Q1Q2,
T4 = (Clk)Q0Q1'Q2', T5 = (Clk)Q0Q1'Q2, T6 = (Clk)Q0'Q1Q2, T7 = (Clk)Q0Q1Q2.
12.35 (a)
Q
0
UV
= 00
0
1
1
+
Q = U'Q + VQ'
UV
= 01
x
UV
= 11
1
UV
= 10
0
x
0
0
12.35 (c)
12.35 (b)
Q Q+
00
UV
x0
01
11
10
1x
11
00
Q+
Q
0
AB
= 00
0
AB
= 01
0
AB
= 11
1
AB
= 10
1
1
0
1
1
1
141
Q
0
AB
= 00
x0
1
1x
U = A'B' + Q'
V = AQ'
U V
AB
AB
= 01
= 11
x0
11
00
AB
= 10
11
00
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
00
Unit 12 Solutions
12.36 (a)
12.36 (b)
Q+
Q
MF
= 00
1
0
MF
= 01
1
MF
= 11
0
MF
= 10
x
0
0
x
1
1
Q+ = F' + Q'M'
12.36 (c)
Q Q+
00
MF
11
01
0x
10
x1
11
00
Q+
Q
MF
0
CD
= 00
0
CD
= 01
1
CD
= 11
1
CD
= 10
0
1
0
0
1
1
12.37 (a) Q Q+
}
0 0
X0
1 0}
1 0
}1X
11
0 0
0X
0 1}
0 1
X1
11
01
10
11
0
11 1
CD
= 00
11
CD
= 01
0x
CD
= 11
0x
CD
= 10
11
x1
00
00
1
x1
M = D'Q'
F = C' + Q'
12.37 (b) A B C A+B+C+
00 0 1 0 0
00 1 0 0 0
01 0 X XX
01 1 0 0 1
10 0 1 0 1
10 1 1 1 1
11 0 X XX
LM
00
Q
A+
B C
A
B+
0
1
00
1
1
01
0
11
10
B C
A
C+
0
1
00
0
0
1
01
0
0
0
11
X
X
10
B C
A
0
1
00
0
1
1
01
0
1
0
1
11
1
1
X
X
10
X
X
0
1
0 1 1
12.37 (b) LA = B, MA = C; LB = A', MB = A' + C'; LC = A'B',
(cont.) MC = A'
B C
A
0
1
00
X
0
01
X
11
10
A
0
1
00
0
X
0
01
1
X
1
11
X
X
10
LA = B
B C
A
1
00
1
1
X
01
1
1
0
11
X
X
10
1
00
X
X
X
01
X
1
X
11
X
X
10
LB = A'
142
B C
A
0
0
MA = C
B C
A
B C
A
0
1
00
X
X
00
1
0
0
01
1
0
01
X
X
X
X
11
0
0
11
X
X
X
X
10
X
X
10
X
X
MB = A' + C'
B C
LC = A'B'
MC = A'
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 12 Solutions
12.38
12.39
AB CD
00 0 0
A+B+C+D+
0 0 1 1
JA KA JB KB JC KC JD KD
00 0 1
0 1 0 0
0 X 1 X 0 X X 1
00 1 0
0 1 0 1
0 X 1 X X 1 1 X
00 1 1
0 1 1 0
0 X 1 X X 0 X 1
01 0 0
0 1 1 1
0 X X 0 1 X 1 X
01 0 1
1 0 0 0
1 X X 1 0 X X 1
01 1 0
1 0 0 1
1 X X 1 X 1 1 X
01 1 1
1 0 1 0
1 X X 1 X 0 X 1
10 0 0
1 0 1 1
X 0 0 X 1 X 1 X
10 0 1
1 1 0 0
X 0 1 X 0 X X 1
10 1 0
1 1 0 1
X 0 1 X X 1 1 X
10 1 1
1 1 1 0
X 0 1 X X 0 X 1
11 0 0
1 1 1 1
X 0 X 0 1 X 1 X
11 0 1
XXXX
X X X X X X X X
11 1 0
XXXX
X X X X X X X X
11 1 1
XXXX
X X X X X X X X
Clock
Cycle
0
1
2
3
4
5
6
0 X 0 X 1 X 1 X
Using Karnaugh maps:
JA = A + BD + BC, KA = 0; JB = C + D, KB = C + D;
JC = D', KC = D'; JD = 1, KD = 1
Input
Accumulator
Data EnIn EnAd LdAc LdAd
Register
18
1
0
1
0
0
13
1
0
0
1
18
15
0
1
1
0
18
93
1
0
0
1
31
47
0
1
1
0
31
22
1
0
0
1
124
0
0
1
0
0
124
Addend
Register
0
0
13
13
93
93
22
Bus
18
13
31
93
124
22
146
Description
Input to accumulator
Input to addend
Sum to accumulator
Input to addend
Sum to accumulator
Input to addend
Sum on bus
Note: Register values change after the clock edge. So a value loaded from the bus appears in the register on the next
clock cycle after the load signal and bus value are present.
143
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 12 Solutions
12.40
(a), (b)
8
E 0'
CE
En
Ck
A
8
X
E0
8
8 NAND gates
Y
8
8
8
R
CE
En
Ck
G0
G1
B
8
Ck
CE
En
C
Ck
CE
En
8
E1
D
8
E2
E 1'
E 2'
2-to-4
decoder
E 1'
E2
12.40 (c) Call the values beginning in the A & D registers X and Y, respectively. We want C = X + Y = (X'Y')'. Invert using
M' = 1 NAND M. To invert a value on the right side, in register C or D, we will need a 1 on the left side, in register A
or B. This can be accomplished using 1 = 0 NAND (anything.)
There are several solutions using different registers. Here is an example:
Clock
Cycle G0G1
1
00
E0
0
E1E2
Description
1 1 1 NAND A = A' = X' → A
2
01
1
10
0 NAND B = 1 → B
3
11
1
01
B NAND D = 1 NAND Y = Y' → D
4
10
0
01
A NAND D = X' NAND Y' = X + Y → C
Alternate three-cycle solution:
Use X + Y = X + X'Y = (X' (X'Y)')'
Clock
Cycle G0G1
1
00
E0
0
E1E2
Description
1 1 1 NAND A = A' = X' → A
2
11
0
01
A NAND D = (X'Y)' → D
3
10
0
01
A NAND D = (X' (X'Y)')' = X + Y → C
12.41 (a) For bit reversal using the D inputs of the shift
register: Sh = 0, Ld = 1
Ld
Sh
SI
Clk
Q3
Q2
Q1
Q0
D3
D2
D1
D0
144
12.41 (b) Same as Figure 12-10 (b) on FLD p. 382, except
that for the "11" input of each MUX, instead of SI,
Q3, Q2, or Q1, use Q0, Q1, Q2, or Q3, respectively.
Also, replace Sh with A and Ld with B.
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 13 Solutions
13.2
Unit 13 Problem Solutions
Notice that this is a shift register. At each falling clock edge, Q3 takes on the value Q2 had right before the clock edge,
Q2 takes on the value Q1 had right before the clock edge, and Q1 takes on the value X had right before the clock edge.
For example, if the initial state is 000 and the input sequence is X = 1100, the state sequence is = 100, 110, 011, 001,
and the output sequence is Z = (0)0011. Z is always Q3, which does not depend on the present value of X. So it’s a
Moore machine. See FLD p. 758 for the state graph.
13.3 (a) A+ = AKA' + A'JA= A (B' + X) + A'(BX' + B'X)
B + = B'JB + BKB' = AB'X + B (A' + X')
Z = AB
A+
B+
X
AB
0
1
00
0
0
0
01
1
1
1
11
1
0
0
1
00
0
1
01
1
11
0
10
1
X
AB
10
1
0
Present
State
Next State
A+B +
AB
X=0 X=1
00
10
11
01
01
10
10
11
00
01
11
10
0
1
0
13.3 (b) X =
0 1 1 0 0
AB = 00 00 10 11 01 11
Z = (0) 0 0 1 0 1
1
00
0
1
10
0
Z
0
0
1
0
0
11
1
1
0
01
0
1
13.3 (c) See FLD p. 758 for solution.
13.4 (a)
Q2 Q3
X Q1
Q2 Q3
X Q1
00
Q2 Q3
X Q1
00
11
10
1
1
1
1
00
01
1
1
1
1
1
11
0
0
1
0
10
0
0
1
11
10
0
0
0
0
00
01
1
1
1
1
0
11
1
1
1
1
10
0
0
0
01
11
10
00
0
0
0
0
00
01
0
0
0
0
11
0
0
0
10
1
1
1
Q1+ = D1
X Q1
00
01
01
00
Q2+ = D2
Q3+ = D3
Q2 Q3
01
11
10
0
0
1
1
01
0
0
1
1
1
11
1
1
0
0
1
10
1
1
0
0
Z
Z depends on the input X, so this is a Mealy machine. Because there are more than 2 state variables, we cannot put
the state table in Karnaugh Map order (i.e. 00, 01, 11, 10), but we can still read the next state and output from the
Karnaugh map. For example, when the input is X = 1 and the state is Q1Q2Q3 = 110, we can read the next state and
output from the XQ1Q2Q3 = 1110 position in the Karnaugh maps for Q1+, Q2+, Q2+, and Z. So in this case, the next state
is Q1+Q2+Q3+ = 101 and the output is Z = 0. The entire table can be derived from the Karnaugh maps in this manner.
Note: We can also fill in the state table directly from the equations, without using Karnaugh maps. See FLD p. 758
for the state table and state graph.
13.4 (b - d) See FLD p. 759 for solutions.
145
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 13 Solutions
13.5 (a) Mealy machine, because the output, Z, depends on
the input X as well as the present state.
13.5 (b)
Z
BC
13.5 (c - d) See FLD p. 759 for solutions.
XA
00
01
11
10
00
1
1
0
0
01
1
1
0
0
11
0
0
1
1
10
0
0
1
1
Note: Not all Karnaugh map entries are needed.
See FLD p. 759 for the state table.
13.6 (a) After a rising clock edge, it takes 4 ns for the flip-flop outputs to change. Then the ROM will take 8 ns to respond to
the new flip-flop outputs. The ROM outputs must be correct at the flip-flop inputs for at least the setup time of 2 ns
before the next rising clock edge. So the minimum clock period is (4 + 8 + 2) ns = 14 ns.
13.6 (b) The correct output sequence is 0101. See FLD p. 760 for the timing diagram.
13.6 (c) Read the state transition table from ROM truth table. See FLD p. 760 for the state graph and table.
Present
State
Q1Q2
00
01
10
11
Next State
Q +Q +
1
2
Z
X=0 X=1 X=0 X=1
10
10
0
0
00
11
0
0
11
01
0
1
01
11
1
1
Alternate solution: Using Karnaugh map order, swap states S2 and S3 in the graph and table.
13.7 (a) Q + = J Q ' + K 'Q = XQ ' + XQ 'Q
1
1 1
1 1
1
2 1
Q2+ = J2Q2' + K2'Q2 = XQ2' + XQ1Q2
Z = X'Q2' + XQ2
Present
State
Q1Q2
00
01
11
10
Next State
Q +Q +
1
2
Z
X=0 X=1 X=0 X=1
00
11
1
0
00
10
0
1
00
01
0
1
00
11
1
0
13.7 (b)
Clock
X
Q1
Q2
13.7 (c) Z = 00011
false
146
{
{
Z
false
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 13 Solutions
13.8 (a) Q + = J Q ' + K 'Q = XQ 'Q ' + X'Q
1
1 1
1 1
2 1
1
Q2+ = J2Q2' + K2'Q2 = X Q1Q2' + X'Q2
Z = XQ2' + X'Q2
Present
State
Q1Q2
00
01
11
10
0
1
1
S3
0
Z
2
X=0 X=1 X=0 X=1
00
10
0
1
01
00
1
0
11
00
1
0
10
01
0
1
0
13.8 (b)
1
0
S1
1
0
S0
1
Next State
Q +Q +
1
0
1
1
0
S2
1
0
Clock
X
Q1
Q2
13.8 (c) Z = 10110
S0
S1
S3
S2
Q1Q2
00
01
11
10
Next State
00
00
11
11
10
00, 01, 10
01
01
11
10
10
11
01
01
10
00
Z
10
00
11
10
00
11
0
0
0
1
X1
X2
Q1
Q2
Z
S1
0
0
13.9 (c) Z = (0)000110
00, 01, 10
00, 01
01, 10, 11
S3
0
1
00
10, 11
13.10(a) Q1+ = D1 = X1X2Q1 + Q1Q2 + X2Q2
Q2+ = D2 = (X1' + X2')Q2 + (X1 + X2)Q1'
Z = Q1Q2'
State
Present
State
S0
S1
S3
S2
Q1Q2
00
01
11
10
00
S0
X1X2 =
01
11
01
01
11
11
11
10
00
10
01, 10, 11
0
Next State
00
00
01
11
00
00, 10
Z
10
01
01
11
00
147
0
0
0
1
0
00, 01, 10
S2
1
11
S1
11
01, 11
S3
0
00, 01, 10
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
{
1
Clock
11
S0
S2
X1X2
1
13.9 (b)
13.9 (a) Q1+ = D1 = (X1' + X2' + Q1)(Q1 + Q2)(X1' + Q2)
Q2+ = D2 = (X1'X2' + Q1')(X1X2 + Q2)
Z = Q1Q2'
Present
State
0
{
1
State
{
{
{
Z
0
Unit 13 Solutions
13.10(b)
13.10(c)
Clock
Z = (0)000110
X1
X2
Q1
Q2
Z
13.11 (a) Notice that Z depends on the input X, so this is a
Mealy machine.
Q1+ = J1Q1' + K1'Q1 = XQ1'Q2 + X'Q1
Q2+ = J2Q2' + K2'Q2 = XQ1'Q2' + X'Q2
Z = Q2 ⊕ X = XQ2' + X'Q2
State
Present
State
S0
S1
S2
S3
Q1Q2
00
01
11
10
Next State
Q +Q +
1
Z
2
Q1 Q2
X
0
1
00
0
0
01
0
11
10
Q1 Q2
X
0
1
00
0
1
1
01
1
1
0
11
1
0
10
Q1+
X=0 X=1 X=0 X=1
00
01
0
1
01
10
1
0
11
00
1
0
10
00
0
1
Q1 Q2
X
0
1
00
0
1
0
01
1
0
1
0
11
1
0
0
0
10
0
1
Z
Q2+
Alternate solution: Swap states S2 and S3.
0
S2
1
0
1
0
1
0
0
S3
13.11
(b)
0
Clock
X
Q1
S0
1
1
1
0
1
0
S1
Q2
Z
1
{
13.11 (a)
(cont.)
false
Correct output: Z = 11101
13.12(a) Notice that Z does not depend on either input, so
this is a Moore machine.
Q1+ = X1X2Q1 + Q1Q2 + X1Q2
Q2+ = Q1' (X1 + X2) + Q2 (X1' + X2')
= X1Q1' + X2Q1' + X1'Q2 + X2'Q2
Z = Q1Q2'
Q
Q2
1
0
1
0
0
1
1
0
0
Q1 Q2
X1 X2
00
01
11
10
Q1 Q2
X1 X2
00
01
11
10
00
0
0
0
0
00
0
1
1
1
01
0
0
1
1
01
1
1
1
1
11
1
1
1
1
11
1
1
0
1
10
0
0
1
0
10
0
0
0
0
Q1+
Q2+
Z
148
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 13 Solutions
13.12(a)
(cont.)
State
Present
State
S0
S1
S2
S3
Q1Q2
00
01
11
10
Next State
00
00
01
11
00
X1X2 =
01
11
01
01
01
11
11
10
00
10
00
Z
10
01
11
11
00
00, 01
S0
01, 10, 11
0
0
0
0
1
0
00, 01, 10
1
13.12(b)
10, 11
S2
11
S3
11
S1
0
00, 01, 10
13.13
Clock
Clock
X1
X
Q1
X2
Q2
Q3
Q1
{
Z
Q2
false
Correct output: Z = 1011
Z
Correct output: Z = (0)00110
13.14
Clock
X
Q1
Q2
Q3
{
{
Z
false
false
Correct output: Z = 0011
13.15 (a)
Q2 Q3
X Q1
00
01
11
10
X Q1
00
01
11
10
01
11
10
0
0
1
00
0
0
0
0
00
1
1
1
1
00
0
0
1
1
01
0
0
0
1
01
1
1
1
1
01
1
1
1
1
01
0
0
1
1
11
0
0
0
1
11
1
1
1
1
11
0
0
1
1
11
1
1
0
0
10
1
1
1
1
10
1
1
0
0
10
0
0
1
1
10
1
1
0
0
149
01
11
10
D 3 = Q 3+
Q2 Q3
X Q1
00
0
D 2 = Q 2+
Q2 Q3
X Q1
00
00
D 1 = Q 1+
Q2 Q3
Z
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 13 Solutions
13.15 (a)
(cont.)
13.15 (b)
State
Present
State
Next State
S0
S1
S2
S3
S4
S5
S6
S7
Q1Q2Q3
000
001
010
011
100
101
110
111
Q1+Q2+Q3+
Z
X=0 X=1 X=0 X=1
001
101
0
1
011
111
0
1
110
101
1
0
010
111
1
0
001
001
0
1
011
011
0
1
110
101
1
0
010
011
1
0
0
S0
0
S1
0
1
0
1
1
0
S3
1
0,
1
0
S4
1
0, 1
0
0
1
1
0
1
1
1
S5
1
0
0
0
0
S7
0
1
1
S6
1
S2
13.15 (c) From diagram: 0, 1, (0), 1, 0, 1
From graph:
0, 1, 1, 0, 1
(they are the same, except for the false output)
Clock
X
Q1
13.15 (d) Change the input on the falling edge of the clock
(assuming negligible circuit delays).
Q2
Q3
{
Z
false
13.16 (a)
Q2 Q3
X Q1
00
01
11
10
Q2 Q3
X Q1
00
01
11
10
X Q1
00
01
11
10
1
1
0
0
00
0
1
1
1
00
0
0
1
1
00
1
1
0
0
01
0
0
0
0
01
0
0
1
1
01
0
0
1
1
01
0
0
1
1
11
0
0
0
0
11
0
0
0
0
11
0
1
1
0
11
0
0
1
1
10
1
1
0
0
10
0
1
1
0
10
0
1
1
0
10
1
1
0
0
S0
S1
S2
S3
S4
S5
S6
S7
Q1Q2Q3
000
001
010
011
100
101
110
111
11
10
Next State
Z
Q1+Q2+Q3+
X=0 X=1 X=0 X=1
100
011
1
0
000
011
0
1
100
000
1
0
000
000
0
1
110
011
1
0
000
011
0
1
111
011
1
0
001
001
0
1
150
Q2 Q3
D 3 = Q 3+
D 2= Q 2+
D1 = Q1+
Present
State
01
X Q1
00
00
State
Q2 Q3
1
0
0
1
S0
0
0
0
1
0, 1
0
1
S5
0
0
S2
0
1
1
1
S3
1
S1
Z
1
S4
0
1
0
0
S6
0
1
0 1
0, 1
1
1
S7
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 13 Solutions
13.16 (b)
13.16 (c)
From diagram: 1 0 1 (0) 1 1
From graph:
1 0 1 1 1
(they are the same, except for the false
output)
X
Clock
Q1
13.16 (d)
Change the input on the falling edge of the
clock (assuming negligible circuit delays).
Q2
Q3
{
Z
false
13.17 (a) Circuit 1
Q2Q1Q0 Present
State
000
S0
001
S1
010
S2
011
S3
100
S4
101
S5
110
S6
111
S7
Next
X=0
001
101
001
101
000
000
000
000
State
X=1
011
101
011
111
000
000
000
000
Output
Z
0
0
0
0
0
0
1
1
Next
X=0
001
101
001
101
000
000
010
010
State
X=1
011
101
011
111
010
000
010
010
Output
Z
0
0
1
0
0
0
1
0
0,1
0,1
S0
S3
1
0
0
0
S1
0
Circuit 2
Q2Q1Q0 Present
State
000
S0
001
S1
010
S2
011
S3
100
S4
101
S5
110
S6
111
S7
13.17 (b) Both circuits examine 3 consecutive inputs and
produce an output of 1 if the three consecutive
inputs represent a binary number larger than 5.
13.17 (c) The output of both circuits does not depend upon
the input so they are Moore circuits.
.
151
S7
1
1
0
S5
0,1
0
0,1
S2
1
S0
0
S3
1
0
1
0
0
S1
0
1
0
0,1
S7
0
S5
0
0,1
13.17 (d) Circuit 1 produces the 1 output when the 3rd bit
is present on the input, i.e., prior to the active
clock edge when the 3rd bit is present. Circuit 2
produces the 1 output when the circuit enters the
next state after receiving the 3rd bit. Circuit 1 has
the functional dependence of a Moore circuit but
the timing of a Mealy circuit. Circuit 2 is a Moore
circuit both from the functional dependence and
from the timing viewpoint.
.
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 13 Solutions
13.18 (c)
13.18 (a) D1 = Q1′ + Q2, D2 = x, z = Q1 + Q2′
13.18 (b)
Present
Q1Q2
00
01
10
11
Next
x=0
10
10
00
10
State
x=1
11
11
01
11
0
00
Output
z
1
0
1
1
10
0
1
1
1
0
1
0
11
1
01
0
1
1
13.18 (d) Any input sequence ending with an odd number of
0’s (1, 3, 5, etc.) followed by a single 1.
13.19 (c)
13.19 (a) D1 = Q1′ + Q2, D2 = xQ2′, z = Q1 + Q2′
13.19 (b)
Present
Q1Q2
00
01
10
11
Next
x=0
10
10
00
10
State
x=1
11
10
01
10
0
00
Output
z
1
0
1
1
10
0
1
0, 1
1
1
1
0, 1
11
01
0
1
13.19 (d) Any sequence ending with an odd number of 0’s
(1, 3, 5, etc.) followed by an odd number of 1’s.
13.20 (a) Q1+ = J1Q1' + K1'Q1
= (XQ2' + XQ'2)Q1' + (X + Q2')Q1
= XQ1'Q2' + X'Q1'Q2 + XQ1 + Q1Q2'
= X Q2' + X'Q1'Q2 + XQ1 + Q1Q2'
Q2+ = J2Q2' + K2'Q2
= XQ1'Q2' + (X' + Q1)Q2
= XQ1'Q2' + X'Q2 + Q1Q2
Z = Q1Q2
Present
State
Next State
Q +Q +
Q 1Q 2
00
01
10
11
X=0 X=1
00
11
11
00
10
10
01
11
1
2
0, 1
0
S2; 0
S0; 0
1
1
S1; 0
0
0
S3; 1
1
The circuit is a Moore circuit. State 2 is
unused.
Z
13.20 (b)
0
0
0
1
Clock
X
Q1
Q2
Z
13.20 (c) Z = (0)01101
152
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 13 Solutions
13.21
Clock Cycle
Information Gathered
1
Q1Q2 = 00, X = 0 ⇒ Z = 1, Q1+Q2+ = 01
2
Q1Q2 = 01, X = 0 ⇒ Z = 0; X = 1 ⇒ Z = 1, Q1+Q2+ = 11
3
4
5
6
7
8
Present
State
Q1Q2 = 10, X = 0 ⇒ Z = 1; X = 1 ⇒ Z = 0, Q1+Q2+ = 00
Q1Q2 = 00, X = 1 ⇒ Z = 0, Q1+Q2+ = 10
Q1Q2 = 10, X = 1 ⇒ (Z = 0); X = 0 ⇒ (Z = 1), Q1+Q2+ = 11
Q1Q2 = 11, X = 0 ⇒ (Z = 0); X = 1 ⇒ (Z = 1), Q1+Q2+ = 01
0
00
Q1Q2 = 01, X = 1 ⇒ (Z = 1); X = 0 ⇒ (Z = 0), Q Q = 00
+
2
Q1Q2 = 00, X = 0 ⇒ (Z = 1)
Note: Information inside parentheses was already obtained in a previous
clock cycle.
9
Z
1
2
X=0 X=1 X=0 X=1
01
10
1
0
00
11
0
1
11
00
1
0
10
01
0
1
Q1Q2
00
01
10
11
Q1Q2 = 11, X = 1 ⇒ Z = 1; X = 0 ⇒ Z = 0, Q1+Q2+ = 10
+
1
Next State
Q +Q +
1
0
1
0
13.22
Clock Cycle
Information Gathered
1
Q1Q2 = 00, X = 0 ⇒ Z = 0, Q1+Q2+ = 10
2
Q1Q2 = 10, X = 0 ⇒Z = 1; X = 1⇒ Z = 0, Q1+Q2+ = 01
3
4
5
6
7
8
13.23
Q1Q2 = 11, X = 0 ⇒ Z = 0, Q1+Q2+ = 11
Q1Q2 = 11, X = 0 ⇒ (Z = 0); X = 1 ⇒ Z = 1, Q1+Q2+ = 01
Q1Q2 = 01, X = 1 ⇒ (Z = 0), Q1+Q2+ = 00
00
Q1Q2 = 00, X = 1 ⇒ Z = 1, Q1+Q2+ = 11
1
4
5
Present
State
Q1Q2
00
01
11
10
1
11
0
Z
1
0
1
0
01
1
1
0
0
1
X=0 X=1 X=0 X=1
10
11
0
1
10
00
1
0
11
01
1
0
11
01
0
1
00
01
10
11
Q1Q2 = 10, X = 0 ⇒ (Z = 1), Q1+Q2+ = 11
0
1
1
Q1+Q2+
11
Clock Cycle
Information Gathered
1
Q1Q2 = 00, X1X2 = 01 ⇒ Z1Z2 = 10, Q1+Q2+ = 01
2
Q1Q2 = 01, X1X2 = 01 ⇒ Z1Z2 = 01; X1X2 = 10 ⇒ Z1Z2 = 10, Q1+Q2+ = 10
3
1
Next State
Q1Q2
Q1Q2 = 01, X = 1 ⇒ Z = 0; X = 0⇒ Z = 1, Q1+Q2+ = 10
Q1Q2 = 11, X = 1 ⇒ (Z = 1)
Note: Information inside parentheses was already obtained in a previous
clock cycle.
9
Present
State
01
0
0
0
10
1
Q1Q2 = 10, X1X2 = 10 ⇒ Z1Z2 = 00; X1X2 = 11 ⇒ Z1Z2 = 00, Q1+Q2+ = 01
0
1
1
0
10
1
Note: When Q1Q2 = 01,
the outputs Z1Z2 vary
depending on the inputs
X1X2, so this is a Mealy
machine.
Q1Q2 = 01, X1X2 = 11 ⇒ Z1Z2 = 11; X1X2 = 01 ⇒ (Z1Z2 = 01), Q1+Q2+ = 11
Q1Q2 = 11, X1X2 = 01 ⇒ Z1Z2 = 01
Q1+Q2+
Z1Z2
X1X2=
X1X2=
00 01 11 10 00 01 11 10
? 01 ?
? ? 10 ?
?
? 11 ? 10 ? 01 11 10
? ? ?
? ? 01 ?
?
? ? 01 ? ? ? 00 00
153
0
0
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 13 Solutions
13.24
Present
State
Q1Q2
00
01
11
10
Q1+Q2+
Z1Z2
X1X2=
X1X2=
00 01 11 10 00 01 11 10
? 01 ?
? ? 10 ?
?
? 11 ? 10 ? 01 11 10
? ? ?
? ? 01 ?
?
? ? 01 ? ? ? 00 00
13.25(a) Q1+ = D1 = X'Q1 + XQ1'Q2
Q2+ = D2 = X'Q2 + XQ1'Q2'
Z = X'Q2 + XQ1'Q2' + XQ1Q2'
Present
State
1
Q1Q2
S0=00
S1=01
S3=11
S2=10
? indicates next state or output values that cannot
be determined from the timing chart
13.25(b)
Next State
Q +Q +
Clock
X=0 X=1 X=0 X=1
00
01
0
1
01
10
1
0
11
00
1
0
10
00
0
1
0
X
S3
Q1
1
0
1
0
1
Q2
Z
{
0
false
0
Z
2
0
S0
1
1
S2
1
0
1
0
S1
1
13.25(c) Z = 11101
13.26 (a)
13.26 (b)
X1
Present
State
Q1Q2
00
01
10
11
X2
Clock
Q1
Q2
00
10
01
10
Z1
Q1+Q2+
X1X2=
00 01 10
00 00 01
11 11 10
11 00 11
10 01 10
00
01
00
11
01
Z2
10
false
Correct output: Z1Z2 = 10, 10, 00, 01
154
11
01
10
00
01
Z1Z2
X1X2=
00 01 10 11
10 10 10 10
00 10 01 11
00 00 01 01
00 00 00 00
10 11
10 , 10
10
11 01,
11
00 10
00 , 01
00 10
00, 00
01
01
00
11
00
00
00
01
10
11
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 13 Solutions
13.27
Transition table using a straight binary state
assignment:
State
Present
State
S0
S1
S2
S3
S4
Q1Q2Q3
000
001
010
011
100
Clock
X
Next State
Q1+Q2+Q3+
Z
X=0 X=1 X=0 X=1
001
011
0
0
010
011
0
0
001
011
0
1
100
000
0
0
011
000
0
1
Q1
Q2
Q3
Z
Correct output: Z = 0, 0, 1, 0, 0, 1
13.28 (a)
5ns
10ns
15ns
20ns
25ns
30ns
35ns
Clock
All flip-flop inputs are stable for more than the setup
time before each falling clock edge. So the circuit is
operating properly.
X
A
B
13.25(b) If X is changed early enough:
Minimum clock period = Flip-flop propagation
delay + Two NAND-gate delays + Setup time
= 4 + (3 + 3) + 2 = 12 ns
X can change as late as 8 ns (two NAND-gate
delays plus the setup time) before the next falling
edge without causing improper operation.
JA
KA
JB = KB
Z
13.29
Correct output: Z = 1 0 1 0 1
Clock
Deriving the State Table:
JK flip-flop equation:
Q+ = JQ' + K'Q
∴ A+ = (X'C + XC') A' + X'A
[As, JA = X'C + XC', KA = X, Q = A]
= A'X'C + A'XC' + X'A
Similarly, B+ = XC' + XA + X'A'C
A
B
C
X
{
Z
C+ = 0' ⋅ C + (XB'A) ⋅ C' = C + XB'A
Z = XB + X'C' + X'B'A
false
155
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Unit 13 Solutions
13.29
(cont.)
A+
XA
BC
B+
00
01
11
10
00
0
1
0
1
01
1
1
0
11
1
1
10
0
1
BC
XA
C+
00
01
11
10
00
0
0
1
1
0
01
1
0
1
0
0
11
1
0
0
1
10
0
0
BC
XA
Z
00
01
11
10
00
0
0
1
0
0
01
1
1
1
1
0
11
1
1
1
1
10
0
0
XA
BC
00
01
11
10
00
1
1
0
0
1
01
0
1
0
0
1
1
11
0
0
1
1
0
0
10
1
1
1
1
From the Karnaugh maps, we can get the state table
that follows:
13.30
(cont.)
State
Present
State
S0
S1
S2
S3
S4
S5
S6
S7
ABC
000
001
010
011
100
101
110
111
State
Present
State
S0
S1
S2
S3
AB
00
01
10
11
13.30
Next State
A+B+C+
Z
X=0 X=1 X=0 X=1
000
110
1
0
111
001
0
0
000
110
1
1
111
001
0
1
100
011
1
0
101
011
1
0
100
010
1
1
101
011
0
1
A+B+
X1X2=
00 01
11 01
11 01
10 00
10 00
10
10
01
10
11
11
00
01
10
01
Z 1Z 2
X1X2=
00 01 10
10 10 00
11 00 11
01 00 01
00 00 00
R = X2 (X1' + B)
S = X2' (X1' + B')
A+ = A[(X2 ) (X1' + B)]' + X2' (X1' + B')
= A (X2' + X1B') + X2'X1' + X2'B'
A+ = AX2' + AX1B' + X2'X1' + X2'B'
T = X1'BA + X1'B'A'
B+ = BT' + B'T
= B(X1'BA + X1'B'A')' B' (X1'BA + X1'B'A')'
= B [(X1'BA)' (X1'B'A')'] + X1'B'A'
= B [(X1 + B' + A') (X1 + B + A)] + X1'B'A'
= (BX1 + BA') (X1 + B + A) + X1'B'A'
= BX1 + BX1 + BX1A + BA'X1 + BA' + X1'B'A'
= X1B(1 + 1 + A + A') + A' (B + X1'B)
= X1B + A'B + X1'A'
01 10 11
00 11 00
11
00
00
00
00
01
10
S1
00
11
11
11
S0
00
00
10
01
00
S3
10
00
156
00
00
00
10
00
01
00
S2
00 10 11
01 01 00
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 14 Solutions
14.4
Unit 14 Problem Solutions
The state meanings are given in the following table:
Typical input and output sequences:
X = 0 1 0 0 0 0 0 1 0 1 0 1 1 ...
Z = (0) 0 0 0 0 0 0 0 1 1 1 ... (output remains 1)
X = 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 1 0 1 ...
Z = (0) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 ... (output remains 1)
X = 0 1 0 1 0 1 ...
Z = (0) 0 0 0 1 1 1 ... (output remains 1)
See FLD p. 761 for state graph.
14.5
State
S0
S1
S2
S3
S4
S5
S6
S7
S8
Meaning
Reset
One 0, no 1’s
≥ Two 0’s, no 1’s
≥ Two 0’s and one 1
≥ Two 0’s and ≥ Two 1’s
≥ One 1, no 0’s
≥ Two 1’s, no 0’s
≥ Two 1’s and one 0
One 0 and one 1
Typical input and output sequence:
X = 0 0 1 0 1 0 1 1 0 0 1 0 1 0 0 ...
Z1 = 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 ... (output remains 0 after 100 received)
Z2 = 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 ... (at this point, the sequence 01 has occurred, so Z1 = 0 from now on)
The graph needs two distinct parts. The first checks for 010 and 100. If 100 is received, we proceed to the second
part of the graph, which checks only for 100. The two parts are joined by a one-way arc, so once in the second part it
is impossible to go back to the first.
See FLD p. 761 for state table and graph.
The state meanings are given in the following table:
State
S0
S1
S2
S3
S4
S5
S6
S7
Meaning
Reset
Last input was 0, 100 has never occurred
Last input was 01, 100 has never occurred
Last input was 1, 100 has never occurred
Last input was 10, 100 has never occurred
Last input was 0, 100 has occurred at least once
Last input was 1, 100 has occurred at least once
Last input was10, 100 has occurred at least once
157
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Unit 14 Solutions
14.6
This should be solved in the same way as Example 3 on FLD p. 471-472. Assign a state to each possible input (00,
01, 11, 10) with an output of 0, and another state to each input with an output of 1. This gives eight states.
See FLD p. 762 for the state table.
State
S0
S1
S2
S3
Z=0
Last input was 00
Last input was 01
Last input was 11
State
Last input was 10
S7
S4
S5
S6
Z=1
Last input was 00
Last input was 01
Last input was 11
Last input was 10
Each input takes you to the state defined by that input (e.g. an input of 01 takes you to either S1 or S5). The only thing
in question is whether the output is 0 or 1. Determine the output by checking whether the last two inputs correspond
to the three input sequences.
Alternate Solution: Notice that when Z = 0, “causes the output to become 0” is the same as remaining constant, and
“causes the output to become 1” is the same as toggling the output. The situation is similar when Z = 1. So we can
use only four states, as follows:
State
S0
S1
S2
S3
Meaning
Z= 0 and last input was either 00 or 01
Z = 0 and last input was either 10 or 11
Z = 1 and last input was either 00 or 11
Z = 1 and last input was either 01 or 10
State
S0
S1
S2
S3
Next State
X1X2 = 00
S0
S2
S2
S0
01
S0
S0
S3
S3
10
S1
S1
S3
S3
11
S1
S1
S2
S2
Z
0
0
1
1
Note: The state table with 8 states reduces to this 4-state table using methods in Unit 15.
00,01
10,11
S0
0
00,11
1
00
01,10
11
10,11
0
01
00
S2
S1
S3
01,10
1
14.7 (a) Typical input and output sequence:
X = 0 0 1 0 0 1 1 0 0 0 1 1 0 1 0 0 1 ...
Z = 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 1 0 ...
See FLD p. 762 for state graph.
State
S0
S1
S2
Meaning
Number of 1’s is divisible by three
Number of 1’s is one more than divisible by 3
Number of 1’s is two more than divisible by 3
14.7 (b) Typical input and output sequence:
X = 0 0 0 0 1 1 1 1 0 0 0 1 1 0 1 1 1 1 ...
Z = 0 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 ...
See FLD p. 762 for state graph.
158
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Unit 14 Solutions
14.7 (b)
(cont.)
State
S0
S1
S2
S3
S4
S5
S6
S7
S8
Meaning
Number of 1’s is divisible by three, no 0’s
Number of 1’s is one more than divisible by 3, no 0’s
Number of 1’s is two more than divisible by 3, no 0’s
Number of 1’s is divisible by three, number of 0’s is odd
Number of 1’s is one more than divisible by 3, number of 0’s is odd
Number of 1’s is two more than divisible by 3, number of 0’s is odd
Number of 1’s is divisible by three, number of 0’s is even and < 0
Number of 1’s is one more than divisible by 3, number of 0’s is even and < 0
Number of 1’s is two more than divisible by 3, number of 0’s is even and < 0
14.8 (a) Typical input and output sequence:
X1 = 1 0 0 1 0 0 1 1 1 0 ...
X2 = 1 0 0 0 1 1 0 0 1 1 ...
Z1 = 0*0 0 1 0 0 1 0 1 0 ...
Z2 = 0*1 0 0 1 0 0 0 0 1 ...
*
Regardless of any value of N.
See FLD p. 762 for state table.
00
00
00
01
01
00
00
S1
Meaning
S0
S1
S2
Reset
Previous input was 00
Previous input was 01
S3
S4
01
11
01
11
Previous input was 11
01
00
S4
01
10
01
10
Meaning
S0
S1
S2
Reset state / current output is = 00
Previous input was 00 / current output is = 00
Previous input was 00 / current output is = 01
S5
S6
S7
S8
S9
S10
Previous input was 01 / current output is = 10
Previous input was 01 / current output is = 00
Previous input was 01 / current output is = 01
Previous input was 10 / current output is = 10
Previous input was 10 / current output is = 00
Previous input was 10 / current output is = 01
Previous input was 11 / current output is = 10
Previous input was 11 / current output is = 00
See FLD p. 763 for state table.
1
Meaning
1
0
10
11
State
S4
0
10
11
S3
01
00
Previous output bit was 0
Previous output bit was 1
00
01
Previous input was 10
00
00
10
S3
S0
S1
10
10
01
00
See FLD p. 763 for state table.
State
10
S2
10
11
10
01
14.8 (b) Similar to part (a), but we need a separate state for each
possible output and previous input.
14.9 (a)
00
00
10
State
S0
S0
1
S1
0
1
0
159
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Unit 14 Solutions
14.9 (b)
State
S0
S1
Meaning
Output bit is 0
Output bit is 1
0
1
S0
0
1
See FLD p. 763 for state table.
S1
0
1
14.9 (c) A false output occurs in NRZI just before the input
NRZ goes from 1 to 0.
14.9 (d) Notice that the Moore output is delayed to the next
clock cycle.
14.10
14.11
See FLD p. 763 for solution.
See FLD p. 764 for state graph.
State
Reset
S2
Button pressed. First full clock cycle with
Z = 1.
Second full clock cycle with Z = 1.
S4
Fourth full clock cycle with Z = 1.
S1
14.12 (a)
State
A
B
C
D
E
State
x=1
A
A
D
A
A
1
2
3
4
5
6
7
8
Third full clock cycle with Z = 1.
S5
X has not yet returned to 0.
State
z
0
0
0
1
0
A
B
C
E
Next State
x=0
B
C
E
E
x=1
A
A
A
A
State
Meaning
A
B
C
Sequence ending in 1 except x1001
Sequence ending in 10
Sequence ending in 100
D
Sequence ending in 1001
E
Sequence ending in 000
z
x=0 x=1
0
0
0
0
0
1
0
0
Meaning
A
B
C
Sequence ending in 1
Sequence ending in 10
Sequence ending in 100
E
Sequence ending in 000
14.13 (b)
14.13 (a)
State
S3
14.12 (b)
Next State
x=0
B
C
E
B
E
Meaning
S0
Next State
x=0
2
4
5
7
7
8
1
1
x=1
3
4
6
7
8
8
1
1
z
x=0 x=1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
State
Meaning
Initial State
1st bit was 0
1st bit was 1
1st 2 bits were 01st 2 bits were 10
1st 2 bits were 11
1st 3 bits were 0-- or -00
1st 3 bits were 1-1 or 11-
14.13 (c) The ‘Mealy’ circuit of Part (a) is such a Moore
circuit. This is possible since the output does not
depend upon the fourth (least significant) bit.
160
State
1
2
3
4
5
6
7
8
9
Next State
x=0
2
4
5
7
7
8
1
9
2
x=1
3
4
6
7
8
8
1
9
3
z
0
0
0
0
0
0
0
0
1
State
Meaning
Initial State, Valid BCD digit
1st bit was 0
1st bit was 1
1st 2 bits were 01st 2 bits were 10
1st 2 bits were 11
1st 3 bits were 0-- or -00
1st 3 bits were 1-1 or 11Invalid BCD digit
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 14 Solutions
14.14 (b)
14.14 (a)
State
1
2
3
4
5
6
7
Next State
x=0
1
3
1
6
3
1
6
x=1
2
4
5
7
4
5
7
z
x=0 x=1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
State
Meaning
State
Previous 3 bits were -00
Previous 3 bits were 001
Previous 3 bits were 010
Previous 3 bits were 011
Previous 3 bits were 101
Previous 3 bits were 110
Previous 3 bits were 111
14.14 (c) The ‘Mealy’ circuit of Part (a) is such a Moore
circuit. This is possible since the output does not
depend upon the fourth (least significant) bit.
1
2
3
4
5
6
7
8
9
10
11
12
13
Next State
x=0 x=1
1
2
3
4
1
5
6
7
8
9
10
11
12
13
1
5
6
7
1
2
8
9
10
11
12
13
State
Meaning
z
0
0
0
0
0
0
0
1
1
1
1
1
1
Previous 4 bits: -000, 0-00
Previous 4 bits:-001
Previous 4 bits: 0010
Previous 4 bits: 0011
Previous 4 bits: 0101
Previous 4 bits: 0110
Previous 4 bits: 0111
Previous 4 bits: 1010
Previous 4 bits: 1011
Previous 4 bits: 1100
Previous 4 bits: 1101
Previous 4 bits: 1110
Previous 4 bits: 1111
Note: A more obvious solution uses 16 states; it
can be reduced to the 13 states above using the
method described in Section 15.1.
14.15 (b)
14.15 (a)
State
1
2
3
4
5
6
Next State
x=0
2
3
5
6
1
1
x=1
2
4
6
6
1
1
z
x=0 x=1
0
0
0
0
0
0
0
0
0
0
0
1
State
Meaning
State
Initial State
1st bit was 1st 2 bits were -0
1st 2 bits were -1
1st 3 bits were -00
1st 3 bits were --1 or -1-
1
2
3
4
5
6
7
Next State
x=0
2
3
5
6
1
1
2
x=1
2
4
6
6
1
7
2
z
0
0
0
0
0
0
1
State
Meaning
Valid digit
1st bit was 1st 2 bits were -0
1st 2 bits were -1
1st 3 bits were -00
1st 3 bits were --1 or -1Invalid digit
14.15 (c) It is not possible in this case since the output does
depend upon the fourth (most significant) bit.
14.16 (b)
14.16 (a)
State
1
2
3
Next State
x=0
1
3
1
x=1
2
2
2
z
State
Meaning
x=0 x=1
0
0
Previous 3 bits were -00
0
1
Previous 3 bits were --1
0
1
Previous 3 bits were -10
14.16 (c) It is not possible in this case since the output does
depend upon the fourth (most significant) bit.
161
State
1
2
3
4
Next State
x=0
1
3
1
3
x=1
2
4
4
4
z
0
0
0
1
State
Meaning
Previous 4 bits were --00
Previous 4 bits were -001
Previous 4 bits were --10
Previous 4 bits were --11
or -101 (invalid digit)
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 14 Solutions
14.17 (a)
State
1
2
3
4
5
6
7
8
9
10
14.17 (b)
Next State
x=0
2
4
5
7
9
10
1
1
1
1
x=1
3
5
6
8
9
7
1
1
1
1
z
x=0 x=1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
State
Meaning
Initial State
1st bit was 0
1st bit was 1
1st 2 bits were 00
1st 2 bits were 01 or 10
1st 2 bits were 11
1st 3 bits were 000 or 111
1st 3 bits were 001
1st 3 bits were 01- or 101st 3 bits were 110
14.17 (c) It is not possible because the output depends on the
value of the fourth bit, e.g., see state 8 in Part (a).
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
10
11
Next State
x=0
2
4
5
7
9
10
11
11
1
1
2
x=1
3
5
6
8
9
7
11
1
1
11
3
z
0
0
0
0
0
0
0
0
0
0
1
State
Meaning
Valid digit
1st bit was 0
1st bit was 1
1st 2 bits were 00
1st 2 bits were 01 or 10
1st 2 bits were 11
1st 3 bits were 000 or 111
1st 3 bits were 001
1st 3 bits were 01- or 101st 3 bits were 110
Invalid digit
14.18 (b)
14.18 (a)
State
State
Next State
x=0
1
3
5
7
1
3
5
7
x=1
2
4
6
8
2
4
6
8
z
x=0 x=1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
State
Meaning
Previous 3 bits were 000
Previous 3 bits were 001
Previous 3 bits were 010
Previous 3 bits were 011
Previous 3 bits were 100
Previous 3 bits were 101
Previous 3 bits were 110
Previous 3 bits were 111
14.18 (c) It is not possible because the output depends on the
value of the fourth bit, e.g., see state 2 in Part (a).
162
State
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Next State
x=0
1
3
5
7
9
11
5
13
1
3
5
11
5
13
x=1
2
4
6
8
10
4
12
14
2
4
6
4
12
14
z
1
1
1
0
0
0
0
0
0
0
0
1
1
1
State
Meaning
Previous 4 bits were 0000
Previous 4 bits were 0001
Previous 4 bits were 0010
Previous 4 bits were -011
Previous 4 bits were -100
Previous 4 bits were 0101
Previous 4 bits were 0110
Previous 4 bits were 0111
Previous 4 bits were 1000
Previous 4 bits were 1001
Previous 4 bits were 1010
Previous 4 bits were 1101
Previous 4 bits were 1110
Previous 4 bits were 1111
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 14 Solutions
14.19 (b)
14.19 (a)
z
x=0 x=1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
Next State
State
x=0
2
4
5
7
7
8
1
1
1
1
2
3
4
5
6
7
8
9
x=1
3
5
6
8
9
9
1
1
1
State
Meaning
State
Initial State
1st bit was 0
1st bit was 1
1st 2 bits were 00
1st 2 bits were 01 or 10
1st 2 bits were 11
1st 3 bits were -00 or 0-0
1st 3 bits were 001 or 110
1st 3 bits were -11 or 1-1
1
2
3
4
5
6
7
8
9
10
Next State
x=0
2
4
5
7
7
8
10
1
1
2
x=1
3
5
6
8
9
9
1
1
10
3
z
0
0
0
0
0
0
0
0
0
1
State
Meaning
Initial State, Valid digit
1st bit was 0
1st bit was 1
1st 2 bits were 00
1st 2 bits were 01 or 10
1st 2 bits were 11
1st 3 bits were -00 or 0-0
1st 3 bits were 001 or 110
1st 3 bits were -11 or 1-1
Initial State, Invalid digit
14.19 (c) It is not possible because the output depends on the
value of the fourth bit, e.g., see state 7 in Part (a).
14.20 (b)
14.20 (a)
z
Next State
State
x=0
1
3
1
6
3
1
1
2
3
4
5
6
x=1
2
4
5
4
4
5
State
Meaning
x=0 x=1
1
0
0
0
1
0
0
1
0
1
0
0
State
Previous 3 bits were -00
Previous 3 bits were 001
Previous 3 bits were 010
Previous 3 bits were -11
Previous 3 bits were 101
Previous 3 bits were 110
14.20 (c) It is not possible because the output depends on the
value of the most significant (fourth) bit.
x=1
2
4
5
8
8
5
2
8
z
0
0
0
0
0
0
1
1
State
Meaning
Previous 4 bits:1100
Previous 4 bits: -001
Previous 4 bits: -010
Previous 4 bits: 0011
Previous 4 bits: -101
Previous 4 bits: -110
Previous 4 bits: -000, 0-00
Previous 4 bits: -111
Plot 0’s horizontally. Plot 1’s vertically. Receiving
a 0 takes us one state to the right. Receiving a 1
takes us one state down. The output is a 1 only in
the “three 0’s or more, one 1 or more” state:
14.21
S0
0
S1
0
S2
0
0
1
1
1
2
3
4
5
6
7
8
Next State
x=0
7
3
7
6
3
1
7
6
1
S4
0
0
1
S3
0
0
0
1
S5
0
0
S6
0
0
1
0
1
S7
1
0, 1
1
163
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 14 Solutions
14.22
S0
1
00
1
00
S6
1
00
1
00
S7
0
00
S1
0
10
0
00
1
00
0
00
S3
0
00
0
00
S4
1*
01
1
00
0
00
S2
1
01
S5
0
00
State
* When this point in the graph is reached,
011 has been received, and we are only
looking for 011 to occur again.
Meaning
S0
S1
S2
Reset
Previous input was 0 / 011 has not occurred
Previous input was 01 / 011 has not occurred
S4
Previous input was 0 / 011 has occurred
S6
Previous input was 1 / 011 has not occurred
S3
(No sequence) / 011 has occurred
S5
Previous input was 01 / 011 has occurred
S7
10,11
S0
10,11
00,01
00,01
S1
0
01
10
State
01,11
10
S0
S2
S2
S0
11
S0
S0
S3
S3
Z
0
0
1
1
Z = 0, last input was 10 or 11
Z = 0, last input was 00 or 01
Z = 1, last input was 00 or 10
S3
S3
01
S1
S1
S3
S3
Z1Z2
X=0 X=1
00
00
00
00
00
01
00
00
00
00
00
01
00
00
10
00
Meaning
S0
S1
S2
1
00
01,11
10
S2
00,10
X1X2 = 00
S1
S1
S2
S2
S0
S1
S2
S3
0
11
Next State
State
X=0 X=1
S1
S6
S1
S2
S7
S3
S4
S3
S4
S5
S4
S3
S7
S6
S1
S2
S0
S1
S2
S3
S4
S5
S6
S7
Previous input was 10 / 011 has not occurred
14.23
Next State
State
Z = 1, last input was 01 or 11
1
Alternate solution has 8 states, similar to problem 14.6:
State
Meaning
S0
S1
S2
Z = 0, last input was 10 (reset)
Z = 0, last input was 00
Z = 0, last input was 01
S4
Z = 1, last input was 10
S6
Z = 1, last input was 01
S3
Z = 0, last input was 11
S5
Z = 1, last input was 00
S7
Z = 1, last input was 11
State
S0
S1
S2
S3
S4
S5
S6
S7
164
Next State
X1X2 = 00
S1
S1
S1
S1
S5
S5
S5
S5
01
S2
S2
S2
S2
S6
S6
S6
S6
10
S0
S4
S4
S0
S4
S4
S0
S0
11
S3
S3
S3
S3
S7
S7
S7
S7
Z
0
0
0
0
1
1
1
1
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 14 Solutions
14.24 (a) We need four states to describe the
1’s received, as there are four possible
remainders when dividing by four. An
input of 1 takes us to the next state in
cyclic fashion. An input of zero leaves
us in the same state.
0
0
1
1
S0
0
0
0
1
S1
1
Remainder:
0
1
0
0
0
1
S2
1
0
2
0
S3
3
14.24 (b) Now, expand the state graph into two dimensions: one for 1’s and the other for 0’s. We need two states to describe
the zeros, odd and even.
0
S1
1
0
S3
1
1
1
1
0
0
0
0
0
S5
1
0
0
0
S7
0
S0
0
1
0
0
Left column: odd zeros
Right column: even zeros
S2
0
1
0
0
1
0
S4
0
1
0
}
First row: Remainder = 0
Second row: Remainder = 1
Third row: Remainder = 2
Fourth row: Remainder = 3
As part (a)
0
S6
0
14.25 (a) We need four states, one for each of the possible past inputs. The next state is just the one that describes that input.
The output Z1 is formed by adding the value of the present state to the present input. Z2 is found in a similar way:
State
S0
S1
S2
S3
00
S0
S0
S0
S0
Next State
01
S1
S1
S1
S1
10
S2
S2
S2
S2
11
S3
S3
S3
S3
00
00
00
00
10
Z1Z2
01 10
00 00
00 10
10 11
11 11
State
11
10
11
11
11
S0
S1
S2
S3
Meaning
Previous input was 00 (0)
Previous input was 01 (1)
Previous input was 10 (2)
Previous input was 11 (3)
14.25 (b) The Moore version is less intuitive. Again, we need
a state for each past input. We do not, however, need
a state for every possible output (this would give 4 ×
4 = 16 states) since some outputs never occur. For
instance, if the last input was zero, Z2 can never be 1,
because anything multiplied by zero is zero. In fact,
only ten states are needed:
Note: The output can never be 01. If two integers
between 0 and 3 multiply to a number greater than 2,
their sum is also greater than 2, i.e. (Z2 = 1) ⇒ (Z1 = 1)
165
Previous
Input
State
00
00
01
01
01
10
10
10
11
11
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
00
S0
S0
S0
S0
S0
S0
S0
S0
S1
S1
X1X2
01 10
S2 S5
S2 S5
S2 S6
S2 S6
S2 S6
S3 S7
S3 S7
S3 S7
S4 S7
S4 S7
11 Z1Z2
S8 00
S8 10
S9 00
S9 10
S9 11
S9 00
S9 10
S9 11
S9 10
S9 11
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 14 Solutions
14.26
There are two identical parts: one with an output of
0 and one with an output of 1.
1
0
1
S0
0
State
Meaning
S1, S4
S2, S5
S3, S0
Previous input was 0
Previous inputs were 01
Previous input was 1 / Reset (S0)
S1
0
S5
0
1
1
0
0
S2
1
S4
0
0
1
1
S3
0
1
1
14.27
There are two identical parts: one with an output of 0 and one
with an output of 1.
State
Meaning
S0
S1
S2
0
S2
0
0
1
Previous inputs were 00
0
1
1
S5
1
Previous inputs were 10 (start of second 101)
S5
14.28
S0
0
Previous inputs were 101 (first 101)
S4
S1
0
1
0
Reset
Previous input was 1
Previous inputs were 10
S3
1
0
S3
1
S4
1
0
1
This is another problem similar to 14.10. Plot the
number of 0’s horizontally and the number of pairs
vertically:
no 0's
one zero
S0
no pairs
11
0
S1
one pair
11
0
two pairs
11
0
S4
01
0 10
0
00
0
01
0 10
0
01 10
0, 0
00
0
two zeros
three zeros
four zeros
00
0
S2
00
0
11 01
0
0 10
0
S5
11
0
01 10
0, 0
S3
00
0
11 01
0
0 10
0
S6
11
0
01 10
0, 0
11
0
00
0
166
S7
00
1
to S0
S8
00 01 10
1, 1, 1
to S0
00 01 10 11
1, 1, 1, 1
to S0
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 14 Solutions
14.28
(cont.)
14.29
Pairs
0
1
1
1
2
2
2
2
2
Present
State
0’s
0
0
1
2
0
1
2
3
4
00
S3
S6
S7
S8
S6
S7
S0
S0
S0
S0
S1
S2
S3
S4
S5
S6
S7
S8
Next State
01
S2
S5
S6
S7
S5
S6
S7
S0
S0
10
S2
S5
S6
S7
S5
S6
S7
S0
S0
11
S1
S4
S5
S6
S4
S5
S6
S7
S0
00
0
0
0
0
0
0
1
1
1
Z1Z2
01 10
0 0
0 0
0 0
0 0
0 0
0 0
0 0
1 1
1 1
11
0
0
0
0
0
0
0
0
1
Note: There is a seven-state solution.
0’s are plotted horizontally. 1’s are plotted
vertically.
State
S0
S1
S2
S3
S4
S5
14.30
State
S0
S1
S2
S3
Next State
X=0 X=1
S2
S1
S3
S0
S4
S3
S5
S2
S2
S5
S3
S4
Next State
X=0 X=1
S1
S0
S1
S2
S1
S3
S1
S0
S0
Z
0
1
0
1
0
1
0
1
1
00
S0
1
00
0
S0
S1
S2
S3
0
1
00
00
S2
10
1
0
S5
0
odd 0's
State
1
1
0
no 0's
Z 1Z 2
X=0 X=1
00
00
00
00
00
10
00
01
S1
S3
0
even 1's
0
0
1
S1
00
S4
1
0
0
0
1
0
0
S2
0
1
odd 1's
even 0's
Meaning
Reset, 0111
0
01
011
00
S3
01
167
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 14 Solutions
14.31
State
S0
S1
S2
S3
00
S0
S0
S0
S0
X1X2
01 10
S1 S2
S1 S2
S3 S2
S3 S3
State
11
S3
S3
S3
S3
Z
0
0
0
1
S0
S1
S2
S3
00
Meaning
Reset
Previous input was 01, Z = 0
Previous input was 10, Z = 0
0
Meaning
S0
S1
S2
No sequence
0
00
S3
S4
01
S1
0
11
Z = 1 (Until input 00)
00
10
10, 11
00
S2
Example: X = 0 0 1 1 0 0 1 1 0 1 0 1
Z=001110111101
Note: Overlapping sequences are allowed.
State
00
S0
10
14.32
01
S3
0
01, 11
1
Next State
Z
X=0 X=1 X=0 X=1
0
1
S1
S0
0
1
S2
S0
0
1
S2
S3
0
1
S1
S4
1
1
S1
S0
State
S0
S1
S2
S3
S4
001
1
0011
1
0
1
1
S0
0
0
0
0
S1
0
S2
1
1
1
1
1
S3
S4
0
1
0
0
1
14.33
State
S0
S1
S2
S3
S4
S5
S6
State
S0
S1
S2
S3
S4
S5
S6
Next State
X=0 X=1
S0
S1
S6
S2
S3
S6
S3
S4
S6
S5
S5
S6
S6
S6
S0
Z
0
0
0
0
0
1
0
0
0
1
S1
0
1
S2
0
0
1
0
Meaning
0
No 1’s
One 1 in first group
Two 1’s in first group
S3
S4
0
One 1 in second group
0,1
0
0
1
First group 11 complete, had exactly two 1’s
S6
0
1
1
Two 1’s in second group (Z = 1)
0
“Disqualified” state (Z = 0)
168
S5
1
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
01, 10, 11
Unit 14 Solutions
14.34
To delay by two clock periods, we need to
remember the previous two inputs. So we have
four states, one for each combination of two inputs:
State
S0
S1
S2
S3
Next State
X=0 X=1
S0
S1
S2
S3
S0
S1
S2
S3
Z
X=0 X=1
0
0
0
0
1
1
1
1
0
0
1
0
S0
S1
0
0
0
1
1
0
1
1
S2
S3
0
1
1
1
State
Meaning
S0
S1
S2
Previous two inputs were 00
Previous two inputs were 01
Previous two inputs were 10
S3
Previous two inputs were 11
Note: Just go to the state that represents the last
two inputs.
14.35
This is the same as 14.34, except that we need to
remember the last three inputs. So we have eight
states:
0
S0
0
State
S0
S1
S2
S3
S4
S5
S6
S7
X=0 X=1
S0
S1
S2
S3
S4
S5
S6
S7
S0
S1
S2
S3
S4
S5
S6
S7
1
Z
S4
X=0 X=1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
S1
1
0
Next State
1
S3
0
1
0
0
0
S2
1
0
0
1
0
1
1
0
S5
0
1
1
1
S7
1
0
1
S6
1
0
1
Note: The state number expressed in binary gives
the last 3 inputs.
14.36 (a)
State
S0
S1
S2
S3
S4
S5
S6
S6
Next State
X=0 X=1
S0
S1
S2
S3
S4
S5
S6
S7
S0
S1
S2
S3
S4
S5
S6
S7
Z
0
0
0
0
1
1
1
1
Note: The state
number expressed in
binary gives the last
3 inputs.
169
14.36 (b) 16 states are required since the last four inputs must
be remembered.
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 14 Solutions
14.37
State
S0
S1
S2
S3
S4
S5
Next State
X=0 X=1
S1
S1
S2
S4
S3
S3
S0
S0
S3
S5
S0
S0
State
S0
S1
S2
S4
S3
S5
14.38
State
S0
S1
S2
S3
S4
S5
State
S0
S1
S2
S4
S3
S5
SV
X=0 X=1
00
10
10
00
00
10
00
10
10
00
10
01
0 1
00, 10
S2
0
S0
0 1
00, 10
10
0 1
00, 10
S3
0
10
S1
1
00
S4
1
00
S5
0 1
10, 01
Meaning
No bits received
One bit received
Two bits received; Carry-in = 0
Two bits received; Carry-in = 1
Three bits received; Carry-in = 0
Three bits received; Carry-in = 1
Next State
X=0 X=1
S1
S1
S2
S3
S4
S5
S5
S5
S0
S0
S0
S0
DB
X=0 X=1
00
10
10
00
10
00
00
10
11
00
00
10
0 1
11, 00
S2
0
S0
0 1
00, 10
0
10
S43
10
1
00
S1
1
00
S3
0 1
00, 10
S5
0 1
00, 10
Meaning
No bits received
One bit received
Two bits received; Borrow-in = 1
Two bits received; Borrow-in = 0
Three bits received; Borrow-in = 1
Three bits received; Borrow-in = 0
170
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 14 Solutions
14.39
This is similar to 14-15, and should be answered in
the same way. See the solution to 14-15 for more
information.
S0
S1
S2
S3
S4
S5
S6
S7
S8
14.40
Next State
X=0 X=1
S3
S1
S4
S2
S5
S0
S6
S4
S7
S5
S8
S0
S0
S7
S0
S8
S0
S0
1
1
S0
Horizontally: Number of 1’s modulo 3
Vertically: Number of 0’s modulo 3.
State
0
1
S1
00
S2
01
0
S5
1
01
0
10
0
S6
S8
1
01
0
10
0
This problem is essentially a circular counting
exercise. Pairs of 1’s take you further around the
state graph. Pairs can overlap, so if the last input
was a 1, and the present input is a 1, you move on.
If the sequence is interrupted, you branch off while
you wait for the next 1. Then, you go back to the
cycle of counting.
State
S0
S1
S2
S3
S4
S5
S6
S7
Next State
X=0 X=1
S0
S1
S0
S2
S3
S4
S3
S2
S5
S6
S5
S4
S7
S0
S7
S6
1
1
2
0
1's take you
around
S0
00
S7
0
S5
0
S1
00
1
S4
1
0
1
11
0
11
1
S6
1
YZ
00
00
01
01
10
10
11
11
1
0
S7
1
00
0
0
0
S4
1
00
1
10
0
S3
YZ
00
01
10
00
01
10
00
01
10
2
10
0
1
1
S2
1
01
0
10
S3
01
Interruption to
the flow of 1's
171
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
0
Unit 14 Solutions
14.41
We notice that input ABXX becomes output AABB.
It can be seen that it is not necessary to remember
both A and B at once. We remember A for the first
two clocks and B for the next two. Notice that if
the output were, say, ABAB, we could not do this.
S0
S1
1 0
0, 0
0
0
1
1
0
0
0
0
1
S5
1
1
S2
1 0
0, 0
S4
14.42
1
1 0
1, 1
State
S0
S1
S2
S3
S4
S5
S6
Z
X=0 X=1
0
1
0
0
0
0
1
1
0
0
1
1
1
1
Next State
X=0 X=1
S1
S5
S2
S3
S4
S4
S6
S6
S0
S0
S2
S3
S0
S0
State
Meaning
S0
S1
S5
Reset
A=0
A=1
S3, S6
B=1
S2, S4
B=0
S3
1 0
1, 1
S6
This problem is simply addition. We need a state
to describe every possible sum of money entered,
i.e., 0¢ to 45¢ in 5¢ intervals.
$
.00
.05
.10
.15
.20
.25
.30
.35
.40
.45
Just go to the state with the correct sum. The 25¢
state dispenses the product (R = 1) and resets.
States above this in value cascade down to S5
by giving out a nickel. When they get to S5, the
product is dispensed.
14.43 (a) Look at Figure 14-19, FLD p. 473, to see that
Manchester 01 gives NRZ 00
Manchester 10 gives NRZ 11
Other Manchester inputs are presumed not to occur.
Present
State
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S0
0
0
NDQ
100 010
S1 S2
S2 S3
S3 S4
S4 S5
S5 S6
-
001 RC
S5 00
S6 00
S7 00
S8 00
S9 00
10
01
01
01
01
-
1
1
1
0
S1
000
S0
S1
S2
S3
S4
S0
S5
S6
S7
S8
S2
0
1
Next State
Z
X=0 X=1 X=0 X=1
0
1
S0
S1
S2
0*
0
S1
S0
1
1*
S2
S0
* Filled in to prevent False outputs.
State
172
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Unit 14 Solutions
14.43 (b) This is the same as the Mealy, except that we need
two reset states, one with an output of zero, the
other with an output of 1. Invalid inputs never
occur.
14.43
(c), (d)
State
S0
S1
S2
S3
Next State
X=0 X=1
S1
S2
S0
S3
S1
S2
S0
0
Z
0
0
1
1
1
0
1
S1
0
0
S1
A'R'
CLOCK2
Manchester
NRZ (Mealy)
NRZ (Moore)
false outputs
Note: Moore output is delayed one clock cycle of CLOCK2.
14.44
State
Meaning
Reset
S0
One ring, waiting for two (or answer)
S1
S3, S4, S5 One, two, or three rings, respectively;
waiting for four (or answer)
Activate answering machine; wait for
S2
it to answer
Note: Another solution requires only 5 states. If
testing S is deferred until after the first ring, states
S1 and S3 can be combined.
14.45
Present
State
S0
S1
S2
14.46
00
S1
S1
S2
Next State
01
S0
S2
S1
10
S2
S0
S0
11
S2
S0
S0
00
01
00
00
Z1Z2
01 10
10 01
11 00
00 00
14.44
cont.
R'
S0
0
RS
AR'
A'R' S
3
0
RS'
AR'
0
R AR'
A'R'
R
A
S4
0
AR'
S2
R
Z
R
S5
A'
0
11
01
00
00
A'R'
In state S0 there is no specification for X1X2'. This
can be corrected by adding an arc for X1X2' or
changing X1X2 to X1 or changing X1' X2' to X2'.
In state S1 there is a conflict for X1X2. This can be
corrected by changing X1 to X1X2' or changing X2
to X1' X2.
X2'*
*Changed
X1X2
X1'X2'
X1
S1
Z2
X1'X2'
173
S0
Z1
X1'X2
X1'X2
X1'X2*
S2
1
1
S2
Z3
X1
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
0
S3
1
Unit 14 Solutions
14.47
Noting that the six illegal sequences only need to
be distinguished by their parity produces this table.
Present
State
S0
0
S1
1
S2
00
S3
10
S4
01
S5
11
S6
000
S7
100,010,111 S8
110,101,011 S9
001
S10
14.48
14.49
Next
X=0
S1
S3
S5
S7
S8
S10
S9
S0
S0
S0
S0
State
X=1
S2
S4
S6
S8
S9
S9
S8
S0
--S0
Output
X =0
0
0
0
0
0
0
0
1
0
1
0
(Z)
X=1
0
0
0
0
0
0
0
0
--1
Distinguishing between legal and illegal sequences
and combining sequences with the same parity
produces the table below.
Present Next State Output (Z)
State
X = 0 X = 1 X =0
X=1
S0
S1
S2
0
0
0
S1
S3
S4
0
0
1
S2
S4
S5
0
0
00
S3
-S6
-0
10, 01
S4
S7
S8
0
0
11
S5
S9
-0
0
001
S6
-S0
-1
100, 010 S7
S0
S0
0
1
101, 011 S8
S0
S0
1
0
110
S9
S0
-1
-Distinguishing between legal and illegal sequences
and combining sequences with the same parity
produces the table below.
Present Next State Output (Z)
State
X = 0 X = 1 X =0
X=1
S0
S1
S2
0
0
0
S1
S3
S4
0
0
1
S2
S5
S6
0
0
00
S3
S7
S8
0
0
01
S4
-S9
-0
10
S5
S8
S7
0
0
11
S6
-S10
-0
000, 101 S7
S0
S0
1
0
001, 100 S8
S0
S0
0
1
011
S9
S0
-1
-111
S10
S0
-0
--
174
This table can be reduced using techniques of Unit
15. Alternatively, it can be reduced by noting that
all sequences of length 2 and all of length 3 only
need to be distinguished by their parity.
Present
State
S0
0
S1
1
S2
00,11
S3
10,01
S4
000,110,101,011 S5
001,100,010,111 S6
Next
X=0
S1
S3
S4
S5
S6
S0
S0
State
X=1
S2
S4
S3
S6
S5
S0
S0
Output
X =0
0
0
0
0
0
1
0
(Z)
X=1
0
0
0
0
0
0
1
This table can be reduced using techniques of Unit
15. Alternatively, it can be reduced by noting that
all sequences of length 2 and all of length 3 only
need to be distinguished by their parity.
Present
State
S0
0
S1
1
S2
00, 11
S3
10, 01
S4
001, 100, 010 S5
101, 011, 110 S6
Next
X=0
S1
S3
S4
S6
S5
S0
S0
State
X=1
S2
S4
S3
S5
S6
S0
S0
Output
X =0
0
0
0
0
0
0
1
(Z)
X=1
0
0
0
0
0
1
0
This table can be reduced using techniques of Unit
15. Alternatively, it can be reduced by noting that
all sequences of length 2 and all of length 3 only
need to be distinguished by their parity.
Present
State
S0
0
S1
1
S2
00, 11
S3
01, 10
S4
000, 101, 011 S5
001, 100, 111 S6
Next
X=0
S1
S3
S4
S5
S6
S0
S0
State
X=1
S2
S4
S3
S6
S5
S0
S0
Output
X =0
0
0
0
0
0
1
0
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
(Z)
X=1
0
0
0
0
0
0
1
Unit 14 Solutions
14.50
Distinguishing legal and illegal sequences
produces the following table.
0
1
00
01
10
11
14.51
Present
State
S0
S1
S2
S3
S4
S5
S6
Next
X=0
S1
S3
S5
S0
S0
S0
S0
Present
State
S0
0
S1
1
S2
00
S3
01,10 S4
State
X=1
S2
S4
S6
S0
-S0
--
Next
X=0
S1
S3
S4
S0
S0
This table can be reduced using techniques of Unit
15. Alternatively, it can be reduced by combining
the sequences of length 2 that have the same parity.
Output
X=0 X=1
------1
0
0
-0
1
1
--
State
X=1
S2
S4
-S0
S0
Present
State
S0
0
S1
1
S2
00, 11 S3
01, 10 S4
Next
X=0
S1
S3
S4
S0
S0
State
X=1
S2
S4
S3
S0
S0
Output
X=0 X=1
------1
0
0
1
Output
X=0 X=1
------1
0
0
1
175
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 14 Solutions
176
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 15 Solutions
Unit 15 Problem Solutions
15.1 (a) Implication chart after one pass:
Complete implication chart
B
B
C
F-H
D
C-E
E
C
F-H
B-E
F-H
D
C-E
C-D B-D
A-F
A-F A-H
E
C-D B-D
A-F
A-F A-H
A-B
E-F
F
F
C-D B-D
F-H
G
D-E A-H
F-H
B-H
F-G
A
B
C
D
E
H
F
G
State
A
B
C
F
15.2
b
Next State
X=0 X=1
A
C
C
F
B
A
B
F
X=0 X=1
1
0
0
0
0
0
1
0
c-h
e-a
h-f
f
i-e
h-g
g
e-h
e-b
c-h
e-b
h
i
c-f
b-e
b
C
D
E
F
G
So λ1(B, 100) = 010 ≠ 011 = λ2(G, 100), and B ≡ G.
(Alternative: λ1(B, 110) = 001 ≠ 000 = λ2(G, 110).
Also, λ1(B, 00101) ≡ λ2(G, 00101), but this requires
an X of length 5.
See FLD p. 766 for
reduced state table.
i-e
f-g
a-b
c-i
d-h
e-f
e-b
a
B
Input: X:
1 0 0
Starting Z:
0 1 0
in B: State: (B) F B
Starting Z:
0 1 1
in G: State: (G) H
H
a≡b
c≡e
h≡f
d≡g≡i
e
B-H
F-G
E-G
F ≡ H because B ≡ H, (and also because F ≡ G), and
B ≡ H because the output differs for X = 0.
So use the sequence X = 100.
Output
c-e
e-h
e-a
D-E A-H
F-H
15.1 (b) B ≡ C because F ≡ H, (and also because C ≡ D)
c
d
C-D B-D
F-H
A
Reduced state table:
B-E
F-H
A-B
E-F
G
E-G
H
A≡H
C≡E≡G
B≡D
c
c-i
f-d
h-f
a-b
d
c-e
g-d
h-f
e
f
g
177
h
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 15 Solutions
15.3
S0
S1
S2
S3
S4
S5
S6
S5 − a
S1 − b
S5 − a
S1 − c
S2 − a
S6 − b
S2 − a
S6 − c
S5 − a
S6 − b
S4 − a
S3 − b
S0 − a
S1 − b
S5 − a
S6 − c
S4 − a
S3 − c
S0 − a
S1 − c
a
15.4 (a)
X3 Q
15.3 (a) a ≡ S0, S5
b ≡ S1
c ≡ S3, S6
b
X1 X2
00
S0 − a
S1 − b
S0 ≡ a
S1 ≡ b
S3 ≡ c
S5 ≡ a
S6 ≡ c
S2 and S4 have no
equivalent states.
Since S2 and S4 do not have corresponding states,
the circuits are not equivalent.
15.3 (b) Starting from S0, it is not possible to reach S2 or S4.
So then the circuits would perform the same.
S5 − a
S1 − b
c
15.4 (b)
01
11
10
X3 Q
X1 X2
00
X3 Q
X1 X2
00
01
11
10
0
1
0
1
01
0
X
X
0
0
11
X
0
0
X
0
10
0
1
0
1
01
11
10
00
0
1
0
1
00
X
0
X
0
00
01
0
1
1
0
01
1
0
0
1
11
1
0
0
1
11
0
1
1
10
0
1
0
1
10
X
0
0
D = X2'X3Q + X1'X2Q' + X1X2'Q' + X2X3'Q
R = X2X3Q + X2'X3'Q
Z=Q
S = X1'X2Q' + X1X2'Q'
Z=Q
15.5 (a) The first row may be all 0’s, because if a column has a 1 in the first row, we can invert it so that it has a 0 in the first
row without changing the number of gates. No column should be all 0’s, because that is the same as the two flipflop case. There are only 3 columns which fit these criteria: 001, 010, and 011. No column may be used twice,
because again that is the same as the two flip-flop case. So we need only check one assignment (which consists of the
three columns in any order) to see whether a three flip-flop solution is better than a two flip-flop solution. One such
assignment is:
0 0 0
0 1 1
1 0 1
15.5 (b) Excluding 0000, there are 7 possible columns. All possible non-repeating combinations are given below. Those with
repeating rows are crossed out; 29 assignments remain to try.
178
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Unit 15 Solutions
15.5 (b)
(cont.)
00 0
00 0
01 1
10 1
(1 2 3)
00 0
01 1
00 0
10 1
(1 4 5)
00 0
00 1
11 1
01 1
(2 3 7)
00 0
01 1
10 1
10 1
(3 4 7)
00 0
00 1
01 1
11 1
(1 3 7)
00 0
00 1
11 1
01 0
(2 3 6)
00 0
01 1
10 1
10 0
(3 4 6)
00 0
00 1
01 0
10 0
(1 2 4)
00 0
01 1
00 1
10 0
(1 4 6)
00 0
01 1
10 0
00 1
(2 4 5)
00 0
01 1
10 1
11 0
(3 4 6)
00 0
00 1
01 0
10 1
(1 2 5)
00 0
01 1
00 1
10 1
(1 4 7)
00 0
01 1
10 1
00 0
(2 4 6)
00 0
01 1
10 1
11 1
(3 5 7)
00 0
00 1
01 1
10 0
(1 2 6)
00 0
01 1
00 1
11 0
(1 5 6)
00 0
01 1
10 1
00 1
(2 4 7)
00 0
01 1
11 1
10 1
(3 6 7)
15.6 (a) Group (S1, S4, S6, S7) and (S2, S3, S5, S8).
A
00 0
00 1
01 0
11 0
(1 3 4)
00 0
01 1
01 1
10 1
(1 6 7)
00 0
01 1
10 1
01 1
(2 5 7)
00 0
11 1
00 1
01 1
(4 5 7)
BC
A
00 0
00 1
01 0
11 1
(1 3 5)
00 0
00 1
11 0
01 0
(2 3 4)
00 0
01 1
11 1
00 1
(2 6 7)
00 0
11 1
01 1
00 1
(4 6 7)
0
00 0
00 1
01 1
11 0
(1 3 6)
00 0
00 1
11 0
01 1
(2 3 5)
00 0
01 1
10 0
10 1
(3 4 5)
00 0
11 1
01 1
10 1
(5 6 7)
1
0
1
00
S1
S2
00
1
01
S4
S3
01
1
11
S6
S5
11
1
10
S7
S8
10
1
BC
One possible assignment:
S1 = 000 S5 = 111
S2 = 100 S6 = 011
S3 = 101 S7 = 010
S4 = 001 S8 = 110
00 0
00 1
01 1
10 1
(1 2 7)
00 0
01 1
00 1
11 1
(1 5 7)
00 0
01 1
10 1
01 0
(2 5 6)
00 0
11 1
00 1
01 0
(4 5 6)
Z=A
15.6 (b) I: (S3, S4) (S1, S8) (S3, S7) (S5, S8)
II: (S4, S5) (S1, S6) (S7, S8) (S1, S7) (S2, S3)
(S2, S4) (S6, S8) (S3, S5)
Adjacencies that are satisfied are checked ()
BC
One possible assignment:
S1 = 000 S5 = 101
S2 = 010 S6 = 110
S3 = 011 S7 = 001
S4 = 111 S8 = 100
BC
XA
A
01
11
10
00
1
1
0
1
S5
01
1
0
0
1
S3
S4
11
0
0
0
1
S2
S6
10
0
1
0
1
1
00
S1
S8
01
S7
11
10
BC
XA
00
0
DA = A'B' + X'AC' + XA'
00
01
11
10
00
0
0
1
1
01
1
1
1
11
0
0
10
0
1
State
00
01
11
10
00
1
1
1
1
0
01
0
0
1
0
0
0
11
1
1
0
0
1
1
10
0
1
0
0
DB = X'B'C + ABC' + XC' + XAB'
BC
XA
DC = B'C' + X'BC + XAB' + X'AC'
179
S1
S7
S2
S3
S8
S5
S6
S4
ABC
000
001
010
011
100
101
110
111
A+B+C+
X=0 X=1
101 111
110 100
000 110
001 100
101 011
010 011
111 010
001 000
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 15 Solutions
15.7 (a) Guidelines:
1. (A, D, F) (C, E) (A, D) (C, E) (B, F)
2. (F, D)×2 (D, B) (A, C)×2 (B, F)
3. (A, B, D, F) (C, E)
See FLD p. 766 for one good solution.
15.7 (b) See FLD p. 766 for solution.
15.8 (a) Guidelines:
1. (B, D)×2 (C, D)×2 (A, B)
2. (B, D) (A, C) (A, C, B) (A, B, C, D)
3. (A, B)×2 (B, D)×2 (C, D)×2
Q2
Best assignment: A = 00, B = 01, C = 10, D = 11
15.8 (b)
X1 X2
Q1 Q2
00
01
11
10
X1 X2
Q1 Q2
1
0
A
C
1
B
D
Q2
Q1
0
A
D
1
B
C
X1 X2
Q1 Q2
00
A
D
1
C
B
(C, D) not
satisfied
0
0
0
01
0
0
0
0
0
11
0
1
1
0
0
10
0
1
1
0
0
1
1
0
00
01
1
0
0
0
01
0
1
1
0
11
0
1
1
1
11
1
1
0
10
1
1
0
0
10
1
1
0
Q2+
Q1 Q2
00
0
0
10
00
X1 X2
1
10
11
1
10
0
11
01
0
11
Q1
01
00
0
01
Q2
(B, D) not
satisfied
0
Q1 Q2
00
1
0
00
Z1 = Q2X1
01
11
10
X1 X2
Q1 Q2
00
01
11
10
00
0
0
1
0
00
0
0
0
0
00
0
0
1
1
01
1
0
1
1
01
0
0
0
0
01
0
0
1
1
11
0
1
0
0
11
1
0
1
0
11
0
0
0
1
10
1
1
1
1
10
1
0
1
0
10
0
0
0
1
T1 = X1X2' + Q1Q2X1' +
Q1'Q2X1 + Q2'X1'X2
15.9
0
Satisfies all
adjacencies
Q1+
X1 X2
Q1
T2 = Q1'Q2'X1 + Q1Q2X1
Z2 = Q1Q2' + Q1X1'
See FLD p. 767 for solution using Q1, Q2, and Q3.
Alternate solution using Q0, Q1 and Q2:
D0 = X'Q0 + XY'Q2
D1 = XQ0 + YQ2 + X'Q1
D2 = YQ1 + X'Y'Q2
P = XQ0 + Y'Q2 + XQ1
S = X'Q0 + XY'Q2
180
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Unit 15 Solutions
15.10 (a) b
State
a≡g≡h
d≡f
e≡b
c
d
h-f
b-h
e
f-h
b-g
g
h-g
h
h-a
a
h-g
g-a
b
c
d
d-e
f-g
e
b-e
f-g
e-g
f-g
15.12
(a), (b)
f
a
b

d-g
g

b
c
d
e
0
0
0
0
Equivalent States: S0 ≡ S8, S3 ≡ S11, S4 ≡ S12,
S7 ≡ S15.
Present
Next State
Output
Pattern
State
-000
0001
0010
-011
-100
0101
0110
-111
1001
1010
1101
1110
S0
S1
S2
S3
S4
S5
S6
S7
S9
S10
S13
S14
X=0 X =1
S0
S1
S2
S3
S4
S5
S6
S7
S0
S9
S10
S3
S4
S13
S14
S7
S2
S3
S4
S5
S10
S3
S4
S13
Z
0
0
1
1
1
0
1
0
1
0
1
0
e
c
b
Output
X=0 X=1
0
1
0
1
c
f
b
1
0
1
0
1
0
15.11 (b) Input: 000
Output starting in state a:
0
0
0
001 (state a→
state e→
state g→
state e)
Output starting in state b:
0
0
0
000 (state b→
state d→
state b→
state d)
b-e
c-d
f
Input
Next State
X=0 X=1
e
c
b
f
c
e
f
b-g
b-e
c-d
b
a
g
b≡d
c≡g
f
a
e
a
d
Output
X=0 X=1
1
0
0
1
15.10 (b) Input: 00
Output starting in state c:
0
0
01 (state c→
state a→
state a)
Output starting in state d:
0
0
00 (state d→
state d→
state d)
State
c
d
c
d
d-f
f
15.11 (a) b
a
b
Next State
X=0 X=1
a
c
c
d
181
15.12 (c)
Input
Present
Pattern
State
-000
0001
0010
-011
-100
0101
0110
-111
1001
1010
1101
1110
S0
S1
S2
S3
S4
S5
S6
S7
S9
S10
S13
S14
Z
X=0 X =1 X=0 X=1
0
0
S0
S1
1
1
S2
S3
1
0
S4
S5
1
0
S6
S7
0
1
S0
S1
0
1
S10
S3
1
1
S4
S13
0
0
S14
S7
1
1
S2
S3
1
0
S4
S5
0
1
S10
S3
1
1
S4
S13
Next State
Output
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 15 Solutions
15.12 (d) S1 ≡ S9, S2 ≡ S10, S5 ≡ S13, S6 ≡ S14.
Input
Present
Pattern
State
-000
-001
-010
-011
-100
-101
-110
-111
S0
S1
S2
S3
S4
S5
S6
S7
Z
X=0 X =1 X=0 X=1
0
0
S0
S1
1
1
S2
S3
1
0
S4
S5
1
0
S6
S7
0
1
S0
S1
0
1
S2
S3
1
1
S4
S5
0
0
S6
S7
Next State
Output
15.13 (a) Moore circuit.
15.13
(b), (c)
15.14 (a)
S8 ≡ S9 ≡ S10 ≡ S11 ≡ S12
and S13 ≡ S14 ≡ S15.
Input
Present
Pattern
State
0
1
00
01
10
11
-00, 0-1-1, 11-
S1
S2
S3
S4
S5
S6
S7
S8
S13
Input
Present
Pattern
State
0
1
00
01
10
11
000
001
010
011
100
101
110
111
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S4 ≡ S5.
Z
X=0 X =1 X=0 X=1
0
0
S2
S3
0
0
S4
S5
0
0
S6
S7
0
0
S8
S8
0
0
S8
S8
0
0
S8
S13
0
0
S13
S13
0
0
S1
S1
1
1
S1
S1
Next State
Output
Z
X=0 X =1 X=0 X=1
0
0
S2
S3
0
0
S4
S5
0
0
S6
S7
0
0
S8
S9
0
0
S10
S11
0
0
S12
S13
0
0
S14
S15
0
0
S1
S1
0
1
S1
S1
0
1
S1
S1
0
1
S1
S1
0
0
S1
S1
0
1
S1
S1
0
1
S1
S1
0
1
S1
S1
Next State
Output
182
15.14
(b), (c)
Input
Present
Pattern
State
0
1
010
11
-00, 0-1-1, 11-
S1
S2
S3
S4
S6
S7
S8
S13
Z
X=0 X =1 X=0 X=1
0
0
S2
S3
0
0
S4
S4
0
0
S6
S7
0
0
S8
S8
0
0
S8
S13
0
0
S13
S13
0
0
S1
S1
1
1
S1
S1
Next State
Output
S9 ≡ S10 ≡ S11 ≡ S13 ≡ S14 ≡ S15
and S8 ≡ S12.
Input
Present
Pattern
State
0
1
00
01
10
11
-00
-01, -1-
S1
S2
S3
S4
S5
S6
S7
S8
S9
Output Z
X=0 X =1 X=0 X=1
0
0
S2
S3
0
0
S4
S5
0
0
S6
S7
0
0
S8
S9
0
0
S9
S9
0
0
S8
S9
0
0
S9
S9
0
0
S1
S1
0
1
S1
S1
Next State
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 15 Solutions
15.14(b), Equivalent States: S4 ≡ S6 and S5 ≡ S7.
(c)
Input
Present
Next State
Output Z
(cont.)
Pattern
State
X=0 X =1 X=0 X=1
0
0
S1
S2
S3
0
0
0
S2
S4
S5
1
0
0
S3
S4
S5
-0
0
0
S4
S8
S9
-1
0
0
S5
S9
S9
-00
0
0
S8
S1
S1
-01, -10
1
S9
S1
S1
15.15 (a) b
15.15 (b) b
a-d
c-e
c
d
a-b
e-c
b-d
f
Present
State
a
c
f
b
00
a
c
f
Next State
01
c
a
a
11
c
f
a
d
10
a
a
a
Pattern
State
-0
-1
-00
-01, -1-
S1
S2
S4
S5
S8
S9
b-e
b-c
b-f
c-g
Z
X=0 X =1 X=0 X=1
0
0
S2
S2
0
0
S4
S5
0
0
S8
S9
0
0
S9
S9
0
0
S1
S1
0
1
S1
S1
Next State
Output
b≡d
g≡h
c≡f
b-d
e-f
d-g
f
c-f
a-d
f-a
b-d
e
d
Present
b-e
c-d
e
a-d
a-b
e-f
a-b
f-a
b-d
c
Input
c
a≡b≡d
c≡e
e-c
a-b
e
a
Equivalent States: S2 ≡ S3.
e-f
b-g
g-h
d-b
g
h

i
a-h
a-i
g
a
Z
0
1
1
State
a
b
c
e
g
i
183
b
c
d
e
f
Next State
Z
X=0 X=1 X=0 X=1
1
0
b
c
1
0
e
b
1
1
g
b
1
0
c
g
0
1
g
i
0
1
a
a
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
g-a
i-a
h
Unit 15 Solutions
15.16 (a) b
i-c
c-f
c
d
d-c, d-e
f-g
e
i-c
i-f
f
b-f, i-c
g-k
b-j, c-g
i-k, g-h
b-e
i-f
b-i, c-i
g-d
i-f
b-f, i-c
f-i, g-k
b-j, c-k
f-g, g-h
b-e
c-f
b-i, c-i
f-i, g-d
c-f
g
h
i
j
a≡h≡j
b≡e
d≡k
f≡i
k
a
b
b-f, c-i
g-k
b-j, c-k
i-g, g-h
b-e, c-f
i-c
b-i, c-i
g-d
c-f
c-i
a-h, d-e h-a
d-c, f-g
c
d
e
f-j, i-k
i-g, k-h
f-e, i-f
i-c, k-g
k-d
Present
State
00
b
b
a
a
f
a
a
b
c
d
f
g
Next State
01
f
c
d
c
f
d
f-b, i-f
i-c, k-g
j-e, k-f
h-g, g-c
j-i, k-i e-i, f-i
g-i, h-d c-i, g-d
j-b, k-f e-b
g-c, h-g
i-b, i-c
d-g, i-f
f
g
i
h
11
c
f
d
b
f
g
Z
0
0
1
1
0
0
10
g
g
f
g
d
a
j
15.16 (b) b
c
d
a-g, a-c
k-i
k-i
e
f
a≡d≡j
b≡e≡i≡k
c≡f≡h
g-a
c-d
Present
State
c-f, f-h
d-a
a-g, a-c
g-d
a-d
i-k
a-g, d-c
g-d, i-k
a-g, a-h
g-d
a-d
i-k
a-g, d-h
g-d, i-k
a
b
c
g
g
h
i
j
c-h
f-h
k
b
01
a
c
c
a
11
g
g
a
g
10
b
a
b
b
00
1
0
1
0
Z
01 11
0 0
0 0
0 0
1 0
c-h
a-j
i-k
f-c
a
Next State
f-h
a-d
g-j, c-j
a-g, i-k

00
a
c
g
c
c
d
g-j, c-j
d-g
f-c, h-c
a-d
e
f
184
g-j, h-j
d-g
h-c
g
h
i
j
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
10
0
0
0
0
Unit 15 Solutions
15.17 (a) S0 ≡ e ≡ f, S1 ≡ c ≡ d, S2 ≡ S3 ≡ a ≡ b
Since every state in N has an equivalent state in M, and
vice versa, N and M are equivalent.
S0
E − S3
D − S1
S1
S2
E − S0
A − S2
S3
E − S0
A − S3
A
F − S0
B − S2
F − S0
B − S3
B
E − S0
D − S1
E − S3
C − S1
E − S0
C − S1
C
D
B − S3
D − S1
B − S0
D − S1
B − S0
C − S1
E
S0
S1
S2
S3
Next State
X =0
S1
S0
S3
S0
1
S0
S2
S3
S3
Note:
S10
S11
S12
S13
Next State
X =0
S11
S10
S13
S10
1
S10
S12
S12
S13
15.18 (b) S S − S1
0
1
1
S0 − S10
S1 S0 − S11
S2 − S10
S2
Output
0
0
1
0
S0
S1
S2
S3
Next State
X =0
S1
S3
S2
S2
1
S2
S2
S2
S2
1
S1
S1
S2
X =0 1
A
E A 1
C
E C 0
E
A C 0
E ≡ F, C ≡ D, A ≡ B
0
0
1
S2 ≡ A
S1 ≡ C
S0 ≡ E
S1 − S10
S0 − S12
S0 − S10
S2 − S12
S3 S0 − S11 S0 − S10
S3 − S10 S3 − S12
S10
S11
S1 − S10
S0 − S13
S3 − S13
S3 − S12
S12
S0 − S10
S2 − S13
S0 − S10
S3 − S13
S13
S2 and S12 have no corresponding states,
∴ N and N' are not equivalent.
Output
0
0
1
0
15.18 (c) X = 0 1 1
Z = (0) 0 1 1
Z1 = (0) 0 1 0
15.19 (a) Set don’t care to 0 so S2 ≡ S4 ≡ S5:
Present
State
N
F
Set don’t care to S2 so S4 ≡ S1:
Present
State
M
X =0
S0
S2
S1
S0
S2
S0
S2 ≡ S3
B − S3
C − S1
15.18 (a) Set don’t care to S3 so S4 ≡ S3:
Present
State
15.17 (b)
Output
X=0 X=1
0
0
1
1
0
1
1
1
Set don’t care to 0 so S1 ≡ S3 ≡ S4:
Present
State
S01
S11
S21
S51
Next State
X =0
S11
S11
S12
S15
1
S15
S12
S11
S12
Output
X=0 X=1
0
0
1
1
0
1
0
1
15.19 (b) S S − S1
15.19 (c) X = 1 0
0
1
1
Z= 01
S2 − S15
Z1 = 0 0
S1
S3 − S11
S2 − S12
No equivalent
S2
S2 − S12 S2 − S15
states.
S2 − S11 S2 − S12
S3
S2 − S11
S2 − S12
S01
S11
S12
S15
185
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 15 Solutions
15.20 (a) Invert all three columns of assignment (iv), and
then swap the first and last columns. Then (iii)
and (iv) are the same, therefore, Assignment (iii) ≡
Assignment (iv).
15.20 (b) Equivalent assignments to each column having 000
as the starting state. Invert any column with 1 in
the first row.
15.20 (c) Many state assignments are not equivalent to
(i) through (v), for example:
101
000
011
100
010
110
15.21 (a)
or
011
101
000
100
010
110
Straight
Binary
Assignment
000
001
010
011
100
101
110
111
(ii) - (c'2)
000
101
011
100
010
110
S0
S1
S2
S3
S4
S5
iii - c'1
000
001
100
101
011
010
iv - c'1c'2 v - c'3
000
000
100
110
001
100
101
010
110
001
010
011
Equivalent State Assignments (any three)
c2 ↔ c3
c1 ↔ c3
c1 ↔ c2
c1 → c3→ c2→ c1
c1 → c2→ c3→ c1
000
001
000
100
000
010
000
010
000
100
100
101
010
011
110
111
010
110
001
101
011
111
001
011
100
110
101
111
100
110
001
011
101
111
001
101
010
110
011
111
15.21 (b) Many state assignments are not equivalent to the
straight binary assignment, for example:
15.22 (a) 1. (A, H) (B, G) (A, D) (E, G)
2. (D, G) (E, H) (B, F) (F, G) (C, A) (H, C) (E, A)
(D, B)
3. (A, C, E, G) (B, D, F, H)
Consider Guideline #3 only:
111
101
111
001
110
100
011
010
001
000
010
011
100
101
000
110
Q2 Q3
Q1
etc.
0
1
00
B
A
01
D
11
10
Q2 Q3
Q1
0
1
00
0
1
C
01
0
1
F
E
11
0
1
H
G
10
0
1
Z = Q1
186
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 15 Solutions
15.22 (b) Consider Guidelines #1, 2:
A = 000, B = 111, C = 110, D = 001, E = 010,
F = 101, G = 011, H = 100
Q1
Q2 Q3
X Q1
00
Q2 Q3
11
10
0
0
1
0
00
01
1
1
1
0
B
11
0
0
1
C
10
1
1
1
1
00
A
H
00
01
D
F
11
G
10
E
Q2 Q3
X Q1
00
01
0
11
10
0
0
1
1
00
01
0
0
1
1
0
11
1
1
0
0
10
1
1
0
D1 = X'Q2'Q3 + X'Q2Q3' + XQ1
15.23 (a) 1. (A, C)×2 (B, C)×2 (A, D)
2. (A, C) (B, D) (A, B, D)
(A, B, C, D)
3. (A, D)
Adjacencies that are satisfied are checked ()
Q2
Q1
0
1
0
A
C
1
D
B
Q1Q2
00
11
10
01
00
00
11
00
01
Q
01
00
01
00
11
X Q1
00
01
Q2 Q3
01
11
10
1
1
1
1
01
1
0
0
1
0
11
0
0
0
0
0
10
0
1
1
0
D2 = X'Q2 + XQ2'
15.23 (b)
D3 = Q1'Q2' + Q1Q3'
X1 X2
00
Q1 Q2
01
11
10
00
0
0
1
1
01
0
1
0
1
11
1
0
1
0
10
0
0
1
0
11
10
1
1
1
1
Q1+
Q
11
10
11
11
00
+
1
+
2
10
10
01
01
10
00
01
11
11
01
Z1Z2
01 11
01 01
11 11
11 00
01 01
X1 X 2
00
Q1 Q2
01
00
10
01
11
00
01
01
1
1
11
1
1
10
Q2+
15.23 (b)
(cont.)
Q1 Q2
X1 X2
00
01
11
10
Q1 Q2
X1 X2
00
01
11
10
Q1 Q2
X1 X2
00
01
11
10
Q1 Q2
X 1 X2
00
01
11
10
00
0
0
1
1
00
X
X
X
X
00
0
0
0
0
00
X
X
X
X
01
0
1
0
1
01
X
X
X
X
01
X
X
X
X
01
0
0
1
1
11
X
X
X
X
11
0
1
0
1
11
X
X
X
X
11
0
0
0
0
10
X
X
X
X
10
1
1
0
1
10
0
0
1
1
10
X
X
X
X
J1 = X1'X2Q2 + X1X2' + X1Q2'
K1 = X1'X2 + X1X2' + X2'Q2'
K1 = X1'X2 + X1X2' + X1'Q2'
187
J2 = X1Q1
K2 = X1Q1'
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 15 Solutions
15.24 (a) Equations for one-hot state assignment:
DA = X(A + B + D + E), DB = X'(A + D),
DC = X'B, DD = XC, DE = X'(C + E), z = D
15.24 (b) Guidelines:
1. (A, D)x2 (C, E) (A, B, D, E)
2. (A, B)x2 (A, C) (D, E) (A, E)
Q1+Q2+Q3+
z
Q1Q2Q3 X = 0 1
000
001 000
0
010
111 000
0
011
011 000
0
010
001 000
1
110
--- --111
011 010
0
101
--- --100
--- --D1 = X'Q2'Q3, D2 = X'Q3 + Q1, D3 = X',
z = Q2Q3'
The following assignment satisfies all but (A, E),
(A, C) and (B, D):
Q1
0
1
00
A
-
01
B
-
11
E
C
10
D
-
Q2 Q3
15.25 (a) B
C A-F
B-G
D
E A-I
B-G
F A-H
B-I
G
A≡F≡H
B≡I
D≡G
E-A
F-I
E-F
State
A
B
C
D
E
I-H
G-I
A-F
G-B
B
I-F
G-B
H-F
I-B
A-E

A
Q2 Q3
F-H
G-I
H A-F
I
15.25 (b) 1. (A, C) (B, D) (C, E)
2. (A, B) (C, E) (A, D) (A, C) (B, D)
3. (A, C, E) (B, D)
Adjacencies that are satisfied are checked ()
A = 000, B = 100, C = 001, D = 101, E = 011
All are satisfied except (A, D)
Alternate:
C
Next State
X=0 X=1
A
B
C
E
A
D
C
A
B
D
D
Q1
Q1
0
1
00
A
B
00
A
01
C
D
01
C
11
E
11
E
10
B
Q2 Q3
10
0
1
D
F-E
E
F
G
H
15.25 (c)
X
1
0
1
0
1
Q1Q2Q3
000
100
001
101
011
188
Q1+Q2+Q3+
X=0 1
000 100
001 011
000 101
001 000
100 101
Z
1
0
1
0
1
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 15 Solutions
15.25 (c) (cont.)
X Q1
00
Q2 Q3
X Q1
00
0
1
0
0
1
00
0
0
1
0
00
0
1
1
0
00
1
0
01
0
0
0
1
01
0
0
0
0
01
0
1
0
1
01
1
0
11
1
X
X
1
11
0
X
X
0
11
0
X
X
1
11
1
X
10
X
X
X
X
10
X
X
X
X
10
X
X
X
X
10
X
X
10
X Q1
11
10
X Q1
00
00
01
11
10
00
0
X
X
1
00
01
0
X
X
1
11
1
X
X
10
X
X
X
Q2 Q3
Q2 Q3
X Q1
00
Q2 Q3
X Q1
00
11
10
X
1
1
X
00
01
X
1
1
X
1
11
X
X
X
X
10
X
X
X
X Q1
00
Q2 Q3
Z = Q1'
Q2 Q3
X Q1
00
01
11
10
X
X
X
X
01
X
X
X
X
X
11
1
X
X
1
X
10
X
X
X
X
10
0
0
1
0
00
01
0
0
0
0
X
11
X
X
X
X
10
X
X
X
K2 = 1
J2 = XQ1Q3'
01
11
10
0
1
1
0
00
X
X
X
X
01
X
X
X
X
01
1
0
1
0
11
X
X
X
X
11
1
X
X
0
10
X
X
X
X
10
X
X
X
X
10
10
11
00
11
11
01
K1 = 1
01
01
Q3+ = X'Q1 + X Q1'Q3 + Q1Q3'
01
J1 = Q2 + X
15.25 (d)
Q2 Q3
Q2+ = XQ1Q3'
Q1+ = Q2 + XQ1'
Q2 Q3
01
Q2 Q3
Q1
0
11
Q2 Q3
X Q1
00
00
01
K3 = X'Q1' + XQ1
J3 = Q1
Output Z equation is the same for D and J-K flip-flops.
(Actually, it is the same for any flip-flop.)
15.26 (a) B I-B
C-I
C I-C B-C
C-G I-G
D
Present
State
E
I-D
C-E
F

G
I-E
C-F
H I-H
C-A
I

A
B-H
I-A
B-A
I-C
B
A
B
C
D
E
G
A≡I
B≡H
D≡F
C-H
G-A
C-A
G-C
C
D
D-I
E-C
D-E
E-F
E
Next State
X =0
A
B
C
A
D
E
1
C
A
G
C
E
D
Output
1
1
1
0
0
0
I-E
C-F
F
G
189
H-A
A-C
H
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 15 Solutions
15.26 (b) 1. (A, D)×2
2. (A, C)×2 (A, B) (C, G) (D, E)×2
3. (A, B, C) (D, E, G)
There are several solutions. Here is one satisfying
all guidelines:
A = 000, B = 010, C = 001, D = 100, E = 110,
G = 101
Q2 Q3
Q1
0
1
00
A
D
01
C
G
B
E
11
10
15.26 (c)
Q1Q2Q3
000
010
001
100
110
101
Q2 Q3
Q1+Q2+Q3+
X=0 1
000 001
010 000
001 101
000 001
100 110
110 100
X Q1
00
Z
1
1
1
0
0
0
01
11
10
X Q1
00
Q2 Q3
01
11
10
Q2 Q3
X Q1
00
01
11
10
00
0
0
0
0
00
0
0
0
0
01
0
1
1
1
01
0
1
0
0
11
X
X
X
X
11
X
X
X
X
10
0
1
1
0
10
1
0
1
0
D2 = X'Q1'Q2 + X'Q1Q3 + XQ1Q2
D1 = Q1Q3 + Q1Q2 + XQ3
Q2 Q3
Q1
0
1
00
0
0
1
1
00
1
0
01
1
0
0
1
01
1
0
11
X
X
X
X
11
X
X
10
0
0
0
0
10
1
0
Z = Q 1'
D3 = Q1'Q3 + XQ2'Q3'
15.26 (d) Again, Z = Q1':
Q2 Q3
X Q1
00
01
11
10
Q2 Q3
X Q1
00
11
10
Q2 Q3
X Q1
00
01
11
10
00
0
X
X
0
00
0
0
0
0
00
0
0
1
1
01
0
X
X
1
01
0
1
0
0
01
X
X
X
X
11
X
X
X
X
11
X
X
X
X
11
X
X
X
X
10
0
X
X
0
10
X
X
X
X
10
0
0
0
0
J2 = X'Q1Q3
J1 = XQ3
Q2 Q3
01
X Q1
00
01
11
10
Q2 Q3
X Q1
00
J3 = XQ2'
01
11
10
Q2 Q3
X Q1
00
01
11
10
00
X
1
1
X
00
X
X
X
X
00
X
X
X
X
01
X
0
0
X
01
X
X
X
X
01
0
1
1
0
11
X
X
X
X
11
X
X
X
X
11
X
X
X
X
10
X
0
0
X
10
0
1
0
1
10
X
X
X
X
K1 = Q2'Q3'
K2 = X'Q1 + XQ1'
190
K3 = Q1
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 15 Solutions
15.27 (a)
Present
State
Next State
X =0
S1
S1
S3
S5
S0
S1
S2
S3
S4
S5
Q2 Q3
Output
X=0 X=1
0
0
0
0
1
0
0
0
1
S4
S2
S4
S2
S3 S4
S1 S2
X Q1
00
00
01
11
X
X
01
1
1
11
1
X
0
0
Q2 Q3
10
X Q1
00
X Q1
00
Q2 Q3
00
S3
11
S2
10
S1
X
00
01
1
1
01
1
11
X
X
11
1
1
1
1
1
Q2 Q3
X Q1
00
10
X
X
X
00
1
X
01
X
X
X
X
11
1
1
1
X
10
11
X
X Q1
00
01
11
X
X
00
01
1
X
11
1
X
10
Q2 Q3
S1 = X'Q3
One alternative assignment:
0
0
1
2
1
3
5
4
11
10
X
X
1
00
1
1
01
X
1
11
1
1
10
X
X Q1
00
11
X
X
10
X
X
X
00
X
01
1
1
11
X
X
X
X
X Q1
00
X
00
01
1
1
01
X
11
X
X
11
X
X
X
X
10
Q2 Q3
X
1
11
X
X
X
X
10
X
X
X
01
11
10
X
X
1
X
X
X
X
1
1
X
10
S2 = X'Q3' + Q1
S3 = X
(a) D1 = XQ1'Q2' + Q2 + X'Q1Q3'; D2 = X; D3 = X'Q2'
Z = X'Q1'Q2 + XQ1Q3
(b) S1 = XQ1'Q3' + Q2; R1 = XQ1Q2' + Q3; S2 = X;
R2 = X'; S3 = X'Q2'; R3 = X; Z = X'Q1'Q2 + XQ1Q3
191
10
1
R3 = X'Q1
11
00
01
11
1
01
Z = X'Q2Q3 + XQ1Q3'
Q3+ = Q1'Q3 + X
01
10
10
01
10
10
Q2 Q3
X Q1
00
11
10
X Q1
00
Q2 Q3
01
R2 = Q2Q3
X
Q2 Q3
Q1 00
Q1+Q2+Q3+
Z
X=0 1 X=0 X=1
010 001
0
0
010 011
0
0
101 001
1
0
110 011
0
0
101 001
0
0
010 011
0
1
01
X
R1 = X + Q3'
Q2 Q3
X Q1
00
X
1
11
01
Q1Q2Q3
000
010
011
101
001
110
S5
Q2 Q3
10
01
X
10
S4
Q2+ = X'Q3' + Q1 + Q2Q3'
Q1+ = X'Q3
15.27 (b)
01
11
10
10
00
S0
1
1. (S0, S1, S5) (S0, S2, S4) (S1, S3, S5)
2. (S1, S4) (S1, S2)×2 (S3, S4)×2 (S2, S5)
3. (S0, S1, S3, S4)
S0 = 000. S1 = 010, S2 = 011, S3 = 101, S4 = 001,
S5 = 110
01
00
X
0
Q 2 Q3
0
1
Q1
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 15 Solutions
15.28
Present
State
Next State
X=0
S2
S5
S3
S3
S4
S4
S0
S1
S2
S3
S4
S5
Q1 Q2
Q3 00
01
11
0
0
2
3
1
1
5
4
1
S1
S0
S1
S4
S3
S0
10
Z
0
0
0
0
1
0
Q1+Q2+Q3+
X=0 1
010 001
011 000
110 001
110 111
111 110
111 000
Q1Q2Q3
000
001
010
110
111
011
Z
0
0
0
0
1
0
1. (S2, S3) (S4, S5) (S0, S2) (S1, S5)
2. (S1, S2) (S0, S5) (S1, S3) (S3, S4)×2 (S0, S4)
S0 = 000, S1 = 001, S2 = 010, S3 = 110, S4 = 111,
S5 = 011
Guideline 3 is of no use for this state table.
15.28 (b)
15.28 (a)
Q2 Q3
X Q1
00
01
11
10
Q2 Q3
X Q1
00
10
Q2 Q3
X Q1
00
01
11
10
Q2 Q3
X Q1
00
0
X
X
0
00
X
X
X
X
00
01
11
10
0
X
X
0
00
0
X
X
0
01
0
X
X
0
01
0
X
X
0
01
X
X
X
X
01
0
X
X
0
11
1
1
1
0
11
1
X
X
0
11
X
0
0
X
11
1
0
0
0
10
1
1
1
0
10
1
X
X
0
10
X
0
0
X
10
1
0
0
0
J1 = X'Q2
X Q1
00
01
11
10
Q2 Q3
X Q1
00
T1 = X'Q1'Q2
K1 = 0
01
11
10
Q2 Q3
X Q1
00
01
11
10
Q2 Q3
X Q1
00
01
11
10
00
1
X
X
0
00
1
X
X
0
00
X
X
X
X
00
1
X
X
0
01
1
X
X
0
01
1
X
X
0
01
X
X
X
X
01
1
X
X
0
11
1
1
1
0
11
X
X
X
X
11
0
0
0
1
11
0
0
0
1
10
1
1
1
0
10
X
X
X
X
10
0
0
0
1
10
0
0
0
1
J2 = X'
Q2+
Q2 Q3
11
00
Q1+
Q2 Q3
01
X Q1
X Q1
00
00
01
11
10
00
0
X
X
1
00
0
X
X
01
1
X
X
0
01
X
X
11
1
1
0
0
11
X
10
0
0
1
1
10
0
Q3+
Q2 Q3
01
11
T2 = X'Q2' + XQ1'Q2
K2 = XQ1'
10
Q2 Q3
X Q1
00
01
11
10
Q2 Q3
X Q1
00
01
11
10
0
X
X
1
01
0
X
X
1
1
11
0
0
1
1
X
10
0
0
1
1
1
00
X
X
X
X
00
X
X
01
0
X
X
1
X
X
X
11
0
0
1
0
1
1
10
X
X
X
J3 = X
192
K3 = X
T3 = X
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 15 Solutions
15.29
See solutions to 14.22 for the state table.
I. (S0, S1, S7) (S2, S6) (S3, S4, S5) (S0, S6) (S1, S7)
(S2, S3, S5)
II. (S1, S6) (S6, S7) (S1, S2)×2 (S3, S7) (S3, S4)×2
(S4, S5)
III. (S0, S1, S3, S4, S6) (S2, S5)
Q 2 Q3
Q1
0
1
00
S0
S6
01
S1
S5
11
S3
S4
10
S7
S2
Q2 Q3
Q1Q2Q3
000
001
110
011
111
101
100
010
X Q1
00
01
11
10
Q2 Q3
X Q1
00
01
11
10
00
0
1
0
0
1
01
0
1
1
1
0
11
1
1
0
1
10
0
1
00
0
0
1
1
01
0
1
0
11
1
1
10
0
0
Q1+Q2+Q3+
Z
X=0 1 X=0 X=1
001 100
00
00
001 110
00
00
010 011
00
01
111 011
00
00
111 101
00
00
111 011
00
01
010 100
00
00
001 110
10
00
Q2 Q3
X Q1
00
01
11
10
00
1
0
0
0
1
01
1
1
1
0
0
1
11
1
1
1
1
1
1
10
1
0
1
0
++ Q 'Q Q
+ '=
+
X'Q
+ 3X'Q1 Q3 + X QQ
+ X'Q
X QQ
'+X
Q 'Q33' 1+
Q1 += X'QQ21+Q=3 +
X'Q
'QQ
X3 Q2'QQ
' 1'++= Q
Q +QQ
X'Q
2 2
1 122+ Q
2Q13Q
1'Q
11'Q
1Q
2Q
2 3= X'Q
2Q
3+
3+3 X=QX'Q
2Q3Q
2 13' + Q 21Q33+ Q 1 Q3 + X Q 1 Q2
3
+ XQ2'Q3 + XQ2Q3'
+ XQ1'Q2' + XQ1'Q3'
+ XQ1Q2
+ XQ2'Q3' + Q1Q2Q3
Q2 Q3
X Q1
00
01
11
10
X Q1
00
01
11
10
00
0
0
0
0
00
0
0
0
0
01
0
0
0
0
01
0
0
1
0
11
0
0
0
0
11
0
0
0
0
10
1
0
0
0
10
0
0
1
0
Z1 = X'Q1'Q2 Q3'
15.30
Q2 Q3
Z 2 = X Q 1Q 2'Q 3 + X Q 1Q2 Q 3'
See FLD p. 761 for the state table.
I. (S0, S1) (S2, S3) (S4, S5, S7) (S0, S2, S3) (S1, S4)
(S5, S6, S7)
II. (S1, S3) (S1, S2) (S3, S4)×2 (S2, S5) (S5, S6)×2
(S6, S7)
III. (S0, S1, S3, S5, S6) (S4, S7)
S0 = 000, S1 = 001, S2 = 010, S3 = 011, S4 = 111,
S5 = 110, S6 = 100, S7 = 101
193
Q1Q2Q3
000
001
010
011
111
110
100
101
Q1+Q2+Q3+
Z
X=0 1 X=0 X=1
001 011
00
00
001 010
00
00
111 011
10
00
111 011
00
00
110 010
01
00
110 100
00
00
101 100
00
00
110 100
01
00
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 15 Solutions
15.30 (cont.)
01
11
10
0
X Q1
Q2 Q 3
00
00 0
X
X
0
0
01
X
X
0
X Q1
00
Q2 Q 3
00 0
01
11
10
1
1
01
1
1
11
10
0
1
1
1
0
1
0
1
0
11
0
1
10
1
Q1+
X
X
0
X
0
X Q1
00
01
11
10
0
0
1
01
0
1
0
1
11
1
1
1
1
10
1
1
0
1
X Q1
00
Q2 Q 3
01
11
10
0
0
0
1
01
0
1
0
11
X
X
10
X
X
X Q1
00
01
11
10
1
0
1
00
01
1
0
0
0
11
1
0
0
10
1
0
0
Q2 Q3
0
0
X
01
X
0
0
X
11
X
0
1
X
10
X
0
0
X
Q2 Q 3
X Q1
00
01
11
10
X
X
X
X
1
01
X
X
X
X
X
X
11
0
0
0
0
X
X
10
0
0
1
0
11
10
1
1
0
1
01
X
X
X
1
11
X
X
1
10
1
0
Q2 Q3
K2 = X Q1Q3'
X Q1
00
X Q1
00
01
11
10
00
0
0
0
0
01
0
0
0
0
11
0
0
0
0
10
1
0
0
0
X Q1
00
01
11
10
00
0
0
0
0
01
0
1
0
0
11
0
1
0
0
10
0
0
0
0
Z 2 = X'Q 1 Q 3
01
11
10
00
X
X
X
X
X
01
0
1
1
1
X
X
11
0
1
1
0
0
1
10
X
X
X
X
Q2 Q 3
K3 = Q1 + X Q 2'
J 3 = Q1' + X'Q2'
3
Q2 Q3
Z 1 = X'Q1'Q2 Q 3'
00
01
Q+
10
X
J 2 = X'Q1Q3 + XQ1'Q2'
X Q1
00
Q2 Q 3
00 1
11
K1 = X Q2 Q 3
00
Q 2+
01
00
J1 = X'Q 2
X Q1
00
Q2 Q 3
00 0
15.31
X
Q2 Q 3
Row reduction of the solution to 14.6 given on FLD p. 762 easily gives 4 states. Renaming them gives:
Present
State
S0
S1
S2
S3
Q2
Q1
0
00
S0
S0
S2
S2
1
0
S0
S2
1
S1
S3
Next State
01
S1
S1
S3
S3
11
S1
S1
S2
S2
Z
0
0
1
1
10
S0
S3
S0
S3
Q1 Q 2
See p. 158 in this manual for the state
table.
I. (S0, S1)×3 (S2, S3)×2 (S0, S2) (S1, S3)
II. (S0, S1) (S0, S1, S3) (S0, S2, S3) (S2, S3)
III. (S0, S1) (S2, S3)
S0 = 00, S1 = 01, S2 = 10, S3 = 11
X1 X2
00
Q1Q2
00
01
10
11
01
11
10
Q1 Q 2
X1 X2
00
01
11
10
Q1+Q2+
01 11
01 01
01 01
11 10
10
00
11
00
Z
0
0
1
10 11 10 11
1
00
00
00
10
Q2
Q1
00
0
1
0
1
0
0
01
0
1
1
1
1
1
1
11
0
1
1
0
0
1
10
0
1
0
0
00
0
0
0
0
01
0
0
1
11
1
1
10
1
1
D1 = X1 X2 Q2 + X1'Q1 + X2'Q1
194
0
0
1
0
1
1
Z = Q1
D 2 = X1'X2 + X1 X2'Q 1' + X 2 Q 2
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 15 Solutions
15.32
See answers to 14.23 for the state table.
The four-state table is minimum.
I. (S0, S1)×3 (S0, S3) (S1, S2) (S2, S3)×3
II. (S0, S1) (S0, S1, S2) (S2, S3) (S0, S2, S3)
III. (S0, S1) (S2, S3)
Q1Q2
00
01
11
X1 X2
00
X1 X2
Q1 Q 2
00
00 0
01
11
10
0
0
0
00
01
0
0
0
1
11
1
1
1
10
1
1
1
Q1 Q 2
W A
00
B C
Z
0
0
1
11 10 00 10
1
01
11
10
1
1
0
0
01
1
1
0
0
1
11
1
0
0
1
0
10
1
0
0
0
Q2
Q2
Q1
Q1
0
1
0
S0
S3
1
S1
S2
0
1
0
0
1
1
0
1
Z = Q1
D2 = X1'X 2' + X1'Q1' + X2'Q 1Q 2
D1 = X1'Q1 + X1 X2'Q 2+ X2 Q 1
15.33
10
00
00
10
00
01
01
11
10
Q1+Q2+
01 11
01 00
01 11
10 11
B C
W A
00
01
11
10
0
0
0
00
0
1
1
1
00
1
1
0
1
01
0
1
1
1
01
1
0
0
0
01
0
1
0
0
11
1
0
1
0
11
1
0
0
1
11
0
1
1
1
10
1
1
0
1
10
1
0
1
0
10
0
0
0
1
10
11
10
W A
00
0
11
01
B C
00
01
TA
W A
00
B C
TB
01
11
10
B C
W A
00
TC
01
11
10
B C
W A
00
01
11
10
1
1
0
1
00
0
1
1
0
00
0
1
1
1
00
01
0
0
0
1
01
1
0
0
0
01
1
0
1
1
11
1
1
0
0
11
0
1
1
0
11
1
0
0
0
10
1
0
1
1
10
0
1
0
1
10
0
0
0
1
A+
ABC
000
001
010
011
100
101
110
111
A+B+C+
W =0 1
001 011
011 101
100
101
111
000
010
110
111
000
110
001
100
010
C+
B+
0
0
0
1
0
0
0
1
0
Z
1
0
0
0
0
0
0
0
0
Present
State
Next State
0
1
W =0
1
3
1
3
5
0
0
0
2
3
4
5
6
7
4
5
7
0
2
6
7
0
6
1
4
2
1
0
0
0
1
0
195
Z
0≡1≡3≡5
1
0
0
0
0
0
0
0
0
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 15 Solutions
15.33
(cont.)
I. None
II. (4, 7) (6, 7) (2, 4) (2, 6)
Assignment:
S0 = 000, S2 = 100, S4 = 111, S6 = 110, S7 = 101
B C
A
00
0
Present
State
1
S0
S0
S2
S4
S6
S7
S2
01
S7
11
S4
10
S6
Next State
W =0
S0
S4
S7
S2
S6
1
S0
S7
S6
S4
S2
Present
State
Output
0
0
1
0
0
0
1
0
0
0
0
0
000
100
111
110
101
Next State
W =0
000
111
101
100
110
1
000
101
110
111
100
Output
0
0
1
0
0
0
1
0
0
0
0
0
T input equations derived from the transition table using Karnaugh maps:
TA = 0; TB = W'A; TC = WB + AB'; Z = W'AB'C'
15.34
By inspecting incoming arrows, we get:
D0 = Q0+ = X'Y'Q0 + XYQ3
D1 = Q1+ = XQ0 + Y'Q1 + XY'Q3
D2 = Q2+ = X'YQ0 + X'Q2 + X'YQ3
D3 = Q3+ = YQ1 + XQ2 + X'Y'Q3
S = YQ1 + XQ2
P = X'Y'Q3
X'Y'
0
X
Y'
S0
0
XY
S1
XY'
0
Y
S
X'Y
0
S
S2
X'Y
0
0
X
S3
X'
0
S
X'Y'
P
15.35
15.36
By inspecting incoming arrows, we get:
Q0+ = D0 = X'YQ0 + Y'Q1 + X'YQ2
Q1+ = D1 = XY'Q0 + XYQ1 + Y'Q2
Q2+ = D2 = XYQ0 + X'Y'Q0 +X'YQ1 + XYQ2
Z = X'YQ1 + XYQ2 + X'YQ2 = X'YQ1 + YQ2
Q2Q1Q0
000
010
010
011
100
101
110
111
15.37 (a) By inspecting incoming arrows, we get:
DA = QA+ = X
DB = QB+ = X'QA
DC = QC+ = X'QB
DD = QD+ = X'(QC + QD)
Z = XQC
15.37 (b)
196
Clr, Ld, Cnt
X=0 1
101
101
101
0----------
101
101
101
11---------
Clr = Q1' + Q0' + x
Ld = Q1Q0
Cnt = 1
P2 = 0
P1 = 0
P0 = 1
Q1+Q0+
Z
Q1Q0
X=0 1 X=0 X=1
00
01 00
0
0
01
11 00
0
0
11
10 00
0
1
10
10 00
0
0
D1 = X'(Q1 + Q0), D0 = X'Q1', Z = XQ1Q0
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 15 Solutions
15.37 (c) For the counter, a better state assignment is A = 00,
B = 01, C = 10 and D = 11.
s1s0
Z
X=0 1 X=0 X=1
Q1Q0
00
01 11
0
0
01
01 11
0
0
11
00 11
0
0
10
01 11
0
1
s1 = X, s0 = X + Q1' + Q0', Z = XQ1Q0'
P3 = -, P2 = -, P1 = -, P0 = -
s1s0
Z
Q3Q2 Q1Q0 X = 0 1 X = 0 X = 1
0000
01 11
0
0
1000
01 11
0
0
1100
01 11
0
1
1110
00 11
0
0
s1 = X, s0 = X + Q1', Z = XQ2Q1', Sin = 1,
P3 = -, P2 = -, P1 = -, P0 = -
15.37 (d) Another possibility is to duplicate state D and use
(cont.) 1110 and 1111 as state assignments for the two D's.
s1s0
Z
Q3Q2 Q1Q0 X = 0 1 X = 0 X = 1
0000
01 11
0
0
1000
01 11
0
0
1100
01 11
0
1
1110
01 11
0
0
1111
01 11
0
0
s1 = X, s0 = 1, Z = XQ2Q1', Sin = 1,
P3 = -, P2 = -, P1 = -, P0 = 15.38 (b)
Q1Q2
00
01
11
10
Q1+Q2+
X=0 1
00
00
00
00
Q1Q2
00
01
11
10
01
10
11
11
15.37 (d) For the shift register, the state assignment A = 0000,
B = 1000, C = 1100 and D = 1110 makes use of the
shift function.
T1T2
X=0 1
00
00
00
00
01
10
11
11
15.38 (a) Q1+ = XQ1 + XQ2 = XQ1 + XQ2(Q1 + Q1')
= XQ1 + XQ2Q1' = (X + Q1')(X' + Q2' + Q1)Q1
+ (X'Q1 + XQ2Q1')Q1'
= (X'Q1 + XQ2Q1')'Q1 + (X'Q1 + XQ2Q1')Q1'
so T1 = (X'Q1 + XQ2Q1')
Q2+ = XQ1 + XQ2' = XQ1(Q2 + Q2') + XQ2'
= XQ1Q2 + XQ2'
so T2 = (XQ1)'Q2 + XQ2'
= X'Q2 + Q1'Q2 + XQ2'
15.38 (c) Q1+ = XQ1 + XQ2 = XQ1 + XQ2(Q1 + Q1')
= XQ1 + XQ2Q1'
so J1 = XQ2, K1 = X'
Q2+ = XQ1 + XQ2' = XQ1(Q2 + Q2') + XQ2'
= XQ1Q2 + XQ2'
so J2 = X, K2 = (XQ1)' = X' + Q1'
The equations for T1 and T2 are the same as in Part
(a).
15.38 (d)
15.39 (a) Q1+ = J1Q1' + K1'Q1 = Q2Q1' + Q1'Q1 = Q2Q1'
so T1 = Q1 + Q2Q1' = Q1 + Q2
Q2+ = J2Q2' + K2'Q2 = (X + Q1')Q2' + (1)'Q2
= (X + Q1')Q2'
so T2 = Q2 + (X + Q1')Q2'
= Q2 + X + Q1'
J1K1, J2K2
Q1Q2
X =0
X =1
00
01
11
10
0-, 00-, -1
-1, 0-1, -1
0-, 11-, -1
-0, 1-0, -0
The equations for J1, K1, J2 and K2 are the same as
in Part (c).
197
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 15 Solutions
15.39 (b)
J1K1, J2K2
Q1Q2
X=0
X=1
00
01
11
10
00, 11
10, 11
11, 01
01, 01
00, 11
10, 11
11, 11
01, 11
Q1Q2
00
01
11
10
Q1+Q2+
X=0 1
01
10
00
00
T1T2
X=0 1
Q1Q2
01
10
00
01
00
01
11
10
01
11
11
10
01
11
11
11
The equations for T1 and T2 are the same as in Part
(a).
15.39 (c) Q1+ = S1 + R1'Q1 = Q2Q1' + Q1'Q1
so S1 = Q2Q1' and R1 = Q1
Q2+ = S2 + R2'Q2 = (X + Q1')Q2' + (Q2)'Q2
so S2 = (X + Q1')Q2' and R2 = Q2
15.39 (d)
S1R1, S2R2
Q1Q2
X=0
X=1
00
01
11
10
0-, 10
10, 01
01, 01
01, 0-
0-, 10
10, 01
01, 01
01, 10
The equations for S1, R1, S2 and R2 are the same as
in Part (c).
15.40
The implication chart verifies the answer.
S7 ~ S9 and S8 ~ S10 so the table reduces to
Present Next State Output (Z)
State
X = 0 X = 1 X =0
X=1
S0
S1
S2
0
0
S1
S3
S4
0
0
S2
S5
S6
0
0
S3
S7
S8
0
0
S4
S8
S7
0
0
S5
S8
S7
0
0
S6
S7
S8
0
0
S7
S0
S0
1
0
S8
S0
S0
0
1
Now S3 ~ S6 and S4 ~ S5 so the table reduces to
Present Next State Output (Z)
State
X = 0 X = 1 X =0
X=1
S0
S1
S2
0
0
S1
S3
S4
0
0
S2
S4
S3
0
0
S3
S7
S8
0
0
S4
S8
S7
0
0
S7
S0
S0
1
0
S8
S0
S0
0
1
S1
S1, S3
S2, S4
S2
S1, S5
S2 , S 6
S3, S5
S3
S1, S7
S2, S8
S3, S7 S5, S7
S4, S8 S6, S8
S4
S1, S8 S3, S8 S5, S8 S7, S8
S2, S9 S4, S9 S6, S9 S8, S9
S5
S1, S10 S3, S10 S5, S10 S7, S10
S8, S10
S2, S9 S4, S9 S6, S9 S8, S9
S6
S1, S9 S3, S9 S5, S9
S7, S9 S8, S9
S2, S8 S4, S8 S6, S8
S4, S6
S9, S10
S8, S9
S7
S8
S0, S1
S0, S3 S0, S5
S0, S7 S0, S8 S0, S10 S0, S9
S9
√
S10
√
S0
S1
S2
S3
S4
S5
S6
S7
S8
Maximal Compatibles: (S3 S6), (S4 S5), (S7 S9), (S8 S10)
198
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
S9
Unit 15 Solutions
15.41 (a)
15.41 (b)
S ,S
S1 S1, S3
2 3
S2
S1, S4
S2, S3
S0 S1 S3
S0 S2 S3
S0 S1 S4
S3, S4
S ,S
S3 0 1 S0, S3
S0, S2
S0, S3
S0, S4
S ,S
S4 S0, S1 S0, S3
0 2
S0, S3
S0, S4
S0
15.43 (a)
S1
S3
Maximal Compatibles: (S0 S1 S3), (S0 S1 S4),
(S0 S2 S3), (S0 S2 S4)
15.42 (a)
S1
S1, S3
S2, S4
S4
S1, S6 S3, S6
S2, S7 S4, S7
S1, S7 S3, S7
S ,S S ,S
S2, S6 S4, S6 5 7 6 7
S6, S7
S1
S2
Present
State
S0
S1
S2
S3
S4
S6
S7
Next
X=0
S1
S3
S4
S6
S7
S0
S0
State
X=1
S2
S4
-S7
S6
S0
S0
S0, S7
S3
S4
S5
Maximal Compatibles: (S0), (S1), (S2), (S3),
(S4 S5), (S6), (S7)
15.42 (b)
S1, S6 S3, S6
S5, S6
S2, S7 S4, S7
S4
S1, S7 S3, S7
S ,S S ,S
S2, S6 S4, S6 5 7 6 7
S7
√
S0, S5
S0
S3
S6
S6
S7
Output
X=0 X=1
0
0
0
0
0
1
S1, S3
S2, S4
S5 S1, S7 S3, S7 S5, S7
S5, S6
S5 S1, S7 S3, S7 S5, S7
State
X=1
B
B
B
S2 S1, S5 S3, S5
S2 S1, S5 S3, S5
S3
Next
X=0
A
C
A
15.41 (c) Any sequence ending in 1, places the circuit in
state B; if that is followed by inputs 01, the final
output is 1. If started in state A, it is a sliding
window sequence detector for 101.
S2
S1
Present
State
A
B
C
√
S0, S1 S0, S3
S0, S6 S0, S6
S0, S5
S0, S7
S0, S2 S0, S4
S0, S7 S0, S7
S0, S1 S0, S3
S0, S6 S0, S6
S0, S5
S ,S
S0, S2 S0, S4
S0, S7 S0, S7 0 7
S3
S6
S2
S4
S5
S0
S1
Maximal Compatibles: (S0 S1 S3 S6), (S0 S1 S3 S7),
(S0 S1 S4 S5 S6), (S0 S1 S4 S5 S7), (S0 S2 S3 S6),
(S0 S2 S3 S7), (S0 S2 S4 S5 S6), (S0 S2 S4 S5 S7)
S6
15.43 (b)
Output
X=0 X=1
0
0
0
0
0
-0
0
0
0
1
0
0
1
S6, S7
S0 S1 S3 S6
S0 S2 S4 S5 S7
S0 S1 S4 S5 S7
S0 S2 S4 S5 S6
S0 S1 S3 S7
Present
State
A
B
C
D
E
Next
X=0
A
C
E
C
A
State
X=1
B
D
D
D
B
Output
X=0 X=1
1
0
0
1
0
1
1
0
0
1
The same solution can be obtained using compatibles:
(S0 S1 S3 S6), (S0 S2 S4 S7), (S0 S1 S5 S7),
(S0 S2 S4 S6), (S0 S1 S3 S7)
199
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 15 Solutions
15.44 (a)
S1
S2
S3
15.44 (b)
S1, S3
S2, S4
S1, S5
S2, S6
S0 S1 S3 S6
S0 S2 S4 S5
S0 S2 S3 S6
S0 S1 S4 S5
S3, S5
S4, S6
S0, S1 S0, S3 S0, S5
S0, S2 S0, S4 S0, S6
Present
State
A
B
C
D
Next
X=0
A
D
D
A
State
X=1
B
C
C
B
Output
X=0
1
0
1
0
X=1
0
1
0
1
S4 S0, S1 S0, S3 S0, S5
S5
S0, S1 S0, S3 S0, S5
S0, S2 S0, S4 S0, S6
S6 S0, S1 S0, S3 S0, S5
S0
S1
S2
√
√
S3
S4
S5
Maximal Compatibles: (S0 S1 S3 S6), (S0 S1 S4 S5),
(S0 S2 S3 S6), (S0 S2 S4 S5)
15.45 (a)
S1
15.45 (b) Starting with any maximal compatible requires all
other maximal compatibles. Eight states would be
required.
S1, S3
S2, S4
S2
S1, S4
S3, S4
S2, S3
S3
S1, S5 S3, S5 S4, S5
S2, S6 S4, S6 S3, S6
S4
S1, S6 S3, S6 S4, S6
S2, S5 S4, S5 S3, S5
S5
S0, S1 S0, S3 S0, S4 S0, S5
S0, S2 S0, S4 S0, S3 S0, S6
S0, S6
S6
S0, S1 S0, S3 S0, S4 S0, S5
S0, S2 S0, S4 S0, S3 S0, S6
S0, S6
S0
S1
15.45 (c)
S2
S0 S3
S1 S5
S2 S6
S0 S4
S1 S6
S2 S5
S0, S5
Present
State
A
B
C
D
E
F
Next
X=0
B
A
D
E
A
D
State
X=1
C
D
A
F
D
A
Output
X=0
-1
0
-0
1
S0, S5
S3
S4
S5
Maximal Compatibles:
(S0 S1 S3 S5), (S0 S1 S3 S6), (S0 S2 S3 S5),
(S0 S2 S3 S6), (S0 S1 S4 S5), (S0 S1 S4 S6),
(S0 S2 S4 S5), (S0 S2 S4 S6)
200
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
X=1
-0
1
-1
0
Unit 16 Solutions
Unit 16 Problem Solutions
16.1 16.14
See Lab Solutions in this manual.
16.15
See FLD p. 767 for solution.
16.16
See FLD p. 768 for solution.
16.17 (a) The state meanings are given in the following table:
Name
S0
S1
S2
S3
Meaning
No 1’s have occurred
One 1 has occurred (an odd number < 2)
Two 1’s or an even number of 1’s > 2
have occurred
An odd number of 1’s > 2 has occurred.
16.17 (b)
Next State
State X = 0 X = 1
S0
S0
S1
S1
S1
S2
S2
S2
S3
S3
S3
S2
ai bi
Z
0
0
0
1
I: (1, 3)
II: (0, 1) (1, 2) (2, 3)2x
bi
ai
0
1
0
S0
S1
1
S2
S3
State
S0
S1
S2
S3
S0
0
aibi
00
10
01
11
xi
S1
0
0
0
1
00
0
1
01
0
1
11
1
0
10
1
0
1
1
S2
0
0
S3
1
0
1
xi
ai'
ai+1
x i'
ai
ai+1 = xia'i + x'a
i i
ai+1 = xi'ai + xi ai'
ai bi
ai+1bi+1
X=0 X=1
00
10
10
01
01
11
11
01
0
1
Z
0
0
0
1
xi
0
1
00
0
0
01
1
1
11
1
1
10
0
1
bi+1 = bi + xi ai
xi
ai
bi+1
bi'
bi+1 = b'i + xiai
ai+1
bi+1
Z
z = an+1bn+1
Note: Solution in FLD p. 768 uses state assignment S0 = 00,
S1 = 01, S2 = 10, S3 = 11.
16.17 (c) Since no 1’s have occurred, a1 and b1 are the same
as S0 or, a1 = 0; b1 = 0;
a2 = x1a1' + x1'a1 = x1;
first cell
b2 = b1 + x1a1 = 0
}
201
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Unit 16 Solutions
16.17 (d)
xi
ai
a i+1
Q
D
CK
b i+1
bi
Z
Q
D
CK
Typical Cell
16.18 (a)
ai
0
1
xi = 0
0
1
ai+1
xi = 1
1
1
xi = 0
0
1
Clk
yi
16.18 (a)
xi = 1
1
0
yi
xi
D
Clk
16.18 (b) ai+1 = ai + xi
yi = ai ⊕ xi
16.19 (a)
aibi
00
01
10
11
xi yi =
00
00
01
10
--
ai+1bi+1
xi yi = xi yi =
01
11
10
00
10
01
10
10
---
16.20 (a)
xi yi =
10
01
01
01
--
aibi
00
01
10
11
Clk Q'
ai+1bi+1
xi yi = xi yi =
01
11
10
00
01
01
10
10
10
11
xi yi =
10
01
01
10
01
Note: Since a1 = x1 and b1 = y1, the initial state of the
iterative circuit can be any one of the four states 00, 01, 10
or 11. Subsequent values are specified by the table.
16.19 (b) ai+1 = aixi' + aiyi + xi'yi
bi+1 = bixi + biyi' + xiyi'
16.20 (b) ai+1 = aixi' + aiyi + aibi + bi'xi'yi
bi+1 = bixi + biyi' + ai'bi + ai'xiyi'
xi yi =
00
00
01
10
11
Q
16.20 (d)
Si
16.20 (c) Z1 = an+1bn+1'
Z2 = an+1bn+1 + an+1'bn+1' = an+1 XNOR bn+1
Z3 = an+1'bn+1
Initial
X=Y>0
X>Y
X<Y
X=Y<0
S-1
S0
S1
S2
S3
xi yi =
00
S0
S0
S1
S2
S3
xi yi =
01
S1
S2
S1
S2
S2
Si+1
xi yi =
11
S3
S0
S1
S2
S3
xi yi =
10
S2
S1
S1
S2
S1
If the states are encoded as S-1 = abc = - - 0, S0 = 001, S1
= 011, S2 = 101 and S3 = 111, then Z1 = (ab')c, Z2 = (ab
+ a'b')c, Z3 = (a'b)c. States S0, S1, S2 and S3 correspond
to states 00, 01, 10 and 11, respectively, of the iterative
circuit.
202
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Unit 16 Solutions
16.21 (a) The output becomes 1 whenever an even #0's or an
even #1's (greater than 0) occurs.
Present
State
1
1
S0
S0
S1
S2
S3
S1
1
0
0
0
1
0
0
0
1
1
S2
S3
1
B
0
The state meanings are given in the following table:
Name
S0
S1
S2
S3
DA
AB
AB
00
01
11
10
0
1
0
S0
S3
1
S1
S2
A + B+
X =0 1
11
01
10
00
00
10
01
11
AB
00
01
11
10
even #0's and even #1's received
even #0's and odd #1's received
odd #0's and even #1's received
odd #0's and odd #1's received
DB
0
1
00
1
0
01
1
11
10
AB
Z
X
0
1
00
1
1
0
01
0
0
1
11
0
1
10
DA = X'A' + XA
16.21 (b)
A
Meaning
X
JA KA
X =0 1
1X 0X
1X 0X
X1 X0
X1 X0
X
0
1
00
0
0
0
01
0
1
0
0
11
1
0
1
1
10
1
1
DB = B'
AB
00
01
11
10
1
S1
S0
S3
S2
Output
X=0 X=1
0
0
0
1
1
0
1
1
Guidelines: I: -II: (1, 2)2x, (0, 3)2x
An assignment is
1
0
Next State
X =0
S2
S3
S0
S1
JB KB
X =0 1
1X 1X
X1 X1
X1 X1
1X 1X
AB
Z = X'A + XA'B + AB'
JA
AB
X
KA
0
1
00
1
0
01
1
11
10
AB
X
0
1
00
X
X
0
01
X
X
X
X
11
1
0
X
X
10
1
0
JA = X'
203
Z
X=0 X=1
0
0
0
1
1
0
1
1
KA = X'
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 16 Solutions
16.21 (b)
(cont.)
JB
X
AB
16.21 (c) The state meanings are given in the following table:
KB
0
1
00
1
1
01
X
11
10
X
AB
0
1
00
X
X
X
01
1
1
X
X
11
1
1
1
1
10
X
X
JB = 1
16.21 (c)
(cont.)
S0
S1
0
S5
1
1
0
1
S4
S3
1
1
0
1
Meaning
reset state
even #0's and even #1's received
odd #0's and even #1's received
odd #0's and even #1's received
even #0's and odd #1's received
even #0's and odd #1's received
odd #0's and odd #1's received
Next State
1
S5
S5
S6
S6
Z
0
1
0
1
S4
S6 S1
1
S5
S6 S1
0
S6
S4 S3
0
S0
S1
S2
S3
1
0
0
1
Present
State
1
0
0
S0
S1
S2
S3
S4
S5
S6
KB = 1
0
S2
Name
X =0
S2
S2
S1
S1
0
0
1
S6
S0
S1
ABC
000
001
S6
-S5
S4
S3
S2
011
010
100
101
111
110
0
Guidelines: I: (0, 1)2x, (2, 3)2x, (4, 5)2x
II: (2, 5)2x, (1, 6)4x, (3, 4)
An assignment is
BC
A
0
1
00
S0
S5
01
S1
S4
11
S6
S3
10
X
S2
204
A+B+C+
X=0 1
110 100
110 100
101
--011
011
001
001
111
--001
001
011
011
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Z
0
1
0
0
1
1
0
Unit 16 Solutions
16.21 (c)
(cont.)
TA
TB
XA
BC
00
01
11
10
00
1
1
1
1
01
1
1
1
11
1
1
10
X
1
XA
BC
TC
XA
BC
Z
AB
0
0
X
JB
1
0
1
1
S0
S1
0
1
A + B+
X =0 1
00
01
00
11
01
11
---
S2
carry
=1
carry
=2
0
0
1
00
X
X
X
01
1
0
X
X
11
0
0
X
X
10
X
X
0
1
X
01
X
1
0
11
X
X
10
X
X
11
X
X
10
KA = X'
16.22 (c) A B X
-1 1
1- - - 1
01 0
Z = X'A'B + XB' + XA
-0 1
Z = (X + B )(X + A')(X'+ A + B')
1- 1
205
JB = X
DADB Z
1 0 0
0 1 0
0 1 0
0 0 1
0 0 1
0 0 1
AB
X
0
00
X
Z
X=0 X=1
0
1
1
0
0
1
KB
1
01
AB
X
0
1
X
AB
X
X
X
TC = A'B'C + AC'
AB
00
01
11
10
X
10
X
For assignment S0 = 00, S1 = 01, S2 = 11:
00
1
1
carry
=0
1
0
1
0
0
0
11
X
16.22 (a)
KA
0
10
TB = X'
X
1
X
1
10
01
0
X
0
1
0
10
1
0
0
X
1
00
0
1
0
1
0
1
11
0
11
1
1
X
0
11
1
JA = XB
0
1
1
10
1
1
1
11
0
0
01
0
0
1
0
01
1
1
0
0
01
01
0
0
0
1
0
00
0
0
00
1
1
0
10
0
1
1
11
AB
0
1
01
X
00
00
00
JA
10
10
Z = B'C + AC
16.22 (b)
11
11
TA = 1
Z
01
01
BC
XA
00
00
KB = X'A'
DA = XB
DB = X + A
Z = X'A'B + XB' + XA
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
1
1
Unit 16 Solutions
16.23 (a)
16.23 (b)
011,
100
Inputs: X2X1X0
Outputs: ID
S0
00
00-,
0-0
011,
100
S1
011,
100
11-,
1-1
11-, 1-1
00-, 0-0
00
S2
00
00-,
0-0
011,
100
11-,
1-1
S3
00
11-,
1-1
00-,
0-0
00-,
0-0
011,
100
S5
00-,
0-0
11-,
1-1
10
S4
00
11-,
1-1
D0 = X2'X1X0 + X2X1'X0'
D1 = (X2'X1' + X2'X0')(Q0 + Q2 + Q4 + Q6)
D3 = (X2'X1' + X2'X0')Q1
D5 = (X2'X1' + X2'X0')(Q3 + Q5)
D2 = (X2X1 + X2X0)(Q0 + Q1 + Q3 + Q5)
D4 = (X2X1 + X2X0)Q2
D6 = (X2X1 + X2X0)(Q4 + Q6)
I = Q5
D = Q6
011,
100
011,
100
S6
01
11-,
1-1
00-,
0-0
16.23 (c) Using the assignment S0 = 000, S1 = 001, S2 = 010, S3 = 011, S4 = 100, S5 = 101,
S6 = 110, S7 = 111:
D0 = (X2'X1X0 + X2X1'X0')(S0 + S1 + S2 + S3 + S4 + S5 + S6)
= (X2'X1X0 + X2X1'X0')(Q0' + Q1' + Q2')*
= X2'X1X0 + X2X1'X0'*
D1 = (X2X1 + X2X0)(S0 + S1 + S3 + S5 + S4 + S6) + (X2'X1' + X2'X0')S1
= (X2X1 + X2X0)(Q1' + Q2'Q0 + Q2Q0') + (X2'X1' + X2'X0')Q2'Q1'Q0
= (X2X1 + X2X0)(Q1' + Q0 + Q2) + (X2'X1' + X2'X0')Q2'Q1'Q0*
D2 = (X2X1 + X2X0)(S2 + S4 + S6) + (X2'X1' + X2'X0')(S3 + S5)
= (X2X1 + X2X0)(Q2Q0' + Q1Q0') + (X2'X1' + X2'X0')(Q2'Q1Q0 + Q2Q1'Q0)
= (X2X1 + X2X0)(Q2Q0' + Q1Q0') + (X2'X1' + X2'X0')(Q1Q0 + Q2Q0)*
I = S5 = Q2Q1'Q0 = Q2Q0*
D = S6 = Q2Q1Q0' = Q2Q1*
* S7 never occurs so 111 is a don’t care input combination.
16.24 (a)
Inputs: X2X1X0
011,100/00
16.24 (b)
Outputs: ID
S0
00-,0-0/00
011,100/00
S1
11-,1-1/00
011, 011,
100
100
/00
/00
11-,1-1/00
00-,0-0/00
S3
00-,0-0/10
S2
00-,0-0/00
11-,1-1/
00
00-,0-0/
00
D0 = X2'X1X0 + X2X1'X0'
D1 = (X2'X1' + X2'X0')(Q0 + Q2 + Q4)
D3 = (X2'X1' + X2'X0')(Q1 + Q3)
D2 = (X2X1 + X2X0)(Q0 + Q1 + Q3)
D4 = (X2X1 + X2X0)(Q2 + Q4)
I = (X2'X1' + X2'X0')Q3
D = (X2X0 + X2 X1)Q4
011,100/00
11-,1-1/00
S4
11-,1-1/01
206
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 16 Solutions
16.24 (c) Using the assignment S0 = 000, S1 = 001, S2 = 010, S3 = 011, S4 = 100:
D2 = X2X0Q1Q0' + X2X1Q1Q0' + X2X0Q2 + X2X1Q2 or
= X2X0Q2'Q1' + X2X1Q2'Q1' + X2X0Q0 + X1X0'Q0 + X2'X1'Q0
D1 = X2X0Q2'Q1' + X2X1Q2'Q1' + X2X1Q0 + X1'X0Q0 + X2'X0'Q0
D0 = X2'X1' + X2'X0'
I = X2'X1'Q1Q0 + X2'X0'Q1Q0
D = X2X0Q2 + X2 X1Q2
16.25 (a)
Inputs: XY
S0
000
00,
11
01,
10
01, 10
S1
001
16.25 (b) D0 = 0
D1 = (X'Y' + XY)(Q0 + Q4 + Q5 + Q6)
D2 = (X'Y' + XY)Q1
D3 = (X'Y' + XY)(Q2 + Q3)
D6 = (X'Y + XY')(Q0 + Q1 + Q2 + Q3)
D5 = (X'Y + XY')Q6
D4 = (X'Y + XY')(Q4 + Q5)
Z0 = Q1 + Q3 + Q5
Z1 = Q2 + Q3 + Q6
Z2 = Q4 + Q5 + Q6
Outputs: Z2Z1Z0
S6
110
00, 11
00,
11
01,
10
01,
10
S2
010
00,
11
00,
11
00,
11
01,
10
S3
011
S5
101
01,
10
S4
100
01,
10
16.25 (c) Using the assignment S0 = 000, S1 = 001, S2 = 010, S3 = 011, S4 = 100, S5 = 101, S6 = 110:
D0 = (X'Y' + XY)(S0 + S4 + S5 + S6 + S2 + S3) + (X'Y + XY')S6
= (X'Y' + XY)(Q0' + Q2'Q1 + Q2Q1') + (X'Y + XY')Q2Q1Q0'
= (X'Y' + XY)(Q0' + Q1 + Q2) + (X'Y + XY')Q2Q1*
D1 = (X'Y' + XY)(S1 + S2 + S3) + (X'Y + XY')(S0 + S1 + S2 + S3)
= (X'Y' + XY)( Q2'Q1 + Q2'Q0) + (X'Y + XY')Q2'
D2 = (X'Y + XY')(S0 + S1 + S2 + S3 + S4 + S5 + S6)
= (X'Y + XY')(Q0' + Q1' + Q2')* = (X'Y + XY')*
Z0 = S1 + S3 + S5 = Q1'Q0 + Q2'Q0 = Q0*
Z1 = S2 + S3 + S6 = Q2'Q1 + Q1Q0' = Q1*
Z2 = S4 + S5 + S6 = Q2Q1' + Q2Q0' = Q2*
* S7 never occurs so 111 is a don’t care input combination.
16.26 (a)
Inputs: XY
01,10/110
00,11/001
S1
01,10/110
00,11/011
S6
00,11/001
00,11/010
S2
16.26 (b) D0 = 0
D1 = (X'Y' + XY)(Q0 + Q5 + Q6)
D2 = (X'Y' + XY)(Q1 + Q2)
D6 = (X'Y + XY')(Q0 + Q1 + Q2)
D5 = (X'Y + XY')(Q6 + Q5)
Z0 = (X'Y' + XY)(Q0 + Q2 + Q5) +Q6
Z1 = (X'Y + XY')Q0 + Q1 + Q2
Z2 = (X'Y + XY')
Outputs: Z2Z1Z0
S0
00,11/001
01,
10/110
01,10/101
S5
01,10/100
207
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 16 Solutions
16.26 (c) Using the assignment S0 = 000, S1 = 001, S2 = 101,
S6 = 111, S5 = 011
D2 = Q1'Q0 + XY'Q1' + X'YQ1' or
= Q1'Q0 + XY'Q0' + X'YQ1' or
= Q1'Q0 + XY'Q1' + X'YQ0' or
= Q1'Q0 + XY'Q0' + X'YQ0'
D1 = X'Y + XY'
D0 = 1
Z2 = X'Y + X Y'
Z1 = Q1'Q0 + XY'Q1' + X'YQ1' or
= Q1'Q0 + XY'Q0' + X'YQ1' or
= Q1'Q0 + XY'Q1' + X'YQ0' or
= Q1'Q0 + XY'Q0' + X'YQ0'
Z0 = X'Y'Q0' + XYQ0' + X'Y'Q2 + XYQ2
+ Q2Q1 + X'Y'Q1 + XYQ1
16.27 (a)
Inputs: XY
S0
Outputs: Z2Z1Z0
000
00,
11
01,
10
01, 10
S1
001
S7
111
00, 11
00,
11
S2
010
00,
11
S3
01,
10
01,
10
01,
10
00,
11
00,
11
011
00,
11
S6
110
01,
10
S5
101
01,
10
S4
100
01,
10
16.27 (c) Using the assignment S0 = 000, S1 = 001, S2 = 010,
S3 = 011, S4 = 100, S5 = 101, S6 = 110, S7 = 111:
D0 = (X'Y' + XY)(S0 + S4 + S5 + S6 + S7 + S2 +
S3) + (X'Y + XY')(S0 + S1 + S2 + S3 + S6)
= (X'Y' + XY)(Q0' + Q1 + Q2) +
(X'Y + XY')(Q2' + Q1Q0')
D1 = (X'Y' + XY)(S1 + S2 + S3) +
(X'Y + XY')(S0 + S1 + S2 + S3 + S7)
= (X'Y' + XY)(Q2'Q1 + Q2'Q0) +
(X'Y + XY')(Q2' + Q1Q0)
D2 = (X'Y + XY')
16.27 (b) D0 = 0
D1 = (X'Y' + XY)(Q0 + Q4 + Q5 + Q6 + Q7)
D2 = (X'Y' + XY)Q1
D3 = (X'Y' + XY)(Q2 + Q3)
D7 = (X'Y + XY')(Q0 + Q1 + Q2 + Q3)
D6 = (X'Y + XY')Q7
D5 = (X'Y + XY')Q6
D4 = (X'Y + XY')(Q4 + Q5)
Z0 = Q1 + Q3 + Q5 + Q7
Z1 = Q2 + Q3 + Q6 + Q7
Z2 = Q4 + Q5 + Q6 + Q7
16.28 (a)
Inputs: XY
Outputs: Z2Z1Z0
S0
01,10/111
00,11/001
S1
01,10/111
S7
00,11/001
00,11/010
S2
Z0 = S1 + S3 + S5 + S7 = Q0
Z1 = S2 + S3 + S6 + S7 = Q1
Z2 = S4 + S5 + S6 + S7 = Q2
00,11/001
01,
10/111
16.28 (b) D0 = 0
D1 = (X'Y' + XY)(Q0 + Q5 + Q6 + Q7)
D2 = (X'Y' + XY)(Q1 + Q2)
D7 = (X'Y + XY')(Q0 + Q1 + Q2)
D6 = (X'Y + XY')Q7
D5 = (X'Y + XY')(Q5 + Q6)
Z0 = Q0 + (X'Y' + XY)(Q2 + Q5)
+ (X'Y + XY')(Q1 + Q6)
Z1 = Q1 + Q2 + (X'Y + XY')(Q0 + Q7)
Z2 = (X'Y + XY')
01,10/110
S6
01,10/101
00,11/011
00,11/001
S5
01,10/100
208
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 16 Solutions
16.28 (c) Using the assignment S0 = 000, S1 = 001, S2 = 100, 16.29 (a)
S5 = 011, S6 = 010, S7 = 111:
D2 = X'YQ1' + XY'Q1' + Q1'Q0
D1 = X'Y + X Y'
D0 = Q1' + X'Y' + XY + Q2'
Z2 = X'Y + XY'
Z1 = X'YQ1' + XY'Q1' + Q1'Q0 + X'YQ2 + XY'Q2
Z0 = Q0' + X'Y Q1' + XY'Q1' + X'Y'Q1 + XYQ1
+ Q2Q1'
16.29 (b)
FS'2
N1'N2DC
N1
R1DO,
N1'N2 DC'
0,
N1'N2'
0
Call i
FBi
FS2
S0
S1
S2
S3
R2DO
N1N2'DC
S3
FS'1
Meaning
Staying on first floor
Moving from first to second floor
Staying on second floor
Moving from second to first floor
N2
R2DO,
N1N2'DC'
N1'N2' 0,
0
S2
R1DO
Ni
Clock
S1
UP
Di Qi
Ri
Name
UP
S0
FS1
Ni = Qi+ = (Qi + FBi + CALLi )Ri'
= QiRi' + FBiRi' + CALLiRi'
DOWN
DOWN
16.29 (c) With the state assignment S0 = 00, S1 = 01, S2 = 10, S3 = 11, we have:
D1 = FS2Q1'Q2 + FS1'Q1 + Q1Q2';
D2 = FS2'Q1'Q2 + FS1'Q1Q2 + N1'N2DCQ1'Q2' + N1N2'DCQ1Q2'
R1 = FS1Q1Q2 + N1Q1'Q2';
R2 = FS2Q1'Q2 + N2Q1Q2';
UP =FS2'Q1'Q2 + N1'N2DCQ1'Q2'
DOWN = FS1'Q1Q2 + N1N2'DCQ1Q2';
DO = FS2Q1'Q2 + FS1Q1Q2 + N1Q1'Q2' + N2Q1Q2'
16.30 (a)
L'R'H'
H'
L'H'
S3
111000
LH'
S2
011000
LR'H'
S1
001000
LH'
H'
S0
000000
L'H'
L'RH'
S4
000100
R'H'
H
R'H'
-
H
RH'
S5
000110
RH'
S6
000111
H
H
H
H
S7
H
111111
Outputs: LC, LB, LA, RA, RB, RC
209
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 16 Solutions
16.30 (b) First, assign LC = Q1, LB = Q2, LA = Q3, RA = Q4, RB = Q5, RC = Q6. So S0 = 000000, S1 = 001000, S2 = 011000, etc.
This state machine has too many state variables to use Karnaugh maps. Instead, we will write down equations for
each flip-flop by inspection.
First consider Q1. Q1 = 1 in states S3 or S7 only.
• S7 is reached whenever H = 1 and we are not already in S7: H(Q1Q2Q3Q4Q5Q6)'. But S7 is the only state in which
both Q3 = 1 and Q4 = 1, so assuming we are always in a valid state, we can use H(Q3Q4)' = HQ3' + HQ4'. Note:
Any combination of one left light and one right light will also work, i.e. HQ1' + HQ5'.
•
S3 is reached whenever we are in S2 and L = 1 while H = 0: LH'Q1'Q2Q3Q4'Q5'Q6'. But Q3 = 1 whenever Q2 = 1,
and Q4 = Q5 = Q6 = 0 whenever Q1 = 0. So we can use LH'Q1'Q2.
•
So D1 = LH'Q1'Q2 + HQ3' + HQ4' = LQ1'Q2 + HQ3' + HQ4' (using X + X'Y = X + Y)
Similarly Q2 = 1 in states S3, S2, and S7 only.
•
S3 and S2 are reached whenever we are in S2 or S1 and L = 1 while H = 0.
LH'Q1'Q2Q3Q4'Q5'Q6' + LH'Q1'Q2'Q3Q4'Q5'Q6' = LH'Q1'Q3Q4'Q5'Q6'
But again, Q4 = Q5 = Q6 = 0 whenever Q1 = 0, so D2 = LQ1'Q3 + HQ3' + HQ4'
We can also get by inspection: D3 = LQ1'Q4' + HQ3' + HQ4'; D4 = RQ3'Q6' + HQ3' + HQ4';
D5 = RQ4Q6' + HQ3' + HQ4'; D6 = RQ5Q6' + HQ3' + HQ4'
16.30 (c) State LRH = 000
S0
S0
S1
S0
S2
S0
S3
S0
S4
S0
S5
S0
S6
S0
S7
S0
001
S7
S7
S7
S7
S7
S7
S7
S0
010
S4
S0
S0
S0
S5
S6
S0
S0
011
S7
S7
S7
S7
S7
S7
S7
S0
100
S1
S2
S3
S0
S0
S0
S0
S0
101 110 111
S7 S7 S7 S7 S7 S7 S7 S0 -
LC
0
0
0
1
0
0
0
1
LB
0
0
1
1
0
0
0
1
LA RA
0 0
1 0
1 0
1 0
0 1
0 1
0 1
1 1
RB
0
0
0
0
0
1
1
1
RC
0
0
0
0
0
0
1
1
I. (S0, S1, S2, S3, S4, S5, S6) for S7 in LRH = 001, 011, 101
(S1, S2, S3, S6, S7) for S0 in LRH = 010
(S3, S4, S5, S6, S7) for S0 in LRH = 100
II. Every state matches S0 and S7. But S0 and S7 match the best, so (S0, S7)×(many times)
III. (S1, S2, S3, S7) (S4, S5, S6, S7) etc.
From LogicAid:
D1 = HQ2 + RQ1Q2Q3' + HQ3 + LQ1'Q2'Q3 + HQ1' + RQ1'Q2'Q3'
D2 = RH'Q1'Q2'Q3' + RH'Q1Q2 + LH'Q1'Q2'Q3'
D3 = LH'Q1'Q2Q3' + LH'Q1'Q2'Q3 + RH'Q1Q2
LC = Q1Q2';
LB = Q1Q2' + Q2'Q3 ;
LA = Q1Q2' + Q2'Q3 + Q1'Q2Q3'
RC = Q1Q2'Q3' + Q1'Q2Q3; RB = Q1Q2'Q3' + Q2Q3; RA = Q1Q3' + Q2Q3
Other minimum solutions can be found for D2 and D3 with this assignment.
210
Q2 Q3
Q1
0
1
00
S0
S7
01
S2
S3
11
S6
S5
10
S1
S4
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 16 Solutions
16.31
RE' FF' PL'
IDLE
0
FF
ST
REW
R
ST' FF' PL'
PL
RE
ST, FF
ST, RE
ST, FF, RE
PLAY
P
PL
PL RE
PL
PL FF
SBACK
R
ST
ST' RE' PL'
ST' RE' FF'
ST' M'
FFWD
F
ST' M'
ST' M
SFWD
F
ST' M
Note: This state graph assumes that only one of the buttons ST, PL, RE, and FF can be pressed at any given time.
The graph is incompletely specified and must be augmented before using LogicAid. For example, the arc from REW
to PLAY should be labeled PL ST' FF'.
P
ST
RE
FF
PL
M
Q1
+
D
Q2+
D
Q2
CK
Q3+
D
F
Q1
CK
PLA
R
Q3
D1 = ST' FF PS Q1' Q2' Q3 + ST' RE PL Q1' Q2' Q3
+ ST' M Q1
D2 = ST' FF Q1' Q2' Q3' + ST' RE Q1' Q2' Q3'
+ ST' RE' PL' Q2 Q3 + ST' FF' PL' Q2 Q3'
D3 = ST' RE' FF Q1' Q2' Q3' + ST' RE' FF' Q3
+ ST' FF' PL Q2 Q3' + ST' RE' Q2 Q3
+ ST' M' Q1 + ST' Q1 Q3 + ST' RE' PL Q1' Q2'
P = Q1'Q2'Q3;
R = Q2Q3' + Q1Q3';
F = Q2Q3 + Q1Q3
CK
Clock
211
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 16 Solutions
16.32 (a)
1
1
0000
0000
0000
0000
0000
0000
0000
0001
0011
0
1
1
0
1
1
1
0000
0000
0000
0000
0001
0010
0100
0000
0001
0010
0101
0000
0001
0011
0110
0011
0111
0100
1001
1001
1001
16.32 (c) The tables of combinations for the BCD multiply
by 2 circuit are
x3x2x1x0
0000
0001
y3y2y1y0
0000
0001
x3x2x1x0
1000
1001
y3y2y1y0
1011
1100
0010
0011
0100
0101
0110
0111
0010
0011
0100
1000
1001
1010
1010
1011
1100
1101
1110
1111
-------------------
16.32 (b) 99910 = 3E716 = 11 1110 01112
16.32 (c)
cont.
y3
x1 x0
x3 x2
00
y2
01
11
10
x3 x2
x1 x0
y1
00
01
11
10
x1 x0
x3 x2
00
01
11
10
00
0
0
X
1
00
0
1
X
0
00
0
0
X
1
01
0
1
X
1
01
0
0
X
1
01
0
0
X
0
11
0
1
X
X
11
0
0
X
X
11
1
1
X
X
10
0
1
X
X
10
0
0
X
X
10
1
0
X
X
y3 = x3 + x2x1 + x2x0
y0
x3 x2
x1 x0
y2 = x2x1'x0' + x3x0
00
01
11
10
00
0
0
X
1
01
1
0
X
0
11
1
0
X
X
10
0
1
X
X
y1 = x3x0' + x1x0 + x2'x1
y0 = x3x0' + x2x1x0' + x3'x2'x0
16.33 (a)
0
S2
0
0
S0
0
1
1
S4
0
1
S1
SS66
0
1
0
0
0
11
1
S3
0
212
0, 1
0
S5
1
0
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 16 Solutions
16.33 (b)
Present
State
Next State
1
S1
S3
S4
S3
Z
0
0
0
0
S4
S2 S6
0
S5
S0 S6
0
S6
S6 S6
1
X =0
S0
S2
S0
S5
S0
S1
S2
S3
ai+1
bi ci
xi ai
00
bi+1
01
11
10
Z
bn cn
S2
S3
S5
S4
S6
--
010
011
100
101
110
111
000
100
000
010
110
---
ci+1
01
11
10
bi ci
Z
0
0
101
011
110
110
110
---
xi ai
00
0
0
0
0
1
-
01
11
10
00
0
0
1
0
00
0
0
1
0
00
0
0
0
1
01
0
0
1
0
01
1
1
1
1
01
0
0
0
1
11
1
X
X
0
11
0
X
X
1
11
0
X
X
1
10
0
1
1
1
10
0
1
1
0
10
0
0
0
1
ai+1 = xi'bici + aibi + xibici' + xiai
16.33 (c)
bi ci
xi ai
00
S0
S1
ABC
000
001
A+B+C+
X=0 1
000 001
010 011
bi+1 = bi'ci + aibi + xici + xiai
ci+1 = xiai'
16.34 (a)
an
0
1
00
0
0
01
0
0
11
0
X
10
0
1
0
0
S0
0
1
S2
1
0
S3
0
0,1
1
S1
1
1
Z = anbn
213
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 16 Solutions
16.34 (b)
Next State
State xi = 0 xi = 1
S0
S0
S1
S1
S2
S3
S2
S2
S1
S3
S3
S3
aibi
00
11
10
01
ai+1bi+1
xi = 0 xi = 1
00
11
10
01
10
11
01
01
bi
Z
0
1
1
0
ai
0
1
0
S0
S2
1
S3
S1
xi
ai bi
Z
0
1
1
0
xi
0
1
an+1
0
bn+1
1
00
0
1
0
0
1
0
01
1
1
1
0
1
1
0
11
0
1
1
1
10
0
1
0
1
00
0
1
01
0
11
10
ai bi
Z = an+1
bi+1 = (xi + bi ) (xi + ai')
ai+1 = (xi + ai ) (xi'+ bi')
16.34 (c) a1 = b1 = 0
a2 = (x1 + 0)(x1' + 1) = x1
b2 = (x1 + 1)(x1 + 0) = x1
16.34 (d)
xi
ai
Typical Cell
a i+1
Q
D
Z
CK
bi
b i+1
D
Q
CK
Clk
214
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 17 Solutions
17.1
Unit 17 Problem Solutions
17.2
See FLD p. 770 for solution.
17.3 (a),
(b)
Q(7)Q(6)Q(5)Q(4)
CO
CLK
CO
Q(3)Q(2)Q(1)Q(0)
CLRn
LOAD
ENT
ENP
UP
Up/Down
CO1
CO
Up/Down
CLK
D(7)D(6)D(5)D(4)
CLRn
LOAD
ENT
ENP
UP
D(3)D(2)D(1)D(0)
See FLD p. 771-772 for solutions.
17.4
See FLD p. 770 for solution.
17.5
See FLD p. 772 for solution.
See FLD p. 772-773 for solution.
17.6 (a), See FLD p. 773 for solutions.
(b)
X1
X2
Q1+
4
Q1
2 X4
ROM
Z1
Z2
D Q
CLK
Q2
Q2+
D Q
CLK
17.7 (a) See FLD p. 774 for solution.
CE
LdA
LdB
17.7 (b)
Q(1)
Q(2)
Q
Q
D
CLK
CE
D
CLK
CE
LdA
LdB
Q(1)
Q(2)
Q
Q
CE
D
D
CLK
CLK
1
0
A(1)
B(1)
LdA
1
0
A(2)
B(2)
LdA A(1) LdA' LdB B(1) LdA A(2) LdA' LdB B(2)
17.8
See FLD p. 774 for solution.
215
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LdA
Unit 17 Solutions
17.9
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity srff is
port (clk, s, r : in std_logic;
q, qn : out std_logic);
end srff;
architecture Behavioral of srff is
signal qint : std_logic:='0';
begin
q <= qint;
qn <= not qint;
process(clk)
begin
if clk'event and clk='1' then
if (not s and r)='1' then qint <= '0';
elsif (s and not r)='1' then qint<='1';
elsif (s and r)='1' then qint<='X'; end if;
end if;
end process;
end Behavioral;
17.11
A rising edge triggered D-CE flip flop with
asynchronous clear and preset.
17.12
8
En
8
8-bit Register
Ld
Clk
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- D-G Latch
entity dglatch is
port (d, g : in bit;
q : out bit);
end dglatch;
architecture Behavioral of dglatch is
begin
process(g, d)
begin
if g='1' then q <= d; end if;
end process;
end Behavioral;
-- D flip flop using D-G latches
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff is
port (d, clk : in bit;
q : out bit);
end dff;
architecture Behavioral of dff is
component dglatch is
port (d, g: in bit;
q : out bit);
end component;
signal p, clkn : bit;
begin
clkn <= not clk;
dg1 : dglatch port map(d, clkn, p);
dg2 : dglatch port map(p, clk, q);
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity myreg is
port(en, ld, clk : in std_logic;
d : in std_logic_vector(7 downto 0);
q : out std_logic_vector(7 downto 0));
end myreg;
architecture Behavioral of myreg is
signal qint : std_logic_vector(7 downto 0):="00000000";
begin
q <= qint when en ='1' else "ZZZZZZZZ";
process(clk)
begin
if clk' event and clk='1' then
if ld='1' then qint <= d; end if;
end if;
end process;
end Behavioral;
Q
Qint
17.10
8
D
216
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 17 Solutions
17.13
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity encoder is
port (y0, y1, y2, y3 : in bit;
a, b, c : out bit);
end encoder;
architecture Behavioral of encoder is
begin
process(y0, y1, y2, y3)
begin
if y3='1' then a <= '1'; b <= '1'; c <= '1';
-- y3 has highest priority
elsif y2='1' then
a <= '1'; b <= '0'; c <= '1';
elsif y1='1' then
a <= '0'; b <= '1'; c <= '1';
elsif y0='1' then
a <= '0'; b <= '0'; c <= '1';
else a <= '0'; b <= '0'; c <= '0'; end if;
end process;
end Behavioral;
17.15
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity super is
port (a: in std_logic_vector(2 downto 0);
d : in std_logic_vector(5 downto 0);
rsi, lsi, clk : in std_logic;
q : out std_logic_vector(5 downto 0));
end super;
architecture Behavioral of super is
signal qint: std_logic_vector(5 downto 0);
begin
q <= qint;
process(clk)
begin
if clk' event and clk='1' then
case a is
when "111"=> qint <= d;
when "110"=> qint <= qint-1;
when "101"=> qint <= qint+1;
when "100"=> qint <= "111111";
when "011"=> qint <= "000000";
when "010"=> qint <= rsi&qint(5 downto 1);
when "001"=> qint <= qint(4 downto 0)&lsi;
when others=> NULL;
end case;
end if;
end process;
end Behavioral;
217
17.14
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comparator is
port (a, b : in std_logic_vector(3 downto 0);
agb, alb, aeb : out std_logic);
end comparator;
architecture Behavioral of comparator is
begin
process(a, b)
begin
if a > b then agb <= '1'; alb <= '0'; aeb <= '0';
elsif a < b then agb <= '0'; alb <= '1'; aeb <= '0';
else agb <= '0'; alb <= '0'; aeb <= '1'; end if;
end process;
end Behavioral;
17.16
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bcd_seven is
port (bcd : in bit_vector(3 downto 0);
seven : out bit_vector(7 downto 1));
end bcd_seven;
architecture Behavioral of bcd_seven is
begin
process(bcd)
begin
case bcd is
when "0000"=> seven <= "0111111";
when "0001"=> seven <= "0000110";
when "0010"=> seven <= "1011011";
when "0011"=> seven <= "1001111";
when "0100"=> seven <= "1100110";
when "0101"=> seven <= "1101101";
when "0110"=> seven <= "1111101";
when "0111"=> seven <= "0000111";
when "1000"=> seven <= "1111111";
when "1001"=> seven <= "1101111";
end case;
end process;
end Behavioral;
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 17 Solutions
17.17 (a)
17.17 (b)
17.17 (d)
17.17 (c)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Mealy_XOR is
Port (CLK, clr, x : in std_logic;
z : out std_logic);
end Mealy_XOR;
entity Moore_XOR is
Port (CLK, clr, X : in std_logic;
Z : out std_logic);
end Moore_XOR;
architecture df1 of Mealy_XOR is
signal q, d: std_logic;
begin
z <= x XOR q after 10ns;
d <= x ;
process (CLK, clr)
begin
if clr = '0' then
q <= '0' after 10ns;
elsif CLK'event and CLK = '1'
then q <= d after 10ns;
end if;
end process;
end df1;
architecture df1 of Moore_XOR is
signal Q1, Q2, D1, D2: std_logic;
begin
Z <= Q1 XOR Q2 after 10ns;
D1 <= X;
D2 <= Q1;
process (CLK, clr)
begin
if clr = '0' then
Q1 <= '0' after 10ns;
Q2 <= '0' after 10ns;
elsif CLK'event and CLK = '1'
then Q1 <= D1 after 10ns;
Q2 <= D2 after 10ns;
end if;
end process;
end df1;
Signal Current 0ns
CLK '0'
clr
'1'
x
'1'
U
z
'0'
U
q
'1'
d
'1'
40ns
80ns
120ns
160ns
200ns
240ns
280ns
320ns
360ns
Signal Current 0ns
CLK
'0'
40ns
80ns
120ns
160ns
200ns
240ns
280ns
320ns
360ns
clr
X
Z
'1'
'1'
'0'
Q1
Q2
'1'
'1'
D1
D2
'1'
'1'
U
U
U
U
218
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 17 Solutions
17.17 (e) The Mealy model output is valid before the positive clock edge while the corresponding Moore model output
(cont.) becomes valid after the clock edge. Also, the Mealy output is not valid after the clock edge until the input has
changed to its next value. The Meal model does not have an output corresponding to the Moore output prior to the
first clock edge.
Signal Current 0ns
CLK
'0'
X
Z
'1'
'0'
U
z
'0'
U
40ns
80ns
120ns
17.18 (a) )Z0 = Q0 Q1'Q3' or Q1'Q2'Q3'
Z1 = Q0 Q1
Z2 = Q0'Q1 Q2' or Q0'Q2'Q3'
Z3 = Q1 Q2
Z4 = Q1'Q2 Q3' or Q0'Q1'Q3'
Z5 = Q2 Q3
Z6 = Q0'Q2'Q3 or Q0'Q1'Q2'
Z7 = Q0 Q3
17.18 (b) D0
D1
D2
D3
=
=
=
=
160ns
200ns
240ns
280ns
320ns
360ns
17.18 (d) library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mod8_counter is
port (CLK, ClrN : in std_logic;
Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7 : out std_logic);
end mod8_counter;
Q1'Q2'
Q2'Q3'
Q0'Q3'
Q0'Q1'
17.18 (c) CE0 = Q2', D0 = Q1' or CE0 = Q1', D0 = Q2'
CE1 = Q3', D1 = Q2' or CE1 = Q2', D1 = Q3'
CE2 = Q3', D2 = Q0' or CE2 = Q0', D2 = Q3'
CE3 = Q1', D3 = Q0' or CE3 = Q0', D3 = Q1'
'
17.18 (d) stt_trnstn: process(CLK,ClrN)
begin
(cont.)
if ClrN = '0' then
Q <= "1000";
elsif Rising_Edge (CLK) then
Q <= Q_plus;
end if;
end process stt_trnstn;
end bhvr;
219
architecture bhvr of mod8_counter is
signal Q, Q_plus: std_logic_vector(0 to 3);
begin
cmb_lgc: process(Q)
begin
Z0 <= '0'; Z1 <= '0'; Z2 <= '0'; Z3 <= '0';
Z4 <= '0'; Z5 <= '0'; Z6 <= '0'; Z7 <= '0';
case Q is
when "1000" =>
Z0 <= '1';
Q_plus <= "1100";
when "1100" =>
Z1 <= '1';
Q_plus <= "0100";
when "0100" =>
Z2 <= '1';
Q_plus <= "0110";
when "0110" =>
Z3 <= '1';
Q_plus <= "0010";
when "0010" =>
Z4 <= '1';
Q_plus <= "0011";
when "0011" =>
Z5 <= '1';
Q_plus <= "0001";
when "0001" =>
Z6 <= '1';
Q_plus <= "1001";
when "1001" =>
Z7 <= '1';
Q_plus <= "1000";
when others =>
Q_plus <= "XXXX";
end case;
end process cmb_lgc;
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 17 Solutions
17.18 (e) library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mod8_counter is
port (CLK, ClrN : in std_logic;
Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7 : out std_logic);
end mod8_counter;
17.18 (f) library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mod8_counter is
port (CLK, ClrN : in std_logic;
Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7 : out std_logic);
end mod8_counter;
architecture df1 of mod8_counter is
signal Q, D : std_logic_vector(0 to 3);
begin
cmb_lgc: process(Q)
begin
Z0 <= Q(0) and not Q(1) and not Q(3);
Z1 <= Q(0) and Q(1);
Z2 <= not Q(0) and Q(1) and not Q(2);
Z3 <= Q(1) and Q(2);
Z4 <= not Q(1) and Q(2) and not Q(3);
Z5 <= Q(2) and Q(3);
Z6 <= not Q(0) and not Q(2) and Q(3);
Z7 <= Q(0) and Q(3);
D(0) <= not Q(1) and not Q(2);
D(1) <= not Q(2) and not Q(3);
D(2) <= not Q(0) and not Q(3);
D(3) <= not Q(0) and not Q(1);
end process cmb_lgc;
architecture df2 of mod8_counter is
signal Q, CE, D : std_logic_vector(0 to 3);
begin
cmb_lgc: process(Q)
begin
Z0 <= Q(0) and not Q(1) and not Q(3);
Z1 <= Q(0) and Q(1);
Z2 <= not Q(0) and Q(1) and not Q(2);
Z3 <= Q(1) and Q(2);
Z4 <= not Q(1) and Q(2) and not Q(3);
Z5 <= Q(2) and Q(3);
Z6 <= not Q(0) and not Q(2) and Q(3);
Z7 <= Q(0) and Q(3);
CE(0) <= not Q(2); D(0) <= not Q(1);
CE(1) <= not Q(3); D(1) <= not Q(2);
CE(2) <= not Q(0); D(2) <= not Q(3);
CE(3) <= not Q(1); D(3) <= not Q(0);
end process cmb_lgc;
stt_trnstn: process(CLK,ClrN)
begin
if ClrN = '0' then
Q <= "1000";
elsif Rising_Edge (CLK) then
Q <= D;
end if;
end process stt_trnstn;
stt_trnstn: process(CLK,ClrN)
begin
if ClrN = '0' then
Q <= "1000";
elsif Rising_Edge (CLK) then
if CE(0) = '1' then Q(0) <= D(0); end if;
if CE(1) = '1' then Q(1) <= D(1); end if;
if CE(2) = '1' then Q(2) <= D(2); end if;
if CE(3) = '1' then Q(3) <= D(3); end if;
end if;
end process stt_trnstn;
end df1;
end df2;
17.18 (e)
wave
form
Signal Current 0ns
CLK
'1'
ClrN
Z0
Z1
Z2
'1'
'0'
'1'
'0'
Z3
Z4
'0'
'0'
Z5
Z6
Z7
'0'
'0'
'0'
Q
D
1100 8
0100 C
40ns
80ns
120ns
160ns
200ns
240ns
280ns
320ns
360ns
C
4
6
2
3
1
9
8
C
4
6
2
3
1
9
8
C
4
220
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 17 Solutions
17.18 (f)
wave
form
Signal Current 0ns
CLK '1'
ClrN '1'
Z0
Z1
Z2
'0'
'1'
'0'
Z3
Z4
'0'
'0'
Z5
Z6
Z7
'0'
'0'
'0'
Q
CE
D
1100
1100
0110
40ns
80ns
120ns
160ns
200ns
240ns
280ns
320ns
360n s
8
C
4
6
2
3
1
9
8
C
D
C
E
6
7
3
B
9
D
C
E
6
7
3
B
9
D
C
E
6
17.19 (a) )Z0 = Q0 Q1'Q3' or Q1'Q2'Q3'
Z1 = Q0 Q2'
Z2 = Q0 Q1 Q2 or Q0Q2Q3'
Z3 = Q0' Q1
Z4 = Q1'Q2 Q3' or Q0'Q1'Q3'
Z5 = Q0' Q3
Z6 = Q0 Q2 Q3 or Q0 Q1'Q2'
Z7 = Q2' Q3
17.19 (b) D0
D1
D2
D3
=
=
=
=
17.19 (d) library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mod8_counter2 is
port (CLK, ClrN : in std_logic;
Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7 : out std_logic);
end mod8_counter2;
Q3 + Q2'
Q0 Q3'
Q0' + Q1
Q1'Q2
17.19 (c) CE0 = Q2', D0 = Q1' or CE0 = Q1', D0 = Q2'
CE1 = Q3', D1 = Q2' or CE1 = Q2', D1 = Q3'
CE2 = Q3', D2 = Q0' or CE2 = Q0', D2 = Q3'
CE3 = Q1', D3 = Q0' or CE3 = Q0', D3 = Q1'
17.19 (d)
(cont.)
when others =>
Q_plus <= "XXXX";
end case;
end process cmb_lgc;
stt_trnstn: process(CLK,ClrN)
begin
if ClrN = '0' then
Q <= "1000";
elsif Rising_Edge (CLK) then
Q <= Q_plus;
end if;
end process stt_trnstn;
end bhvr;
221
architecture bhvr of mod8_counter2 is
signal Q, Q_plus: std_logic_vector(0 to 3);
begin
cmb_lgc: process(Q)
begin
Z0 <= '0'; Z1 <= '0'; Z2 <= '0'; Z3 <= '0';
Z4 <= '0'; Z5 <= '0'; Z6 <= '0'; Z7 <= '0';
case Q is
when "1000" =>
Z0 <= '1';
Q_plus <= "1100";
when "1100" =>
Z1 <= '1';
Q_plus <= "1110";
when "1110" =>
Z2 <= '1';
Q_plus <= "0110";
when "0110" =>
Z3 <= '1';
Q_plus <= "0010";
when "0010" =>
Z4 <= '1';
Q_plus <= "0011";
when "0011" =>
Z5 <= '1';
Q_plus <= "1011";
when "1011" =>
Z6 <= '1';
Q_plus <= "1001";
when "1001" =>
Z7 <= '1';
Q_plus <= "1000";
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 17 Solutions
17.19 (e) library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mod8_counter2 is
port (CLK, ClrN : in std_logic;
Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7 : out std_logic);
end mod8_counter2;
17.19 (f) library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mod8_counter2 is
port (CLK, ClrN : in std_logic;
Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7 : out std_logic);
end mod8_counter2;
architecture df1 of mod8_counter2 is
signal Q, D : std_logic_vector(0 to 3);
begin
cmb_lgc: process(Q)
begin
Z0 <= Q(0) and not Q(1) and not Q(3);
Z1 <= Q(1) and not Q(2);
Z2 <= Q(0) and Q(1) and Q(2);
Z3 <= not Q(0) and Q(1);
Z4 <= not Q(1) and Q(2) and not Q(3);
Z5 <= not Q(0) and Q(3);
Z6 <= Q(0) and Q(2) and Q(3);
Z7 <= not Q(2) and Q(3);
D(0) <= Q(3) or not Q(2);
D(1) <= Q(0) and not Q(3);
D(2) <= not Q(0) or Q(1);
D(3) <= not Q(1) and Q(2);
end process cmb_lgc;
architecture df2 of mod8_counter2 is
signal Q, CE, D : std_logic_vector(0 to 3);
begin
cmb_lgc: process(Q)
begin
Z0 <= Q(0) and not Q(1) and not Q(3);
Z1 <= Q(1) and not Q(2);
Z2 <= Q(0) and Q(1) and Q(2);
Z3 <= not Q(0) and Q(1);
Z4 <= not Q(1) and Q(2) and not Q(3);
Z5 <= not Q(0) and Q(3);
Z6 <= Q(0) and Q(2) and Q(3);
Z7 <= not Q(2) and Q(3);
CE(0) <= Q(2); D(0) <= Q(3);
CE(1) <= not Q(3); D(1) <= Q(0);
CE(2) <= Q(0); D(2) <= Q(1);
CE(3) <= not Q(1); D(3) <= Q(2);
end process cmb_lgc;
stt_trnstn: process(CLK,ClrN)
begin
if ClrN = '0' then
Q <= "1000";
elsif Rising_Edge (CLK) then
Q <= D;
end if;
end process stt_trnstn;
stt_trnstn: process(CLK,ClrN)
begin
if ClrN = '0' then
Q <= "1000";
elsif Rising_Edge (CLK) then
if CE(0) = '1' then Q(0) <= D(0); end if;
if CE(1) = '1' then Q(1) <= D(1); end if;
if CE(2) = '1' then Q(2) <= D(2); end if;
if CE(3) = '1' then Q(3) <= D(3); end if;
end if;
end process stt_trnstn;
end df1;
end df2;
17.19 (e)
Signal Current 0ns
CLK '1'
ClrN
'1'
Z0 '0'
Z1 '1'
Z2
'0'
Z3
Z4
Z5
Z6
'0'
'0'
'0'
'0'
Z7
Q
'0'
1100 8
1110 C
D
40ns
80ns
C
E
120ns
160ns
200ns
240ns
280ns
320ns
360ns
6
2
2
3
3
B
B
9
9
8
8
C
C
E
E
6
222
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 17 Solutions
17.19 (f)
Signal Current 0ns
CLK '1'
ClrN '1'
Z0
Z1
Z2
'0'
'1'
'0'
Z3
Z4
'0'
'0'
Z5
Z6
Z7
'0'
'0'
'0'
Q
CE
D
1100 8
0110 7
0110 4
40ns
80ns
120ns
160ns
200ns
240ns
280ns
320ns
360ns
C
E
6
2
3
B
9
8
C
6
E
C
D
9
B
3
7
6
6
7
3
1
9
D
C
4
6
17.20 (a) go = gi OR (ei AND a AND b')
17.20(b)
eo = ei AND ((a AND b) OR (a' AND b'))
a
gi
ei
b
Cmp
go
eo
17.20(d)
17.20(c)
17.20(c)
(cont.)
library IEEE;
use IEEE.STD_LOGIC_1164 .ALL;
entity mag_comp_1bit is
port (a, b, gi, ei : in std_logic ;
go, eo : out std_logic );
end mag_comp_1bit ;
architecture compdf of mag_comp_1bit is
begin
go <= gi or (ei and a and not b);
eo <= ei and ((a and b) or (not a and not b));
end compdf ;
library IEEE;
use IEEE.STD_LOGIC_1164 .ALL;
-- Code for the 4 bit comparator
entity mag_comp_4bit is
port(x, y : in std_logic_vector (3 downto 0);
ig, ie : in std_logic ;
og, oe : out std_logic );
end mag_comp_4bit ;
223
library IEEE;
use IEEE.STD_LOGIC_1164 .ALL;
entity mag_comp_1bit is
port (a, b, gi, ei : in std_logic ;
go, eo : out std_logic );
end mag_comp_1bit ;
architecture compdf of mag_comp_1bit is
begin
go <= gi or (ei and a and not b);
eo <= ei and ((a and b) or (not a and not b));
end compdf ;
architecture Comp_Struc of mag_comp_4bit is
component mag_comp_1bit
port (a, b, gi, ei : in std_logic ;
go, eo : out std_logic );
end component ;
signal g, e : std_logic_vector (3 downto 0);
begin
mag_comp_1bit_3 : mag_comp_1bit
port map (x(3), y(3), g(3), e(3), g(2), e(2));
mag_comp_1bit_2 : mag_comp_1bit
port map (x(2), y(2), g(2), e(2), g(1), e(1));
mag_comp_1bit_1 : mag_comp_1bit
port map (x(1), y(1), g(1), e(1), g(0), e(0));
mag_comp_1bit_0 : mag_comp_1bit
port map (x(0), y(0), g(0), e(0), og, oe);
g(3) <= ig;
e(3) <= ie;
end Comp_Struc ;
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 17 Solutions
17.21 (a) so = si AND a'
b = si AND a
si
17.21(b)
a
Pr
so
b
17.21(c)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pr_sel_1bit is
port (a, si : in std_logic;
b, so : out std_logic);
end pr_sel_1bit;
architecture prdf of pr_sel_1bit is
begin
so <= si and not a;
b <= si and a;
end prdf;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Code for the 4 bit priority selector
entity pr_sel_4bit is
port(x : in std_logic_vector(3 downto 0);
isel : in std_logic;
y : out std_logic_vector(3 downto 0);
osel : out std_logic);
end pr_sel_4bit;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pr_sel_1bit is
port (a, si : in std_logic;
b, so : out std_logic);
end pr_sel_1bit;
architecture prdf of pr_sel_1bit is
begin
so <= si and not a;
b <= si and a;
end prdf;
17.21 (d) Time
0 ns
5 ns
10 ns
architecture Pr_Struc of pr_sel_4bit is
component pr_sel_1bit
port (a, si : in std_logic;
b, so : out std_logic);
end component;
signal sel : std_logic_vector(3 downto 0);
begin
pr_sel_1bit_3 :pr_sel_1bit
port map (x(3), sel(3), y(3), sel(2));
pr_sel_1bit_2 :pr_sel_1bit
port map (x(2), sel(2), y(2), sel(1));
pr_sel_1bit_1 :pr_sel_1bit
port map (x(1), sel(1), y(1),sel(0));
pr_sel_1bit_0 :pr_sel_1bit
port map (x(0), sel(0), y(0), osel);
sel(3) <= isel;
end Pr_Struc;
X
1000
0111
0000
isel
'1'
'1'
'1'
Y
1000
0100
0000
osel
'0'
'0'
'1'
sel
1000
1100
1111
17.22
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sm1 is
port (x, clk : in std_logic;
z : out std_logic);
end sm1;
architecture Behavioral of sm1 is
type rom8_3 is array(0 to 7) of std_logic_vector(0 to 2);
constant myrom: rom8_3 :=("001","100","111","000","000","010",
"110","101");
signal index, romout: std_logic_vector(0 to 2);
signal q, d: std_logic_vector(1 to 2):="00";
begin
index <= x&q;
romout <= myrom(conv_integer(index));
z <= romout(0);
d <= romout(1 to 2);
process(clk)
begin
if clk' event and clk='1' then q <= d; end if;
end process;
end Behavioral;
224
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 17 Solutions
17.23
X
0
X'
0
S0
X'
X
0
X
Z
S3
17.24
S1
X'
Z
0
S2
X'
Z
X
Z
--The state assignment is as follows (q0q1q2q3)--S0 - 1000; S1 - 0100; S2 - 0010; S3 - 0001
--VHDL code using equations derived by inspection from state graph
entity sm1 is
port (x, clk : in bit;
z : out bit);
end sm1;
architecture equations of sm1 is
signal q0 : bit := '1';
signal q1, q2, q3 : bit:='0';
begin
process(clk)
begin
if clk'event and clk='1' then
q0 <= (x and q0) or (not x and q1) or (not x and q3);
q1 <= (not x and q0) or (x and q3);
q2 <= (x and q2) or (x and q1);
q3 <= not x and q2;
end if;
end process;
z <= (not x and q1) or (x and q3) or q2;
end equations;
There are three problems with this code.
1) The sensitivity list for the process contains the signal select. It should be sel. (Select is a VHDL reserved
word).
2) When sel is true, there are two assignments to muxsel in the process and only the second one has any effect.
Hence, if sel is true for two successive executions of the process, muxsel will be incremented to 2.
3) Since muxsel is not changed until the process terminates, the selection uses the old value of muxsel not the new
value.
17.25
State X = 0 X = 1
S0
S0
S1
S1
S1
S2
S2
S2
S3
S3
S0
S0
17.27
State
S0
S1
S2
Next State
X1X2 = 00
S0
S0
S0
01
S1
S1
S1
17.26
Output
X=0 X=1
10
00
01
01
01
01
00
10
Next State
10
S2
S2
S2
11
S0
S1
S2
Next State
State X = 0 X = 1
S0
S0
S1
S1
S3
S2
S2
S1
S0
S3
S0
S1
Output
1
0
0
0
Z
0
0
1
225
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Unit 17 Solutions
17.28 (a) Present
Next State
State xin = 0 xin = 1
S1
S2
S10
S2
S2
S3
S3
S4
S6
S4
S7
S8
S5
S9
S10
S6
S9
S10
S7
S2
S3
S8
S4
S5
S9
S7
S8
S10
S9
S10
17.28 (c) Present
Next State
State xin = 0 xin = 1
S1
S2
S6
S2
S2
S3
S3
S4
S6
S4
S2
S8
S6
S4
S6
S8
S4
S3
zout
0
0
1
0
1
0
0
1
0
0
zout
0
0
1
0
0
1
17.28 (d) The output is 1 for an input sequence ending in
either 01 or 1011
17.28 (b)
40ns
80ns
120ns
Signal Current 0ns
clk
'0'
rst
'0'
xin
'1'
zout
'0'
s3
s4
s8
state
s10 s1 s2
s3
s6 s4
s7 s8
s5
nextstate s10 s2
160ns
s5
s10
200ns
s10
s9
240ns
s9
s7 s8
280ns
320ns
s8
s5
s5
s10
z = (0)010110011
17.29
df1, df2, and df3 are the same. They have two flip-flops, y0 and y1; y1 has input xin and y0 has input the
complement of y0. The output z is y0 AND (xin XOR y1 or equivalent AND-OR logic.
D
Q
y0
Ck Q'
clr
.
xin
Clk
D
Q
y1
zout
Ck Q'
clr
rst
226
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360ns
s1
Unit 17 Solutions
17.29
(cont.)
df4 is the same except that z is "registered" in a flip-flop.
D
Q
y0
Ck Q'
clr
xin
D
Clk
Q
y1
D
Ck Q'
clr
Ck
Q
zout
Q'
rst
17.29 (b) The output for df4 only changes on positive clock edges and is delayed with respect to the output for df1, df2 and df3.
See the simulation waveforms below..
Simulation for df1, df2 and df3.
Signal Current 0ns
clk
'0'
rst
'0'
xin
'1'
U
zout
'0'
U
y0
'0'
U
y1
'1'
40ns
80ns
120ns
160ns
200ns
240ns
280ns
320ns
360ns
Simulation for df4.
Signal
clk
rst
xin
zout
y0
y1
Current
'0'
'0'
'1'
'0'
'0'
'1'
0ns
40ns
80ns
120ns
160ns
200ns
240ns
280ns
320ns
U
U
U
227
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360ns
Unit 17 Solutions
17.30
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mask_8 is
port (X : in std_logic_vector(7 downto 0);
Store, Set, Clk : in std_logic;
Z : out std_logic_vector(7 downto 0));
end mask_8;
architecture Behavioral of mask_8 is
signal M : std_logic_vector(7 downto 0);
begin
process(Set, Clk)
begin
if Set='1' then M <= "11111111";
elsif Clk'event and Clk='1' then
if Store='1' then M<=X; end if;
end if;
end process;
Z <= M and X;
end Behavioral;
Z
8
M
Store
Set
8
Mask Register
Clk
8
8
X
17.31
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Seq_143 is
port (Clk, X : in std_logic;
Z : out std_logic);
end Seq_143;
architecture Moore of Seq_143 is
signal State : integer := 0;
signal NextState : integer range 0 to 3;
begin
process(State, X)
begin
case State is
when 0 => Z <= '0';
if X = '0' then NextState <= 0;
else NextState <= 1; end if;
when 1 => Z <= '0';
if X = '0' then NextState <= 2;
else NextState <= 1; end if;
when 2 => Z <= '0';
if X = '0' then NextState <= 0;
else NextState <= 3; end if;
when 3 => Z <= '1';
if X = '0' then NextState <= 2;
else NextState <= 1; end if;
end case;
end process;
process(Clk)
begin
if Clk'event and Clk='1' then
State <= NextState; end if;
end process;
end Moore;
228
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Unit 18 Solutions
18.3
Unit 18 Problem Solutions
See FLD p. 775 for circuit. Notice that the Q
output of the flip-flop is bin , while the D input is bout .
St'
0
St'
0
St
S0
St
Sh
S5
0
18.9
A
See FLD p. 776.
CC
D
S
HA
C
18.6
See FLD p. 776.
Sh
S3
X
See FLD p. 776. Compare to divider state graph of
FLD Figure 18-11.
18.8
S2
Sh
18.5
18.7 (b) See FLD p. 776.
- (d)
Sh
S4
See FLD p. 775. AND-ing with xi is like M/Ad if
xi is 1. Shifting is like moving from AND gates
involving x1 to those involving x2, or from x2 to x3.
18.7 (a) Overflow occurs only on division by 0, so
V = y0'y1'y2'y3'y4' = (y0 + y1 + y2 + y3 + y4)'
S1
Sh
18.4
S0
Co
B
St'/-
Z/Q
D
D
Q'
CK
St/L
S1
–/Sh, Dec, C
S2
Clock
Z'/Sh, Dec
Notes: 1) The value in the carry FF does not
matter for the first addition. 2) Only a half-adder
is needed since all the additions are of two bits.
Next State Table: S0 = 00, S1 = 01, S2 = 11
Output Table: L Sh Dec C
St Z
Q1Q0
00
01
00
00
00
01
11
11
11
11
00
10
--D1 = (Q1' + Z')Q0
D0 = (St + Q0)(Q1' + Z')
Q1'Q0 + Z'Q0 + StQ1'
11
01
11
00
--
St Z
10
01
11
11
--
Q1Q0
00
01
00
0000
0000
01
0111
0111
11
0110
0000
10
------L = (St' + Q0)'
Sh = Dec = (Q1' + Z')Q0
C = (Q1 + Q0')'
229
11
1000
0111
0000
----
10
1000
0111
0110
----
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 18 Solutions
18.10
A
X
St'/-
CC
D
S
HA
C
S0
Co
B
Z/Z'/Sh, Dec
Q
D
D
Q'
CK
Sh
St/L
S3
S1
–/Sh, Dec
–/Sh, Dec, C
S2
Clock
Notes: 1) The carry FF must contain 0 for the first
addition. 2) Only a half-adder is needed since all
the additions are of two bits; the first addition will
produce a 0 carry.
Next State Table: S0 = 00, S1 = 01, S2 = 11, S3 =
10
St Z
Q1Q0
00
01
00
00
00
01
11
11
11
10
10
10
10
00
D1 = (Q0 + Z')(Q0 + Q1)
D0 = (Q0 + St)Q1'
18.11
X
A
C
B
Ci
11
01
11
10
00
Output Table: L Sh Dec C
St Z
Q1Q0
00
01
11
00
0000
0000
1000
01
0110
0110
0110
11
0111
0111
0111
10
0110
0000
0000
L = (St' + Q1 + Q0)'
Sh = Dec = (Q0 + Z')(Q0 + Q1)
C = (Q1' + Q0')'
10
01
11
10
10
St'/-
CC
D
S
FA
S0
Co
Z/Z'/Sh, Dec
Q
D
D
Q'
CK
Sh
10
1000
0110
0111
0110
S3
–/Sh, Dec, C
St/L
S1
–/Sh, Dec, C
S2
Clk
Notes: 1) The carry FF must contain 0 for the
first addition. 2) A full-adder is needed since the
second addition may be of three bits. 3)The next
state and output equations are the same as in 18.10
except C = Q0.
230
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Unit 18 Solutions
18.12 (a) Inputs and outputs are given in decimal in the table. Inputs 10 through 14 are assumed to never occur.
A
B
0
A, 0
B, 9
1
B, 9
B, 8
2
B, 8
B, 7
3
B, 7
B, 6
4
B, 6
B, 5
5
B, 5
B, 4
6
B, 4
B, 3
7
B, 3
B, 2
8
B, 2
B, 1
9
B, 1
B, 0
15
A, 15
A, 15
18.12 (b) Use the state assignment Q = 0 for state A and Q = 1 for state B. There are 159 minimum sum-of-product equations
for Q+; one solution is
Q+ = X3'X0 + X3'X2 + X3'X1 + X3X2' + QX2'.
The minimum sum-of-product equations for the outputs are
Z3 = X3'X2'X1'X0 + QX2'X1X0' + QX3'X2'X1' + X3X2 or
= X3'X2'X1'X0 + QX2'X1X0' + QX3'X2'X1' + X3X1
Z2 = X2'X1X0 + X2X1' + Q'X2X0' + QX2'X1 + X3X2 or
= X2'X1X0 + X2X1' + Q'X2X0' + QX2'X1 + X3X1
Z1 = X1X0 + Q'X2X1'X0' + Q'X3X0' + QX1
Z0 = Q'X0 + QX0' + X3X2 or
= Q'X0 + QX0' + X3X1
18.13 (a) Inputs and outputs are given in decimal in the table. Inputs 1, 2, 13, 14, and 15 are assumed to never occur.
A
B
0
A, 0
A, 0
3
A, 3
B, 12
4
B, 12
B, 11
5
B, 11
B, 10
6
B, 10
B, 9
7
B, 9
B, 8
8
B, 8
B, 7
9
B, 7
B, 6
10
B, 6
B, 5
11
B, 5
B, 4
12
B, 4
B, 3
18.13 (b) Use the state assignment Q = 0 for state A and Q = 1 for state B. The minimum sum-of-product equations for Q+ and
the outputs are
Q+ = X3 + X2 + QX0 or
= X3 + X2 + QX1
Z3 = X3'X2 + Q'X3X2'X1'X0' + QX3'X1 or
= X3'X2 + Q'X3X2'X1'X0' + QX3'X0
Z2 = Q'X2X1'X0' + QX3X2' + QX2'X0 + X3X0 + X3X1 or
= Q'X2X1'X0' + QX3X2' + QX2'X1 + X3X0 + X3X1
Z1 = X1'X0 + Q'X1X0' + QX2X1' + QX3X1' + X3'X2'X1 or
= X1'X0 + Q'X1X0' + QX2X1' + QX3X1' + X3'X2'X0
Z0 = Q'X0 + QX2X0' + QX3X0'
18.14
The ONE ADDER is similar to a serial adder,
except that there is only one input. This means that
the carry will be added to X. Thus, if the carry flipflop is initially set to 1, 1 will be added to the input.
The signal I can be used to preset the carry flip-flop
to 1.
Let S0 represent Carry = 0, and let S1 represent
Carry = 1. The state graph is as follows:
X' , X
0
Z
I
X Sh
S0
S1
X' Sh
0
X Sh
Q
1
00
0
0
0
01
0
1
0
1
11
1
0
0
1
10
1
0
1
00
0
1
01
0
11
10
Q+= Q (Sh' + X )
, Sh'
X Sh
Q
0
0
Z = (Q + X)(Q' + X')(X + Sh)
Z = (Q + X)(Q' + X')(Q' + Sh)
0
Z
231
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Unit 18 Solutions
18.14
(cont.)
Q
I
X
Sh'
D
Q
X
Q'
X'
Q'
X or Q'
Sh
PreN
Clk
18.15 (a)
Z
product
Load
Sh
Ad
C
O
N
7
Clk
T
R
O
Done
L
St
6
C4
5
18.15 (c)
S0
St/Load
S7
S9
S1
M/Ad
- /Sh
S6
M'/Sh
M'/Sh
M/Ad
S5
- /Sh
3
2
1
0
multiplier
4-BIT ADDER
St'/0
- /Done
4
multiplicand
M
18.15 (b)
ACC
M'/Sh
S4
S2
0 0
1
0 1
0 0
0 0
1
0 1
0 0
0
0
0
1
0
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
0
1
1
0
1 0 1 add
1 0 1 shift
1 1 0 shift
1 1 1 add
1 1 1 shift
1 1 1
- /Sh
S3
M/Ad
232
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Unit 18 Solutions
18.15 (d)
Present
State
S0
S1
S2
S3
S4
S5
S6
S7
Next State
StM: 00
S0
S3
S3
S5
S5
S7
S7
S0
01
S0
S2
S3
S4
S5
S6
S7
S0
10
S1
S3
S3
S5
S5
S7
S7
S0
I. (S0, S7) (S1, S2) (S3, S4) (S5, S6)
II. (S0, S1) (S2, S3) (S4, S5) (S6, S7)
III. (S1, S3, S5) (S2, S4, S6) etc.
Ad Sh Load Done
00
01
10
11
0000 0000 0010 0010
0100 1000 0100 1000
0100 0100 0100 0100
0100 1000 0100 1000
0100 0100 0100 0100
0100 1000 0100 1000
0100 0100 0100 0100
0001 0001 0001 0001
11
S1
S2
S3
S4
S5
S6
S7
S0
B C
A
0
1
00
S0
S1
01
S3
S2
11
S5
S4
10
S7
S6
(Other assignments are
possible.)
For this assignment, from LogicAid:
JA = StB'C' + MC; KA = M' + B + C; JB = A'C; KB = A'C'; JC = AB'; KC = A'B;
Ad = MAB'C' + MA'C; Sh = M'A + M'C + AB + AC; Load = StA'B'C'; Done = A'BC'
4
3
M
0
Sh
Q7
SI
Sh
Ld
D7
Q6
Q5
D6
Q4
D5
Clk
D4
5
0
Ld Ad
Ld
1
5
0
4
5
Q3
D3
Q2
Q1
D2
Q0
D1
D0
3
0
Ld
1
3
3
multiplier
adder
4
4
multiplicand
St
M
Ad
Sh
Ld
Done
OR gates, AND
gates, & inverters
implement the
equations from
18.15 (d)
J
A
Clk
K
J
B
Clk
K
J
C
Clk
K
233
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Unit 18 Solutions
18.16 (a)
product
Load
Sh
Ad
C
O
8
7
ACC
6
5
4
3
2
1
0
N
Clk
T
R
O
Done
L
St
C5
multiplier
5-BIT ADDER
multiplicand
M
18.16 (b) See solution to 18.15 (b).
18.16 (c)
18.16 (d) Graph is same as 18.15, so from LogicAid, using
the same state assignment:
DA = StA'B'C' + MAB'C' + MA'C
DB = A'C + AB
DC = AB' + B'C + AC
Ad, Sh, Ld, Done: See solution to 18.15 (d)
St
1
-
M
1
1
0
0
-
A
0
1
0
0
1
1
1
1
0
B
0
0
1
0
0
1
C
0
0
1
1
1
1
1
0
DA
1
1
1
0
0
0
0
0
0
0
0
DB
0
0
0
1
1
0
0
0
0
0
0
DC
0
0
0
0
0
1
1
1
0
0
0
Ad Sh Ld Done
0 0 1 0
1 0 0 0
1 0 0 0
0 0 0 0
0 1 0 0
0 0 0 0
0 0 0 0
0 1 0 0
0 1 0 0
0 1 0 0
0 0 0 1
234
0 0 0
0 0 0
1 0
0 1 0
0 0 1
1 0
0 1 1
0 0 1
0
0
1
1
0
1
1
1
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
1
1 1 0 shift
0 1 1 add
0 1 1 shift
0 0 1 add
0 0 1 shift
0 0 0
Ad
Sh
Ld
Done
St
M
Clk
A
B
C
PLA
D Q
Clk
D Q
Clk
D Q
Clk
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 18 Solutions
18.16 (d)
(cont.)
3
M
0
SI
Sh
Ld
Sh
Q8
Q7
Q6
Q5
Q4
Q3
0 1
0 1
0 1
0 1
0 1
0 1
0
0
FA
0
FA
0
FA
0
FA
0
FA
D8
D7
D6
D5
D4
Q2
D3
Q1
D2
Q0
D1
D0
Clk
Ld Ad
3
0
0
Ld
1
3
3
multiplier
multiplicand
18.17 (a)
St'
18.17 (b) State
S0
S1
S2
S1
S2
S1
S0
0
S0
K
Sh
St M
Ad
K'
S1
M
18.18 (a)
M'K
Sh
St M'
Sh
S2
Sh
M'K'
Sh
Counter
00
00
01
01
10
10
00
X
000000111
011001111
001100111
100101111
010010111
101011111
010101111
St
1
0
0
0
0
0
0
M
1
1
1
1
1
1
1
K
0
0
0
0
1
1
0
Ad Sh
1 0
0 1
1 0
0 1
1 0
0 1
0 0
Ad
(alternate solution)
C
C
d7
b8
d6
Full
Subtracter
x7
0
d5
b7 Full
Subtracter
x6
y2
b6 Full
Subtracter
x5
b5 = 0
y1
divisor
235
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Unit 18 Solutions
18.18 (b)
x7
x6
x5
SubtracterComparator
0
18.18 (d)
0 1
1
1 0
1
0 1
1 0
1
0 0
0 1
1
1 0
1
0 1
1 0
1
0 1
x7
x3
x2
Sh
Ld
x0
Su
C
0
1
1
1
0
0
1
1
0
1
1
1
0
1
1
0
x6
y4
Sh
Control
St
V
Clk
1 0 0 1 1
0 0 1 1 0
0 0 1 1
0 1 1 1
0 1 1 1
1 1 1 1
1 1 1 0
1 1 1 0
1 1 0 1
1 1 0 1
18.18 (c)
St'
0
shift C = 0
C
sub. C = 1
1 shift C = 0
0
sub. C = 1
1 shift C = 0
0
shift C = 0
0
sub. C = 1
1 shift C = 0
0
sub. C = 1
1
C=0
Su
St
Ld
S0
C'
, 0
S1
C
S6
V
C
S5
Su
C
S2
C'
Sh
C'
Sh
S4
C
x5
x4
x3
x2
y3
y2
x1
Su
C
18.19 (b)
Sh
Ld
Su
Sh
Control
St
V
St
Clk
y1
St'
0
C
S4
0
0
d7
d6
d5
C
d4
Ld
S1
V
C'
, Su
S3
alternate solution
St
S0
St'
0
C'
Sh
S2
Sh
C
d3
Comparator C
Comparator C
F.A.
x7
1
F.A.
x6
y4
236
F.A.
x5
y3
F.A.
x4
y2
F.A.
x3
Su
C
S3
C'
Sh
C'
Sh
C'
18.19 (c)
C'
Sh
quotient
SubtracterComparator
0
x1
Divisor
remainder
18.19 (a)
x4
1
y1
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Su
Su
Unit 18 Solutions
18.19 (d)
0 1
1
1 0
1
0 1
1
1 0
1
0 0
0
1
1
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
remainder
1
1
0
1
1
1
1
1
0
18.20 (a)
0 1
St'
0
shift C = 0
1 0
St
sub. C = 1
1 1
S0
R
K
shift C = 0
1 0
K'B'
Sh
X
sub. C = 1
1 1
S1
K
K'B'
Sh
K'B
X Sh
K'B
X Sh
S2
0
quotient
18.20 (b) D0 = St'Q0 + KQ1 + KQ2; D1 = StQ0 + K'B'Q1 + K'BQ2; D2 = K'BQ1 + K'B'Q2; R = StQ0
Sh = K'B'Q1 + K'BQ1 + K'BQ2 + K'B'Q2 = K'Q1 + K'Q2; X = KQ1 + K'BQ1 + K'BQ2 = KQ1 + BQ1 + K'BQ2
18.21 (a)
SI
Sh
St
So
Clk
Controller
Clr
K
Counter
Clk
Er
Clk
18.21 (b)
K S'o
St'
0
Sh
S1
K So
,
St
Er
K' S o
S2
Clr
K
K' S o
Sh SI
K' S'o
K'S'o
Sh ,
Sh SI
S3
Sh
0
↓
18.21 (c) D1 = St'Q1 + KQ2 + KQ3
Clr= StQ1
Er=
KS
Q
↓
↓
↓
↓
o 2
↓
↓
D2 = K'So'Q2 + StQ1
Sh = K'So'Q2 + KSo'Q2 + K'SoQ2 + K'Q3
SI
=
K'S
Q
+
K'S
'Q3
↓
↓
o 2
o
D3 = K'SoQ2 + K'Q3
= So'Q2 + K'Q2 + K'Q3
Note: The signal marked by ↓ is the shift register serial output So not a state.
18.22 (a)
St
Control
Clk
K
Counter
Clk
SI
Sh
Sh
Shift Register A
Clk
0
SI
Sh
Shift Register B
a
b
SI
Logic
Circuit
C
Clk
237
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 18 Solutions
18.22 (b)
St'
St'
St
S0
0
S2
0
Present
State
0
K
St
Sh
S1
K
1
-
Q0
1
0
0
Q1
1
-
18.23 (a)
D0
1
1
0
0
D1
0
0
1
0
Control
Clk
0
00
0
0
Sh
01 11
0 1
- 1
0 0
10
1
1
0
1
S1
S2
18.22 (d) SI = C'ab + Cab' + Ca'b
Shift Register A
SI
Sh
Shift Register B
a
b
SI
Logic
Circuit
Clk
St C
Sh D
S1
S0
K
St C'
Sh
S0
1
Clk
K
Clk
St'
0
0
0
SI
Sh
Sh
Counter
18.23 (b)
10
S1
S1
S2
Sh
0
0
0
1
D
St
C
StK
01 11
S0 S1
- S2
S0 S2
K'
Sh
Sh
18.22 (c) I. (S0, S2)×2 (S1, S2) (S0, S1)
II. (S0, S2)×2 (S1, S2) (S0, S1)×2
From Karnaugh maps:
D0 = Q0+ = StQ0 + KQ0'Q1
D1 = Q1+ = St; Sh = StQ0'
Alternative: Q0+ = StQ0 + StKQ1
St
1
1
1
S0
S1
S2
00
S0
S0
K
K'
Sh D
State
Meaning
S0 Reset
S1 Find AND of A & B
S2 Find XOR of A & B
Sh D
Sh
S2
K'
Sh
238
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 18 Solutions
18.23 (c) Q0+ = St'Q0 + KQ1 + KQ2; Q1+ = StCQ0 + K'Q1;
Q2+ = StC'Q0 + K'Q2;
Sh = StCQ0 + StC'Q0 + K'Q1 + KQ1 + K'Q2 + KQ2
D = StCQ0 + K'Q1 + KQ1
St
0
1
1
-
C
1
0
-
K
1
1
0
0
Q0 Q1 Q2 Q1+
1 - 1
- 1 1
- - 1 1
1 - 0
- 1 0
1 - 0
- - 1 0
18.24 (a)
Q2+
0
0
0
1
1
0
0
Q3+
0
0
0
0
0
1
1
Sh
0
1
1
1
1
1
1
D
0
1
0
1
1
0
0
18.24 (b)
X
SI
Sh
18.23 (d) Change C' to D' in 18.22 (d)
SI = D'ab + Dab' + Da'b
Sh
M
-
X0
Control
St
St
Sh
Sh
S1
S3
C1 C2
-
18.24 (c) JA = B; KA = B; JB = St + A; KB = 1;
Sh = St + A + B; M = C1'C2 + X0'C1C2
-
Sh
Sh
S2
Note: M can be determined independently of the
state of the system, so it is not included in the state
graph.
A
B
SI
0
Clk
Ld
Controller
St
18.25 (b)
St'
0
0
S0
Clk
18.25 (a)
St'
S0
Ld
Clk
N
Clk
K'
St
Counter K
18.25 (c)
B
S1
K
3
K
K'
Ld
S2
A
0
StK
State 00 01 11
S0
S0 S0 S1
S1
S1 S2 S2
S2 S0 -
10
S1
-
00
000
010
100
ABLd
01 11
000 001
001 000 -
D1 = KQ2 + K'Q1; D2 = St + K'Q2;
B = K'Q2; Ld = St + KQ2
239
10
001
A = K'Q1;
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 18 Solutions
18.26
St'
0
St
S0
St'
0
St
LdAc, EnIn
0
S1
S6
S2
S5
EnIn, LdAd
Done, EnAd, LdAc
Done
18.27 (a)
ZER1 ZER2'
St'
0
ZER1 ZER2
S0
St
Done
LD2 LD1 CLR
EnIn, LdAd
S1
ZER1'
18.28 (a) Initial PU,PL: 0000 0000
1st Add Lower half PU, PL: 0000 1011
1st Add Upper half PU, PL: 0000 1011
2nd Add Lower half PU, PL: 0000 0110
2nd Add Upper half PU, PL: 0001 0110
3rd Add Lower half PU, PL: 0001 0001
3rd Add Upper half PU, PL: 0010 0001
4th Add Lower half PU, PL: 0010 1100
4th Add Upper half PU, PL: 0010 1100
5th Add Lower half PU, PL: 0010 0111
5th Add Upper half PU, PL: 0011 0111
S3
St
EnAd, LdAc
Clk
Control
S4
EnAd
LdAd
EnIn
LdAc
Done
18.27 (b) J = ST; K = ZER1 ZER2;
Done = ZER1 ZER2 Q; CLR = STQ';
CT2 LD1
LD2 = STQ'; LD1 = STQ' + ZER1 ZER2' Q;
CT1 = ZER1' Q; CT2 = ZER1 ZER2' Q
18.27 (c) (N1 + 1)N2 cycles
CT1
18.28 (b)
S
S'
CP,LA,LB,CC
S0
BZ'
LPL,EA,DB
CP,LA,LB,CC
S1
-
S'
BZ
0
D
S3
S
S2
LPU,MS
D
18.28 (d) Assume two FFs Q1Q0 and the following encoding:
S0 = 00, S1 = 01, S2 = 11, and S3 = 10. Then,
D0 = S(S0) + S2+ (BZ')S1
= SQ1'Q0' + Q1Q0 + (BZ')Q1'Q0
= SQ1'Q0' + Q1Q0 + (BZ')Q0
D1 = (BZ')S1 + (BZ)S1 + S(S3)
= S1 + S(S3)
= Q1'Q0 + SQ1Q0'
CP = LA = LB = CC = S0 = Q1'Q0'
LPL = EA = DB = (BZ')S1 = (BZ')Q1'Q0
LPU = MS = S2 = Q1Q0
D = S3 = Q1Q0'
18.28 (c) Label the 4 FF outputs S0, S1, S2 and S3.
D0 = S'S0 + S'S3
D1 = S(S0) + S2
D2 = (BZ')S1
D3 = (BZ)S1 + S(S3)
CP = LA = LB = CC = S0
LPL = EA = DB = (BZ')S1
LPU = MS = S2
D = S3
240
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 18 Solutions
18.29 (a) When the multiplier is negative, the B counter can
be incremented to zero. Two control inputs are
assumed: DB (decrement B) and IB (Increment
B). Also, when the multiplier is negative, the
multiplicand must be subtracted to produce the
product. This can be done by adding an ExclusiveOR array after the AND array; when IA = 0, the
output of the Exclusive-OR array is equal to its
input and when IA = 1, it inverts its input. To
produce a two's complement subtract, the carry
FF must be set; SC (set carry) has been added to
the carry FF. When the product is negative, (A3 ⊕
B3) = 1, IA must be 1 to extend the sign bit when
adding the carry to the upper half of the product.
Multiplier
B Counter
B3
Zero Detect
4
LA
A Reg
A3
4
EA
4
IA
Controller
4
S
CP,LA,LB
S0
S'
SC
XOR Array
to adder
B3 SC
B3' CC
18.29 (c)
S'
Note: The PU and PL registers are connected the
same way as in Problem 18.28.
AND Array
BZ
S
D
Initial PU,PL: 0000 0000
1st Add Lower half PU, PL: 0000 1011
1st Add Upper half PU, PL: 1111 1011
2nd Add Lower half PU, PL: 1111 0110
2nd Add Upper half PU, PL: 1111 0110
3rd Add Lower half PU, PL: 1111 0001
3rd Add Upper half PU, PL: 1111 0001
4th Add Lower half PU, PL: 1111 1100
4th Add Upper half PU, PL: 1110 1100
5th Add Lower half PU, PL: 1110 0111
5th Add Upper half PU, PL: 1110 0111
Multiplicand
4
LB
DB
IB
18.29 (b) Answer is the same for both parts of Part (b).
CP,LA,LB
S1
S4
S
D
CC
B3BZ'
LPL,EA,IA
B3'BZ'
LPL,EA
S2
BZ
0
D
C FF
S3
A3'B3'
LPU,MS,CC,DB
A3B3'
LPU,MS,CC,DB,IA
A3'B3
LPU,MS,SC,IB,IA
A3B3
LPU,MS,SC,IB
18.29 (d) Label the 5 FF outputs S0, S1, S2, S3 and S4.
D0 = S'S0 + S'S4, D1 = S(S0), D2 = S1 + S3
D3 = (BZ')S2, D4 = (BZ)S2 + S(S4)
CP = LA = LB = S0
CC = B3'(S1 + S3), SC = B3(S1 + S3)
LPL = EA = (BZ')S2
DB = B3'S3, IB = B3S3
IA = B3(BZ')S2 + (A3 ⊕ B3)S3
LPU = MS = S3
D = S4
241
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 18 Solutions
18.29 (e) Assume three FFs Q2Q1Q0 and the following encoding: S0 = 000, S1 = 001, S2 = 011, S3 = 010 and S4 = 100. Then,
D0 = S(S0) + S1+ S3 = SQ2'Q1'Q0' + Q2'Q1'Q0 + Q2'Q1Q0' = SQ1' + Q1'Q0 + Q1Q0' or
= SQ0' + Q1'Q0 + Q1Q0'
D1 = S1 + S3 + (BZ')S2 = Q2'Q1'Q0 + Q2'Q1Q0' + (BZ')Q2'Q1Q0 = Q1'Q0 + Q1Q0' + (BZ')Q1 or
= Q1'Q0 + Q1Q0' + (BZ')Q0
D2 = (BZ)S2 + S(S4) = (BZ)Q2'Q1Q0 + S(Q2Q1'Q0') = (BZ)Q1Q0 + S(Q2)
CP = LA = LB = S0 = Q2'Q1'Q0' = Q1'Q0'
CC = B3'(Q2'Q1'Q0 + Q2'Q1Q0') = B3'(Q1'Q0 + Q1Q0'); SC = B3(Q2'Q1'Q0 + Q2'Q1Q0') = B3(Q1'Q0 + Q1Q0')
LPL = EA = (BZ')Q2'Q1Q0= (BZ')Q1Q0
DB = B3'Q2'Q1Q0' = B3'Q1Q0'; IB = B3Q2'Q1Q0' = B3Q1Q0'
IA = B3(BZ')Q2'Q1Q0 + (A3 ⊕ B3)Q2'Q1Q0'= B3(BZ')Q1Q0 + (A3 ⊕ B3)Q1Q0'
LPU = MS = Q2'Q1Q0' = Q1Q0'
D = Q2Q1'Q0' = Q2
Note: These equations simplify because 101, 110 and 111 are don't-care state combinations.
18.30 (a)
St'
0
EZERO
S0
St
IZERO' EZERO'
DOWN
Done
S1
18.30 (b) D = EZERO' Q + StQ'; Done = EZERO Q;
CLR = StQ';
LOAD = StQ' + IZERO EZERO' Q
DOWN = IZERO' EZERO' Q
UP = IZERO EZERO' Q
CLR LOAD
18.30 (d) The quotient counter reaches 1111, and UP = 1
IZERO EZERO'
again.
UP LOAD
18.30 (c) N1 + (N1/N2) cycles (round down)
18.30 (e) The quotient will count upward forever, and Done
will never be 1.
18.31 (a) A = 11012 = -310, B = 10102 = 610
B X A = 0001 00102 = 1810
bi
0
Op Sin C4
Sh 0
–
1
Ad
Sh
Sh
0
1
Su
Sh
0
1
1
1
0
0
0
1
1
1
1
0
0
0
PU
0 0
0 0
1 0
1 0
1 1
1 1
0 1
0 1
0 0
A = 10002 = -810, B = 01102 = 610
B X A = 1101 00002 = -4810
0
0
1
1
0
1
1
0
1
x
0
1
0
PL
x x
x x
0
1
x
0
x
18.31 (b)
x
bi
0
Op Sin C4
Sh 0
–
1
Ad
Sh
x
x
1
0
0
1
18.31 (b) Since the number in ACC is a two’s complement
number, the sign of this number should be shifted
into ACC7. Before any add or subtract operations
ACC contains 0, so 0 should be shifted into
ACC7. After an Add operation, the sign of ACC
should be the same as the sign of the multiplicand.
After a subtract, the sign of ACC should be
the complement of the sign of the multiplicand
because the multiplier is negative making the
product sign opposite the sign of the multiplicand.
0
0
Ad
Sh
Sh
0
0
1
1
1
1
0
1
1
0
1
1
1
1
18.31 (c)
PU
0 0
0 0
0 0
0 0
1 0
0 0
1 0
0 1
1 0
0
0
0
0
0
0
0
0
1
x
0
PL
x x
x x
x
x
0
0
x
x
0
0
0
0
0
0
x
0
4
4-bit adder
Su
4
4
Multiplicand
242
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 18 Solutions
18.31 (c)
cont.
18.31 (d)
Ad
St'/0
M3
M 3′
J
Su
Q
to ACC 7
–/Sh
Clk
Ad
K
M 3′
Load
M3
S8
Q'
–/Done
S0
St/Load
S1
M'/Sh
M/Ad
M/Su
M'/Sh
S7
Su
–/Sh
Initially, the flip-flop must be cleared; the Load
signal can be used. When an add (subtract)
operation is done, M3 (M′3) should be loaded into
the flip-flop. It should remain unchanged, if no add
or subtract is done.
18.31 (e)
S9
S t'/0
St/Load
S0
–/Done
KM'/Sh
S3
K/Sh
18.32 (a)
S0
St/Load
C/V
S8
C/Su
S9
C′/Sh
–/Sh,Q
S7
–/Sh
S4
1 0111
0 0111
- (0) 1101 - (0) 1101
0 1010
1 1010
1 1011
0 1011
- (0) 1001 - (0) 1001
1 0010
0 0010
K'M/Ad
KM/Su
S2
S1
C′/Sh
18.32 (c) Subtraction should be done if X8 = 1 or if X8 = 0
and b8 = 0, so C = X8 + b8'.
18.32 (d) The controllers for the two dividers use the same
number of state transitions to complete a divide
so they operate at the same speed. The divider of
of Figure 18-14 is a bit simpler since the Mux is
8-wide rather than 9-wide and the subtracter is 4-bit
rather than 5-bit.
S2
C′/Sh
C′/Sh
–/Sh,Q
S3
M/Ad
S5
18.32 (b) The following case cannot occur:
1 101
- (0) 1001
1 0010
If X8 = 1 and X(7:4) would have been greater than
or equal to Y(3:0) before shifting 1 into X8. (If
X>Y, then 23 + (X-1)/2 = (15 + X)/2 > (15 + Y)/2 >
(Y+ Y)/2 = Y.
18.33 (a)
M'/Sh
M/Ad
S1
K'/Sh
–/Sh
M'/Sh
S6
K'M'/Sh
S2
S6
C/Su
C′/Sh
–/Sh,Q
S4
C/Su
S3
–/Sh,Q
C/Su
S5
18.32 (d) The controllers for the two dividers use the same number of state transitions to complete a divide so they operate
at the same speed. The divider of of Figure 18-15 is simpler since the Mux is 4-wide rather than 9-wide and the
subtracter is 4-bit rather than 5-bit. However, the controller requires more states so it will be more complex.
243
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 18 Solutions
18.34
N
8
Ld
Su
Ld
St
Su
Clk
Control
Circuit
St - start
8-bit register
8
Ld - load N into register
and clear counter
8
Su - load subtracter output
into register
Inc - increment counter
8-bit subtracter
B
Clk
8
"000"
Clr
Inc
B - borrow
4
4-bit counter
1
Clk
odd integer
When the done signal comes on, square root is in the 4-bit counter
St
St'
0
S0
B
Ld
S1
B'
Su Inc
Done
244
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 19 Solutions
Unit 19 Problem Solutions
19.1
See FLD p. 777 for solution.
19.2
See FLD p. 777 for solution.
19.3
See FLD p. 778 for solution.
19.4
See FLD p. 778 for solution.
19.5
See FLD p. 778 for solution.
19.6
See FLD p. 779 for solution.
19.7
See FLD p. 779 for solution.
19.8
See FLD p. 779 for solution.
19.9
See FLD p. 779-780 for solution.
19.10
See FLD p. 780 for solution.
19.11
19.12 (a)
19.12 (b)
245
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Unit 19 Solutions
19.14 (a)
19.13
Reset
S0
0
X
1
S1
0
X
1
S2
0
X
1
S3/Z
0
X
1
19.14 (b) Let S0, S1, S2 and S3 be the four FF outputs, then
D0 = x'(S0 + S1 + S2 + S3),
D1 = xS0,
D2 = xS1, and
D3 = x(S2 + S3).
Z = S3
19.14 (d) Using the simplification identity twice,
D1 = x(Q0 + Q1) and D0 = x(Q0' + Q1).
246
19.14 (c) Using state assignment S0 = 00, S1 = 01, S2 = 10
and S3 = 11, and denoting state variables Q1 and
Q0, D1 is the OR of D2 and D3 from Part b) so
D1 = x(S1 + S2 + S3)
= x(Q1'Q0 + Q1Q0 + Q1Q0').
Similarly, D0 is the OR of D1 and D3 from Part b)
so
D0 = x(S0 + S2 + S3)
= x(Q1'Q0' + Q1Q0' + Q1Q0).
Z = Q1Q0
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 19 Solutions
19.15 (a)
19.15 (b) Next State Table for Q1+ Q0+: S1 = 00, S2 = 01 and
S3 = 11.
Reset
Q1Q0
00
01
11
10
S1
0
St
1
Q1Q0
00
01
11
10
Clr
Sh
S2
0 S
o
1
000
00
01
11
--
St K So
001
011
00
00
11
00
11
00
---
010
00
00
00
--
100
01
01
11
--
St K So
101
111
01
01
11
00
11
00
---
110
01
00
00
--
D1 = K'Q1 + K'SoQ0 , D0 = K'Q0 + StQ0'
0
Output Table for Clr Sh Er SI
K
1
Sh, SI
So
0
1
Sh
Er
S3
K
Q1Q0
00
01
11
10
0 S
o
Sh
1
010
0000
0100
0000
--
St K So
Q1Q0
100
101
111
110
00
1000 1000 1000 1000
01
0100 0101 0010 0100
11
0101 0100 0000 0000
10
----Clr = StQ0';
Sh = K'Q0 + Q1'Q0
Er = KSoQ1'Q0; SI = K'So'Q1 + KSoQ1'Q0
1
0
Sh, SI
000
0000
0100
0101
--
St K So
001
011
0000 0000
0101 0010
0100 0000
---
19.15 (c) Label the three FF outputs S1, S2 and S3.
D1 = St'S1 + KS2 + KS3; D2 = K'So'S2 + StS1
D3 = K'SoS2 + K'S3;
Clr = StS1
Sh = K'S2 + KSo'S2 + K'S3 = K'S2 + So'S2 + K'S3
Er = KSoS2;
SI = K'SoS2 + K'So'S3
247
19.15 (d) Label the two FF outputs Q1, Q0 and the decoder
outputs S1 = 00, S2 = 01 and S3 = 11*, then
D0 = K'So'S2 + StS1 + K'SoS2 + K'S3
= K'S2 + StS1 + K'S3
D1 = K'SoS2 + K'S3;
Clr = StS1
Sh = K'S2 + So'S2 + K'S3
Er = KSoS2;
SI = K'SoS2 + K'So'S3
*Note: Other solutions are possible for different
encodings.
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 19 Solutions
19.16
S0 /
SS1
1 //
0 St
M
N
L oad
1
S3 /
1
M
Ad
0
S5 /
1
M
Ad
0
SS2
2 //
Sh
19.17
S7 /
1
Ad
0
S4 /
Sh
Sh
M
0
S6 /
Sh
Sh
Sh
S 9 / Done
1
Ad
S8 /
Sh
Sh
Clock
State
St
S1
S0
S2
S2
S3
S3
S4
State
S0
S0
S1
S1
S1
S2
S2
S3
Q 0 Q1
0 0
0 0
0 1
0 1
0 1
1 1
1 1
1 0
C
Sh
Su
19.18
Done
Load
Sh
Ad
St
M
K
PLA
D Q0
Clk
D Q1
Clk
19.19 (a)
M
0
0
1
-
K Q0+ Q1+
- 0
0
- 0
1
0 0
1
1 1
0
- 1
1
0 0
1
1 1
0
- 0
0
Ad
0
0
0
0
1
0
0
0
Sh Load Done
0
0
0
0
1
0
1
0
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
1
19.19 (b)
Clock
State S0
X1
St
0
1
-
S2
S0
S2
S1
S2
S0
X2
X3
S1
A+ = A'BX2 + A'B'X2 (X1' + X3 ) + {AB}
= BX2 + A'X2 (X1' + X3 )
B+ = A'B' (X2' + X1X3' ) + AB'X1' + A'BX2' + {AB}
= AX1' + A'B'X1X3' + A'X2'
Z1 = A + B + X2; Z2 = A'B'X2'; Z3 = A'B'X1'X2
In the preceding equations, curly brackets ({})
indicate a don’t care term.
Z1
Z2
Z3
248
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 19 Solutions
19.19 (c) PLA table obtained by tracing link paths:
State
S0
S1
S2
19.19 (d) 25 × 5 ROM
AB X1X2X3 A+B+ Z1Z2Z3
00 - 0 01 010
00 01 10 101
00 110
01 100
00 111
10 100
01 - 0 01 100
01 - 1 10 100
10 0 - 01 100
10 1 - 00 100
AB X1X2X3 A+B+ Z1Z2Z3
00 000
01 010
00 001
01 010
00 010
10 101
00 011
10 101
00 100
01 010
19.20 (a) C is loaded with 0.
19.20 (b)
19.21 (a) C is loaded with 0.
19.21 (b)
Reset
Reset
S0/LC, LR
S0/LC, LR
0
s
1
0
1
S1/SR
S1/SR
1
s
1
z
z
0
0
S2/Done
a0
S3/Done
0
1
0
1
1
s
a0
1
s
IncC
IncC
0
0
S2/SR
1
z
0
a0
1
0
249
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 19 Solutions
19.22 (a) C must be at least 4 bits and is loaded with 810
(10002).
19.23 (a) C must be at least 4 bits and is loaded with 710
(01112).
19.22 (b)
19.23 (b)
Reset
Reset
S0/LC, LR
S0/LC, LR
0
s
0
1
1
S3/Done
1
s
a0
0
1
ai
0
1
S3/Done
1
a0
ai
1
1
0
ai
0
ai
ai
19.24 (a) C must be at least 4 bits and is loaded with 810
(10002).
19.24 (b)
Reset
S0/LC, LR
0
1
s
S1/SR, IncC
a0
S5/Done
S2/SR, IncC
1
a0
0
0
1
S4/SR, IncC
0
a0
a0
0
1
0
1
ai
ai
ai
ai
0
1
s
S3/SR, IncC
ov
z
1
250
0
z
1
0
z
0
z
a0
1
s
0
0
1
0
SR
SR
S2/SR, IncC
z
z
0
1
S1/SR, IncC
S2/IncC
S1/IncC
1
s
z
1
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
a0
0
Unit 19 Solutions
19.25 (a)
19.25 (b) Let S0, S1, S2 and S3 be the four FF outputs, then
D0 = s'(S0 + S3); D1 = sS0 + (TC)'S2
D2 = S1;
D3 = (TC)S2
LDN = S1 + S2 or LDN = S1 + S2 + S3
CE = S1 or CE = S1 + S3
z1 = S1; z2 = S2
P3 = 0; P2 = 0; P1 = 1; P0 = 1
Reset
S0
0
s
1
S1/LDN, CE, z1
S2/LDN, z2
0 TC
In order to repeat
the pattern 12 times,
the counter must be
loaded with 0011
in state S0. Thus,
LDN must be 0 in
S0 and 1 in S1 and
S2. (It can be either
0 or 1 in S3.)
19.25 (c) Using state assignment S0 = 00, S1 = 01, S2 = 11,
S3 = 10, and denoting the state variables as Q1 Q0,
D1 is the OR of D2 and D3 from Part (b) so
D1 = S1 + (TC)S2 = Q1'Q0 + (TC)Q1Q0
= Q1'Q0 + (TC)Q0.
Similarly, D0 is the OR of D1 and D2 from Part (b)
so D0 = sS0 + (TC)'S2 + S1
= sQ1'Q0' + (TC)' Q1Q0 + Q1'Q0
= sQ1' + (TC)'Q0 + Q1'Q0.
The outputs are
LDN = S1 + S2 = Q0; CE = S1 = Q1'Q0
z1 = Q1'Q0; and z2 = Q1Q0
1
S3
0
s
1
19.26 (a) Initial PU,PL: 0000 0000
1st Add Lower half PU, PL: 0000 1011
1st Add Upper half PU, PL: 0000 1011
2nd Add Lower half PU, PL: 0000 0110
2nd Add Upper half PU, PL: 0001 0110
3rd Add Lower half PU, PL: 0001 0001
3rd Add Upper half PU, PL: 0010 0001
4th Add Lower half PU, PL: 0010 1100
4th Add Upper half PU, PL: 0010 1100
5th Add Lower half PU, PL: 0010 0111
5th Add Upper half PU, PL: 0011 0111
251
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Unit 19 Solutions
19.26 (b)
19.27
Reset
S1/ LA,LB,CC,CP
S0/CP, LA, LB, CC
0
0
S
S
1
1
S1/
S2/ SB*
BZ
1
0
0
LPL, EA, DB
B0
1
SP,IC
S3/ SP,IC
S2/LPU, MS
C1
S3/D
0
LPU
0
1
S4/ D
S
1
0
19.26 (c) Label the 4 FF outputs S0, S1, S2 and S3.
D0 = S'S0 + S'S3
D1 = S(S0) + S2
D2 = (BZ')S1
D3 = (BZ)S1 + S(S3)
CP = LA = LB = CC = S0
LPL = EA = DB = (BZ')S1
LPU = MS = S2
D = S3
S
1
* Although SB is 1 in state S2, shifting does not
occur until the next clock.
19.26 (d) Assume two FFs Q1Q0 and the following encoding:
S0 = 00, S1 = 01, S2 = 11 and S3 = 10. (The
decoder outputs are labeled S0, S1, S2 and S3.)
Then,
D0 = S(S0) + S2 + (BZ')S1
D1 = (BZ')S1 + (BZ)S1 + S(S3) = S1 + S(S3)
The output equations are the same as in Part (c).
252
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Unit 19 Solutions
19.28 (b) See answer to 18.30 (b).
19.28 (a)
19.29 (a)
To S0
19.29 (b) See answer to 16.26 (c).
253
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Unit 19 Solutions
19.30
254
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Unit 19 Solutions
19.31
19.32
S0 /
0
X
1
0
1
S3 / Z
S1 / Z
X
0
1
0
X
1
X
S2 /
255
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 19 Solutions
256
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Unit 20 Solutions
Unit 20 Problem Solutions
20.1
See FLD p. 781 for solution.
20.3
Replace line 12 with:
20.2
See FLD p. 781-782 for solution.
signal State, Nextstate: integer range 0 to 5;
Replace lines 27 - 33 with:
when 1 | 2 | 3 | 4 =>
if M = '1' then Ad <='1';
Nextstate <= State;
else Sh <='1'; Nextstate <= State + 1; end if;
when 5 => Done <= '1'; Nextstate <= 0;
20.4
See FLD p. 782-783 for solution.
20.5
See FLD p. 783 for solution.
20.6
See FLD p. 784 for solution.
Replace lines 39 - 41 with:
if Load = '1' then ACC <= "00000" & MPlier; end if;
if Ad = '1' then ACC(8 downto 4) <= addout; ACC(0) <= '0'; end if;
20.7
Replace line 14 with:
signal Counter: integer range 0 to 4;
signal State, NextState: integer range 0 to 3;
20.8
Clk
Rb
After line 22, add:
K<='1' when Counter=3 else '0';
Replace lines 33 - 36 with:
when 2 =>
if C = '1' then Su <= '1'; NextState <= 2;
elsif K = '1' then Sh <='1'; NextState <= 3;
else Sh <= '1'; NextState <= 2; end if;
when 3 =>
Replace line 47 with:
Test
Bench
Reset
Sum
Dice
Game
Roll
Win
Lose
if Sh = '1' then Dividend <= Dividend (7 downto 0) & '0';
Counter <= Counter + 1; end if;
20.8
(cont.)
Entity and architecture for DiceGame goes here.
entity GameTest is
end GameTest;
architecture dicetest of GameTest is
component DiceGame
port (CLK, Rb, Reset : in bit;
Sum: in integer range 2 to 12 ;
Roll, Win, Lose: out bit);
end component;
signal rb, reset, clk, roll, win, lose: bit;
signal sum: integer range 2 to 12;
type arr is array(0 to 11) of integer;
constant Sumarray:arr := (7,11,2,4,7,5,6,7,6,8,9,6);
begin
CLK <= not CLK after 20 ns;
Dice: Dicegame port map(rb,reset,clk,sum,roll,win,lose);
Contintued next column
257
process
begin
for i in 0 to 11 loop
Rb <= '1'; -- push roll button
wait until roll = '1';
wait until clk'event and clk = '1';
Rb <= '0'; -- release roll button
wait until roll <= '0';
sum <= Sumarray(i);
-- read roll of dice from array
wait until clk'event and clk = '1';
wait until clk'event and clk = '1';
if win = '1' or lose = '1' then reset <= '1';
end if;
wait until clk'event and clk = '1';
reset <= '0';
end loop;
wait; -- test completed, do not execute process
again
end process;
end dicetest;
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Solutions
20.9
Replace lines 6 - 11 with:
Port (Dividend_in: in std_logic_vector(4 downto 0);
Divisor: in std_logic_vector(4 downto 0);
St, Clk: in std_logic;
Quotient: out std_logic_vector(4 downto 0);
Remainder: out std_logic_vector(4 downto 0);
Replace lines 14 - 17 with:
signal State, NextState: integer range 0 to 6;
signal C, Load, Su, Sh, V: std_logic;
signal Subout : std_logic_vector (5 downto 0);
signal Dividend: std_logic_vector (9 downto 0);
Replace lines 19 - 23 with:
Subout <= '0'&Dividend(9 downto 5) - Divisor;
C <= not Subout (5);
Remainder <= Dividend (9 downto 5);
V <= '1' when Divisor = "00000" else '0';
Quotient <= Dividend (4 downto 0);
State_Graph: process (State, St, C, V)
Replace line 25 with:
Load <= '0'; Sh <= '0'; Su <= '0';
Replace lines 28 - 33 with:
if (St = '1') then
if (V='0') then Load <='1'; NextState <= 1;
else Nextstate <= 0; end if;
else Nextstate <= 0; end if;
when 1 => Sh <='1'; NextState <= 2;
when 2 | 3 | 4 | 5 =>
Replace line 36 with:
when 6 =>
Replace lines 45 - 47 with:
if Load = '1' then Dividend <= "00000" & Dividend_in; end if;
if Su = '1' then Dividend(9 downto 5) <= Subout (4 downto 0); Dividend(0) <= '1'; end if;
if Sh = '1' then Dividend <= Dividend (8 downto 0) & '0'; end if;
258
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Unit 20 Solutions
20.10 (a)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mult20_10 is
Port (CLK, S: in std_logic;
Mplier, Mcand : in std_logic_vector(3 downto 0);
Product : out std_logic_vector(7 downto 0);
D : out std_logic);
end mult20_10;
architecture Behavioral of mult20_10 is
signal State, NextState: integer range 0 to 4;
signal A, B: std_logic_vector (3 downto 0); -- Multiplicand & Multiplier
signall PU, PL: std_logic_vector (3 downto 0); -- Product registers
signal muxout, andarray: std_logic_vector (3 downto 0);
signal addout: std_logic_vector (4 downto 0);
signal BZ, LA, CP, DB, LPU, LPL, EA, MS, CC, C: std_logic;
begin
BZ <= '1' when B = "0000" else '0';
muxout <= PU when MS = '1' else PL;
andarray <= A when EA = '1' else "0000";
addout <= ('0' & muxout) + ('0' & andarray) + ("0000" & C); -- adder output is
Product <= PU & PL;
-- 5 bits including carry
process (S, State, BZ)
begin
CP <= '0'; LA <= '0'; DB <= '0'; MS <= '0'; CC <= '0';
EA <= '0'; LPU <= '0'; LPL <= '0'; D <= '0';
-- control signals are '0' by default
case State is
when 0 =>
CP <= '1'; LA <= '1'; CC <= '1';
if S = '1' then NextState <= 1; else NextState <= 0; end if;
when 1 =>
if BZ = '1' then NextState <= 3; else LPL <= '1'; EA <= '1'; DB <= '1'; NextState <= 2; end if;
when 2 =>
LPU <= '1'; MS <= '1'; NextState <= 1;
when 3 =>
D <= '1';
if S = '1' then NextState <= 3; else NextState <= 0; end if;
end case;
end process;
process (CLK)
begin
if CLK'event and CLK = '1' then
-- update registers on rising edge of clk
if LA = '1' then B <= Mplier; A <= Mcand; end if;
-- load multiplier & multiplicand
if CP = '1' then PU <= "0000"; PL <= "0000"; end if;
-- clear product registers
if DB = '1' then B <= B - 1; end if; -- decrement multiplier
if LPL = '1' then PL <= addout(3 downto 0); end if;
if LPU = '1' then PU <= addout(3 downto 0); end if;
if CC = '1' then C <= '0'; else C <= addout(4); end if
-- load carry flip-flop
State <= NextState;
end if;
end process;
end Behavioral;
259
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Unit 20 Solutions
20.10 (b)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test20_10 is
end test20_10;
architecture test1 of test20_10 is
component mult20_10
port (Clk: in std_logic;
S: in std_logic;
Mplier, Mcand : in std_logic_vector(3 downto 0);
Product : out std_logic_vector(7 downto 0);
D: out std_logic);
end component;
constant N: integer := 4;
type arr is array(1 to N) of std_logic_vector(3 downto 0);
constant Mcandarr: arr := ("1011", "1011", "1111", "0000");
constant Mplierarr: arr := ("0101", "0000", "1111", "1111");
signal CLK: std_logic :='0';
signal S, D: std_logic;
signal Mplier, Mcand: std_logic_vector(3 downto 0);
signal Product: std_logic_vector(7 downto 0);
begin
mult1: mult20_10 port map(CLK, S, Mplier, Mcand, Product, D);
CLK <= not CLK after 10 ns;
-- clock has 20 ns period
process
begin
for i in 1 to N loop
Mcand <= Mcandarr(i);
Mplier <= Mplierarr(i);
S <= '1';
wait until CLK = '1' and CLK'event;
S <= '0';
wait until D = '1' ;
wait until CLK = '1' and CLK'event;
end loop;
end process;
end test1;
260
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Unit 20 Solutions
20.11 (a)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mult20_11 is
Port (CLK, S: in std_logic;
Mplier, Mcand : in std_logic_vector(3 downto 0);
Product : out std_logic_vector(7 downto 0);
D : out std_logic);
end mult20_11;
architecture Behavioral of mult20_11 is
signal State, NextState: integer range 0 to 4;
signal B: std_logic_vector (3 downto 0); -- Multiplier counter
signal A: std_logic_vector (3 downto 0); -- Multiplicand register
signal PU: std_logic_vector (3 downto 0); -- Upper half of product register
signal PL: std_logic_vector (3 downto 0); -- Lower half of product register
signal andarray: std_logic_vector (3 downto 0);
signal addout: std_logic_vector (4 downto 0);
signal muxout: std_logic_vector (3 downto 0);
signal BZ, LA, CP, DB, IB, IA, LPU, LPL, EA, MS, CC, SC, C: std_logic;
alias B3: std_logic is B(3);
alias A3: std_logic is A(3);
begin
BZ <= '1' when B = "0000" else '0';
muxout <= PU when MS = '1' else PL;
andarray <= A when EA = '1' and IA = '0' else
not A when EA = '1' and IA = '1' else
"1111" when EA = '0' and IA = '1' else "0000";
addout <= ('0' & muxout) + ('0' & andarray) + ("0000" & C); -- adder output is 5 bits
Product <= PU & PL;
-- including carry
process (S, State, BZ)
begin
CP <= '0'; LA <= '0'; DB <= '0'; IB <= '0'; MS <= '0'; CC <= '0'; -- control signals are '0'
SC <= '0'; EA <= '0'; IA <= '0'; LPU <= '0'; LPL <= '0'; D <= '0'; -- by default
case State is
when 0 =>
CP <= '1'; LA <= '1';
if S = '1' then NextState <= 1;
else NextState <= 0; end if;
when 1 =>
NextState <= 2;
if B3 = '1' then SC <= '1';
else CC <= '1'; end if;
when 2 =>
if BZ = '1' then NextState <= 4;
else NextState <= 3; LPL <= '1'; EA <= '1'; end if;
if BZ = '0' and B3 = '1' then IA <= '1'; end if;
when 3 =>
LPU <= '1'; MS <= '1'; NextState <= 2;
if B3 = '0' then CC <= '1'; DB <= '1';
else SC <= '1'; IB <= '1'; end if;
if (A3 xor B3) = '1' then IA <= '1'; end if;
when 4 =>
D <= '1';
if S = '1' then NextState <= 4;
else NextState <= 0; end if;
end case;
end process;
261
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Unit 20 Solutions
20.11 (a)
(cont.)
20.11 (b)
process (CLK)
begin
if CLK'event and CLK = '1' then
-- update registers on rising edge of clk
if LA = '1' then B <= Mplier;
A <= Mcand; end if;
-- load multiplier & multiplicand
if CP = '1' then PU <= "0000";
PL <= "0000"; end if;
-- clear product registers
if DB = '1' then B <= B - 1; end if; -- decrement multiplier
if IB = '1' then B <= B + 1; end if; -- increment multiplier
if LPL = '1' then PL <= addout(3 downto 0); end if;
if LPU = '1' then PU <= addout(3 downto 0); end if;
if CC = '1' then C <= '0'; elsif SC = '1' then C <= '1';
else C <= addout(4); end if;
-- load carry flip-flop
State <= NextState;
end if;
end process;
end Behavioral;
--Same as 20-10(b) except
constant N: integer := 6;
type arr is array(1 to N) of std_logic_vector(3 downto 0);
constant Mcandarr: arr := ("0111", "0000", "0111", "1000", "0111", "1000");
constant Mplierarr: arr := ("0111", "0111", "0000", "0111", "1000", "1000");
262
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Unit 8 Design Solutions
III. SOLUTIONS TO DESIGN, SIMULATION,
AND LAB EXERCISES
Solutions to Unit 8 Design Problems
Problems 8.A through 8.S are combinational logic design problems using NAND and NOR gates.
Problems 8.A through 8.R are of approximately equal difficulty so that different students in the
class can be assigned different problems. We ask our students to use the following procedure:
(1) Derive a truth table for the assigned problem.
(2) Use Karnaugh maps to derive logic equations in sum-of-products or product-of-sums form
depending on whether NAND gates or NOR gates are required.
(3) Enter the truth table into LogicAid, derive the logic equations, and check the answers
against the results of step (2).
(4) Draw a circuit of AND and OR gates, trying to minimize the number of gates required by
using common gates where appropriate. Factoring or multiplying out is required in some
cases.
(5) Convert to NAND or NOR gates as specified.
(6) Simulate your answer to (5) using SimUaid, and verify that the circuit works correctly.
Use switches as inputs and probes or a 7-segment indicator as outputs.
In Unit 10, we ask our students to implement the same design problem using VHDL, synthesize it
and download it to a CPLD or FPGA on a hardware board that has switches, LEDs, and 7-segment
indicators.
For each design problem, the solutions that follow show a SimUaid circuit that meets the problem
specifications, but the solution does not necessarily use the minimum number of gates. Each solution
shows the truth table and the equations derived using LogicAid, and in several cases the Karnaugh
maps are shown to help identify common terms.
8.A
ABCD X1 X2 X3 X4 X5 X6 X7
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1
0
1
1
0
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
0
1
1
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
0
1
1
1
0
1
1
0
0
1
1
1
1
1
0
1
1
X1
X1
X2
X3
X4
X5
X6
X7
X7
=
=
=
=
=
=
=
=
=
B'D' + B D + A + C D = B'D' + BC'D + A + CD (used in circuit)
B'D' + B D + A + B'C
B' + C'D' + C D
C' + D + B
B'D' + B'C + B C'D + C D'
B'D' + C D'
C'D' + B C' + B D' + A
B'C + B C' + A + C D' (used in circuit)
B'C + B C' + A + B D'
This solution uses 15 gates and 41 gate inputs.
Students are allowed to use a maximum of 18 gates.
263
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.A
(cont.)
X1
C D
A B
00
00
X2
01
11
10
X
1
00
1
1
X
1
01
1
1
X
X
11
1
X
X
10
1
1
01
11
1
10
1
A B
00
C D
C D
A B
00
00
X5
01
1
01
1
11
1
10
1
1
11
10
X
1
A B
00
C D
00
X
C D
A B
00
1
01
1
X
1
X
X
X
X
11
1
10
1
1
1
00
1
1
X
1
X
1
01
1
1
X
1
X
X
11
1
1
X
X
X
X
10
1
X
X
X3 = C' + D + B
X6
01
1
11
10
X
1
C D
A B
00
00
X
10
10
X
X
X
X
1
1
11
X
00
10
X
11
10
11
X
X
11
01
X
X
01
10
01
X 4 = B'D' + B'C + B C'D + C D'
X7
11
1
C D
A B
00
01
X 2 = B' + C'D' + C D
X1 = B'D' + B C'D + A + C D
X4
X3
1
1
01
X5 = B'D' + C D'
X7 = B'C + B C' + A + B D'
1
01
11
10
1
X
1
1
X
1
X
X
X
X
1
X6 = C'D' + B C' + B D' + A
C
D
X1
B'
D'
1
0
A
0
A'
1
0
B
0
B'
1
0
B
C'
D
C
0
B
X2
B'
C
D'
X3
C'
D'
C'
1
0
D
0
D'
C
D'
1
2
3
4
5
6
7
X4
B'
C
X5
B
C'
X6
B
D'
X7
264
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.B
ABCD X1 X2 X3 X4 X5 X6 X7
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
X
X
X
1
0
1
1
0
1
1
1
1
1
X
X
X
1
1
1
1
1
0
0
1
1
1
X
X
X
1
1
0
1
1
1
1
1
1
1
X
X
X
1
0
1
1
0
1
1
0
1
1
X
X
X
1
0
1
0
0
0
1
0
1
0
X
X
X
1
0
0
0
1
1
1
0
1
1
X
X
X
0
0
1
1
1
1
1
0
1
1
X1
X2
X3
X3
X4
X4
X5
X6
X7
X7
=
=
=
=
=
=
=
=
=
=
B' + C'D + C D' + A
C+B
D' + C + A (used in circuit)
D' + C + B'
C'D + B'D + B C D' + A C' (used in circuit)
C'D + A'C D' + B'D + A C'
C'D + B'D
C D + A C'
A D + B C + C'D + A C' (used in circuit)
A D + B C + A C' + B D
This solution uses 15 gates and 38 gate inputs.
Students are allowed to use a maximum of 16 gates.
C'
D
B
X1
B'
C'
X2
C'
D
X3
C
D'
1
0
A
0
A'
1
0
0
B
B'
1
0
1
C
C'
1
0
1
C'
B
C
D'
B'
D
X4
1
2
3
4
5
6
7
X5
D
D'
C
D
X6
X7
D
B
C
265
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.C
ABCDE W X Y Z
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
0
0
0
0
0
0
X
X
0
0
0
0
0
0
X
X
0
0
0
0
1
1
X
X
0
0
0
1
1
1
0
0
0
0
0
0
X
X
0
0
0
0
1
1
X
X
0
0
1
1
0
0
X
X
0
0
1
0
1
1
0
0
0
0
0
0
X
X
0
0
1
1
0
0
X
X
0
1
0
1
0
1
X
X
0
1
1
0
0
1
0
0
0
0
0
0
X
X
0
1
0
1
0
1
X
X
0
0
0
0
0
0
X
X
0
1
0
1
0
1
W = A(C + D) (B + C) (C + E) = A(C + BDE) (used in circuit)
W = A(C + D) (B + C) (D' + E)
W = A(C + D) (C + E) (B + D')
W = A(C + D) (B + D') (D' + E)
X = (C + D) (B' + C + E') (A + C) (B + C') =
(B + C') (C + AD(B' + E')) (used in circuit)
X = (C + D) (B' + C + E') (B + C') (A + D')
X = (C + D) (B + C') (A + D') (B' + D' + E')
X = (C + D) (B' + C + E') (B + D) (A + D')
X = (C + D) (B + D) (A + D') (B' + D' + E')
X = (C + D) (A + C) (B + C') (B' + D' + E')
X = (C + D) (B' + C + E') (A + C) (B + D)
X = (C + D) (A + C) (B + D) (B' + D' + E')
Y = (A + B) (A + D) (B + E) (D + E) (A' + B' + D' + E') = (A + BD) (E + BD)
(A' + B' + D' + E') = (AE + BD)(A' + B' + D' + E')
Z = BE
This solution uses 14 gates and 32 gate inputs.
Student are allowed to use a maximum of 15 gates.
1
0
B'
D'
E'
A
0
B'
E'
D'
B
0
X
C
B'
1
0
0
C
A'
1
0
W
0
B
C'
C
0
E'
C'
Y
0
B'
D'
1
0
0
D
B'
D'
E'
D'
Z
0
1
0
0
B'
E'
E
E'
266
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.D
ABCDE W X Y Z
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
0
0
0
0
0
0
X
X
0
0
0
0
0
0
X
X
0
0
0
0
1
1
X
X
0
0
0
1
1
1
0
0
0
0
0
0
X
X
0
0
0
0
1
1
X
X
0
0
1
1
0
0
X
X
0
0
1
0
1
1
0
0
0
0
0
0
X
X
0
0
1
1
0
0
X
X
0
1
0
1
0
1
X
X
0
1
1
0
0
1
0
0
0
0
0
0
X
X
0
1
0
1
0
1
X
X
0
0
0
0
0
0
X
X
0
1
0
1
0
1
W = AC+ABDE
X = B C + A B'D + A D E'
Y = A'B D + A B'E + A D'E + B D E'
Z = BE
This solution uses 14 gates and 38 gate inputs.
Students are allowed to use a maximum of 14 gates.
W
B C
D E
X
00
00
1
A 01
0
11
01
1
11
1
1
1
X
X
X
X
10
10
B C
D E
1
1
0
X
01
1
0
11
10
0
11
0
1
1
1
0
X
1
1
X
X
X
X
X
X
1
1
X
1
0
0
0
X
X
X
X
00
1
X
01
11
10
1
A 01
0
C
1
1
X
11
X
X
1
1
X
X
10
1
A
1
X
X
X
Z = BE
W
0
B
D
E
B
B
C
X
0
B'
D
C
D
E'
C'
1
0
1
X
X
B C
D E
10
1
B'
1
0
X
00
A'
1
0
1
1
X = B C + A B'D + A D E'
Y = A'B D + A B'E + A D'E + B D E'
1
0
10
1
10
X
00
A 01
11
1
1
11
Z
00
01
A 01
W = AC+ABDE
Y
00
00
X
X
B C
D E
D
B'
E
D'
D'
E
E
B
D
Y
0
B
D
E'
E'
Z
0
B
E
267
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.E
ABCD X1 X2 X3 X4 X5 X6 X7
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
1
1
1
1
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
0
1
1
1
0
1
1
0
0
0
0
0
0
1
1
0
1
1
1
0
1
1
1
C
B'
D
1
0
1
0
0
0
A
C'
D'
A'
B
X1
This solution uses 17 gates and 44 gate
inputs.
Students are allowed to use a maximum of
18 gates.
B
B'
X1 = A B + A'C + B'D +
C'D' (used in circuit)
X1 = A C' + B C + B'D + A'D'
X1 = A D + B C + C'D' + A'B'
X1 = A C' + B D' + C D + A'B'
X1 = A B + C D + A'D' + B'C'
X1 = A D + B D' + A'C + B'C'
X2 = A' + C' + B'D' + B D
X3 = A C + B D + C'D' +
A'B' (used in circuit)
X3 = A B + B'C + A'D + C'D'
X3 = A B + C D + A'C' + B'D'
X3 = A D' + B D + B'C + A'C'
X3 = A D' + B C' + C D + A'B'
X3 = A C + B C' + A'D + B'D'
X4 = A B + A'C + B'D +
C'D' (used in circuit)
X4 = X1
X5 = B'D + B D' + C'D' +
A'B' (used in circuit)
X5 = B'D + B D' + C'D' + A'D'
X5 = B'D + B D' + A'D' + B'C'
X5 = B'D + B D' + A'B' + B'C'
X6 = A'B' + C'D' + A C
X7 = B C + A D + A C
C
B'
D'
X2
B
D
1
0
0
C
B'
X3
C'
C
1
0
0
D
1
2
3
4
5
6
7
X4
D'
X5
B
D'
X6
X7
D
B
C
268
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.F
ABCD X1 X2 X3 X4 X5 X6 X7
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
0
1
1
X
X
0
X
1
1
1
1
X
X
1
X
1
1
1
1
X
X
1
X
1
1
0
1
X
X
0
X
1
1
1
0
X
X
1
X
1
1
1
1
X
X
1
X
1
0
1
1
X
X
0
X
1
1
1
0
X
X
1
X
1
0
0
1
X
X
0
X
0
1
1
0
X
X
0
X
1
0
0
0
X
X
1
X
1
1
1
0
X
X
1
X
0
0
1
1
X
X
1
X
1
1
1
0
X
X
1
X
X1
X1
X1
X2
X3
X4
X4
X4
X4
X4
X5
X6
X7
X7
=
=
=
=
=
=
=
=
=
=
=
=
=
=
A + B'C + B'D' (used in circuit)
A + B'C + C'D'
A + B'D' + C D
A' + C' + D
C' + D' + A
A C' + B'D' + A B + A'C D (used in circuit)
A C' + A'B'C + A D' + C'D'
A C' + A'B'C + B'D' + A D'
A C' + A'B'C + B'D' + A B
A C' + B'D' + A D' + A'C D
A'C'D' + A'C D + A C'D + A B'C D'
C'D' + B + A C' + A D'
A'C + A C' + A D' (used in circuit)
A'C + A C' + C D'
This solution uses 18 gates and 51 gate inputs.
Students are allowed to use a maximum of 20 gates.
B'
D'
1
0
A
0
B'
C
A'
1
0
C
D'
B
0
X1
C
D
C
D
B'
X2
X3
X4
B
1
2
3
4
5
6
7
C'
1
0
0
C
C'
D'
C'
X5
C'
D
1
0
0
B'
C
D'
D
D'
C'
D'
B'
X6
C'
D'
X7
C
269
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.G
8.H
K N3 N2 N1 N0
M3 M2 M1 M0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
X
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
X
ABCD X1 X2 X3 X4 X5 X6 X7
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
1
0
1
1
X
1
X
0
X
1
X
1
X
1
X
1
1
1
1
1
X
1
X
1
X
0
X
0
X
1
X
1
1
1
1
0
X
1
X
1
X
1
X
1
X
1
X
1
1
0
1
1
X
1
X
0
X
1
X
1
X
0
X
1
1
0
0
1
X
0
X
0
X
0
X
1
X
0
X
1
1
0
1
0
X
0
X
1
X
1
X
1
X
0
X
0
1
0
1
1
X
1
X
1
X
1
X
1
X
0
X
M3 = N2 N1 N0 + N3 + K N2 N1 = N3 + N2 N1(K + N0)
M2 = N2 N1' + K'N2 N0' + N2'N1 N0 + K N2' N1
= N2 N1' + K' N2 N0' + N2' N1(K + N0)
M1 = K'N1 N0' + K N1' + N1'N0
= K' N1 N0' + N1'(K + N0)
M0 = K' N0' + K N0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
This solution uses 13 gates and 31 gate inputs.
Students are allowed to use a maximum of 13 gates.
M3
0
1
0
0
K
N2
N0'
N3'
N1
K'
1
0
0
N3
N3'
1
0
0
N2
N2'
N1
N2
N1'
N2
N0'
N2'
N1'
1
0
0
N1
M2
0
M1
0
N1
N0'
N1'
N0'
1
0
0
N0
N0'
X1
X2
X3
X4
X5
X6
X7
X7
=
=
=
=
=
=
=
=
N0
A'C' + D + B + A C
A' + B'C' + B C
B' + C + A
X5 + D + A'B + A B'C
A'C' + B C'
B'C' + D + A B' + A C'
D + A'B + A B' + B C' (used in circuit)
D + A'B + A B' + A C'
This solution uses 17 gates and 45 gate inputs.
Students are allowed to use a maximum of 20 gates.
270
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
M0
1
Unit 8 Design Solutions
8.H
(cont.)
C'
1
0
X1
C
A
0
B'
D'
B'
C'
A'
X2
B
C
1
0
B
0
1
0
1
0
B'
C
C
0
0
X3
B
C'
B'
X5
C'
B
D
B
C'
X4
D'
1
2
3
4
5
6
7
X5
D'
B'
X6
D'
C'
X7
D'
8.I
ABCD X1 X2 X3 X4 X5 X6 X7
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
X1
X2
X2
X2
X2
X3
X3
X4
X4
X4
X5
X6
X7
X7
=
=
=
=
=
=
=
=
=
=
=
=
=
=
X
X
1
0
1
1
0
1
1
1
1
1
X
X
1
1
1
1
1
0
0
1
1
1
X
X
1
1
0
1
1
1
1
1
1
1
X
X
1
0
1
1
0
1
1
0
1
1
X
X
1
0
1
0
0
0
1
0
1
0
X
X
1
0
0
0
1
1
1
0
1
1
X
X
0
0
1
1
1
1
1
0
1
1
1
0
A
0
A'
1
0
0
B
B'
B'
D'
1
B'
C
C'
D
C
C'
1
0
0
X1
B
D
B
D'
1
0
C
X2
B
C'
D'
X3
X4
D
D'
C'
D'
1
2
3
4
5
6
7
X5
B'D' + C' + B D + A
B'C + C'D + B D' (used in circuit)
X6
B
C
B'C + A'D' + C'D
B'D + C D' + B C'
X7
B'D + A'C' + C D'
C
B'
D + C + B' (used in circuit)
D+C+A
B'D' + B D + A C + C'D' (used in circuit)
B'D' + B D + A C + B C'
B'D' + B D + A C + A'C'
B'D' + C'D'
B C + A C + B'D'
B + A C + C'D' (used in circuit)
This solution uses 15 gates and 38 gate inputs.
B + A C + A D'
Students are allowed to use a maximum of 17 gates.
271
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.J
ABCDE W X Y Z
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
1
1
1
0
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
1
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
0
1
0
1
1
1
1
1
W = (A + B + C) (C + D) (B' + C + E) (used in circuit)
W = (A + B + C) (C + D) (A + C + E)
X = (A + B + D) (B' + C + E') (A' + C + E) (B' + C + D) (used in circuit)
X = (A + B + D) (B' + C + E') (A' + C + E) (C + D + E)
X = (A + B + D) (B' + C + E') (A' + C + E) (A + C + D)
Y = (A + B + E) (B' + C + D' + E') (A' + C + D) (A + D + E) (used in circuit)
Y = (A + B + E) (B' + C + D' + E') (A' + C + D) (B' + D + E)
Z = (A + B) (C + E) (A + D + E) (used in circuit)
Z = (A + B) (C + E) (B' + D + E)
This solution uses 17 gates and 51 gate inputs.
Students are allowed to use a maximum of 19 gates.
1
0
B
C
0
A
A'
1
0
0
B
B'
1
0
0
C
C'
1
0
0
D
D'
1
0
0
B'
C
E
W
0
C
D
C
E
B
D
X
0
B'
C
D
B'
C
E'
B'
C
D'
E'
E
C
D
E'
B
E
Y
0
D
E
Z
0
B
C
E
272
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.K
ABCDE W X Y Z
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
W =AB
X = B C + A B'
Y = B'C D + A'B C' + A B'D + A C
Z = A'C'D E + B D E + A'B'C D' + A B'C'D' + A'B C'D + A'B C'E + A C D + A C E
= DE(B + A'C') + B'D'(A'C + AC') + A'BC'(D + E) + AC(D + E)
= DE(B + A'C') + B'D'(A + C)(A' + C') + A'BC' (D + E) + AC(D + E)
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
This solution uses 19 gates and 47 gate inputs.
Students are allowed to use a maximum of 22 gates.
W
0
B
1
0
A
0
B'
A'
1
0
B
C
B
0
B'
C
1
0
0
1
0
C
B
C'
C'
B'
D
B'
C
D
D
0
1
0
D'
E'
E
0
B'
ABCD X1 X2 X3 X4 X5 X6 X7
1
1
1
1
0
1
1
0
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
1
1
0
1
1
1
1
1
1
0
1
0
0
0
1
0
1
0
1
1
1
1
0
0
0
1
1
1
0
1
1
1
1
1
0
0
1
1
1
1
1
0
1
1
X1
X2
X3
X4
X5
X6
X6
X6
X7
=
=
=
=
=
=
=
=
=
C
Z
0
C
C'
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
Y
0
D'
E'
8.L
X
0
B'
D'
D
E
(A + B' + C + D) (B' + C' + D')
(B + C) (A + B + D)
(A + B + D) (A + C + D')
(A + B' + C + D) (B' + C' + D') (A' + C' + D)
(B' + D) (B' + C') (A' + D) = (B' + D) (B' + C' + D') (A' + D)
(A' + C' + D) (A + B' + D) (A + B' + C) (used in circuit)
(A' + C' + D) (A + B' + C) (B' + C' + D)
(A' + C' + D) (A + B' + D) (B' + C + D')
(A + B + C' + D') (A + B' + C + D) (A' + C' + D)
This solution uses 18 gates and 50 gate inputs.
Students are allowed to use a maximum of 18 gates.
273
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.L
(cont.)
A B
00
C D
01
00
11
10
00
0
X
01
0
X
11
X
10
0
01
11
0
10
A B
00
C D
A B
00
01
00
11
10
11
00
0
10
A B
00
00
10
00
0
0
01
0
10
01
11
10
0
0
0
01
11
0
X
0
X
X3 = (A + B + D) (A + C + D')
C D
A B
00
01
0
X
01
0
11
0
X
10
0
X
10
X
00
11
11
0
X
X
0
A B
00
0
10
X5 = (B' + D) (B' + C' + D') (A' + D)
11
10
X
X
0
X
0
X6 = (A'+ C'+ D) (A + B'+ C) (A + B'+ D)
10
0
01
11
01
C D
11
01
X
10
X
X
X4 = (A'+ C'+ D) (B'+ C'+ D') (A + B'+ C + D)
C D
X
0
A B
00
C D
0
01
11
X2 = (B + C) (A + B + D)
X1 = (A + B'+ C + D) (B'+ C'+ D')
C D
01
X
0
X
X
B'
C
D
0
1
0
X7 = (A'+ C'+ D) (A + B'+ C + D) (A + B + C'+ D')
0
A
A'
1
0
X1
B'
C'
D'
B
C
X2
B
D
0
B
X3
B'
C
D'
X4
1
0
C'
D
0
C
C'
D
B'
C'
1
0
0
D
D'
X5
B'
D
B'
D
X6
B'
C
B
C'
D'
274
X7
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
1
2
3
4
5
6
7
Unit 8 Design Solutions
8.M
WXYZ X1 X2 X3 X4 X5 X6 X7
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
X
1
0
1
0
1
1
1
0
0
0
X
1
0
0
1
0
0
1
1
0
1
X
1
1
0
1
0
0
1
1
0
1
X
0
1
1
1
1
0
1
0
0
1
X
1
1
1
1
1
1
0
1
1
1
X
1
1
1
0
1
1
1
1
1
0
X1
X2
X2
X2
X3
X4
X5
X6
X6
X7
X
1
1
0
1
1
1
1
1
0
0
=
=
=
=
=
=
=
=
=
=
W'(X + Z) (Y + Z)
(X' + Y + Z') (W' + Z') (W + Y' + Z ) (W + X + Y') (used in circuit)
(X' + Y + Z') (W' + Z') (W + X + Y') (X' + Y' + Z)
(X' + Y + Z') (W' + Z') (W + Y' + Z) (X + Y' + Z')
(X + Y' + Z') (X' + Y + Z') (X' + Y' + Z) (W' + Z')
(X + Y) (X' + Y' + Z)
(X' + Y' + Z')
(W' + Y') (W + Y + Z) (used in circuit)
(W' + Y') (X' + Y + Z)
(X + Y' + Z') (W' + Z') (W' + Y')
This solution uses 19 gates and 50 gate inputs.
Students are allowed to use a maximum of 22 gates.
X
Z
Y
Z
1
0
0
W
W'
1
0
0
X
X'
X1
X
Y'
Y'
Z
X'
Y
Z'
X2
Z'
1
0
0
Y
Y'
1
0
1
Z
Z'
X'
Y
Z'
X'
Y'
Z
X
Y'
Z'
X
Y
X'
Y'
Z'
X3
X4
1
2
3
4
5
6
7
X5
Y'
Y
Z
X6
X7
275
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.N
ABCDE X Y Z
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
8.O
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
X = A'BC(D + E) (D' + E')
Y = ABE(C + D) (C' + D')
Z = (A + B) (A + C' + D' + E) (A' + B' + C + D' + E') (B' + C' + D + E')
= (A + B) (A + C' + D' + E) [B' + E'+ (A' + C + D') (C' + D)]
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
This solution uses 17 gates and 41 gate inputs.
Students are allowed to use a maximum of 19 gates.
1
0
1
0
1
1
0
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
B'
C'
A'
1
0
0
1
0
D'
E'
C
0
X
0
D
E
B
B'
B'
E'
C'
Y
0
C
D
1
0
D
0
C'
D'
D'
1
0
E
0
B
E'
C'
D
Z
0
C'
D'
E
B'
E'
C
D'
ABCD X1 X2 X3 X4 X5 X6 X7
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
A
0
1
0
1
1
0
1
1
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
0
1
1
1
0
1
1
0
0
1
1
1
1
1
0
1
1
X1
X2
X3
X4
X5
X6
X7
=
=
=
=
=
=
=
(A + B + C + D') (B' + D) = (A + B + C + D') (B' + C' + D) (B' + C + D)
(B' + C + D') (B' + C' + D)
(B + C' + D)
(B + C + D') (B' + C + D) (B' + C' + D')
D' (B' + C) = D' (B' + C + D)
(A + B + D') (B + C') (C' + D')
(A + B + C) (B' + C' + D')
This solution uses 18 gates and 48 gate inputs.
Students are allowed to use a maximum of 19 gates.
276
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.O
(cont.)
CD
AB
00
00
01
01
11
0
X
0
AB
CD
0
00
01
11
00
X
11
10
10
01
X
X
X
X
0
11
10
X1 = (A + B + C + D)(B'+ C + D)(B'+ C' + D)
AB
CD
00
00
0
10
00
11
0
X
10
CD
AB
X
01
X
X
X
11
X
X
10
X
X
11
X
X
10
0
00
01
0
0
X
0
01
0
11
0
0
X
X
11
0
X
X
10
0
0
11
CD
10
00
00
01
X3 = (B + C'+ D )
00
X5 = (D')(B'+ C + D)
10
X
AB
CD
11
00
X2 = (B'+ C + D')(B'+ C'+ D)
01
01
X
01
10
AB
CD
AB
00
01
11
00
0
X
X
01
0
X
X
11
X
X
10
11
0
X
0
0
10
X
0
X
X
X
X
X4 = (B'+ C'+ D')(B'+ C + D)(B + C + D')
X
X
01
0
10
X
X
X
X
X7 = (B'+ C'+ D')(A + B + C)
X 6 = (C'+ D')(B + C')(A + B + D')
To save one gate, use:
X6 = (B' + C' + D')(B + C')(A + B + D')
1
0
1
0
0
0
A
A'
B
C
D'
B
B'
C'
D
B'
C
D
B'
1
0
0
C
C'
1
0
0
X1
D
D'
B'
C
D'
X2
B
C'
D
X3
B
C
D'
X4
B'
C'
D'
D
1
2
3
4
5
6
7
X5
B
D'
B
C'
X6
C'
D'
B
C
277
X7
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.P
ABCD X1 X2 X3 X4 X5 X6 X7
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
0
1
1
X
X
0
X
1
1
1
1
X
X
1
X
1
1
1
1
X
X
1
X
1
1
0
1
X
X
0
X
1
1
1
0
X
X
1
X
1
1
1
1
X
X
1
X
1
0
1
1
X
X
0
X
1
1
1
0
X
X
1
X
1
0
0
1
X
X
0
X
0
1
1
0
X
X
0
X
1
0
0
0
X
X
1
X
1
1
1
0
X
X
1
X
0
0
1
1
X
X
1
X
1
1
1
0
X
X
1
X
X1
X2
X3
X4
X5
= (A + C + D') (A + B')
= (A' + C' + D)
= (A + C' + D')
= (A + C + D') (A + B') (A' + C' + D')
= B'(A + C + D') (A + C' + D) (A' + C + D) (A' + C' + D')
= B' (A + (C + D') (C' + D)) (A' + C + D) (A' + C' + D')
X6 = (A + D') (A + B + C') (C' + D')
X7 = (A + C) (A' + C' + D')
This solution uses 21 gates and 50 gate inputs.
Students are allowed to use a maximum of 21 gates.
1
0
0
A
B'
A'
X1
C
D'
1
0
0
B
1
0
0
X2
C'
D
B'
C
X3
C'
D'
C'
X4
1
0
0
C'
D'
D
D'
C'
D
X5
C
D'
B
C
D
D'
C'
D'
X6
B
C'
X7
C
8.Q
ABCD X1 X2 X3 X4 X5 X6 X7
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
1
0
1
1
X
1
X
0
X
1
X
1
X
1
X
1
1
1
1
1
X
1
X
1
X
0
X
0
X
1
X
1
1
1
1
0
X
1
X
1
X
1
X
1
X
1
X
1
1
0
1
1
X
1
X
0
X
1
X
1
X
0
X
1
1
0
0
1
X
0
X
0
X
0
X
1
X
0
X
1
1
0
1
0
X
0
X
1
X
1
X
1
X
0
X
0
1
0
1
1
X
1
X
1
X
1
X
1
X
0
X
X1
X2
X3
X4
X5
X6
X7
=
=
=
=
=
=
=
(A + B + C' + D) (A' + B + C)
(A' + B + C') (A' + B' + C)
(A + B' + C)
(A + B + C' + D) (A' + B + C) (A' + B' + C')
C'(A' + B) = C'(A' + B + C)
(A + C' + D) (A + B' + C) (A' + B' + C')
(A + B + D) (A' + B' + C')
This solution uses 15 gates and 40 gate inputs.
Students are allowed to use a maximum of 17 gates.
278
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
1
2
3
4
5
6
7
Unit 8 Design Solutions
8.Q
(cont.)
X1
C D
A B
00
X2
01
11
00
A B
00
C D
10
X3
01
00
0
11
C D
10
A B
00
00
0
X4
01
11
C D
10
A B
00
0
00
01
X
X
X
01
X
X
X
01
X
X
X
01
11
X
X
X
11
X
X
X
11
X
X
X
11
10
10
0
X5
C D
A B
00
01
11
00
01
11
0
10
0
C D
10
X7
01
00
0
11
10
C D
A B
00
00
01
11
10
X
X
01
X
X
X
01
X
X
X
X
X
11
X
X
X
11
X
X
X
0
10
0
0
10
0
X 6 = (A + B'+ C ) (A'+ B'+ C') (A + C'+ D )
10
X
X
X
X
X
X
0
0
0
0
X
0
11
X4 = (A'+ B'+ C') (A'+ B + C ) (A + B + C'+ D )
X3 = (A + B'+ C )
X
0
0
A B
00
0
X5 = (C') (A'+ B + C )
1
0
10
0
X 2 = (A'+ B'+ C ) (A'+ B + C')
X 1 = (A'+ B + C ) (A + B + C'+ D )
10
01
0
0
X7 = (A'+ B'+ C') (A + B + D )
A
A'
B
C
1
0
0
B
B
C'
D
B'
1
0
1
0
0
0
X1
C
B
C'
C'
B'
C
D
B'
C
X2
X3
X4
D'
B'
C'
C
1
2
3
4
5
6
7
X5
C'
D
B'
X6
B'
C'
B
D
279
X7
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.R
ABCD X1 X2 X3 X4 X5 X6 X7
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
CD
AB
X
X
1
0
1
1
0
1
1
1
1
1
00
X
X
1
1
1
1
1
0
0
1
1
1
01
X
X
1
1
0
1
1
1
1
1
1
1
11
X
X
1
0
1
1
0
1
1
0
1
1
X
X
1
0
1
0
0
0
1
0
1
0
X
X
1
0
0
0
1
1
1
0
1
1
X1
X2
X2
X3
X3
X4
X4
X5
X6
X6
X6
X7
X7
X
X
0
0
1
1
1
1
1
0
1
1
10
=
=
=
=
=
=
=
=
=
=
=
=
=
(A + B + D') (B' + C' + D)
(B' + C' + D') (B + C + D) (used in circuit)
(B' + C' + D') (A' + C + D)
(B' + C + D) (used in circuit)
(A + C + D)
(A + B + D') (B' + C' + D) (B + C + D') (used in circuit)
(A + B + D') (B' + C' + D) (A' + C + D')
(D') (B' + C') = D'(B' + C' + D)
(B + C + D') (A + B + D') (A + C) (used in circuit)
(A + B + D') (C + D') (A + C)
(A + B + D') (C + D') (B' + C)
(A + B) (B + C + D') (used in circuit)
(A + B) (A' + C + D')
This solution uses 15 gates and 37 gate inputs.
Students are allowed to use a maximum of 16 gates.
AB
CD
00
01
11
10
0
AB
CD
CD
10
AB
00
X
0
X
00
X
X
X
X
01
X
X
0
X
X
00
X
X
01
X
X
01
X
X
01
11
0
X
11
X
11
X
11
X
10
X
10
X
10
0
X1 = (B'+ C'+ D ) (A + B + D')
CD
AB
00
X2 = (B'+ C'+ D') (B + C + D)
01
11
10
AB
CD
X
01
11
00
X
00
X
0
X
01
X
0
X
0
01
X
0
X
11
0
0
X
0
11
0
0
X
10
10
X5 = (D') (B'+ C' + D)
1
0
0
0
1
0
X
X
B
D'
B'
C'
D
X
00
01
11
00
X
X
01
X
X
11
0
X
10
0
X
10
0
X7 = (A + B ) (B + C + D')
X1
B'
C'
D'
B
X2
B
C
D
C
B'
C
D
C'
1
0
0
A
B'
1
0
0
X 6 = (B + C + D')(A + B + D')(A + C)
A'
1
0
AB
CD
10
0
10
X4 = (B'+ C'+ D ) (A + B + D') (B + C + D')
X3 = (B'+ C + D )
00
11
11
X
10
01
01
00
0
00
00
D
X3
X4
B
C
D'
D'
D
C
D'
X5
1
2
3
4
5
6
7
X6
C
X7
B
280
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.S
A1A2 A3
X1 X2 X3 X4 X5 X6 X7
0
0
0
0
1
1
1
1
0
1
1
1
1
0
1
0
0
0
1
1
0
0
1
1
1
0
0
1
0
1
0
1
0
1
1
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
1
0
1
1
0
1
1
0
1
0
X1
X2
X3
X4
X5
X6
X7
=
=
=
=
=
=
=
(A1 + A2 + A3) (A1' + A3')
(A2 + A3') (A1' + A3')
0
0
0
(A2' + A3') (A1' + A3')
(A1 + A2' + A3) (A1' + A3')
This solution uses 9 gates and 20 gate inputs.
Students are allowed to use a maximum of 11 gates.
A1
0
A1'
A3'
1
0
0
A2
A2'
1
0
0
A2
A3
X2
A2
A3'
A3
A3'
X1
X6
1
2
3
4
5
6
7
A2'
A3'
X7
A2'
A3
281
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
282
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 10 Design Solutions
Solutions to Unit 10 Design and Simulation Problems
Assignment 1:
We use Problems 10.A through 10.M to introduce students to the use of a VHDL Simulator for testing and debugging their
VHDL code. We ask our students to do the following:
(1) Work out the logic design for your assigned problem, including a block diagram for the main module showing
inputs, outputs, and internal connections.
(2) Write VHDL code that describes your design.
(3) Simulate and debug the VHDL code.
(4) Print out a simulator listing that verifies the correct operation of your design for the prescribed test sequences.
Test sequences for problems 10.A through 10.N are given in FLD. The command sequences and the listing outputs given in
the solutions that follow make use of the DirectVHDL simulator, which is provided on the CD.
Assignment 2:
In Unit 8, we asked students to design and simulate a combinational circuit using NAND and NOR gates. In this assignment,
we ask the students to convert their SimUaid circuit from Unit 8 to VHDL code, compile the VHDL code, download it to a
Xilinx CPLD or FPGA board, and test its operation.
One of the features of SimUaid is the automatic conversion of circuit diagrams to VHDL. The VHDL converter removes all
switches, probes, and other I/O devices from the circuit, and puts the corresponding signals into the input and output ports
of a VHDL module. Each SimUaid component is instantiated as a VHDL component and the signals that connect to the
component inputs and outputs are placed in the component port. The resulting VHDL code can be compiled and synthesized
using appropriate software. The necessary VHDL components are defined in the SimUaid synthesis libraries provided on the
CD. We use the Xilinx ISE software to synthesize the VHDL code and download it to a Xilinx CPLD or FPGA.
10.A
Output (from DirectVHDL):
I0
Time
0 ns
5 ns
10 ns
15 ns
Z
I1
SEL
I0
I1
B
I2
F
A
I3
B
Test Sequence: I0 = I2 = 1,
I1 = I3 = 0, AB = 00, 01, 11, 10.
Command Sequence:
force i0 1
force i2 1
force i1 0
force i3 0
force a 0
force b 0
run 5ns
force b 1
run 5ns
force a 1
run 5ns
force b 0
run 5ns
i0
'1'
'1'
'1'
'1'
-- Code for the 2 to 1 MUX
entity mux2_1 is
port (i0, i1, sel : in bit;
z : out bit);
end mux2_1;
architecture eqn of mux2_1 is
begin
z <= (i0 and not sel) or (i1 and sel);
-- alt: z <= i1 when sel = '1' else i0;
end eqn;
-- Code for the 4 to 1 MUX
entity mux4_1 is
port (i0, i1, i2, i3, a, b : in bit;
f : out bit);
end mux4_1;
architecture eqn of mux4_1 is
component mux2_1 is
port (i0, i1, sel : in bit;
z : out bit);
end component;
signal c, d : bit;
begin
m1 : mux2_1 port map(i0, i1, b, c);
m2 : mux2_1 port map(i2, i3, b, d);
m3 : mux2_1 port map(c, d, a, f);
end eqn;
283
i1
'0'
'0'
'0'
'0'
i2
'1'
'1'
'1'
'1'
i3
'0'
'0'
'0'
'0'
a
'0'
'0'
'1'
'1'
b
'0'
'1'
'1'
'0'
f
'1'
'0'
'0'
'1'
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
d
'1'
'0'
'0'
'1'
c
'1'
'0'
'0'
'1'
Unit 10 Design Solutions
10.B
BCD(0)
BCD(1)
BCD(2)
16 x 4
ROM
GRAY(0)
GRAY(1)
GRAY(2)
GRAY(3)
BCD(3)
Test Sequence: BCD = 0010, 0101, 1001.
Command Sequence:
force bcd 0010
run 5ns
force bcd 0101
run 5ns
force bcd 1001
run 5ns
Output (from DirectVHDL):
Time bcd gray index
0 ns 0010 0011 2
5 ns 0101 1110 5
10 ns 1001 1000 9
10.C
library bitlib;
use bitlib.bit_pack.all;
entity rom is
port (bcd : in bit_vector(3 downto 0);
gray : out bit_vector(3 downto 0));
end rom;
architecture eqn of rom is
type rom16_4 is array (0 to 15) of bit_vector (3 downto 0);
constant rom1 : rom16_4 := (“0000”, “0001”, “0011”, “0010”,
“0110”, “1110”, “1010”, “1011”, “1001”, “1000”, others =>
“1111”);
signal index : integer range 0 to 15;
begin
index <= vec2int(bcd);
gray <= rom1(index);
end eqn;
Note: See solution to Problem 4.40 for derivation of the half-adder
A
B
Half-Adder
S1
C1
Half-Adder
C2
Cin
Test Sequence: a b cin = 0 0 1, 0 1 1, 1 1 1, 1 1 0, 1 0 0.
Command Sequence:
force a 0
force b 0
force cin 1
run 5ns
force b 1
run 5ns
force a 1
run 5ns
force cin 0
run 5ns
force b 0
run 5ns
Output (from DirectVHDL):
Time
a
b cin sum
0 ns '0' '0' '1' '1'
5 ns '0' '1' '1' '0'
10 ns '1' '1' '1' '1'
15 ns '1' '1' '0' '0'
20 ns '1' '0' '0' '1'
cout
'0'
'1'
'1'
'1'
'0'
c2
'0'
'1'
'0'
'0'
'0'
c1
'0'
'0'
'1'
'1'
'0'
284
s1
'0'
'1'
'0'
'0'
'1'
-- Code for the half adder
entity ha is
port (a, b : in bit;
Sum
s, c : out bit);
end ha;
Cout architecture eqn of ha is
begin
s <= a xor b;
c <= a and b;
end eqn;
-- Code for the full adder
entity fa is
port (a, b, cin : in bit;
sum, cout : out bit);
end fa;
architecture eqn of fa is
component ha is
port (a, b : in bit;
s, c : out bit);
end component;
signal s1, c1, c2 : bit;
begin
ha1 : ha port map(a, b, s1, c1);
ha2 : ha port map(s1, cin, sum, c2);
cout <= c1 or c2;
end eqn;
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 10 Design Solutions
10.D
Test Sequence: a b c = 0 0 0, 0 1 0, 1 1 0, 1 1 1, 0 1 1.
y0
A
B
C
3 - to - 8
line
decoder
y1
y2
Command Sequence:
force a 0
force b 0
force c 0
run 5ns
force b 1
run 5ns
force a 1
run 5ns
force c 1
run 5ns
force a 0
run 5ns
count(1)
y3
y4
y5
count(0)
y6
y7
-- Code for the 3 to 8 decoder
entity decoder is
port (a, b, c : in bit;
y0, y1, y2, y3, y4, y5, y6, y7 : out bit);
end decoder;
architecture eqn of decoder is
begin
y0 <= not a and not b and not c;
y1 <= not a and not b and c;
y2 <= not a and b and not c;
y3 <= not a and b and c;
y4 <= a and not b and not c;
y5 <= a and not b and c;
y6 <= a and b and not c;
y7 <= a and b and c;
end eqn;
-- Code for the main module
entity fa is
port (a, b, c : in bit;
count : out bit_vector(1 downto 0));
end fa;
architecture eqn of fa is
component decoder is
port (a, b, c : in bit;
y0, y1, y2, y3, y4, y5, y6, y7 : out bit);
end component;
signal y0, y1, y2, y3, y4, y5, y6, y7 : bit;
begin
d1 : decoder port map(a, b, c, y0, y1, y2, y3, y4, y5,
y6, y7);
count(0) <= y1 or y2 or y4 or y7;
count(1) <= y3 or y5 or y6 or y7;
end eqn;
Output (from DirectVHDL):
Time
a
b
c count
0 ns '0' '0' '0' 00
5 ns '0' '1' '0' 01
10 ns '1' '1' '0' 10
15 ns '1' '1' '1' 11
20 ns '0' '1' '1' 10
y7
'0'
'0'
'0'
'1'
'0'
285
y6
'0'
'0'
'1'
'0'
'0'
y5
'0'
'0'
'0'
'0'
'0'
y4
'0'
'0'
'0'
'0'
'0'
y3
'0'
'0'
'0'
'0'
'1'
y2
'0'
'1'
'0'
'0'
'0'
y1
'0'
'0'
'0'
'0'
'0'
y0
'1'
'0'
'0'
'0'
'0'
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 10 Design Solutions
10.E
BCD(0)
BCD(1)
BCD(2)
Seven(0) = X1
16 x 7
ROM
BCD(3)
Seven(1) = X2
Seven(2) = X3
Seven(3) = X4
Seven(4) = X5
Seven(5) = X6
Seven(6) = X7
Test Sequence: BCD = 0000, 0001, 1000, 1001.
Command Sequence:
force bcd 0000
run 5ns
force bcd 0001
run 5ns
force bcd 1000
run 5ns
force bcd 1001
run 5ns
library bitlib;
use bitlib.bit_pack.all;
entity rom is
port (bcd : in bit_vector(3 downto 0);
seven : out bit_vector(6 downto 0));
end rom;
architecture eqn of rom is
type rom16_7 is array (0 to 15) of bit_vector (6
downto 0);
constant rom1 : rom16_7 := (“0111111”, “0000110”,
“1011011”, “1001111”, “1100110”, “1101101”,
“1111101”, “0000111”, “1111111”, “1101111”, others
=> “0000000”);
signal index : integer range 0 to 15;
begin
index <= vec2int(bcd);
seven <= rom1(index);
end eqn;
Output (from DirectVHDL):
Time bcd seven index
0 ns 0000 3f
0
5 ns 0001 6
1
10 ns 1000 7f
8
15 ns 1001 6f
9
286
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 10 Design Solutions
10.F
y0
A
B
C
3 - to - 8
line
decoder
y1
y2
X1
y3
y4
Output
y5
y6
y7
X2
entity decoder is
port (a, b, c : in bit;
y0, y1, y2, y3, y4, y5, y6, y7 : out bit);
end decoder;
architecture eqn of decoder is
begin
y0 <= not a and not b and not c;
y1 <= not a and not b and c;
y2 <= not a and b and not c;
y3 <= not a and b and c;
y4 <= a and not b and not c;
y5 <= a and not b and c;
y6 <= a and b and not c;
y7 <= a and b and c;
end eqn;
-- Code for the main module
entity main is
port (a, b, c : in bit;
output : out bit);
end main;
architecture eqn of main is
component decoder is
port (a, b, c : in bit;
y0, y1, y2, y3, y4, y5, y6, y7 : out bit);
end component;
signal y0, y1, y2, y3, y4, y5, y6, y7 : bit;
signal x1, x2 : bit;
begin
d1 : decoder port map(a, b, c, y0, y1, y2, y3, y4, y5,
y6, y7);
x1 <= y0 or y1 or y2;
x2 <= y5 or y6 or y7;
output <= x1 or x2;
end eqn;
Output (from DirectVHDL):
Time
a
b
c output
0 ns '0' '0' '0' '1'
5 ns '1' '0' '0' '0'
10 ns '1' '0' '1' '1'
15 ns '0' '0' '1' '1'
20 ns '0' '1' '1' '0'
y7
'0'
'0'
'0'
'0'
'0'
287
y6
'0'
'0'
'0'
'0'
'0'
y5
'0'
'0'
'1'
'0'
'0'
Test Sequence:
a b c = 0 0 0, 1 0 0, 1 0 1, 0 0 1, 0 1 1.
Command Sequence:
force a 0
force b 0
force c 0
run 5ns
force a 1
run 5ns
force c 1
run 5ns
force a 0
run 5ns
force b 1
run 5ns
y4
'0'
'1'
'0'
'0'
'0'
y3
'0'
'0'
'0'
'0'
'1'
y2
'0'
'0'
'0'
'0'
'0'
y1
'0'
'0'
'0'
'1'
'0'
y0
'1'
'0'
'0'
'0'
'0'
x2
'0'
'0'
'1'
'0'
'0'
x1
'1'
'0'
'0'
'1'
'0'
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 10 Design Solutions
10.G
x
y
bin
D
D2
D3
x'
y
bout
x'
bin
bout
y
bin
FS3
X 3 Y3
-- Code for the full subtracter
entity sub1 is
port (X, Y, bin : in bit;
D, bout : out bit);
end sub1;
architecture eqn of sub1 is
begin
D <= X xor Y xor bin after 5 ns;
bout <= (not X and bin) or (not X and Y) or (bin and
Y) after 5 ns;
end eqn;
-- Code for the 4 bit subtracter
entity sub4 is
port (X, Y : in bit_vector(3 downto 0);
bin : in bit;
D : out bit_vector(3 downto 0);
bout : out bit);
end sub4;
architecture eqn of sub4 is
component sub1 is
port (X, Y, bin : in bit;
D, bout : out bit);
end component;
signal b : bit_vector(3 downto 1);
begin
FS0 : sub1 port map (X(0), y(0), bin, D(0), b(1));
FS1 : sub1 port map (X(1), y(1), b(1), D(1), b(2));
FS2 : sub1 port map (X(2), y(2), b(2), D(2), b(3));
FS3 : sub1 port map (X(3), y(3), b(3), D(3), bout);
end eqn;
288
b3
FS2
D0
D1
b2
X 2 Y2
FS1
b1
X 1 Y1
FS0
b in
X 0 Y0
Test Sequence: 1100-0101, 0110-1011
Command Sequence:
force X 1100
force Y 0101
force bin 0
run 25ns
force X 0110
force Y 1011
run 25ns
Output (from DirectVHDL):
Time X
Y
bin
0 ns 1100 0101 '0'
5 ns 1100 0101 '0'
10 ns 1100 0101 '0'
15 ns 1100 0101 '0'
20 ns 1100 0101 '0'
25 ns 0110 1011 '0'
30 ns 0110 1011 '0'
35 ns 0110 1011 '0'
D
0000
1001
1011
1111
0111
0111
0011
1011
bout
'0'
'0'
'0'
'0'
'0'
'0'
'1'
'1'
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
b
000
001
011
111
111
111
011
011
Unit 10 Design Solutions
10.H
D
11
Cout =D(10)
Sum=D(9 downto 0)
10-bit Adder
10
10
"00"&C
L2
L1
8-bit Shifter
0
8
8-bit Shifter
0
8
C
Test Sequence: C = 10100101, 11111111
Command Sequence:
force C 10100101
run 10ns
force C 11111111
run 10ns
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity shifter is
port (Rin : in std_logic;
A : in std_logic_vector(7 downto 0);
B : out std_logic_vector(7 downto 0);
Lout : out std_logic);
end shifter;
architecture Behavioral of shifter is
begin
B(0) <= Rin;
B(7 downto 1) <= A(6 downto 0);
Lout <= A(7);
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mult3 is
port (C : in std_logic_vector(7 downto 0);
D : out std_logic_vector(10 downto 0));
end mult3;
architecture Behavioral of mult3 is
component shifter
port (Rin : in std_logic;
A : in std_logic_vector(7 downto 0);
B : out std_logic_vector(7 downto 0);
Lout : out std_logic);
end component;
signal E, F : std_logic_vector(7 downto 0);
signal L1, L2 : std_logic;
begin
Shifter1 : shifter port map('0', C, E, L1);
Shifter2 : shifter port map('0', E, F, L2);
D <= ('0' & L1 & L2 & F) + C;
end Behavioral;
Output (from DirectVHDL):
Time
0 ns
10 ns
C
D
F
E
L2 L1
10100101 01100111001 10010100 01001010 '0' '1'
11111111 10011111011 11111100 11111110 '1' '1'
289
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 10 Design Solutions
10.I
Y(0:3)
Y(4:7)
4
4
4-to-2
priority
encoder
a1
b1
c1
a2
4-to-2
b
priority 2
encoder c2
b
d
c
a
Test Sequence: Y = 00000000, 10000000,
11000000, ... , 11111111
Command Sequence:
force y 00000000
run 5ns
force y 10000000
run 5ns
force y 11000000
run 5ns
force y 11100000
run 5ns
force y 11110000
run 5ns
force y 11111000
run 5ns
force y 11111100
run 5ns
force y 11111110
run 5ns
force y 11111111
run 5ns
Output (from DirectVHDL):
Time y
a
b
0 ns 00000000 '0' '0'
5 ns 10000000 '0' '0'
10 ns 11000000 '0' '0'
15 ns 11100000 '0' '1'
20 ns 11110000 '0' '1'
25 ns 11111000 '1' '0'
30 ns 11111100 '1' '0'
35 ns 11111110 '1' '1'
40 ns 11111111 '1' '1'
c
'0'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
290
-- Code for the 4 to 2 priority encoder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity four_to_two_pe is
port (y : in std_logic_vector(0 to 3);
a1, b1, c1 : out std_logic);
end four_to_two_pe;
architecture equation of four_to_two_pe is
begin
a1 <= y(2) or y(3);
b1 <= y(3) or (y(1) and not y(2));
c1 <= y(0) or y(1) or y(2) or y(3);
end equation;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Code for the 8 to 3 priority encoder
entity eight_to_three_pe is
port (y : in std_logic_vector(0 to 7);
a, b, c, d : out std_logic);
end eight_to_three_pe;
architecture Structure of eight_to_three_pe is
component four_to_two_pe
port (y : in std_logic_vector(0 to 3);
a1, b1, c1 : out std_logic);
end component;
signal a1, b1, c1, a2, b2, c2 : std_logic;
begin
four_to_two_pe1 : four_to_two_pe
port map (y(0 to 3), a1, b1, c1);
four_to_two_pe2 : four_to_two_pe
port map (y(4 to 7), a2, b2, c2);
a <= c2;
b <= a1 when c2 = '0' else a2;
c <= b1 when c2 = '0' else b2;
d <= y(0) or y(1) or y(2) or y(3) or y(4) or y(5) or
y(6) or y(7);
-- d <= '0' when y=0 else '1'; (alternate solution for d)
end Structure;
d
'0'
'1'
'1'
'1'
'1'
'1'
'1'
'1'
'1'
c2
'0'
'0'
'0'
'0'
'0'
'1'
'1'
'1'
'1'
b2
'0'
'0'
'0'
'0'
'0'
'0'
'1'
'0'
'1'
a2
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'1'
'1'
c1
'0'
'1'
'1'
'1'
'1'
'1'
'1'
'1'
'1'
b1
'0'
'0'
'1'
'0'
'1'
'1'
'1'
'1'
'1'
a1
'0'
'0'
'0'
'1'
'1'
'1'
'1'
'1'
'1'
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 10 Design Solutions
10.J
bout
c out
D(7:4)
D(3:0)
4-bit
adder
4-bit
adder
A(7:4) B(7:4)
A(3:0) B(3:0)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity adder4 is
port (X, Y : in std_logic_vector(3 downto 0);
in : in std_logic;
S : out std_logic_vector(3 downto 0);
cout : out std_logic);
end entity;
architecture addeqn of adder4 is
signal sum : std_logic_vector(4 downto 0);
begin
sum <= '0' & X + Y + cin;
S <= sum(3 downto 0);
cout <= sum(4);
end addeqn;
1
Command Sequence:
force A 11011011
force B 01110110
run 10ns
force A 01110110
force B 11011011
run 10ns
Test Sequence: 11011011-01110110,
01110110-11011011
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity subtracter8 is
port(A, B : in std_logic_vector(7 downto 0);
D : out std_logic_vector(7 downto 0);
bout : out std_logic);
end entity;
architecture subeqn of subtracter8 is
component adder4
port (X, Y : in std_logic_vector(3 downto 0);
cin : in std_logic;
S : out std_logic_vector(3 downto 0);
cout : out std_logic);
end component;
signal b1, cout : std_logic;
signal notB : std_logic_vector(7 downto 0);
signal D1, D2 : std_logic_vector(3 downto 0);
begin
notB <= not B;
ADDERA : adder4 port map(A(3 downto 0),
notB(3 downto 0), '1', D2, b1);
ADDERB : adder4 port map(A(7 downto 4),
notB(7 downto 4), b1, D1,cout);
D <= D1 & D2;
bout <= not cout;
end subeqn;
Output (from DirectVHDL):
Time A
B
D
bout bout1 b1 notB
D2
D1
0 ns 11011011 01110110 01100101 '0' '1'
'1' 10001001 0101 0110
10 ns 01110110 11011011 10011011 '1' '0'
'0' 00100100 1011 1001
291
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 10 Design Solutions
10.K
Test Sequence: s1 s2 = 00, 01, 10, 11
A
S1
S2
2-to-4
line
decoder
B
C
D
6
6
6
E
6
6
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tsb is
port (A : in std_logic_vector(5 downto 0);
B : in std_logic;
Z : out std_logic_vector(5 downto 0));
end tsb;
architecture Behavioral of tsb is
begin
Z <= A when B = '1' else “ZZZZZZ”;
end Behavioral;
Output (from DirectVHDL):
Time A
B
0 ns 000111 101010
5 ns 000111 101010
10 ns 000111 101010
15 ns 000111 101010
C
111000
111000
111000
111000
292
Command Sequence:
force a 000111
force b 101010
force c 111000
force d 010101
force s1 0
force s2 0
run 5ns
force s2 1
run 5ns
force s1 1
force s2 0
run 5ns
force s2 1
run 5ns
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pkc is
port (A, B, C, D : in std_logic_vector(5 downto 0);
E : out std_logic_vector(5 downto 0);
s1, s2 : in std_logic);
end pkc;
architecture Behavioral of pkc is
component tsb
port (A : in std_logic_vector(5 downto 0);
B : in std_logic;
Z : out std_logic_vector(5 downto 0));
end component;
signal internal : std_logic_vector (3 downto 0);
begin
internal(0) <= '1' when (s1 = '0' and s2='0') else '0';
internal(1) <= '1' when (s1 = '0' and s2='1') else '0';
internal(2) <= '1' when (s1 = '1' and s2='0') else '0';
internal(3) <= '1' when (s1 = '1' and s2='1') else '0';
tsb0 : tsb port map(A, internal(0), E);
tsb1 : tsb port map(B, internal(1), E);
tsb2 : tsb port map(C, internal(2), E);
tsb3 : tsb port map(D, internal(3), E);
end Behavioral;
D
010101
010101
010101
010101
E
000111
101010
111000
010101
s1
'0'
'0'
'1'
'1'
s2
'0'
'1'
'0'
'1'
internal
0001
0010
0100
1000
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 10 Design Solutions
10.L
Count
4
c out
3
Sum
3-bit adder
B
ROM1
3
3
C
ROM2
3
A(11:8)
D
3
ROM3
3
3
A(7:4)
A(3:0)
Test Sequence: A = 111111111111,
010110101101, 100001011100
Command Sequence:
force A 111111111111
run 5ns
force A 010110101101
run 5ns
force A 100001011100
run 5ns
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ROM4_3 is
port (ROMin : in std_logic_vector(0 to 3);
ROMout : out std_logic_vector(0 to 2));
end ROM4_3;
architecture Behavioral of ROM4_3 is
type ROM16X3 is array (0 to 15) of std_logic_
vector(0 to 2);
constant ROM1: ROM16X3 := (“000”, “001”, “001”,
“010”, “001”, “010”, “010”, “011”, “001”, “010”, “010”,
“011”, “010”, “011”, “011”, “100”);
signal index : integer range 0 to 15;
begin
index <= conv_integer(ROMin);
ROMout <= ROM1(index);
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lab10l_soln is
port (A : in std_logic_vector(11 downto 0);
count : out std_logic_vector(3 downto 0));
end lab10l_soln;
architecture Behavioral of lab10l_soln is
component ROM4_3
port (ROMin: in std_logic_vector(0 to 3);
ROMout: out std_logic_vector(0 to 2));
end component;
signal B, C, D : std_logic_vector(0 to 2);
begin
RO1 : ROM4_3 port map (A(11 downto 8), B);
RO2 : ROM4_3 port map (A(7 downto 4), C);
RO3 : ROM4_3 port map (A(3 downto 0), D);
count <= “0” & B + C + D;
end Behavioral;
Output (from DirectVHDL):
Time
A
0 ns
111111111111
5 ns
010110101101
10 ns 100001011100
293
COUNT
1100
0111
0101
D
100
011
010
C
100
010
010
b
100
010
001
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 10 Design Solutions
10.M
bo
Di(2)
Di(1)
Di(0)
Full
Subtracter
Full
Subtracter
Full
Subtracter
M(2)
N(2)
M(1)
N(1)
M(0)
Test Sequence: 110-010 w/ borrow input of 1,
011-101 w/ borrow input of 0
bi
N(0)
library bitlib;
use bitlib.bit_pack.all;
entity FSub is
port (X, Y, Bin : in bit;
Bout, Dout : out bit);
end FSub;
architecture Behavioral of FSub is
type ROM8x2 is array ( 0 to 7 ) of bit_vector(0 to 1 );
constant ROM1 : ROM8x2 := (“00”, “11”, “11”, “10”,
“01”, “00”, “00”, “11”);
signal index : integer range 0 to 7;
signal F : bit_vector(0 to 1);
begin
index <= vec2int(X&Y&Bin);
F <= ROM1(index);
Bout <= F(1);
Dout <= F(0);
end Behavioral;
library bitlib;
use bitlib.bit_pack.all;
entity lab10m is
port (M, N : bit_vector (2 downto 0);
BI : in bit;
BO : out bit;
DI : out bit_vector(2 downto 0));
end lab10m;
architecture arch of lab10m is
component FSub
port (X, Y, Bin : in bit;
Bout, Dout : out bit);
end component;
signal C : bit_vector (2 downto 1);
begin
SB0 : FSub port map (M(0), N(0), BI, C(1), DI(0));
SB1 : FSub port map (M(1), N(1), C(1), C(2), DI(1));
SB2 : FSub port map (M(2), N(2), C(2), BO, DI(2));
end arch;
294
Command Sequence:
force M 110
force N 010
force BI 1
run 5ns
force M 011
force N 101
force BI 0
run 5ns
Output (from DirectVHDL):
Time M
N
BI BO DI C
0 ns 110 010 '1' '0' 011 11
5 ns 011 101 '0' '1' 110 00
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 10 Design Solutions
10.N
a
a2
4-to-2
Y(4:7)
b
2
priority
En1
encoder c 2
4
main_enable
Y(0:3)
b
c
d
a1
4-to-2
b
priority 1
En2
encoder c1
4
Test Sequence: Y = 00000000, 10000000,
11000000, ..., 11111111
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fourtwoencoder is
port(y : in std_logic_vector(0 to 3);
enable : in std_logic;
a1, b1, c1 : out std_logic);
end entity;
architecture fourtwoarch of fourtwoencoder is
begin
a1 <= enable and (y(2) or y(3));
b1 <= enable and (y(3) or (y(1) and not y(2)));
c1 <= enable and (y(0) or y(1) or y(2) or y(3));
end fourtwoarch;
architecture eightthreearch of
eightthreeencoder is
component fourtwoencoder
port(y: in std_logic_vector(0 to 3);
enable: in std_logic;
a1,b1,c1: out std_logic);
end component;
signal a1,b1,c1,x,a2,b2,c2: std_logic;
begin
x <= not c2;
ENCA: fourtwoencoder port map(y(0 to
3),x,a1,b1,c1);
ENCB: fourtwoencoder port map(y(4 to 7),
main_enable,a2,b2,c2);
a <= c2;
b <= a1 or a2;
c <= b1 or b2;
d <= c1 or c2;
end eightthreearch;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity eightthreeencoder is
port(y: in std_logic_vector(0 to 7);
main_enable: in std_logic;
a,b,c,d: out std_logic);
end entity;
Output (from DirectVHDL):
Time y
main_enable
0 ns 00000000 '1'
5 ns 10000000 '1'
10 ns 11000000 '1'
15 ns 11100000 '1'
20 ns 11110000 '1'
25 ns 11111000 '1'
30 ns 11111100 '1'
35 ns 11111110 '1'
40 ns 11111111 '1'
a
'0'
'0'
'0'
'0'
'0'
'1'
'1'
'1'
'1'
b
'0'
'0'
'0'
'1'
'1'
'0'
'0'
'1'
'1'
295
c
'0'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
Command Sequence:
force main_enable 1
force y 00000000
run 5ns
force y 10000000
run 5ns
force y 11000000
run 5ns
force y 11100000
run 5ns
force y 11110000
run 5ns
force y 11111000
run 5ns
force y 11111100
run 5ns
force y 11111110
run 5ns
force y 11111111
run 5ns
d
'0'
'1'
'1'
'1'
'1'
'1'
'1'
'1'
'1'
c2
'0'
'0'
'0'
'0'
'0'
'1'
'1'
'1'
'1'
b2
'0'
'0'
'0'
'0'
'0'
'0'
'1'
'0'
'1'
a2
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'1'
'1'
x
'1'
'1'
'1'
'1'
'1'
'0'
'0'
'0'
'0'
c1
'0'
'1'
'1'
'1'
'1'
'0'
'0'
'0'
'0'
b1
'0'
'0'
'1'
'0'
'1'
'0'
'0'
'0'
'0'
a1
'0'
'0'
'0'
'1'
'1'
'0'
'0'
'0'
'0'
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 10 Design Solutions
296
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 12 Design Solutions
Solutions to Unit 12 Design and Simulation Problems
Problem 12.10 is a simulation exercise where students are required to design and simulate a counter. The problem has
14 parts of equal difficulty, so that different students can be assigned different parts. We ask students to do the following
preparation and lab work:
1.
Read Unit 12 in the course textbook, completing Study Guide parts 1 through 5.
2.
Read Section 2.2, “Simulating Flip-Flops with SimUaid” in the SimUaid User’s Guide on the CD.
3.
Answer the following questions:
(a) How can a D flip-flop be set to logic 0 without using the clock input?
(b) How can it be set to logic 1 without using the clock input?
(c) Explain the term Asynchronous Input.
4.
Design a counter that counts in the sequence assigned to you. Use D flip-flops, NAND gates, and inverters.
Draw your circuit explicitly showing all connections to gate and flip-flop inputs. Explicitly means that you
should draw in all wires, don’t just label the inputs and outputs. Show switches connected to the Preset
and Clear inputs of the flip-flops. Use one switch for all clears and a separate switch for each preset.
5.
Explain in detail how you can set the flip-flops to the two missing states not in the prescribed counting sequence
without using the clock input. Your explanation should describe each change you make to a switch position.
After you have cleared or set a flip-flop, in what position (0 or 1) should you leave the switches?
6.
After a proctor has approved your preparation, go to one of the computer labs and work through the exercise
for simulating a D flip-flop using SimUaid, found in Section 2.2 “Simulating Flip Flops with SimUaid” of the
SimUaid User’s Guide on the CD.
7.
Enter your circuit from part 4 into SimUaid. In the space below, draw the complete state graph determined
experimentally using your SimUaid circuit. Include the 6 states in the counting sequence and the 2 states not in
the sequence.
The complete solution for problem 12.10(a) follows. The solutions for parts (b) through (n) are similar, so only the state
table, D flip-flop input equations (derived using Karnaugh maps), and the state graphs determined in part 6 are given.
The D flip-flop input equations can also be derived using LogicAid by entering a state table with zero input variables.
12.10(a)
C B A
0 0 0
C+ B+ A+
0 0 1
0
0
0
1
1
1
1
0 1 1
0 0 0
1 0 1
X X X
1 1 1
X X X
0 1 0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
B A
C
1
00
0
X
1
01
1
1
0
11
0
X
10
1
00
0
X
01
0
11
10
DC = C'B A + C B'
297
B A
C
0
0
C
0
1
00
1
X
1
01
1
1
0
1
11
1
0
0
X
10
0
X
DB = B'A + C
B A
DA = B' + C'A
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 12 Design Solutions
12.10(a)
(cont.)
1
0
PREC
1
D
R
CLK
1
0
S
Q
Q'
C
C'
0
1
0
PREB
1
D
S
R
1
0
Q'
B
B'
PREA
1
D
1
0
Q
S
R
CLR
Q
Q'
A
A'
1
State graph determined experimentally:
100
000
12.10(b) C B A
0 0 0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
C+ B+ A+
0 1 1
X X X
1 1 0
1 0 1
X X X
1 1 1
0 0 0
0 1 0
001
011
101
*DC = C'B + B'A
*DB = C'A' + C A
110
111
010
DC = C'B + C B'
*DA = B' + C'A
Circuit based on equations marked * was used to obtain the following
state graph
100
000
298
001
011
101
111
010
110
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 12 Design Solutions
12.10(c)
C B A
0 0 0
C+ B+ A+
1 1 0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0 0 0
X X X
X X X
1 0 1
0 0 1
1 1 1
1 0 0
12.10(d) C B A
0 0 0
C+ B+ A+
1 0 0
0
0
0
1
1
1
1
12.10(e)
12.10(f)
0
1
1
0
0
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1 1 0
X X X
X X X
0 0 1
1 1 1
1 0 1
0 0 0
C B A
0 0 0
C+ B+ A+
0 1 0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
X X X
1 1 1
1 1 0
X X X
0 1 1
0 0 0
1 0 1
C B A
0 0 0
C+ B+ A+
1 0 0
0
0
0
1
1
1
1
1 1 1
X X X
X X X
0 0 1
0 0 0
1 0 1
1 1 0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
*DC = A' + B
*DA = C B' + B A'
*DB = C'A' + B A'
DA = C B' + C A'
Circuit based on equations marked * was used to obtain the following
state graph
011
010
000
110
111
100
*DC = C' + B'A + B A'
*DA = C B' + B A' 101
001
*DB = B'A
DA = C B' + C A'
Circuit based on equations marked * was used to obtain the following
state graph
011
000
010
100
DC = C'B + B A DA = C'B A' + C A
001
110
101
111
101
011
110
110
101
DB = C' + B'
State graph determined experimentally:
100
001
000
010
111
DC = C' + B DA = C'A + C A'
DB = C'A + B A
State graph determined experimentally:
010
000
299
011
100
001
111
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 12 Design Solutions
12.10(g)
C B A
0 0 0
C+ B+ A+
0 1 0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
1 1 0
1 1 1
X X X
X X X
0 0 1
0 0 0
1 0 1
12.10(h) C B A
0 0 0
C+ B+ A+
1 0 1
0
0
0
1
1
1
1
12.10(i)
12.10(j)
0
1
1
0
0
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1 1 0
0 1 1
0 0 1
X X X
0 1 0
0 0 0
X X X
C B A
0 0 0
C+ B+ A+
1 0 0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
1 1 0
0 0 1
X X X
0 1 0
X X X
1 1 1
0 0 0
C B A
0 0 0
C+ B+ A+
0 0 1
0
0
0
1
1
1
1
1 1 1
1 1 0
0 0 0
X X X
X X X
0 1 1
0 1 0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
DC = C'A + C'B + B A DA = C'B + C A
DB = C'
State graph determined experimentally:
100
011
000
010
101
111
*DC = C'B' *DA = C'B + C'A'
DA = C'A' + B A
001
110
*DB = B'A + C'B A'
DA = C'B + B'A'
Circuit based on equations marked * was used to obtain the following state
graph
100
111
000
010
101
*DC = C'B' + C B A' DB = C A' + B'A 011
001
110
*DB = C A' + C'A
*DA = B A'
Circuit based on equations marked * was used to obtain the following
state graph
101
011
000
100
010
DC = B'A + C'B A' DA = B' + C A'
001
110
111
DB = B'A + B A' + C
State graph determined experimentally:
101
000
300
001
100
111
010
110
011
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 12 Design Solutions
12.10(k) C B A
0 0 0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
1 0 1
0 0 1
X X X
0 1 0
1 1 1
X X X
0 0 0
C B A
0 0 0
C+ B+ A+
0 1 1
0
0
0
1
1
1
1
1
0
1
0
1
0
1
1 0 0
X X X
1 1 1
0 0 0
X X X
0 0 1
1 1 0
12.10(m) C B A
0 0 0
C+ B+ A+
1 0 0
12.10(l)
0
0
0
1
1
1
1
0
1
1
0
0
1
1
C+ B+ A+
1 0 0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
X X X
0 1 1
0 0 0
1 1 1
X X X
0 1 0
1 1 0
12.10(n) C B A
0 0 0
C+ B+ A+
0 1 1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
X X X
1 0 0
1 1 1
0 0 0
X X X
0 1 0
1 1 0
*DC = C'B' + B'A *DA = B'A + B A' *DB = C B'
DA = B'A + C'B
Circuit based on equations marked * was used to obtain the following
state graph
011
110
000
100
DC = A DA = C'A' + C'B + B A'
010
001
111
101
DB = C'A' + B A
State graph determined experimentally:
010
000
101
011
111
DC = B' + C A DA = C'B A' + C B'
110
001
100
010
011
DB = B A' + C
State graph determined experimentally:
001
000
101
100
111
DC = C'B + A DA = C'B' + C'A
110
DB = C'B' + A + C B
State graph determined experimentally:
001
000
301
011
101
111
110
010
100
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 12 Design Solutions
302
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 16 Design Solutions
Solutions to Unit 16 Design and Simulation Problems
Problems 16.1 through 16.14 are Mealy sequential circuit design and simulation problems. These problems are of
approximately equal difficulty so that different students can be assigned different problems. In this exercise, students
first complete their designs using gates and D flip-flops. They then test their designs using the SimUaid simulator.
Next, they convert their design to VHDL, synthesize the VHDL code, and download it to a CPLD or FPGA board to
test their design using hardware.
We ask our students to use the following procedure:
(1) Derive a state graph and state table for the assigned problem. Reduce the table to a minimum number of
states. Check the reduced table using the LogicAid state table checker. Encoded solution files are found in
the Lab16 folder on the CD.
(2) Make a state assignment using the guidelines. Derive the transition table, and then derive the D flip-flop
input equations and output equation(s) using Karnaugh maps.
(3) Use LogicAid to derive the same equations and verify that the equations derived in step (2) are correct.
Then derive one or more sets of equations for different state assignments using LogicAid.
(4) Design the circuit using NAND gates, NOR gates, and three D flip-flops. Choose the equations from step
(3) that lead to the lowest cost circuit, and make sure that it meets the specifications.
(5) Input the logic circuit into SimUaid using switches for the X input, clock, reset, and preset inputs. Use
probes for the Z output and flip-flop outputs. Use SimUaid to verify the transition table by presetting the
flip-flops to each state and observing the next state and outputs. Then use SimUaid to manually test the
operation of the circuit by applying the required test sequences and observing the outputs, being very careful
to read the outputs at the proper time.
(6) Replace the clock and X input switches with a clock module and an input device. Program the input device
to produce the proper test waveform. Display the simulator timing waveforms for clock, X, Z, and the flipflop outputs. Print the waveforms and mark the times to read the Z output. Verify that the output sequence
is correct.
(7) Replace the X and reset switches and the Z probe with a checker module (found on the SimUaid device
menu), run the checker and verify that the circuit passes the test. The checker automatically generates input
sequences and verifies that the output sequences are correct. Test files to use with the checker are provided
in the SimUaid/Checkers directory on the CD.
After a proctor has verified that your design is correct and meets specifications, you will implement your design in
hardware using the following steps:
(6) Use SimUaid to generate a VHDL file from your circuit file.
(7) Use the Xilinx ISE software to synthesize the circuit from the VHDL file.
(8) Generate a programming file and download it to the CPLD or FPGA on the hardware board.
(9) Test your circuit manually using the switches on the hardware board for the clock, reset, and X inputs. Use
the same test sequence as you did in step (5).
(10) If you have an automatic hardware tester available, connect it to the circuit board and verify that your circuit
passes.
The solution for 16.1 includes the complete SimUaid circuit and the VHDL code generated by SimUaid. The other
solutions only give the logic equations for the flip-flop inputs and for Z.
303
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 16 Design Solutions
16.1
S0
S1
S2
S3
S4
S5
1
0
S3
S4
S3
S3
S4
S2
S2
S5
S2
S2
1
0
X'
X
0
0
0
1
1
From Q+ maps:
A+ = X'BC + XA'BC'
B+ = X + C + B
C+ = B'C' + X
Z = X'A
BC
1
D
S
R
0
A
Q
A'
Q'
CLK
1
1
0
PreB
1
X'
C'
B'
D
S
R
1
0
B'
C'
1
0
0
0
0
0
0
PreA
1
1
0
Assignment by guidelines:

I.
(1, 3, 4) (2, 5) (0, 1, 2, 4, 5)



II. (1, 2)
(2, 3)2 (2, 4)2 (3, 5)


III. (0, 1, 2, 3) (4, 5)
X=0 1 X=0 1
S1
S2
0
0
0
Clear
01
S1
11
S2
S5
10
S3
S4
B'
Q'
See p. 287 for VHDL code
generated by SimUaid.
C
0
Q
Si mUai
d:Uai Unt
t l ied3
C'
Si m
d: iUnt
t l ed2
R
WS08WS08-335
335
Q'
M
odif fi ied:
ed: 0
M
odi
Z
1
0
X'
A
Test sequences:
a)
X = 001101001010100010010010
Z = 000000010100001001101101
b)
X=
Z=
X 10 ns
(20 ns./div)
CLK
X
A
B
C
Z
To generate waveforms, replace the X
switch with
and the CLK switch
with
The input device should be programmed to
generate the corresponding waveform.
110011001010100101010010
000100010100001010000101
10
20
30
40
50
60
70
80
90
100
110
1
0
0
0
0
0
304
1
S0
Q
1
S
0
00
B
PreC
D
X'
A
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 16 Design Solutions
16.2
S0
S1
S2
S3
S4
S5
X=0 1 X=0 1
S2
S1
0
0
S2
S2
S5
S2
S2
S3
S4
S3
S3
S4
0
0
0
0
0
0
0
0
1
1
Guidelines and state assignments are the same as for16.1
Flip-flop and output equations and logic circuit are the same
as 16.1, except interchange X and X' throughout
Test sequences
16.3
X
t3
0
0
0
0
0
1
1
1
1
1
S0
S1
S2
S3
S4
S5
S6
t2
0
1
1
1
1
0
0
0
0
1
t1
1
0
0
1
1
0
0
1
1
0
t0
1
0
1
0
1
0
1
0
1
0
t3
0
0
0
0
0
0
0
0
1
1
Z
t2
0
0
0
0
1
1
1
1
0
0
t1
0
0
1
1
0
0
1
1
0
0
a)
X=
Z=
110010110101011101101101
000000010100001001101101
b)
X=
Z=
001100110101011010101101
000100010100001010000101
t0
0
1
0
1
0
1
0
1
0
1
X=0 1 X=0 1
S2
S1
1
0
S4
S4
S5
S6
S0
-
S3
S4
S5
S5
S0
S0
1
0
0
1
0
-
0
1
1
0
1
0
A
BC
Assignment by guidelines:



I.
(1, 2)
(5, 6) (3, 4)



II.
(1, 2)
(3, 4) (5, 6)


III.
(0, 1, 4) (2, 3, 5)
0
1
00
S0
01
S1
S2
11
S4
S3
10
S6
S5
From Q+ maps:
A+ = XA'C + ABC + X'A'C'
or A+ = XA'C + ABC + X'B'C'
Test sequence:
B+ = C
C+ = B'
Z = X'A' + XA
X=
1100 0010 1010
Z=
0000 1000 0100 1100 0010 1010 0110 1110 0001 1001
305
0110 1110 0001 1001 0101 1101 0011
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 16 Design Solutions
16.4
t3
0
0
0
0
0
0
0
0
1
1
X
t2 t1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0 0
t0
0
1
0
1
0
1
0
1
0
1
Z
t2
1
1
0
0
0
0
1
1
1
1
t3
0
0
1
1
1
1
1
1
1
1
S0
S1
S2
S3
S4
S5
t1
1
1
0
0
1
1
0
0
1
1
t0
0
1
0
1
0
1
0
1
0
1
00
S3
S5
S5
S0
-
1
1
0
0
1
0
0
1
1
-
A+ = X'B' + A'C + A'B' + XAB
B+ = C
C+ = B'
S1
11
S3
S2
10
S4
S5
X=
0000 1000 0100
1100 0010 1010 0110 1110 0001 1001
Z=
0110 1110 0001 1001 0101 1101 0011 1011 0111 1111
S0
S1
S2
S3
S4
S5
Assignment by guidelines:




I.
(0, 1, 4) (2, 3, 5) (0, 3, 5) (1, 4)


II.
(1, 5) (1, 2)2 (3, 4) (4, 5)2
From Q+ maps:
=X
S0
Z = XA' + X'A
16.5
A+
1
Assignment by guidelines:


I.
(4, 5)
(2, 3)


II.
(2, 3)
(4, 5)


III.
(0, 3, 4) (1, 2, 5)
From Q+ maps:
Test sequence:
0
01
X=0 1 X=0 1
S1
S1
0
1
S2
S4
S5
S0
S0
A
BC
B+
C+ = X'A' + A'B
= A' + C' + X'
S1
S4
S4
S1
S4
BC
S2
S3
S5
S2
S5
A
0
0
1
0
0
0
0
0
1
0
0
1
S0
S3
11
S1
S2
10
S4
S5
00
01
Z = X'AB' + XA'BC'
Test sequences: a)
X=
Z=
0011011110010100
0000110000000100
b)
X=
Z=
1010001111011000
0010000000010100
306
X=0 1 X=0 1
S1
S5
0
0
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 16 Design Solutions
16.6
0
S0
1
0
0
0
0
S1
0
0
0
S2
0
1
0
S4
1
1
1
0
0
S0
S3
S1
S2
S3
S4
S5
1
0
X=0 1 X=0 1
S1
S4
0
0
S1
S3
S1
S1
S5
0
S5
0
0
0
0
0
0
0
0
1
0
0
A
0
1
00
S0
S2
01
S1
S4
11
S3
S5
10
Assignment by guidelines:



I.
(0, 1, 3, 4) (1, 3) (2, 4, 5)


II.
(1, 4) (1, 2)2 (3, 5) (1, 5)

III.
(0, 1, 2, 4, 5)
1
0, 0
From Q+ maps:
C+ = X' + A + C' Z = XA'B
A+ = X + AB B+ = AC' + XA + AB
Test sequences: a)
X=
Z=
010100010110
000100000100
b)
X=
Z=
101010110101
000010100000
16.7
0
0
S2
S0
S0
1
0
1
0
0
1
0
1
S2
S5
S2
S5
S5
B C
1
0
S1
1
0
0
0
S1
S2
S3
S4
S5
X=0 1 X=0 1
S2
S1
0
0
S3
S4
S5
S4
S5
S3
S4
1
0
1
1
S0
S1
S0
S5
S4
0
1
0
1
0
B C
0
0
0
0
1
A
0
1
00
S0
S4
01
S1
S5
11
S3
10
S2
Assignment by guidelines:


I.
(0, 2) (1, 3) (2, 4) (3, 5)
0
0
S5
II.
0
0
III.

(2, 1) (3, 0) (4, 1) (5, 0) (4, 5)2

(0, 1, 3) (2, 4)
From Q+ maps:
A+ = A + X'B B+ = X'A'B'
C+ = X'C + XC'
Z = XAC + X'AC' + X'BC'
Test sequences: a)
X=
Z=
0110010100
0000100111
b)
X=
Z=
101111001110
000000001011
307
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 16 Design Solutions
16.8
S0
S1
S2
S3
S4
S5
X=0 1 X=0 1
S1
S5
0
0
S2
S2
S1
S1
S1
S5
S3
S4
S4
S4
0
0
0
1
0
B C
0
0
1
0
0
A
0
1
00
S0
01
S3
11
S4
S1
10
S5
S2
Assignment by guidelines:



I.
(0, 3, 4, 5) (1, 2) (0, 1) (3, 4, 5)


II.
(2, 3) (1, 4)3 (2, 5) (1, 5)

III.
(0, 1, 2, 5)
From Q+ maps:
A+ = X'
B+ = X' + A' + C
C+ = X'A' + XBC' + A'C
Test sequences: a)
X=
Z=
000100011010
000000001100
b)
X=
Z=
111001000110
000100000011
16.9
S0
S1
S2
S3
S4
S5
Z = XB'C + X'A'BC
X=0 1 X=0 1
S1
S5
0
0
S2
S2
S4
S2
S1
S5
S3
S3
S3
S5
0
0
1
1
1
0
0
0
0
1
B C
A
00
0
S0
S5
S1
01
11
1
S4
10
S3
S2
Assignment by guidelines:



I.
(0, 5) (1, 2, 4) (0, 1, 5) (2, 3, 4)




II.
(3, 4) (1, 5)2 (2, 5) (2, 3)2

III.
(0, 1, 2) (3, 4)
From Q+ maps:
A+ = A' + B' + C' + X B+ = B + X'C C+ = XB + ABC + X'B'C'
Test sequences: a)
X=
Z=
100100100011
010011011000
b)
X=
Z=
011000011011
001100000100
308
Z = X'BC + AB'C'
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 16 Design Solutions
16.10
8
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
4
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
-2 -1 8
0 0 0
0 1 1 0 1 1 0 0 0
0 1 0
1 0 0
1 1 0
0 0 1
0 1 0
1 0 0
1 1 0
0 0 0 1 1 0 1 1 1
4
0
1
0
0
0
0
1
1
1
0
2
0
0
1
1
0
0
1
1
0
0
From Q+ maps:
A+ = XB' + X'AC
Test sequence:
B+ = C
1
0
0
1
0
1
0
1
0
1
1
Assignment by guidelines:



I.
(1, 2) (3, 4) (5, 6)



II.
(1, 2) (3, 4) (5, 6)


III.
(0, 1, 3, 5) (2, 4)
C+ = B'
S0
A
0
00
S0
1
01
S1
S2
11
S3
S4
10
S5
S6
B C
X=0 1 X=0 1
S1
S2
0
1
S1
S2
S3
S4
S5
S6
S3
S4
S5
S6
S0
S0
S4
S4
S5
S5
S0
S0
0
1
0
1
0
-
Z = XA' + X'A
X=
0000 0010 1010
0110 1110 0001 1001 0101 1101 1111
Z=
0000 0010 1100 0100 1000 0001 1110 0110 1010 1001
16.11
S0
S1
S2
S3
S4
S5
S6
X=0 1 X=0 1
S1
S2
1
0
S3
S3
S5
S6
S0
S0
S3
S4
S6
S6
S0
S0
0
1
1
0
0
1
1
0
0
1
1
-
A
0
S0
1
00
01
S6
S5
11
S3
S4
10
S2
S1
B C
Assignment by guidelines:



I.
(1, 2) (5, 6) (3, 4)



II.
(1, 2) (3, 4) (5, 6)


III.
(0, 2, 3) (1, 4, 5)
From Q+ maps:
A+ = X'B'C' + XA'BC' + X'A'BC
Test sequence:
B+ = C'
C+ = B
Z = XA + X'A'
X=
0000 1000 0100 1100
0010 1010 0110 1110 0001 1001
0101
Z=
1010 0110 1110 0001 1001 0101 1101 0011 1011 0111
1111
309
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
1
0
1
0
1
0
Unit 16 Design Solutions
16.12
X
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
Z
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
S0
S1
S2
S3
S4
S5
S6
Test sequence:
C+ = B
B+ = C'
S3
S3
S5
S6
S0
S0
S3
S4
S6
S6
S0
S0
A
1
0
0
1
1
0
0
S0
1
00
01
S6
S5
11
S3
S4
10
S2
S1
B C
Assignment by guidelines:



I.
(1, 2) (5, 6) (3, 4)



II.
(1, 2) (3, 4) (5, 6)


III.
(0, 2, 3) (1, 4, 5)
From Q+ maps:
A+ = X'B'C' + XA'BC' + X'A'BC
X=0 1 X=0 1
S1
S2
0
1
0
1
1
0
0
-
Z = X'A + XA'
X=
0000 1000 0100 1100 0010 1010 0110 1110 0001 1001
Z=
0101 1001 0001 1110 0110 1010 0010 1100 0100 1000 0000
16.13
S0
S1
S2
S3
S4
S5
X=0 1 X=0 1
S1
S0
0
0
S2
S2
S4
S2
S4
S0
S3
S3
S5
S3
0
0
0
0
1
0
0
0
0
0
0101
B C
A
0
1
00
S0
S2
01
S1
S4
11
S3
10
S5
Assignment by guidelines:




I.
(1, 2, 4) (3, 5) (0, 1) (2, 3, 5)




II.
(0, 1) (0, 2) (2, 3) (3, 4)2 (2, 5)

III.
(0, 1, 2, 3, 4)
From Q+ maps:
A+ = X'C + A B+ = XA C+ = X'A'C' + XAC' + B Z = X'BC'
Test sequences: a)
X=
Z=
100100110101
000000000010
b)
X=
Z=
101000101010
000000000101
310
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 16 Design Solutions
16.14
S0
S1
S2
S3
S4
Assignment by guidelines:



I.
(0, 4) (1, 2) (3, 4)


II.
(0, 1) (2, 4) (2, 3)2 (1, 3)


III.
(0, 4) (1, 2)
X=0 1 X=0 1
S1
S0
0
0
S4
S3
S2
S1
S2
S2
S3
S3
0
0
1
0
B C
A
00
1
1
0
0
0
S0
1
S4
01
S2
11
S1
10
S3
Test sequences: a)
X=
Z=
10001101001
00001100100
b)
X=
Z=
00001010001
00000110100
From Q+ maps:
A+ = X' + A B+ = X'B' + XAC' C+ = XC + X'C' Z = XC + X'BC'
VHDL code for Problem 16.1 automatically generated by SimUaid follows. This code can be synthesized
and downloaded to a CPLD or FPGA board for testing.
-- This file has been automatically generated by SimUAid.
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library SimUAid_synthesis;
use SimUAid_synthesis.SimuAid_synthesis_pack.all;
entity lab16p1 is
port(CLK, PreA, PreB, PreC, Clear, X: in STD_LOGIC;
Z, A, B, C, X_0, CLK_0: out STD_LOGIC
);
end lab16p1;
architecture Structure of lab16p1 is
signal B_p, Vnet_0, Vnet_1, Vnet_2, Vnet_3, Vnet_4, C_p, Vnet_5, Vnet_6, Vnet_7,
X_p, Vnet_8, Vnet_9, Vnet_10, Vnet_11, Vnet_12, Vnet_13, A_p, Vnet_14, Vnet_15: STD_LOGIC;
begin
VHDL_Device_0: Dflipflop port map (CLK, Vnet_5, PreB, Clear, Vnet_3, B_p);
VHDL_Device_1: Dflipflop port map (CLK, Vnet_6, PreC, Clear, Vnet_4, C_p);
VHDL_Device_2: nand2 port map (Vnet_0, Vnet_1, Vnet_2);
VHDL_Device_3: nand4 port map (X, A_p, Vnet_3, C_p, Vnet_1);
VHDL_Device_4: nand3 port map (X_p, C_p, B_p, Vnet_5);
VHDL_Device_5: nand2 port map (Vnet_7, X_p, Vnet_6);
VHDL_Device_6: nand2 port map (B_p, C_p, Vnet_7);
VHDL_Device_7: inverter port map (X, X_p);
VHDL_Device_8: nand2 port map (X_p, Vnet_9, Vnet_11);
VHDL_Device_9: inverter port map (Vnet_11, Z);
VHDL_Device_10: nand3 port map (X_p, Vnet_3, Vnet_4, Vnet_0);
VHDL_Device_11: Dflipflop port map (CLK, Vnet_2, PreA, Clear, Vnet_9, A_p);
B <= Vnet_3;
C <= Vnet_4;
A <= Vnet_9;
CLK_0 <= CLK;
X_0 <= X;
end Structure;
311
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 16 Design Solutions
312
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 17 Design Solutions
Solutions to Unit 17 Simulation and Lab Problems
Problems 17.A through 17.M are relatively easy VHDL problems that use a register, counter, or other clocked device.
We ask students to write VHDL code for their assigned problem, and then simulate, test, and debug their code. We
have provided appropriate test sequences for each of these problems in the solutions that follow. We ask students to
turn in simulation waveforms that demonstrate the operation of their code.
In addition to solving one of the above problems, we ask students to perform the following lab exercise:
(1) Write behavioral VHDL code that implements the state machine that you designed in Unit 16 (one of
problems 16.1 through 16.14). Use a case statement to represent the state table as illustrated in FLD
Figure 17-17. Use two processes – one for the combinational logic and one for the state register. Add an
asynchronous reset input.
(2) Simulate the VHDL code and verify that it works correctly. Use the same test sequences that you used in
Unit 16.
(3) Synthesize the VHDL and download it to a hardware board for testing. (We use the Xilinx ISE software for
synthesizing the code and programming a CPLD or FPGA.)
(4) Verify the correct operation of the hardware implementation of the state machine using the same procedures
as in Unit 16.
17.A
Test data:
- reset
- set Si = 0 1 0 0 1 1 0 0 0 0 0 0
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Lab17A is
port (CLK, ClrN, SI : in std_logic;
SO : out std_logic);
end Lab17A;
architecture Behavioral of Lab17A is
signal Q : std_logic_vector(7 downto 0):="00000000";
begin
SO <= Q(0);
process(ClrN, CLK)
begin
if ClrN='0' then Q <= "00000000";
elsif CLK' event and CLK='1' then
Q <= SI & Q(7 downto 1); end if;
end process;
end Behavioral;
Command sequence:
force CLK 0 0, 1 100 -repeat 200
force ClrN 1 0, 0 25, 1 50
force SI 0 80, 1 280, 0 480, 0 680, 1 880,
1 1080, 0 1280, 0 1480, 0 1680, 0 1880,
0 2080, 0 2280
run 2800ns
Signal
CLK
ClrN
SI
SO
0ns
400ns
800ns
1200ns
1600ns
2000ns
2400ns
2800ns
U
313
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 17 Design Solutions
17.B
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Lab17B is
port (CLK, PreN, En, C : in std_logic;
Qout : out std_logic_vector (3 downto 0));
end Lab17B;
architecture count4bit of Lab17B is
signal Q : std_logic_vector (3 downto 0);
begin
Qout <= Q;
process(PreN,CLK)
begin
if PreN = '0' then Q <= "1111";
elsif CLK'event and CLK = '1' then
if En = '0' then Q <= Q;
elsif En = '1' and C = '0' then Q <= Q + 1;
elsif En = '1' and C = '1' then Q <= Q + 3;
end if;
end if;
end process;
end count4bit;
Q(3) Q(2) Q(1) Q(0)
En
4-bit Counter
C
PreN
CLK
Test data:
- preset
- set En = 0 1 1 1 1 1 1 1 1 1 1 1 1 1
- set C = 0 0 0 0 0 1 1 1 1 1 1 1 1 1
Command sequence:
force CLK 0 0, 1 100 -repeat 200
force PreN 1 0, 0 25, 1 50
force C 0
force En 0
run 200
force En 1 50
run 800
force C 1 50
run 1800
Signal
CLK
PreN
En
C
Qout
17.C
0ns
U
F
400ns
0
1
800ns
2
3
1200ns
6
9
1600ns
C
F
2000ns
2
5
2400ns
8
B
2800ns
E
library IEEE;
signal Q, ROM_out, Index, D : std_logic_vector(0 to 2);
use IEEE.STD_LOGIC_1164.ALL;
begin
use IEEE.STD_LOGIC_ARITH.ALL;
Index <= Q;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ROM_out <= ROM1(conv_integer(Index));
entity counter is
Count <= Q;
port (CLK, ClrN : in std_logic;
D <= ROM_out;
Count : out std_logic_vector(0 to 2));
process(CLK, ClrN)
end counter;
begin
architecture Behavioral of counter is
if ClrN='0' then Q <= "000";
type ROM8X3 is array(0 to 7) of
elsif CLK'event and CLK = '1' then Q <= D; end if;
std_logic_vector(0 to 2);
end process;
constant ROM1 : ROM8X3 := ("010", "011", "100", end Behavioral;
"101", "110", "111", "001", "000");
Test data:
- Counter sequence: 000, 010, 100, 110, 001, 011,
101, 111, 000 ...
Signal
CLK
ClrN
Count
0ns
U
0 2
400ns
4
6
Command sequence:
force CLK 0 0, 1 100 -repeat 200
force ClrN 1 0, 0 25, 1 50
run 2000ns
800ns
1
3
1200ns
5
314
7
1600ns
0
2
2000ns
4
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 17 Design Solutions
17.D
1*
0
2*
*CLKout = 1 in states
1 and 2
reset when F=0
reset when F=0
CLKout
CLK
Counter
Rst
Reset
logic
F
Test data:
- reset
- set F = 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0
Command sequence:
force CLK 0 0, 1 100 -repeat 200
force F 0 0, 1 1000, 0 2400
run 3600ns
Signal
0ns
400ns
800ns
1200ns
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Lab17D is
port (CLK, F : in std_logic;
CLKout : out std_logic);
end Lab17D;
architecture Behavioral of Lab17D is
signal count : integer range 0 to 2 := 0;
signal Rst : std_logic;
begin
CLKout <= '0' when count = 0 else '1';
Rst <= '1' when F = '0' and (count = 1 or count = 2)
else '0';
process(CLK)
begin
if CLK'event and CLK = '1' then
if Rst = '1' then count <= 0;
elsif count = 2 then count <= 0;
else count <= count + 1; end if;
end if;
end process;
end Behavioral;
1600ns
2000ns
2400ns
2800ns
3200ns
3600ns
CLK
F
CLKout
17.E
LSO
RSI
library IEEE;
8-bit serial-in, serial out
right-left shift register
Clk
En
R
RSO
use IEEE.STD_LOGIC_1164.ALL;
LSI
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Lab17E is
port (Clk, ClrN, En, R, RSI, LSI : in std_logic;
RSO, LSO : out std_logic);
end Lab17E;
architecture Behavioral of Lab17E is
signal qint: std_logic_vector(7 downto 0);
begin
RSO <= qint(0);
LSO <= qint(7);
process(ClrN, Clk)
begin
if ClrN='0' then qint <= "00000000";
elsif Clk' event and Clk='1' then
if En='1' and R='1' then qint <= RSI&qint(7 downto 1);
elsif En='1' and R='0' then
qint <= qint(6 downto 0)&LSI; end if;
end if;
end process;
end Behavioral;
ClrN
Test data:
- reset
- set RSI = 1; LSI = 0
- set En = 0 for 2 clock cycles
- set En = 1 for the rest of the test
- Shift Right 9x
- Shift Left 9x
Command sequence:
force Clk 0 0, 1 100 -repeat 200
force ClrN 1 0, 0 25, 1 50
force RSI 1
force LSI 0
force En 0 0, 1 400
force R 1 0, 0 2200, 1 4000
run 4000ns
Signal 0ns
Clk
ClrN
En
R
LSI
RSI
RSO U
LSO U
400ns
800ns
1200ns
1600ns
315
2000ns
2400ns
2800ns
3200ns
3600ns
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 17 Design Solutions
17.F
LSO
RSI
RSO
LSI
6-bit serial-in, serial out
right-left shift register
Clk
L
R
ClrN
Test data:
- reset
- set LSI = 1; RSI = 1
- set R = 0 1 0 1 0 0 0
- set L = 0 0 1 1 0 0 0
Command sequence:
force Clk 0 0, 1 100 -repeat 200
force ClrN 1 0, 0 25, 1 50
force LSI 1
force RSI 1
force R 0 0, 1 200, 0 400, 1 600, 0 800
force L 0 0, 1 400, 0 800
run 1000ns
Signal
Clk
ClrN
R
L
RSI
LSI
RSO
LSO
0ns
200ns
400ns
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Lab17F is
port (Clk, ClrN, R, L, RSI, LSI : in std_logic;
RSO, LSO: out std_logic);
end Lab17F;
architecture Behavioral of Lab17F is
signal Q: std_logic_vector(5 downto 0);
begin
RSO <= Q(0);
LSO <= Q(5);
process(ClrN,Clk)
begin
if ClrN = '0' then Q <= "000000";
elsif Clk' event and Clk='1' then
if L='0' and R='1' then
Q <= RSI&Q(5 downto 1);
elsif L='1' and R='0' then
Q <= Q(4 downto 0)&LSI; end if;
end if;
end process;
end Behavioral;
600ns
800ns
1000ns
U
U
17.G
Accout
ClrN
Ad
CLK
6-bit register
Addout
CO
CI
6-bit adder
D(5:0)
Test data: - reset
-set D 111100 for one clock cycle
- set D = 111100 for the rest of the test
- set CI = 0 for the first clock cycle, 1
for the rest of the test
- set Ad = 1 for 3 clock cycles
- setAd = 0 for the next 2 clock cycles
316
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity acc_6bit is
port (CLK, ClrN, Ad, CI : in std_logic;
D : in std_logic_vector(5 downto 0);
CO : out std_logic;
Accout : out std_logic_vector(5 downto 0));
end acc_6bit;
architecture Behavioral of acc_6bit is
signal Acc : std_logic_vector (5 downto 0);
signal Addout : std_logic_vector(6 downto 0);
begin
Addout <= ('0'&Acc) + D + CI;
CO <= Addout(6);
Accout <= Acc;
process(CLK, ClrN)
begin
if ClrN = '0' then Acc <= "000000";
elsif CLK'event and CLK = '1' then
if Ad = '1' then
Acc <= Addout(5 downto 0); end if;
end if;
end process;
end Behavioral;
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 17 Design Solutions
17.G
(cont.)
17.H
Command sequence:
force CLK 0 0, 1 100 -repeat 200
force ClrN 1 0, 0 25, 1 50
force Ad 1
force CI 0
force D 111011
run 200ns
force CI 1
force D 111100
force Ad 1 0, 0 400
run 800ns
Signal 0ns
CLK
ClrN
Ad
D 3B
CI
CO X
Accout UU 00
En
U
ClrN
CLK
Test data:
- reset
- set En = 1 for 10 clock cycles
- set U = 1 for 4 clock cycles then U = 0 for the
rest of the test
Command sequence:
force CLK 0 0, 1 100 -repeat 200
force ClrN 1 0, 0 25, 1 50
force En 1 0, 0 2000
force U 1 0, 0 800
run 2000ns
Signal 0ns
Clk
Clr
En
U
1
Q 0
17.I
200ns
400ns
2
600ns
3
800ns
4
3
Q(5) Q(4) Q(3) Q(2) Q(1) Q(0)
6-bit up-down counter
En
U
D
PreN
CLK
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
port (CLK, PreN, U, D : in std_logic;
Q : out std_logic_vector(5 downto 0));
end counter;
Test data: - preset
- set U = 0 0 0 1 1 1
- set D = 1 1 1 0 0 0
317
400ns
600ns
800ns
3C
3B
38
35
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
port (CLK, ClrN, En, U : in std_logic;
Q : out std_logic_vector(3 downto 0));
end counter;
architecture Behavioral of counter is
signal W: std_logic_vector(3 downto 0):="0000";
begin
Q <= W;
process(ClrN, Clk)
begin
if ClrN = '0'then
W <= "0000";
elsif CLK'event and CLK='1' then
if En ='1' then
if U = '1' then W <= W+1;
elsif U = '0' then W <= W-1; end if;
end if;
end if;
end process;
end Behavioral;
Q(3) Q(2) Q(1) Q(0)
4-bit up-down counter
200ns
1000ns
1200ns
1400ns
1600ns
1800ns
2
1
0
F
E
architecture Behavioral of counter is
signal W : std_logic_vector(5 downto 0):="000000";
begin
Q <= W;
process(PreN, CLK)
begin
if PreN = '0' then
W <= "111111";
elsif CLK'event and CLK='1' then
if U = '1' and D = '0' then W <= W+1;
elsif U = '0' and D = '1' then W <= W-1; end if;
end if;
end process;
end Behavioral;
Command sequence:
force CLK 0 0, 1 100 -repeat 200
force PreN 1 0, 0 25, 1 50
force U 0 0, 1 600
force D 1 0, 0 600
run 1200ns
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 17 Design Solutions
17.I
(cont.)
Signal 0ns
CLK
PreN
U
D
Q 00 3F
200ns
400ns
3E
3D
600ns
3C
800ns
3D
17.J
Sel
2
2-to-4
decoder
Memin
6
Ld
Register b
Ld
6
6
6
6
6
6
Ld
Register d
6
Clk
0ns
200ns
3
00
21
UU
UU
UU
UU
21
UU
21
3F
Command sequence:
force CLK 0 0, 1 100 -repeat 200
force Memin 100001 0, 000000 200, 010010 400,
001100 600, 000111 800, 111111 1000
force Ld 1 0, 0 200, 1 400, 0 1000
force Sel 11 0, 11 200, 10 400, 01 600, 00 800,
11 1000, 10 1200, 01 1400, 00 1600
run 1800ns
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL
entity Lab17J is
port ( Memin : in std_logic_vector(5 downto 0);
Clk, Ld : in std_logic;
Sel : in std_logic_vector(1 downto 0);
Memout : out std_logic_vector(5 downto 0));
end Lab17J;
architecture Behavioral of Lab17J is
signal Sel_a, Sel_b, Sel_c, Sel_d: std_logic;
signal Reg_a, Reg_b, Reg_c, Reg_d:
std_logic_vector(5 downto 0);
begin
--Code for 2-to-4 decoder
Sel_a <= not Sel(1) and not Sel(0);
Sel_b <= not Sel(1) and Sel(0);
Sel_c <= Sel(1) and not Sel(0);
Sel_d <= Sel(1) and Sel(0);
Signal
Clk
Sel
Ld
Memin
Reg_a
Reg_b
Reg_c
Reg_d
Sel_a
Sel_b
Sel_c
Sel_d
Memout
Memout
Register c
Clk
Ld
6
6
Clk
Ld
6
3E
1200ns
Test data:
- set Memin = 100001, Ld = 1, Sel = 11
- set Memin = 000000, Ld = 0, Sel = 11
- set Ld = 1
- set Memin = 010010, 001100, 000111
while Sel =
10,
01,
00
- set Ld = 0, Memin = 111111
- set Sel = 11, 10, 01, 00
6
Clk
Ld
6
Register a
Ld
Ld
6
1000ns
--Code for tri-state buffers
Memout <= Reg_a when Sel_a = ‘1’ else "ZZZZZZ";
Memout <= Reg_b when Sel_b = ‘1’ else "ZZZZZZ";
Memout <= Reg_c when Sel_c = ‘1’ else "ZZZZZZ";
Memout <= Reg_d when Sel_d = ‘1’ else "ZZZZZZ";
--Code for Registers
process(clk)
begin
if Clk’event and Clk = ‘1’ then
if (Sel_a and Ld) = ‘1’ then
Reg_a <= Memin; end if;
if (Sel_b and Ld) = ‘1’ then
Reg_b <= Memin; end if;
if (Sel_c and Ld) = ‘1’ then
Reg_c <= Memin; end if;
if (Sel_d and Ld) = ‘1’ then
Reg_d <= Memin; end if;
end if;
end process;
end Behavioral;
400ns
600ns
800ns
1000ns
1200ns
1400ns
1600ns
2
1
0
3
2
1
0
12
0C
07
12
0C
07
0C
12
UU
12
UU
0C
318
UU
07
07
3F
21
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 17 Design Solutions
17.K
Test data:
- set ClrN = 1 for 3.5 clock cycles
= 0 for the next half clock cycle
= 1 for the rest of the test
- set L = 1 for 5 clock cycles
= 0 for the next 3 clock cycles
= 1 for the rest of the test
- set SI = 1
- set D = 0101
- set Sh = 0 for 1 clock cycle
= 1 for the next 5 clock cycles
= 0 for the rest of the test
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity shift_reg1210 is
port (CLK, ClrN, Sh, SI, L : in std_logic;
D : in std_logic_vector (3 downto 0);
Q : out std_logic_vector (3 downto 0));
end shift_reg1210;
architecture parallel_ShReg of shift_reg1210 is
signal Qint : std_logic_vector (3 downto 0);
begin
Q <= Qint;
process(CLK, ClrN)
begin
if ClrN = '0' then Qint <= "0000";
elsif CLK'event and CLK = '0' then
if Sh = '1' then Qint <= SI & Qint (3 downto 1);
elsif Sh = '0' and L = '1' then Qint <= D; end if;
end if;
end process;
end parallel_ShReg;
Command sequence:
force clk 1 0, 0 100 -repeat 200
force clrN 1 0, 0 600, 1 700
force l 1 0, 0 1000, 1 1600
force si 1
force d 0101
force sh 0 0, 1 200, 0 1200
run 1800
Signal 0ns
Clk
ClrN
Sh
SI
L
D 5
Q U
17.L
200ns
5
400ns
A
600ns
D
0
Q(7) Q(6) Q(5) Q(4) Q(3) Q(2) Q(1) Q(0)
Sh
Ad
8-bit accumulator
ClrN
CLK
D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0)
Test data:
- reset
- set Acc = 01100000
- set D = 11100010
- set Ad = 1 for 2 clock cycles
= 0 for the rest of the test
- set Sh = 0 for 2 clock cycles
= 1 for 2 clock cycles
= 0 for the rest of the test
Command sequence:
force CLK 0 0, 1 100 -repeat 200
force ClrN 1 0, 0 25, 1 50
force D 01100000
force Ad 1
run 200ns
force D 11100010
force Ad 1 0, 0 400
force Sh 0 0, 1 400, 0 800
run 1200ns
319
800ns
8
1000ns
C
1200ns
1400ns
1600ns
E
5
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sregister is
port (CLK, ClrN, Ad, Sh : in std_logic;
D: in std_logic_vector(7 downto 0);
Q: out std_logic_vector(7 downto 0));
end sregister;
architecture Behavioral of sregister is
signal Acc: std_logic_vector(7 downto 0):= "01100000";
begin
Q <= Acc;
process(CLK, ClrN)
begin
if ClrN ='0' then Acc <= "00000000";
elsif CLK'event and CLK = '1' then
if Ad = '1' then Acc <= Acc + D;
elsif Sh = '1' then Acc <= Acc(6 downto 0)&'0';
else Acc <= Acc; end if;
end if;
end process;
end Behavioral;
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 17 Design Solutions
17.L
(cont.)
Signal 0ns
CLK
ClrN
Ad
Sh U
D 60
Q 60 00
17.M
200ns
60
E2
400ns
42
24
B
8-bit accumulator
D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0)
Test data:
- set D = 10011010
- set Acc = 11100010
- set AB = 00 for 3 clock cycles
= 01 for the next 3 clock cycles
= 10 for the next 3 clock cycles
= 11 for the rest of the test
Command sequence:
force CLK 0 0, 1 100 -repeat 200
force D 11100010
force A 1
force B 0
run 200
force D 10011010
force A 0 0, 1 1200
force B 0 0, 1 600, 0 1200, 1 1800
run 2400
Signal 0ns
CLK
A
B
9A
D E2
UU
E2
Q
400ns
800ns
48
1000ns
1200ns
90
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
CLK entity Lab17M is
port(CLK, A, B : in std_logic;
D : in std_logic_vector(7 downto 0)
Q : out std_logic_vector(7 downto 0));
end Lab17M;
architecture Behavioral of Lab17M is
signal Acc : std_logic_vector(7 downto 0);
begin
Q <= Acc;
process(CLK)
begin
if CLK'event and CLK='1' then
if (A and B)='1' then Acc <= Acc-D;
elsif (A and not B)='1' then Acc <= D;
elsif (not A and B)='1' then
Acc <= '0'&Acc(7 downto 1); end if;
end if;
end process;
end Behavioral;
Q(7) Q(6) Q(5) Q(4) Q(3) Q(2) Q(1) Q(0)
A
600ns
800ns
71
320
1200ns
38
1C
1600ns
9A
2000ns
00
2400ns
66
CC
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
Solutions to Unit 20 Lab Design Problems
As a final lab assignment in our course, we ask students to solve one of the problems 20.A through 20.W. Each of
these problems is designed to fit on a small CPLD or FPGA circuit board with 8 input switches, 4 pushbuttons, and
8 LEDs. We ask our students to follow the procedure given on FLD p. 709. In addition to the given specifications,
they should include an active-high, asynchronous reset input to set the state machine controller to the proper initial
state. Students are asked to use a de-bounced pushbutton to manually clock their circuit and observe the step-bystep operation. Some problems require all 8 switches for input data. In this case, one of the pushbuttons can be used
for the start signal. For problems 20.A through 20.D, the 7 or 8 switches serve as an input bus for loading both the
dividend and the divisor.
20.A
8
Reset
St
Ld1
Su
Sh
C
O
7
Remainder
6
5
R
O
L
0
Ovf
Done
Done
5-BIT SUBTRACTER
Ld2
3
2
1
Divisor
Clk
S0
0
8
Clk
C
3
St
St'
0
Dividend
N
T
4
Quotient
2
1
0
4 Bus_in [3:0]
C
Ld2
S1
S2
Ovf
C'
S6
7
0
Ld1
Bus_in
C
Su,
C'
0
C'
S5
C'
Sh
Sh
S4
C
Sh
S3
Su
C
Su
Note: commented code is for 20.B
-- Lab 20.A One Process
-- Lab 20.A One Process (cont.)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity divider is
port ( Bus_in: in std_logic_vector(6 downto 0);
St, Clk, Reset: in std_logic;
Quotient: out std_logic_vector(2 downto 0);
--Quotient: out std_logic_vector(3 downto 0);
Remainder: out std_logic_vector(4 downto 0);
--Remainder: out std_logic_vector(3 downto 0);
Ovf : out std_logic; --Overflow
Done : out std_logic) ;
end divider;
architecture Behavioral of divider is
signal State : integer range 0 to 6;
--signal State : integer range 0 to 7;
signal C : std_logic;
signal Subout :std_logic_vector(4 downto 0);
--signal Subout :std_logic_vector(3 downto 0);
signal Dividend: std_logic_vector(7 downto 0);
signal Divisor: std_logic_vector(3 downto 0);
--signal Divisor: std_logic_vector(2 downto 0);
begin
Subout<=Dividend(7 downto 3)-('0' & Divisor);
--Subout<=Dividend(7 downto 4)-('0' & Divisor);
C<=not Subout(4);
--C<=not Subout(3);
Remainder<=Dividend(7 downto 3);
--Remainder<=Dividend(7 downto 4);
Quotient<=Dividend(2 downto 0);
--Quotient<=Dividend(3 downto 0);
321
process(CLK, Reset)
begin
if Reset = '1' then State <= 0;
elsif CLK'event and CLK='1' then
case State is
when 0 =>
if St ='1' then
Dividend<='0'& Bus_in;
State<=1;
else State <=0; end if;
when 1 =>
Divisor <= Bus_in (3 downto 0);
--Divisor <= Bus_in (2 downto 0);
State <= 2;
when 2=>
if C='1' then
State <=0;
else
Dividend <= Dividend(6 downto 0) &'0';
State<=3; end if;
when 3|4 =>
--when 3|4|5 =>
if C='1' then
Dividend(7 downto 3)<=Subout;
--Dividend(7 downto 4)<=Subout;
Dividend(0) <='1';
State<=State;
else
Dividend<=Dividend(6 downto 0) &'0';
State<=State+1; end if;
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
20.A
(cont.)
-- Lab 20.A One Process (cont.)
-- Lab 20.A Two Processes (cont.)
when 5=>
--when 6=>
if C='1' then
Dividend(7 downto 3)<=Subout;
--Dividend(7 downto 4)<=Subout;
Dividend(0) <='1'; end if;
State <=6;
-- State <= 7;
when 6=> -- done state
--when 7 =>
State <= 0;
end case;
end if;
end process;
Done <= '1' when State=6 else '0';
--Done <= '1' when State=7 else '0';
Ovf <= '1' when State = 2 and C = '1' else '0';
end Behavioral;
process(State,St,C)
begin
Ld1 <='0'; Ld2 <= '0'; Sh <='0'; Su <='0';
Done <= '0'; Ovf <= '0';
case State is
when 0 =>
if St ='1' then
Ld1 <='1';
NextState<=1;
else
NextState <=0; end if;
when 1=>
Ld2 <= '1';
NextState <= 2;
when 2=>
if C='1' then
NextState <=0;
Ovf <= '1'
else
Sh <='1';
-- Lab 20.A Two Processes
NextState<=3; end if;
when 3|4 =>
library IEEE;
--when 3|4|5 =>
use IEEE.STD_LOGIC_1164.ALL;
if C='1' then
use IEEE.STD_LOGIC_ARITH.ALL;
Su <='1';
use IEEE.STD_LOGIC_UNSIGNED.ALL;
NextState<=State;
entity divider is
else
port (Bus_in : in std_logic_vector (6 downto 0);
Sh <='1';
St, Clk, Reset : in std_logic;
NextState<=State+1;
Done, Ovf : out std_logic;
end if;
Quotient : out std_logic_vector(2 downto 0);
when 5 =>
--Quotient : out std_logic_vector(3 downto 0);
--when 6 =>
Remainder : out std_logic_vector(4 downto 0));
if C='1' then
--Remainder : out std_logic_vector(3 downto 0));
Su <='1'; end if;
end divider;
NextState <=6;
architecture Behavioral of divider is
--NextState <= 7;
signal State, NextState : integer range 0 to 6;
when 6 =>
--signal State, NextState : integer range 0 to 7;
--when 7 =>
signal C,Ld1, Ld2, Su, Sh : std_logic;
NextState <= 0;
signal Subout :std_logic_vector(4 downto 0);
Done <= '1';
--signal Subout :std_logic_vector(3 downto 0);
end case;
signal Dividend: std_logic_vector(7 downto 0);
end process;
signal Divisor : std_logic_vector (3 downto 0);
process(CLK, Reset)
--signal Divisor : std_logic_vector (2 downto 0);
begin
begin
if Reset = '1' then State <= 0;
Subout<=Dividend(7 downto 3) - ('0' & Divisor);
elsif CLK'event and CLK='1' then
--Subout<=Dividend(7 downto 4) - ('0' & Divisor);
State<=NextState;
C<=not Subout(4);
if Ld1='1' then Dividend<='0'& Bus_in; end if;
--C<=not Subout(3);
if Ld2='1' then
Remainder<=Dividend(7 downto 3);
Divisor <= Bus_in (3 downto 0); end if;
--Remainder<=Dividend(7 downto 4);
--Divisor <= Bus_in (2 downto 0); end if;
Quotient<=Dividend(2 downto 0);
if Su='1' then
--Quotient<=Dividend(3 downto 0);
Dividend(7 downto 3)<=Subout;
--Dividend(7 downto 4)<=Subout;
Dividend(0) <='1'; end if;
if Sh='1' then
Dividend<=Dividend(6 downto 0) &'0'; end if;
end if;
end process;
end Behavioral;
322
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
20.A
(cont.)
20.B
Waveform for 1110111 / 1111 = 111 remainder 01110:
Signal
Clk
St
Reset
Bus_in
Divisor
Dividend
Done
Overflow
Quotient
Remainder
State
0ns
200ns
77
U
UU 77
0F
U
7
U
UU 0E
1
0
F
2
400ns
600ns
800ns
1000ns
1200ns
1400ns
EE
77
EE
77
EE
77
6
1D
3
7
0E
6
1D
4
7
0E
6
1D
5
7
0E
6
1600ns
0
For the corresponding code for the one and two
process solutions, refer to problem 20.A.
Commented lines are used for this problem and the
lines above the commented ones are used for 20.A.
-- Lab 20.C One Process (cont.)
20.C
Note: commented code is for 20.D
case State is
when 0 =>
-- Lab 20.C One Process
if St = '1' then
Dividend <= '0' & Bus_in;
library IEEE;
State <= 1;
use IEEE.STD_LOGIC_1164.ALL;
else
use IEEE.STD_LOGIC_ARITH.ALL;
State <= 0; end if;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
when 1 =>
entity divider20c_1 is
Divisor <= Bus_in (2 downto 0);
port ( Bus_in : in std_logic_vector (7 downto 0);
--Divisor <= Bus_in (4 downto 0);
St, Clk, Reset : in std_logic;
State <= 2;
Done, Ovf : out std_logic;
when 2 =>
Quotient : out std_logic_vector (4 downto 0);
if C = '1' then State <= 0;
--Quotient : out std_logic_vector (2 downto 0);
else
Remainder : out std_logic_vector (3 downto 0));
Dividend <= Dividend(7 downto 0) & '0';
--Remainder : out std_logic_vector (5 downto 0));
State <= 3; end if;
end divider20c_1;
when 3|4|5|6 =>
architecture Behavioral of divider20c_1 is
--when 3|4 =>
signal State : integer range 0 to 8;
if C = '1' then
--signal State : integer range 0 to 6;
Dividend (8 downto 5) <= subout;
signal C : std_logic;
--Dividend (8 downto 3) <= subout;
signal subout : std_logic_vector (3 downto 0);
Dividend (0) <= '1'; State <= State;
--signal subout : std_logic_vector (5 downto 0);
else
signal Dividend: std_logic_vector (8 downto 0);
Dividend <= Dividend (7 downto 0) & '0';
signal Divisor : std_logic_vector (2 downto 0);
State <= State + 1; end if;
--signal Divisor : std_logic_vector (4 downto 0);
when 7 =>
begin
--when 5 =>
subout <= Dividend(8 downto 5) - ('0'&Divisor);
if C = '1' then
--subout <= Dividend(8 downto 3) - ('0'&Divisor);
Dividend (8 downto 5) <= subout;
C <= not subout (3);
--Dividend (8 downto 3) <= subout;
--C <= not subout (5);
Dividend (0) <= '1'; end if;
Remainder <= Dividend (8 downto 5);
State <= 8;
--Remainder <= Dividend (8 downto 3);
--State <= 6;
Quotient <= Dividend (4 downto 0);
when 8 =>
--Quotient <= Dividend (2 downto 0);
--when 6 =>
process (Clk, Reset)
State <= 0;
begin
end case;
if Reset = '1' then State <= 0;
end if;
elsif Clk'event and Clk = '1' then
end process;
Done <= '1' when State = 8 else '0';
--Done <= '1' when State = 6 else '0';
Ovf <= '1' when State = 2 and C = '1' else '0';
end Behavioral;
323
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
20.C
(cont.)
20.D
-- Lab 20.C Two Processes (cont.)
-- Lab 20.C Two Processes
case State is
when 0 =>
if St = '1' then Ld1 <= '1'; NextState <= 1;
else NextState <= 0; end if;
when 1 =>
Ld2 <= '1'; NextState <= 2;
when 2 =>
port (Bus_in : in std_logic_vector (7 downto 0);
if C = '1' then NextState <= 0; Ovf <= '1';
St, Clk, Reset : in std_logic;
else Sh <= '1'; NextState <= 3; end if;
Done, Ovf : out std_logic;
when 3|4|5|6 =>
Quotient : out std_logic_vector (4 downto 0);
--when 3|4 =>
--Quotient : out std_logic_vector (2 downto 0);
if C = '1' then Su <= '1'; NextState <= State;
Remainder : out std_logic_vector (3 downto 0));
else Sh <= '1'; NextState <= State + 1; end if;
--Remainder : out std_logic_vector (5 downto 0));
when 7 =>
end divider20c_1;
--when 5 =>
architecture Behavioral of divider20c_1 is
if C = '1' then Su<= '1'; end if;
signal State, NextState : integer range 0 to 8;
NextState <= 8;
--signal State, NextState : integer range 0 to 6;
--NextState <= 6;
signal C, Sh, Su, Ld1, Ld2 : std_logic;
when 8 =>
signal subout : std_logic_vector (3 downto 0);
--when 6 =>
--signal subout : std_logic_vector (5 downto 0);
Done <= '1'; NextState <= 0;
signal Dividend: std_logic_vector (8 downto 0);
end case;
signal Divisor : std_logic_vector (2 downto 0);
end process;
--signal Divisor : std_logic_vector (4 downto 0);
process (Clk, Reset)
begin
begin
subout <= Dividend(8 downto 5) - ('0'&Divisor);
if Reset = '1' then State <= 0;
--subout <= Dividend(8 downto 3) - ('0'&Divisor);
elsif Clk'event and Clk = '1' then
C <= not subout (3);
State <= NextState;
--C <= not subout (5);
if Ld1 = '1' then
Remainder <= Dividend (8 downto 5);
Dividend <= '0' & Bus_in; end if;
--Remainder <= Dividend (8 downto 3);
if Ld2 = '1' then
Quotient <= Dividend (4 downto 0);
Divisor <= Bus_in (2 downto 0); end if;
--Quotient <= Dividend (2 downto 0);
--Divisor <= Bus_in (4 downto 0); end if;
process (State, C, St)
if Sh = '1' then
begin
Dividend <= Dividend (7 downto 0) & '0'; end if;
Sh <= '0'; Su <= '0'; Ld1 <= '0'; Ld2 <= '0';
if Su = '1' then
Ovf <= '0'; Done <= '0';
Dividend (8 downto 5) <= subout;
--Dividend (8 downto 3) <= subout;
Dividend (0) <= '1'; end if;
end if;
end process;
end Behavioral;
For the corresponding code for the one and two
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity divider20c_1 is
process solutions, refer to problem 20.C.
Commented lines are used for this problem and the
lines above the commented ones are used for 20.C.
St'
0
S0
-
20.E
4 inBus[3:0]
-
Sh
4
inBus
Mcand[2:0]
inBus[2:0]
Accumulator[7:0]
3
M
Ld1
Sh
Ad
Accumulator[3:0]
Clk
20E
3 bit Adder
Ld1
S1
done
S10
-
S9
Product[6:0]
St
Control
Ld2
Clk
Clk
324
Ad
-
M
done
Reset
St
20E
M'
Sh
S2
S8
S7
M'
Sh
M'
Sh
Sh
M
Ad
Ld2
S6
-
Sh
M'
Sh
S4
M
S5
Ad
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
M
Ad
S3
-
Sh
Unit 20 Design Solutions
20.E
(cont.)
-- Lab 20 E One Process
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multiplier347 is
port(clk: in std_logic;
-- manual clock to cycle through the multiplier
st: in std_logic;
-- start signal to your circuit
Reset: in std_logic;
-- active high asynchronous reset
done: out std_logic;
--done signal
inBus: in std_logic_vector(3 downto 0);
-- 4-bit inBus from the 8 switches
product: out std_logic_vector(6 downto 0));
-- 7-bit output to LEDs
end multiplier347;
architecture Behavioral of multiplier347 is
signal state, nextstate: integer range 0 to 10;
signal acc: std_logic_vector(7 downto 0);
signal Mcand: std_logic_vector(2 downto 0);
signal m: std_logic;
signal addout: std_logic_vector(3 downto 0);
begin
product <= acc(6 downto 0);
-- for debugging : product <= conv_std_logic_vector(state,7);
m <= acc(0);
addout <= ‘0’ & acc(6 downto 4) + Mcand;
done <= ‘1’ when state = 10 else ‘0’;
process(clk,Reset)
begin
if Reset = ‘1’ then State <= 0; acc <= “00000000”;
elsif clk’ event and clk = ‘1’ then
case state is
when 0 =>
if st = ‘1’ then acc(3 downto 0) <= inBus; state <= 1;
else state <= 0; end if;
when 1 => Mcand <= inBus(2 downto 0); state <=2;
when 2|4|6|8 =>
if m = ‘1’ then acc(7 downto 4) <= addout;
state <= state + 1;
else acc <= ‘0’ & acc(7 downto 1);
state <= state + 2; end if;
when 3|5|7|9 => acc <= ‘0’ & acc(7 downto 1);
state <= state + 1;
when 10 => state <= 0;
end case;
end if;
end process;
end Behavioral;
325
-- Lab 20 E Two Processes
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multiplier347 is
port(clk: in std_logic;
-- manual clock to cycle through the multiplier
st: in std_logic;
-- start signal to your circuit
Reset: in std_logic;
-- active high asynchronous reset
done: out std_logic; --done signal
inBus: in std_logic_vector(3 downto 0);
-- 4-bit input from the 8 switches
product: out std_logic_vector(6 downto 0) );
end multiplier347;
architecture Behavioral of multiplier347 is
signal state, nextstate: integer range 0 to 10;
signal acc : std_logic_vector(7 downto 0);
signal Mcand: std_logic_vector(2 downto 0);
signal m : std_logic;
signal addout : std_logic_vector(3 downto 0);
signal ld1,ld2, ad, sh : std_logic;
begin
product <= acc(6 downto 0);
m
<= acc(0);
addout <= ‘0’ & acc(6 downto 4) + Mcand;
process(state,st,m)
begin
ld1<=’0’ ; ld2<=’0’ ; ad<=’0’ ; sh<=’0’; done <= ‘0’;
case state is
when 0 =>
if st = ‘1’then ld1 <=’1’; nextstate <= 1;
else nextstate <= 0; end if;
when 1 => ld2 <= ‘1’; nextstate <= 2;
when 2|4|6|8 =>
if m = ‘1’ then ad <= ‘1’; nextstate <= state + 1;
else sh <= ‘1’; nextstate <= state + 2; end if;
when 3|5|7|9 => sh <= ‘1’; nextstate <= state + 1;
when 10 => done <= ‘1’; nextstate <= 0;
end case;
end process;
process(clk, Reset)
begin
if Reset = ‘1’ then State <= 0; acc <= “00000000”;
elsif clk’ event and clk = ‘1’ then
if ld1 = ‘1’ then
acc(3 downto 0) <= inBus; end if;
if ld2 = ‘1’ then
Mcand <= inBus(2 downto 0); end if;
if ad = ‘1’ then
acc(7 downto 4) <= addout; end if;
if sh = ‘1’ then
acc <= ‘0’ & acc(7 downto 1); end if;
state <= nextstate;
end if;
end process;
end Behavioral;
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
20.F
St'
0
inBus[2:0]
3
Product[6:0]
Accumulator[7:0]
Mcand[3:0]
inBus[3:0]
4
Clk
20F
4 bit Adder
-
Ld1
Sh
Ad
Accumulator[2:0]
4
inBus
S0
Control
Clk
Clk
M
Reset
St
architecture Behavioral of multiplier437 is
signal state, nextstate: integer range 0 to 8;
signal acc: std_logic_vector(7 downto 0);
signal Mcand: std_logic_vector(3 downto 0);
signal m: std_logic;
signal addout: std_logic_vector(4 downto 0);
begin
product <= acc(6 downto 0);
m <= acc(0);
addout <= ‘0’ & acc(6 downto 3) + Mcand;
done <= ‘1’ when state = 8 else ‘0’;
process(clk,Reset)
begin
if Reset = ‘1’ then State <= 0; acc <= “00000000”;
elsif clk’ event and clk = ‘1’ then
case state is
when 0 =>
if st = ‘1’ then
acc(2 downto 0) <= inBus(2 downto 0); state <= 1;
else state <= 0; end if;
when 1 => Mcand <= inBus; state <=2;
when 2|4|6 =>
if m = ‘1’ then
acc(7 downto 3) <= addout; state <= state + 1;
else acc <= ‘0’ & acc(7 downto 1);
state <= state + 2; end if;
when 8 => state <= 0;
end case;
end if;
end process;
end Behavioral;
S1
-
20F
Ad
S6
-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multiplier437 is
port(clk: in std_logic;
-- manual clock to cycle through the multiplier
st: in std_logic;
-- start signal to your circuit
Reset: in std_logic;
-- active high asynchronous reset
done: out std_logic;
--done signal
inBus: in std_logic_vector(3 downto 0);
-- 4-bit inBus from the 8 switches
product: out std_logic_vector(6 downto 0));
-- 7-bit output to LEDs
end multiplier437;
Ld1
done
M'
Sh
Ld2
S2
done
-- Lab 20 F One Process
326
S8
S7
M
Ld2
Sh
-
St
M'
Sh
M'
Sh
Sh
S4
S5
M
Ad
-- Lab 20 F Two Processes
-
M
Ad
S3
Sh
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multiplier437 is
port(clk: in std_logic;
-- manual clock to cycle through the multiplier
st: in std_logic;
-- start signal to your circuit
Reset: in std_logic;
-- active high asynchronous reset
done: out std_logic; --done signal
inBus: in std_logic_vector(3 downto 0);
-- 4-bit input from the 8 switches
product: out std_logic_vector(6 downto 0));
end multiplier437;
architecture Behavioral of multiplier437 is
signal state, nextstate: integer range 0 to 8;
signal acc: std_logic_vector(7 downto 0);
signal Mcand: std_logic_vector(3 downto 0);
signal m: std_logic;
signal addout: std_logic_vector(4 downto 0);
signal ld1,ld2, ad, sh : std_logic;
begin
product <= acc(6 downto 0);
m <= acc(0);
addout <= ‘0’ & acc(6 downto 3) + Mcand;
process(state,st,m)
begin
ld1<=’0’; ld2<=’0’; ad<=’0’; sh<=’0’; done <= ‘0’;
case state is
when 0 =>
if st = ‘1’ then ld1 <= ‘1’; nextstate <= 1;
else nextstate <= 0; end if;
when 1 => ld2 <= ‘1’; nextstate <= 2;
when 2|4|6 =>
if m = ‘1’ then ad <= ‘1’; nextstate <= state + 1;
else sh <= ‘1’; nextstate <= state + 2; end if;
when 3|5|7 => sh <= ‘1’;
nextstate <= state + 1; done <= ‘0’;
when 8 => done <= ‘1’; nextstate <= 0;
end case;
end process;
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
20.F
(cont.)
20.G
-- Lab 20 F Two Processes (cont.)
process(clk, Reset)
begin
if Reset = ‘1’ then State <= 0; acc <= “00000000”;
elsif clk’ event and clk = ‘1’ then
if ld1 = ‘1’ then
acc(2 downto 0) <= inBus(2 downto 0); end if;
if ld2 = ‘1’ then Mcand <= inBus; end if;
if ad = ‘1’ then
acc(7 downto 3) <= addout; end if;
if sh = ‘1’ then
acc <= ‘0’ & acc(7 downto 1); end if;
state <= nextstate;
end if;
end process;
end Behavioral;
inBus[2:0]
3
Accumulator[8:0]
Product[7:0]
5
20G
5 bit Adder
inBus
Mcand[4:0]
inBus[4:0]
Ld1
Sh
Ad
Accumulator[2:0]
Clk
M
Control
Ld2
5
Clk
Clk
done
St'
0
S0
-
Sh
S8
S7
M
-
St
Ld1
done
S1
-
20G
M'
Sh
Ad
S6
-
Ld2
S2
M'
Sh
M'
Sh
Sh
S4
S5
M
20.G
(cont.)
Reset
St
Ad
-
M
Ad
S3
Sh
-- Lab 20.G One Process
-- Lab 20.G One Process (cont.)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multiplier538 is
port(clk: in std_logic;
-- manual clock to cycle through the multiplier
st: in std_logic;
-- start signal to your circuit
Reset: in std_logic;
-- active high asynchronous reset
done: out std_logic; -- done signal
inBus: in std_logic_vector(4 downto 0);
-- 5-bit inBus from the 8 switches
product: out std_logic_vector(7 downto 0));
-- 8-bit output to LEDs
end multiplier538;
process (clk, Reset)
begin
if Reset = ‘1’ then State <= 0; acc <= “000000000”;
elsif clk’event and clk =’1’ then
case state is
when 0 =>
if st=’1’ then
acc(2 downto 0) <= inBus( 2 downto 0); state <=1;
else state <=0; end if;
when 1 => Mcand <= inBus; state<=2;
when 2|4|6 =>
if m=’1’ then acc(8 downto 3)<=addout;
state <= state + 1;
else acc <=’0’ & acc(8 downto 1);
state <=state + 2; end if;
when 3|5|7 =>
acc <=’0’ &acc(8 downto 1); state <= state + 1;
when 8 => state <= 0;
end case;
end if;
end process;
end Behavioral;
architecture Behavioral of multiplier538 is
signal state, nextstate: integer range 0 to 8;
signal acc: std_logic_vector(8 downto 0);
signal Mcand: std_logic_vector(4 downto 0);
signal m: std_logic;
signal addout: std_logic_vector(5 downto 0);
begin
product <=acc(7 downto 0);
m <= acc(0);
addout <= ‘0’ & acc(7 downto 3) + Mcand;
done <= ‘1’ when state = 8 else ‘0’;
327
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
20.G
(cont.)
-- Lab 20G Two Processes
-- Lab 20G Two Processes (cont.)
library IEEE;
process (state, st, m)
use IEEE.STD_LOGIC_1164.ALL;
begin
use IEEE.STD_LOGIC_ARITH.ALL;
ld1 <= ‘0’ ; ld2 <= ‘0’ ; ad <= ‘0’ ; sh <= ‘0’ ; done <= ‘0’;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
case state is
entity multiplier538 is
when 0 =>
port(clk: in std_logic;
if st = ‘1’ then ld1 <= ‘1’; nextstate <= 1;
-- manual clock to cycle through the multiplier
else nextstate <= 0; end if;
st: in std_logic;
-- start signal to your circuit
when 1 => ld2<=’1’; nextstate <=2;
Reset: in std_logic; -- active high asynchronous reset
when 2|4|6 =>
done: out std_logic; --done signal
if m =’1’ then ad <= ‘1’ ; nextstate <= state + 1 ;
inBus: in std_logic_vector(4 downto 0);
else sh <=’1’; nextstate <= state + 2; end if;
-- 5-bit input from the 8 switches
when 3|5|7 => sh <= ‘1’ ; nextstate <= state + 1;
product : out std_logic_vector(7 downto 0));
when 8 => done <= ‘1’ ; nextstate <= 0 ;
end multiplier538;
end case;
end process;
architecture Behavioral of multiplier538 is
signal state, nextstate: integer range 0 to 8;
process (clk, Reset)
signal acc: std_logic_vector(8 downto 0);
begin
signal Mcand: std_logic_vector(4 downto 0);
if Reset =’1’ then State <= 0; acc <= “000000000”;
signal m: std_logic;
elsif clk’event and clk = ‘1’ then
signal addout: std_logic_vector(5 downto 0);
if ld1 =’1’ then acc(4 downto 0) <= inBus; end if;
signal ld1,ld2, ad, sh: std_logic;
if ld2=’1’ then Mcand <= inBus(4 downto 0); end if;
begin
if ad =’1’then acc(8 downto 3) <= addout; end if;
product <=acc(7 downto 0);
if sh =’1’ then acc <=’0’&acc(8 downto 1); end if;
m <= acc(0);
state <=nextstate;
addout <= ‘0’ & acc(7 downto 3) + Mcand;
end if;
end process;
end Behavioral;
20.H
inBus[4:0]
St'
0
5
Product[7:0]
5
20H
3 bit Adder
inBus
Mcand[2:0]
inBus[2:0] 3
Accumulator[8:0]
Accumulator[4:0]
-
Ld1
Sh
Ad
Clk
M
Control
Ld2
Clk
Clk
-- Lab 20 H One Process
-
Sh
done
Reset
St
Ld1
done
S1
S12
S11
M
St
S0
-
M'
Sh
Ad
20H
S10
-
Sh
Ad
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multiplier358 is
port(clk: in std_logic;
-- manual clock to cycle through the multiplier
st: in std_logic;
-- start signal to your circuit
Reset: in std_logic;
-- active high asynchronous reset
done: out std_logic;
--done signal
inBus: in std_logic_vector(4 downto 0); -- 5-bit inBus from the 8 switches
product: out std_logic_vector(7 downto 0)); -- 8-bit output to LEDs
end multiplier358;
-
M
M'
Sh
M'
Sh
S6
Sh
S7
M
-
M
Ad
-
S4
S3
Sh
Ad
Sh
S5
architecture Behavioral of multiplier358 is
signal state, nextstate: integer range 0 to 12;
signal acc: std_logic_vector(8 downto 0);
signal Mcand: std_logic_vector(2 downto 0);
signal m: std_logic;
signal addout: std_logic_vector(3 downto 0);
328
Ad
M'
Sh
S8
M
S2
M'
Sh
S9
Ld2
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
20.H
(cont.)
-- Lab 20 H One Process (cont.)
begin
product <=acc(7 downto 0);
m <= acc(0);
addout <= ‘0’ & acc(7 downto 5) + Mcand;
done <= ‘1’ when state = 12 else ‘0’;
process (clk , Reset)
begin
if Reset = ‘1’ then State <= 0 ; acc <= “000000000”;
elsif clk’event and clk = ‘1’ then
case state is
when 0 =>
if st = ‘1’ then acc(4 downto 0 ) <= inBus; state <= 1 ;
else state <= 0; end if;
when 1 => mcand <= inBus(2 downto 0 ); state <= 2 ;
when 2|4|6|8|10 =>
if m = ‘1’ then acc(8 downto 5) <= addout ; state <= state + 1 ;
else acc <= ‘0’ & acc(8 downto 1) ; state <= state +2; end if;
when 3|5|7|9|11 => acc <= ‘0’ & acc(8 downto 1); state <= state +1;
when 12 => state <= 0;
end case;
end if;
end process;
end Behavioral;
20.H
(cont.)
-- Lab 20.H Two Processes
-- Lab 20.H Two Processes (cont.)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multiplier358 is
port(clk: in std_logic;
-- manual clock to cycle through the multiplier
st: in std_logic; -- start signal to your circuit
Reset: in std_logic; -- active high asynchronous reset
done: out std_logic; --done signal
inBus: in std_logic_vector(4 downto 0);
-- 5-bit input from the 8 switches
product: out std_logic_vector(7 downto 0));
end multiplier358;
process (state, st, m)
begin
ld1 <= ‘0’ ; ld2 <= ‘0’ ; ad <= ‘0’ ; sh <= ‘0’; done <= ‘0’;
case state is
when 0 =>
if st =’1’ then ld1 <= ‘1’ ; nextstate <= 1;
else nextstate <= 0; end if;
when 1 => ld2<= ‘1’ ; nextstate <= 2 ;
when 2|4|6|8|10 =>
if m =’1’ then ad <= ‘1’ ; nextstate <= state + 1;
else sh <= ‘1’; nextstate <= state +2; end if;
when 3|5|7|9|11 =>
sh <= ‘1’; nextstate <= state +1;
when 12 => done <= ‘1’ ; nextstate <= 0;
end case;
end process;
architecture Behavioral of multiplier358 is
signal state, nextstate: integer range 0 to 12;
signal acc: std_logic_vector(8 downto 0);
signal Mcand: std_logic_vector(2 downto 0);
signal m: std_logic;
signal addout: std_logic_vector(3 downto 0);
signal ld1,ld2, ad, sh: std_logic;
begin
product <=acc(7 downto 0); m <= acc(0);
addout <=’0’&acc(7 downto 5)+ Mcand;
329
process (clk,Reset) begin
if Reset =’1’ then State <=0; acc <= “000000000”;
elsif clk’event and clk =’1’ then
if ld1 =’1’ then acc(4 downto 0) <= inBus; end if;
if ld2=’1’ then mcand <= inBus(2 downto 0); end if;
if ad = ‘1’ then acc(8 downto 5) <= addout; end if;
if sh =’1’ then acc <= ‘0’&acc(8 downto 1); end if;
state <=nextstate;
end if;
end process;
end Behavioral;
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
20.I
sum i
St
V
Ovf
Done
Control
Circuit
Reset
Ld SI
Sh
LdA
LdB
Sh
Accumulator
x7 x6 x5 x4 x3 x2 x1 x0
8
y(0)
Ld SI
Sh
K
Counter
Addend
S0
LdA
KV
Done
S23
K V'
ci+1
Q
D
D
Clk
-- Lab 20.I One Process (cont.)
S1
LdB
S2
-- Lab 20.I One Process
ci
Q' CE
Ovf
Sh
Full
Adder
Clk
0
St
V
sum i
inbus
y7 y6 y5 y4 y3 y2 y1 y0
Clk
St'
Overflow
Logic
Sum
8
K'
Sh
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lab20I_1p is
port ( clk, st, Reset : in std_logic;
inbus : in std_logic_vector(7 downto 0);
sum : out std_logic_vector(7 downto 0);
done, ovf : out std_logic);
end lab20I_1p;
architecture Behavioral of lab20I_1p is
-- X = Acc
signal X,Y : std_logic_vector(7 downto 0);
signal Ci,Ciplus,Sumi,K,V,cat1,cat2 : std_logic;
signal State : integer range 0 to 3;
signal Count : std_logic_vector(2 downto 0);
330
begin
cat1 <= '0'; -- Needed to use the 7 segment display
cat2 <= '1'; -- to provide a 9th LED
Sumi <= X(0) xor Y(0) xor Ci; -- 1-bit adder
Ciplus <= (Ci and X(0)) or
(Ci and Y(0)) or (X(0) and Y(0));
sum <= X;
done <= '1' when state = 3 else '0';
V <= (sumi and not Y(0) and not X(0))
or (not sumi and Y(0) and X(0));
K <= '1' when Count = 7 else '0';
-- Control state machine
process (clk, Reset)
begin
if Reset = '1' then State <= 0;
elsif clk'event and clk='0' then
case State is
when 0 =>
if St = '1' then
X <= inbus; -- load accumulator from bus
Ci <='0'; -- Clear the carry bit
Count <= "000";
State <= 1; end if;
when 1 =>
Y <= inbus;
State <= 2;
when 2 =>
if K = '0' or V = '0' then -- shift
X <= Sumi & X(7 downto 1);
Y <= Y(0) & Y(7 downto 1);
Ci <= Ciplus;
Count <= Count + 1; end if;
if K = '0' then State <= 2;
elsif V = '0' then State <= 3;
else State <= 0; end if;
when 3 =>
State <= 0;
end case;
end if;
end process;
Ovf <= '1' when V = '1' and State = 2 and K = '1'
else '0';
end Behavioral;
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
20.I
(cont.)
-- Lab 20.I Two Processes
-- Lab 20.I Two Processes (cont.)
Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lab20I_2p is
port ( clk, st, Reset : in std_logic;
inbus : in std_logic_vector(7 downto 0);
sum : out std_logic_vector(7 downto 0);
ovf, done : out std_logic);
end lab20I_2p;
architecture Behavioral of lab20I_2p is
-- X = Accumulator
signal X,Y : std_logic_vector(7 downto 0);
signal Sh,Ci,Ciplus,Sumi,K,LdA,LdB,V,cat1,cat2 : std_logic;
signal State, NextState : integer range 0 to 3;
signal count : std_logic_vector(2 downto 0);
begin
cat1 <= ‘0’; -- Needed to use the 7 segment display
cat2 <= ‘1’; -- To provide a 9th LED
Sumi <= X(0) xor Y(0) xor Ci; -- 1-bit adder
Ciplus <= (Ci and X(0))
or (Ci and Y(0)) or (X(0) and Y(0));
sum <= X;
V <= (Sumi and not Y(0) and not X(0))
or (not Sumi and Y(0) and X(0));
K <= ‘1’ when count=7 else ‘0’;
-- Control state machine
process (State,St,K,V)
begin
LdA <= ‘0’; LdB <= ‘0’; Sh <= ‘0’;
Ovf <= ‘0’; Done <= '0';
case State is
when 0 =>
if St = ‘1’ then
LdA <= ‘1’; -- load accumulator from bus
NextState <= 1;
else
NextState <= 0; end if;
when 1 =>
LdB <= ‘1’; NextState <= 2;
when 2 =>
if K = ‘0’ then Sh <= ‘1’; else
if V = ‘0’ then Sh <= ‘1’; NextState <= 3;
else ovf <= ‘1’; NextState <= 0; end if;
end if;
when 3 =>
done <= ‘1’; NextState <= 0;
end case;
end process;
process(clk, Reset)
begin
if Reset = '1' then State <= 0;
elsif clk’event and clk=’0’ then
State <= NextState;
if LdA = ‘1’ then
X<=inbus;
count <= "000"; -- Initialize counter
Ci <= ‘0’; -- Initialize carry
elsif LdB = ‘1’ then Y<=inbus;
elsif Sh=’1’ then
-- Shifting both ACC and Addend
X <= Sumi & X(7 downto 1);
Y <= Y(0) & Y(7 downto 1);
Ci <= Ciplus; -- store carry
count <= count + 1; end if;
end if;
end process;
end Behavioral;
Waveform for 01111111 + 00000001 = 10000000 (overflow):
Signal
Clk
St
Reset
Inbus
Done
Ovf
Sum
State
20.J
0ns
7F
400ns
1200ns
1600ns
2000ns
01
U
7F
0 1
800ns
UU
2
3F
1F
0F
07
03
01
00
0
Same as solution for 20.I except change
all 7's to 6's.
331
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
20.K
-- Lab 20.K One Process
-- Lab 20.K Two Processes
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lab20K_1p is
port ( clk, st, Reset : in std_logic;
inbus : in std_logic_vector(7 downto 0);
diff : out std_logic_vector(7 downto 0);
done, ovf : out std_logic);
end lab20K_1p;
architecture Behavioral of lab20K_1p is
signal X,Y : std_logic_vector(7 downto 0);
-- X = Accumulator
signal Bi,Biplus,diffi,K,V,cat1,cat2 : std_logic;
signal State : integer range 0 to 3;
signal Count : std_logic_vector(2 downto 0);
begin
cat1 <= ‘0’; -- Needed to use the 7 segment display
cat2 <= ‘1’; -- To provide a 9th LED
diffi <= X(0) xor Y(0) xor Bi; -- 1-bit adder
Biplus <= (Bi and not X(0)) or (Bi and Y(0)) or
(not X(0) and Y(0));
diff <= X;
done <= ‘1’ when state = 3 else ‘0’;
V <= (diffi and Y(0) and not X(0)) or
(not diffi and not Y(0) and X(0));
K <= ‘1’ when Count = 7 else ‘0’;
-- Control state machine
process (clk, Reset)
begin
if Reset = ‘1’ then State <= 0;
elsif clk’event and clk=’0’ then
case State is
when 0 =>
if St = ‘1’ then
X <= inbus; -- load accumulator from bus
Bi <=’0’; -- Clear the borrow bit
Count <= "000"; State <= 1;
end if;
when 1 =>
Y <= inbus; State <= 2;
when 2 =>
if K = '0' or V = '0' then -- shift
X <= Diffi & X(7 downto 1);
Y <= Y(0) & Y(7 downto 1);
Bi <= Biplus;
Count <= Count + 1; end if;
if K = '0' then State <= 2;
elsif V = '0' then State <= 3;
else State <= 0; end if;
when 3 =>
State <= 0;
end case;
end if;
end process;
Ovf <= '1' when V = '1' and State = 2 and K = '1'
else '0';
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lab20K_2p is
port ( clk, st, Reset : in std_logic;
inbus : in std_logic_vector(7 downto 0);
diff : out std_logic_vector(7 downto 0);
ovf, done : out std_logic);
end lab20K_2p;
architecture Behavioral of lab20K_2p is
signal X,Y : std_logic_vector(7 downto 0);
-- X = Accumulator
signal Sh,Bi,Biplus,diffi,K,LdA,LdB,V : std_logic;
signal State, NextState : integer range 0 to 3;
signal count : std_logic_vector(2 downto 0);
signal cat1, cat2 : std_logic;
begin
cat1 <= ‘0’; -- Needed to use the 7 segment display
cat2 <= ‘1’; -- To provide a 9th LED
diffi <= X(0) xor Y(0) xor Bi; -- 1-bit adder
Biplus <= (Bi and not X(0)) or (Bi and Y(0) and X(0)) or
(not X(0) and Y(0));
diff <= X;
V <= (diffi and Y(0) and not X(0)) or
(not diffi and not Y(0) and X(0));
K <= ‘1’ when count=7 else ‘0’;
-- Control state machine
process (State,St,K,V)
begin
LdA <= ‘0’; LdB <= ‘0’; Sh <= ‘0’;
Ovf <= ‘0’; Done <= '0';
case State is
when 0 =>
if St = ‘1’ then
LdA <= ‘1’; -- load accumulator from bus
NextState <= 1;
else
NextState <= 0; end if;
when 1 =>
LdB <= ‘1’;
NextState <= 2;
when 2 =>
if K = ‘0’ then Sh <= ‘1’; else
if V = ‘0’ then Sh <= ‘1’; NextState <= 3;
else ovf <= ‘1’; NextState <= 0; end if;
end if;
when 3 =>
done <= ‘1’; NextState <= 0;
end case;
end process;
332
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
-- Lab 20.K Two Processes (cont.)
20.K
(cont.)
20.L
process(clk, Reset)
begin
if Reset = '1' then State <= 0;
elsif clk’event and clk=’0’ then
State <= NextState;
if LdA = '1' then
X<=inbus;
count <= "000"; -- Initialize counter
Bi <= '0'; -- Initialize borrow
elsif LdB = '1' then Y<=inbus;
elsif Sh='1' then
-- Shifting both ACC and Addend
X <= diffi & X(7 downto 1);
Y <= Y(0) & Y(7 downto 1);
Bi <= Biplus; -- store borrow
count <= count + 1;
end if;
end if;
end process;
end Behavioral;
20.M
Same as solution to 20.K except change
all 7's to 6's.
Dividend
X(16:8)
9
Quotient
9
C
Subtracter and Comparator
Clk
K
Counter
Rst
St
Clk
Control
Note: Su loads subtracter
output into X(16:8) and
sets X0 to 1.
8
0
Y(7:0)
Divisor
St
S0
C'
Ld
Su
Sh
X(7:0)
C
-- Lab 20.M Two Processes
Ld
V
S1
C'
Done
K C'
Sh
S23
C
Su
Done
V
Sh
S2
C
Su
K' C'
, Sh
333
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Div16 is
port (CLK, St. Rst : in std_logic;
Dvend : in std_logic_vector(15 downto 0);
Dvsor : in std_logic_vector(7 downto 0);
Quotient : out std_logic_vector(7 downto 0);
Remainder : out std_logic_vector(8 downto 0);
V, Done : out std_logic);
end Div16;
architecture Behavioral of Div16 is
signal state, nextstate : integer range 0 to 2;
signal X : std_logic_vector(16 downto 0); -- dividend register
signal Y : std_logic_vector(8 downto 0); -- divisor register
signal C, Sh, Su, Ld, K : std_logic;
signal Count : std_logic_vector(2 downto 0);
signal subout : std_logic_vector(8 downto 0);
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
20.M
(cont.)
-- Lab 20.M Two Processes (cont.)
begin
Quotient <= X(7 downto 0);
Remainder <= X(16 downto 8);
K <= '1' when Count = 7 else '0';
Subout <= X(16 downto 8) - Y;
C <= not Subout(8);
process (state, St, C, K)
begin
Ld <= '0'; Sh <= '0'; Su <= '0';
V <= '0'; Done <= '0';
case State is
when 0 => if St = '1' then Ld <= '1';
nextstate <= 1; end if;
when 1 =>
if C = '1' then V <= '1'; nextstate <= 0;
else Sh <= '1'; nextstate <= 2; end if;
when 2 =>
if C = '1' then Su <= '1'; nextstate <= 2;
else
Sh <= '1';
if K = '0' then nextstate <= 2;
else nextstate <= 3; end if;
end if;
when 3 =>
if C = '1' then Su <= '1'; nextstate <= 3;
else Done <= '1'; nextstate <= 0; end if;
end case;
end process;
process(clk, Rst)
begin
if Rst = '1' then State <= 0;
elsif clk'event and clk = '1' then
if Ld = '1' then
Count <= "000"; X <= '0'&Dvend; Y <= '0'&Dvsor; end if;
if Sh = '1' then
X <= X(15 downto 0) & '0'; Count <= Count + 1; end if;
if Su = '1' then
X(16 downto 8) <= Subout; X(0) <= '1'; end if;
state <= nextstate;
end if;
end process;
end Behavioral;
334
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
Lab Design Problems 20.N, 20,O, 20.P, and 20.Q.
These problems require the design of a multiplier with a product that is 13 bits long. If your students are using a
board that has only 8 LEDs, two strategies could be used to display the product. One way is to add an extra state to
the circuit and display the upper 5 bits in one state and the lower 8 bits in the next state. Alternatively, if the board
has four 7-segment displays, the product can be displayed as four hexadecimal digits. Since time for our students to
complete this design project is very limited, we give the students VHDL code for the module that displays the hex
values. VHDL code for the hex display module follows.
-- The following module displays a 16-bit answer as four hexadecimal digits.
-- The constant array converts each 4- bit pattern to a 7-bit pattern to drive the 7-segment indicators.
-- The 7-bit LCD output drives all four indicators in parallel.
-- The scan signal selects each of the four 7-segment indicators in turn
-- and multiplexes the four digits from the bit_data input.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hex_display is
port(bit_data: in std_logic_vector(15 downto 0);
LCD: out std_logic_vector( 6 downto 0);
int_clk: in std_logic;
enable_0, enable_1, enable_2, enable_3: out std_logic);
end hex_display;
architecture output_hex_display of hex_display is
type hex_display16_7 is array (0 to 15) of std_logic_vector (6 downto 0);
constant hex_display1: hex_display16_7 := (“0111111”,”0000110”,”1011011”,”1001111”,
“1100110”,”1101101”,”1111101”,”0000111”,
“1111111”,”1100111”,”1110111”,”1111100”,
“1011000”,”1011110”,”1111001”,”1110001”);
signal digit: std_logic_vector(3 downto 0);
signal index: integer range 0 to 15;
signal scan: std_logic_vector(3 downto 0);
signal clk_count: std_logic_vector(8 downto 0):= “000000000”;
begin
digit <= bit_data(3 downto 0) when scan(0) = ‘0’
else bit_data(7 downto 4) when scan(1) = ‘0’
else bit_data(11 downto 8) when scan(2) = ‘0’
else bit_data(15 downto 12) when scan(3) = ‘0’
else “0000”;
index <= conv_integer(digit);
LCD <= not hex_display1(index);
enable_0 <= scan(3); enable_1 <= scan(2); enable_2 <= scan(1); enable_3 <= scan(0);
process(int_clk)
begin
if int_clk’event and int_clk = ‘1’ then
if not((scan = “1110”) or (scan = “1101”) or (scan = “1011”) or (scan = “0111”))
then scan <= “0111”; end if; -- auto-intialize scan register
if clk_count = 0 then scan <= scan(0)&scan(3 downto 1); end if;
clk_count <= clk_count + 1;
end if;
end process;
end output_hex_display;
Note: For consistency with the input to this hex-display module, we have added three
initial 0’s to the 13-bit product in each of the solutions for Problems 20.N, 20.O, 20.P and
20.Q.
335
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
No Counter:
20.N
20N without counter
Accumulator[13:0]
7
"000"
3
6 bit Adder
6 0
Multiplicand[5:0]
Sh
S15
-
Ld2
S13
-
St
Ad
S1
done
-
S11
S10
Ad
-
M'
Sh
M'
Sh
Sh
M
S9
S6
S8
Ad
Control
Rst
St
Ad
S3
M'
Sh
-
Sh
M
M'
Sh
M'
Sh
M
M
S4
S12
Sh
done
Ld2
S2
20N without counter
M'
Sh
M
Ld1
M'
Sh
Ad
product
Clk
Clk
S14
Sh
M
S16
-
S0
13
16
St'
0
M
Ld1
Sh
Ad
Multiplier[6:0]
InBus
-
7
-
M
Sh
Sh
S5
Ad
S7
-- 20N multiplier 6 x 7 (no counter)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity multiplier is
port (Clk: in std_logic;
St: in std_logic;
Rst: in std_logic;
done: out std_logic;
InBus: in std_logic_vector(7 downto 0);
int_clk: in std_logic;
hex_out: out std_logic_vector(6 downto 0);
e0,e1,e2,e3: out std_logic);
end multiplier;
architecture control1 of multiplier is
signal state, nextstate: integer range 0 to 16;
signal mcand: std_logic_vector(5 downto 0);
signal acc: std_logic_vector(13 downto 0);
alias M: std_logic is acc(0);
signal addout: std_logic_vector(6 downto 0);
signal Ld1, Ld2, Ad, Sh: std_logic;
signal product: std_logic_vector(15 downto 0);
-- add component declaration for hex_display here
336
Ad
-- 20N multiplier 6 x 7 (no counter) (cont.)
begin
-- hex: hex_display port map(product, hex_out, int_clk,
-- e0, e1, e2, e3);
product <= “000” & acc(12 downto 0);
addout <= (‘0’ & acc(12 downto 7)) + mcand;
process(state,St,M)
begin
Ld1 <= ‘0’; Ld2 <= ‘0’; Sh <= ‘0’; Ad <=’0’;done <= ‘0’;
case state is
when 0 =>
if St = ‘1’ then Ld1 <= ‘1’; nextstate <= 1;
else nextstate <=0; end if;
when 1 =>
Ld2 <= ‘1’; nextstate <= 2;
when 2|4|6|8|10|12|14 =>
if M = ‘1’ then Ad <= ‘1’; nextstate <= state+1;
else Sh <= ‘1’; nextstate <= state +2; end if;
when 3|5|7|9|11|13|15 =>
Sh <= ‘1’; nextstate <= state + 1;
when 16 =>
done <= ‘1’; nextstate <= 0;
end case;
end process;
process(Clk,Rst)
begin
if Rst = ‘1’ then
state <= 0; acc(13 downto 7) <= “0000000”;
elsif Clk’event and Clk = ‘1’ then
if Ld1 = ‘1’ then
acc(6 downto 0) <= InBus(6 downto 0); end if;
if Ld2 = ‘1’ then mcand <= InBus(5 downto 0); end if;
if Ad = ‘1’ then acc(13 downto 7) <= addout; end if;
if Sh = ‘1’ then acc <= ‘0’ & acc(13 downto 1); end if;
state <= nextstate;
end if;
end process;
end control1;
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
20.N
(cont.)
With Counter:
7
Multiplier[6:0]
InBus
"000"
3
6 bit Adder
Ld2
-
St
S0
Ld1
done
S4
S1
kM'
Sh
Sh
-
k'
Sh
Ld2
S2
S3
M
Ad
k'M'
Sh
20N with counter
-- 20N with counter
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity multiplier is
port (Clk: in std_logic;
St: in std_logic;
Rst : in std_logic;
done: out std_logic;
InBus: in std_logic_vector(7 downto 0);
int_clk: in std_logic;
hex_out: out std_logic_vector(6 downto 0);
e0,e1,e2,e3: out std_logic);
end multiplier;
architecture control1 of multiplier is
signal state, nextstate : integer range 0 to 4;
signal Mcand: std_logic_vector(5 downto 0);
signal count: std_logic_vector(2 downto 0);
signal acc: std_logic_vector(13 downto 0);
alias M: std_logic is acc(0);
signal addout: std_logic_vector(6 downto 0);
signal Ld1, Ld2, Ad, Sh, k: std_logic;
signal product: std_logic_vector(15 downto 0);
-- the component declaration for the
-- hex_display goes here
337
M
done
product
20N with counter
St'
0
Clk
13
16
Multiplicand[5:0]
6
k
Sh
Ld1
Ad
Accumulator[13:0]
7
Control
Rst
St
k
Clk
Counter
-- 20N with counter (cont.)
begin
-- hex: hex_display port map(product, hex_out, int_Clk,
-- e0, e1, e2 ,e3);
product <= “000” & acc(12 downto 0);
addout <= (‘0’ & acc(12 downto 7)) + Mcand;
k <= ‘1’ when count = “110” else ‘0’;
process(state,St,M,k)
begin
Ld1 <= ‘0’; Ld2 <= ‘0’; Sh <= ‘0’; ad <=’0’; done <= ‘0’;
case state is
when 0 =>
if St = ‘1’ then Ld1 <= ‘1’; nextstate <= 1;
else nextstate <=0; end if;
when 1 =>
Ld2 <= ‘1’; nextstate <= 2;
when 2 =>
if M = ‘1’ then Ad <= ‘1’; nextstate <=3;
elsif k = ‘0’ then Sh <= ‘1’; nextstate <=2;
else Sh <= ‘1’; nextstate <= 4; end if;
when 3 =>
if k = ‘0’ then Sh <= ‘1’; nextstate <= 2;
else Sh <= ‘1’; nextstate <= 4; end if;
when 4 =>
done <= ‘1’; nextstate <= 0;
end case;
end process;
process(Clk,Rst)
begin
if Rst = ‘1’ then
count <= “000”; state <= 0;
acc(13 downto 7) <= “0000000”;
elsif Clk’event and Clk = ‘1’ then
if Ld1 = ‘1’ then Mcand <= InBus(5 downto 0); end if;
if Ld2 = ‘1’ then
acc(6 downto 0) <= InBus(6 downto 0); end if;
if Ad = ‘1’ then acc(13 downto 7) <= addout; end if;
if Sh = ‘1’ then
acc <= ‘0’ & acc(13 downto 1);
count <= count +1; end if;
state <= nextstate;
end if;
end process;
end control1;
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
No Counter:
20.O
20O without counter
6
Accumulator[13:0]
7
Ld1
Sh
Ad
Multiplier[5:0]
InBus
"000"
3
7 bit Adder
16
Multiplicand[6:0]
7
13
Ld2
product
Clk
M
Control
St
Clk
St'
0
-
Sh
S13
S14
M
-
S11
-
S1
done
Ld2
Ad
S10
-
M
S2
Ad
M'
Sh
M'
Sh
M
-
20O without counter
S12
-
M'
Sh
S8
S9
M
Ad
S4
M'
Sh
M'
Sh
Sh
S6
M
Sh
done
Ld1
M'
Sh
Ad
Sh
St
S0
Rst
S3
Sh
M
-
Ad
S5
Sh
Ad
S7
-- 20O without counter
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity multiplier is
port (Clk: in std_logic;
St: in std_logic;
Rst: in std_logic;
done: out std_logic;
InBus: in std_logic_vector(7 downto 0);
int_clk: in std_logic;
hex_out: out std_logic_vector(6 downto 0);
e0,e1,e2,e3: out std_logic);
end multiplier;
architecture control1 of multiplier is
signal state, nextstate: integer range 0 to 14;
signal mcand: std_logic_vector(6 downto 0);
signal acc: std_logic_vector(13 downto 0);
signal addout: std_logic_vector(7 downto 0);
alias M: std_logic is acc(0);
signal Ld1, Ld2, Ad, Sh: std_logic;
signal product: std_logic_vector(15 downto 0);
-- component declaration for hex_display goes here
338
-- 20O without counter (cont.)
begin
--hex: hex_display port map(product, hex_out, int_clk,
-- e0, e1, e2, e3);
product <= “000” & acc(12 downto 0);
addout <= (‘0’ & acc(12 downto 6)) + mcand;
process(state,St,M)
begin
Ld1 <= ‘0’; Ld2 <= ‘0’; Sh <= ‘0’; Ad <=’0’; done <= ‘0’;
case state is
when 0 =>
if St = ‘1’ then Ld1 <= ‘1’; nextstate <= 1;
else nextstate <=0; end if;
when 1 =>
Ld2 <= ‘1’; nextstate <= 2;
when 2|4|6|8|10|12 =>
if M = ‘1’ then Ad <= ‘1’; nextstate <=state+1;
else Sh <= ‘1’; nextstate <= state +2; end if;
when 3|5|7|9|11|13 =>
Sh <= ‘1’; nextstate <= state +1;
when 14 =>
done <= ‘1’; nextstate <= 0;
end case;
end process;
process(Clk,Rst)
begin
if Rst = ‘1’ then
state <= 0; acc(13 downto 6) <= “00000000”;
elsif Clk’event and Clk = ‘1’ then
if Ld1 = ‘1’ then
acc(5 downto 0)<= InBus(5 downto 0); end if;
if Ld2 = ‘1’ then mcand <= InBus(6 downto 0); end if;
if Ad = ‘1’ then acc(13 downto 6) <= addout; end if;
if Sh = ‘1’ then acc <= ‘0’ & acc(13 downto 1); end if;
state <= nextstate;
end if;
end process;
end control1;
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
20.O
(cont.)
With Counter:
20O with counter
6
Sh
Ld1
Ad
Accumulator[13:0]
7
Multiplier[5:0]
InBus
"000"
3
7 bit Adder
16
Multiplicand[6:0]
7
13
Ld2
Clk
M
done
product
Control
Rst
St
k
Clk
St'
0
-
St
S0
Ld1
done
S4
k
S1
kM'
Sh
Sh
-
k'
Sh
Ld2
S2
S3
M
Ad
k'M'
Sh
20O with counter
-- 20O with counter
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity multiplier is
port (Clk: in std_logic;
St: in std_logic;
Rst: in std_logic;
done: out std_logic;
InBus: in std_logic_vector(7 downto 0);
int_clk: in std_logic;
hex_out: out std_logic_vector(6 downto 0);
product: out std_logic_vector(15 downto 0);
e0,e1,e2,e3: out std_logic);
end multiplier;
architecture control1 of multiplier is
signal state, nextstate: integer range 0 to 4;
signal Mcand: std_logic_vector(6 downto 0);
signal count: std_logic_vector(2 downto 0);
signal acc: std_logic_vector(13 downto 0);
alias M: std_logic is acc(0);
signal addout: std_logic_vector(7 downto 0);
signal Ld1, Ld2, Ad, Sh, k: std_logic;
signal product: std_logic_vector(15 downto 0);
-- component declaration for hex_display goes here
339
Counter
-- 20O with counter (cont.)
begin
-- hex: hex_display port map(product, hex_out, int_clk,
-- e0, e1, e2, e3);
product <= “000” & acc(12 downto 0);
addout <= (‘0’ & acc(12 downto 6)) + Mcand;
k <= ‘1’ when count = “101” else ‘0’;
process(state,St,M,k)
begin
Ld1 <= ‘0’; Ld2 <= ‘0’; Sh <= ‘0’; Ad <=’0’;done <= ‘0’;
case state is
when 0 =>
if St = ‘1’ then Ld1 <= ‘1’; nextstate <= 1;
else nextstate <=0; end if;
when 1 =>
Ld2 <= ‘1’; nextstate <= 2;
when 2 =>
if M = ‘1’ then Ad <= ‘1’; nextstate <=3;
elsif k = ‘0’ then Sh <= ‘1’; nextstate <=2;
else Sh <= ‘1’; nextstate <= 4; end if;
when 3 =>
if k = ‘0’ then Sh <= ‘1’; nextstate <= 2;
else Sh <= ‘1’; nextstate <= 4; end if;
when 4 =>
done <= ‘1’; nextstate <= 0;
end case;
end process;
process(Clk,Rst)
begin
if Rst = ‘1’ then
count <= “000”; state <= 0;
acc(13 downto 6) <= “00000000”;
elsif Clk’event and Clk = ‘1’ then
if Ld1 = ‘1’ then Mcand <= InBus(6 downto 0); end if;
if Ld2 = ‘1’ then
acc(5 downto 0) <= InBus (5 downto 0); end if;
if Ad = ‘1’ then acc(13 downto 6) <= addout; end if;
if Sh = ‘1’ then acc <= ‘0’ & acc(13 downto 1);
count <= count +1; end if;
state <= nextstate;
end if;
end process;
end control1;
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
No Counter:
20.P
20P without counter
8
5
Ld1
Sh
Ad
Accumulator[13:0]
InBus
Multiplier[4:0]
"000"
3
8 bit Adder
16
Multiplicand[7:0]
8
13
Ld2
Clk
M
product
Control
St
Clk
-- 20P without counter (cont.)
St'
0
-
S0
-
Sh
Ld1
done
S1
S12
S11
M
St
-
Ld2
M'
Sh
Ad
S10
-
20P without counter
S9
S8
M
Ad
-
M
Ad
M'
Sh
M'
Sh
Sh
S2
M'
Sh
M'
Sh
S6
Sh
S7
M
-
M
Ad
-
S4
S3
Sh
Ad
Sh
S5
-- 20P without counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity lab20PwithoutCounter is
port (Clk, St, Rst: in std_logic;
InBus: in std_logic_vector( 6 downto 0 );
done: out std_logic;
-- signals for hex display
int_clk: in std_logic;
hex_out: out std_logic_vector( 6 downto 0 );
e0, e1, e2, e3: out std_logic );
end lab20PwithoutCounter;
architecture behavioral of lab20PwithoutCounter is
signal state, nextstate: integer range 0 to 12;
signal mcand: std_logic_vector( 7 downto 0 );
signal acc: std_logic_vector( 13 downto 0);
signal addout: std_logic_vector( 8 downto 0 );
signal product : std_logic_vector( 15 downto 0 );
alias M: std_logic is acc(0);
signal Ld1, Ld2, Sh, Ad: std_logic;
-- hex_display component
340
Rst
done
component hex_display
port(bit_data: in std_logic_vector(15 downto 0);
LCD: out std_logic_vector( 6 downto 0);
int_clk: in std_logic; enable_0, enable_1,
enable_2, enable_3: out std_logic);
end component;
begin
-- comment this line when simulating
hex: hex_display port map ( product, hex_out, int_clk,
e0, e1, e2, e3 );
product <= “000” & acc(12 downto 0);
-- we need 13 bits for 8 bit x 5 bit
addout <= (‘0’ & acc(12 downto 5 ) ) + mcand;
process ( state, St, M) begin
Ld1 <= ‘0’; Ld2 <= ‘0’; Sh <= ‘0’; Ad <= ‘0’; done <= ‘0’;
case state is
when 0 =>
if st = ‘1’ then Ld1 <= ‘1’; nextstate <= 1;
else nextstate <= 0; end if;
when 1 => Ld2 <= ‘1’; nextstate <= 2;
when 2|4|6|8|10 =>
if M = ‘1’ then Ad <= ‘1’; nextstate <= state + 1;
else Sh <= ‘1’; nextstate <= state + 2; end if;
when 3|5|7|9|11 =>
Sh <= ‘1’; nextstate <= state + 1;
when 12 =>
done <= ‘1’; nextstate <= 0;
end case;
end process;
process ( Clk, Rst ) begin
if ( Rst = ‘1’ ) then state <= 0;
acc <= (others => ‘0’ ); mcand <= (others => ‘0’ );
elsif ( Clk = ‘1’ and Clk’event ) then
state <= nextstate;
if( Ld1 = ‘1’ ) then
acc(4 downto 0) <= InBus(4 downto 0); end if;
if( Ld2 = ‘1’ ) then mcand <= InBus( 7 downto 0 ); end if;
if( Ad = ‘1’ ) then acc( 13 downto 5 ) <= addout; end if;
if( Sh = ‘1’ ) then
acc <= ‘0’ & acc ( 13 downto 1 ); end if;
end if;
end process;
end behavioral;
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
20.P
(cont.)
With Counter:
20P with counter
8
5
Accumulator[13:0]
Sh
Ld1
Ad
Multiplier[4:0]
InBus
"000"
3
8 bit Adder
16
Multiplicand[7:0]
8
Ld2
Clk
13
M
done
product
Control
Rst
St
k
Clk
St'
0
Counter
-- 20P with counter (cont.)
St
begin
-- comment this line when simulating
done
hex: hex_display port map ( product, hex_out, int_clk,
S4
e0, e1, e2, e3 );
S1
product <= “000” & acc(12 downto 0);
kM'
Sh
-- we need 13 bits for 8 bit x 5 bit
k
Ld2
addout
<=
(‘0’
&
acc(12
downto 5 ) ) + mcand;
Sh
k'
Sh
k <= ‘1’ when count = 4 else ‘0’;
process ( state, St, M, k ) begin
S2
S3
Ld1 <= ‘0’; Ld2 <= ‘0’; Sh <= ‘0’; Ad <= ‘0’; done <= ‘0’;
case
state is
k'M'
M
Ad
Sh
when 0 =>
if ( St = ‘1’ ) then Ld1 <= ‘1’; nextstate <= 1;
-- 20P with counter
else nextstate <= 0; end if;
when 1 =>
library ieee;
Ld2 <= ‘1’; nextstate <= 2;
use ieee.std_logic_1164.all;
when 2 =>
use ieee.std_logic_arith.all;
if ( M = ‘1’ ) then Ad <= ‘1’; nextstate <= 3;
use ieee.std_logic_unsigned.all;
elsif ( k = ‘1’ ) then Sh <= ‘1’; nextstate <= 4;
entity lab20PwithCounter is
else Sh <= ‘1’; nextstate <= 2; end if;
port (Clk, St, Rst: in std_logic;
when 3 =>
InBus: in std_logic_vector( 7 downto 0 );
Sh <= ‘1’;
done: out std_logic;
if ( k = ‘1’ ) then nextstate <= 4;
-- signals for hex display
else nextstate <= 2; end if;
int_clk: in std_logic;
when 4 => done <= ‘1’; nextstate <= 0;
hex_out: out std_logic_vector( 6 downto 0 );
end case;
e0, e1, e2, e3: out std_logic );
end process;
end lab20PwithCounter;
process ( Clk, Rst ) begin
architecture behavioral of lab20PwithCounter is
if ( Rst = ‘1’ ) then state <= 0; count <= “000”;
signal state, nextstate: integer range 0 to 4;
acc <= (others => ‘0’ ); mcand <= (others => ‘0’ );
signal mcand: std_logic_vector( 7 downto 0 );
elsif ( Clk = ‘1’ and Clk’event ) then
signal count : std_logic_vector( 2 downto 0 );
state <= nextstate;
signal acc: std_logic_vector( 13 downto 0) ;
if(Ld1 = ‘1’) then
signal addout: std_logic_vector( 8 downto 0 ) ;
acc(4 downto 0) <= InBus(4 downto 0); end if;
signal product: std_logic_vector( 15 downto 0 );
if( Ld2 = ‘1’ ) then
alias M: std_logic is acc(0);
mcand <= InBus( 7 downto 0 ); end if;
signal Ld1, Ld2, Sh, Ad, k: std_logic;
if( Ad = ‘1’ ) then
-- hex_display component
acc(13 downto 5) <= addout; end if;
component hex_display
if( Sh = ‘1’ ) then acc <= ‘0’ & acc ( 13 downto 1 );
port( bit_data: in std_logic_vector(15 downto 0);
count <= count + 1; end if;
LCD: out std_logic_vector( 6 downto 0);
end if;
int_clk: in std_logic;
end process;
enable_0, enable_1, enable_2, enable_3: out std_logic);
end behavioral;
end component;
-
S0
Ld1
20P with counter
341
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
No Counter:
20.Q
20Q without counter
8
8
Ld1
Sh
Ad
Accumulator[13:0]
InBus
Multiplier[7:0]
"000"
3
5 bit Adder
16
Multiplicand[4:0]
5
13
Ld2
product
Clk
M
done
Control
Rst
St
Clk
St'
0
St
Ld1
S0
-
S17
M
S18
S1
done
-
Ld2
M
S3
M'
Sh
S16
20Q without counter
Sh
M'
Sh
-
-
S13
Ad
-
S6
M'
Sh
S12
M
M
Ad
M'
Sh
M'
Sh
Sh
Sh
S4
S14
Ad
Ad
S2
M'
Sh
S15
M
Sh
Ad
-
-
-
M'
Sh
S10
Sh
S11
M
Ad
S8
M'
Sh
Sh
M
M
S5
Sh
Sh
Ad
S7
Ad
S9
-- 20Q without counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity lab20QwithoutCounter is
port (clk, st, Rst: in std_logic;
InBus: in std_logic_vector( 7 downto 0 );
done: out std_logic;
-- signals for hex display
int_clk: in std_logic;
hex_out: out std_logic_vector( 6 downto 0 );
e0, e1, e2, e3: out std_logic);
end lab20QwithoutCounter;
architecture behavioral of lab20QwithoutCounter is
signal state, nextstate: integer range 0 to 18;
signal mcand: std_logic_vector( 4 downto 0 );
signal acc: std_logic_vector( 13 downto 0) ;
signal addout: std_logic_vector( 5 downto 0 ) ;
signal product: std_logic_vector( 15 downto 0 );
alias m: std_logic is acc(0);
signal ld1, ld2, sh, ad: std_logic;
-- hex_display component
342
-- 20Q without counter (cont.)
component hex_display
port( bit_data: in std_logic_vector(15 downto 0);
LCD: out std_logic_vector( 6 downto 0);
int_clk: in std_logic;
enable_0, enable_1, enable_2, enable_3: out std_logic );
end component;
begin
-- comment this line when simulating
hex: hex_display port map ( product, hex_out, int_clk,
e0, e1, e2, e3 );
product <= “000” & acc(12 downto 0);
-- we need 13 bits for 5 bit x 8 bit
addout <= (‘0’ & acc(12 downto 8 ) ) + mcand;
process ( state, st, m ) begin
ld1 <= ‘0’; ld2 <= ‘0’; sh <= ‘0’; ad <= ‘0’; done <= ‘0’;
case state is
when 0 =>
if ( st = ‘1’ ) then ld1 <= ‘1’; nextstate <= 1;
else nextstate <= 0; end if;
when 1 =>
ld2 <= ‘1’; nextstate <= 2;
when 2|4|6|8|10|12|14|16 =>
if ( m = ‘1’ ) then ad <= ‘1’; nextstate <= state + 1;
else sh <= ‘1’; nextstate <= state + 2; end if;
when 3|5|7|9|11|13|15|17 =>
sh <= ‘1’; nextstate <= state + 1;
when 18 =>
done <= ‘1’; nextstate <= 0;
end case;
end process;
process ( clk, Rst ) begin
if ( Rst = ‘1’ ) then state <= 0;
acc <= (others => ‘0’ ); mcand <= (others => ‘0’ );
elsif ( clk = ‘1’ and clk’event ) then
state <= nextstate;
if( ld1 = ‘1’ ) then
acc(7 downto 0) <= InBus(7 downto 0); end if;
if( ld2 = ‘1’ ) then mcand <= InBus( 4 downto 0 ); end if;
if( ad = ‘1’ ) then acc( 13 downto 8 ) <= addout; end if;
if( sh = ‘1’ ) then acc <= ‘0’ & acc (13 downto 1); end if;
end if;
end process;
end behavioral;
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
20.Q
(cont.)
With Counter:
20Q with counter
8
8
Sh
Ld1
Ad
Accumulator[13:0]
Multiplier[7:0]
InBus
"000"
3
5 bit Adder
16
Multiplicand[4:0]
5
13
Ld2
Clk
M
done
product
Control
Rst
St
k
Clk
St'
0
-
St
S0
Ld1
done
S4
k
S1
kM'
Sh
Sh
-
k'
Sh
Ld2
S2
S3
M
Ad
Counter
-- 20Q with counter (cont.)
begin
-- comment this line when simulating
hex: hex_display port map ( product, hex_out, int_clk,
e0, e1, e2, e3 );
product <= “000” & acc(12 downto 0);
-- we need 13 bits for 5 bit x 8 bit
addout <= (‘0’ & acc(12 downto 8 ) ) + mcand;
k <= ‘1’ when count = 7 else ‘0’;
k'M'
Sh
20Q with counter
-- 20Q with counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity lab20QwithCounter is
port (clk, st, Rst: in std_logic;
InBus: in std_logic_vector( 7 downto 0 );
done: out std_logic;
-- signals for hex display
int_clk: in std_logic;
hex_out: out std_logic_vector( 6 downto 0 );
e0, e1, e2, e3: out std_logic );
end lab20QwithCounter;
process ( state, st, m, k ) begin
ld1 <= ‘0’; ld2 <= ‘0’; sh <= ‘0’; ad <= ‘0’; done <= ‘0’;
case state is
when 0 =>
if ( st = ‘1’ ) then ld1 <= ‘1’; nextstate <= 1;
else nextstate <= 0; end if;
when 1 => ld2 <= ‘1’; nextstate <= 2;
when 2 =>
if ( m = ‘1’ ) then ad <= ‘1’; nextstate <= 3;
elsif ( k = ‘1’ ) then h <= ‘1’; nextstate <= 4;
else sh <= ‘1’; nextstate <= 2; end if;
when 3 =>
sh <= ‘1’;
if ( k = ‘1’ ) then nextstate <= 4;
else nextstate <= 2; end if;
when 4 =>
done <= ‘1’; nextstate <= 0;
end case;
end process;
architecture behavioral of lab20QwithCounter is
process ( clk, Rst ) begin
signal state, nextstate: integer range 0 to 4;
if ( Rst = ‘1’ ) then state <= 0; count <= “000”;
signal mcand: std_logic_vector( 4 downto 0 );
acc <= (others => ‘0’); mcand <= (others => ‘0’);
signal count: std_logic_vector( 2 downto 0 );
elsif ( clk = ‘1’ and clk’event ) then
signal acc: std_logic_vector( 13 downto 0) ;
state <= nextstate;
signal addout: std_logic_vector( 5 downto 0 ) ;
if(ld1 = ‘1’) then
signal product: std_logic_vector( 15 downto 0 );
acc(7 downto 0) <= InBus(7 downto 0); end if;
alias m: std_logic is acc(0);
if( ld2 = ‘1’ ) then
signal ld1, ld2, sh, ad, k: std_logic;
mcand <= InBus( 4 downto 0 ); end if;
--hex_display component
if( ad = ‘1’ ) then
component hex_display
acc( 13 downto 8 ) <= addout; end if;
port( bit_data: in std_logic_vector(15 downto 0);
if( sh = ‘1’ ) then acc <= ‘0’ & acc ( 13 downto 1 );
LCD: out std_logic_vector( 6 downto 0);
count <= count + 1; end if;
int_clk: in std_logic;
end if;
enable_0, enable_1, enable_2, enable_3: out std_logic ); end process;
end component;
end behavioral;
343
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
20.R
No Counter:
20R
6
Dividend[10:0]
Remainder[4:0]
Clk
6
5 bit Subtractor
Bus_in
0
Overflow
Logic
divisor[3:0]
S9
Su
C'
-
St
S0
-
ovf
V
-
Su
ovf'
sh
20R
S3
S7
C'
C'
Sh
C
Su
C
Sh
S4
S6
C'
S5
Sh
C
St
V
-- 20R divider 6 / 4 bits to 6 bit quotient (cont.)
Ld2
S2
S8
C
done
Rst
Ld1
S1
done
Sh
Control
Clk
St'
0
C
ovf
Ld2
4
C'
Sh
Ld1
Su
Quotient [5:0]
C'
C
Sh
Su
Su
-- 20R divider 6 / 4 bits to 6 bit quotient
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity divider_20R is
Port( Bus_in: in std_logic_vector(5 downto 0);
Clk, St, Rst: in std_logic;
done, V: out std_logic;
Quotient: out std_logic_vector(5 downto 0);
Remainder: out std_logic_vector(4 downto 0));
end divider_20R;
architecture Behavioral_20R of divider_20R is
signal State, NextState: integer range 0 to 9;
signal C, Ld1, Ld2, Su, Sh, ovf: std_logic;
signal Subout: std_logic_vector(4 downto 0);
signal Dividend: std_logic_vector(10 downto 0);
signal Divisor: std_logic_vector(3 downto 0);
begin
ovf <= ‘1’ when Divisor = “0000” else ‘0’;
Subout <= Dividend(10 downto 6) - (‘0’ & Divisor);
C <= not Subout(4);
Remainder <= Dividend(10 downto 6);
Quotient <= Dividend (5 downto 0);
344
Su
process(St, State, C)
begin
Ld1 <= ‘0’; Ld2 <= ‘0’; Sh <= ‘0’; Su <= ‘0’; V <= ‘0’;
done <= ‘0’;
case State is
when 0 =>
if St = ‘1’ then Ld1 <= ‘1’; NextState <= 1;
else NextState <= 0; end if;
when 1 =>
Ld2 <= ‘1’; NextState <= 2;
when 2 =>
if(ovf = ‘0’) then Sh <= ‘0’; V<= ‘1’; NextState <= 0;
else Sh <= ‘1’; V<= ‘0’; NextState <= 3; end if;
when 3|4|5|6|7 =>
if C = ‘1’ then Su <= ‘1’; NextState <= state;
else Sh <= ‘1’; NextState <= state + 1; end if;
when 8 =>
NextState <= 9;
if C = ‘1’ then Su <= ‘1’;
else Su <= ‘0’; end if;
when 9 =>
NextState <= 0; done <= ‘1’;
end case;
end process;
process(Clk, Rst)
begin
if Rst = ‘1’ then State <= 0;
elsif Clk’event and Clk = ‘1’ then
State <= NextState;
if Ld1 = ‘1’ then
Dividend <= “00000”&Bus_in(5 downto 0); end if;
if Ld2 = ‘1’ then
Divisor <= Bus_in(3 downto 0); end if;
if Su = ‘1’ then
Dividend(10 downto 6) <= Subout(4 downto 0);
Dividend(0) <= ‘1’; end if;
if Sh = ‘1’ then
Dividend <= Dividend(9 downto 0) & ‘0’; end if;
end if;
end process;
end Behavioral_20R;
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
20.S
No Counter:
20S
7
Sh
Ld1
Su
dividend[10:0]
quotient [6:0]
remainder[3:0]
Clk
7
4 bit Subtractor
Bus_in
0
Overflow
Logic
divisor[2:0]
ovf
Control
Ld2
3
done
Rst
St
Clk
V
St'
0
-
C
C
Su
S0
St
Su
C'
Ld1
S1
S10
S9
C'
done
-
ovf
V
-- 20S divider 7 / 3 bits to 7-bit quotient (cont.)
Ld2
S2
-
20S
Sh
C'
S4
Sh
C
Su
S7
C'
Sh
S6
C
C
S3
S8
C'
ovf'
sh
C'
S5
C'
Sh
C
Su
Sh
C
Su
Sh
Su
Su
-- 20S divider 7 / 3 bits to 7-bit quotient
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity divider_20S is
Port( Bus_in: in std_logic_vector(6 downto 0);
Clk, St, Rst: in std_logic;
done, v: out std_logic;
Quotient: out std_logic_vector(6 downto 0);
Remainder: out std_logic_vector(2 downto 0));
end divider_20S;
architecture Behavioral_20S of divider_20S is
signal State, NextState: integer range 0 to 10;
signal C, Ld1, Ld2, Su, Sh, ovf: std_logic;
signal Subout: std_logic_vector(3 downto 0);
signal Dividend: std_logic_vector(10 downto 0);
signal Divisor: std_logic_vector(2 downto 0);
begin
ovf <= ‘1’ when Divisor = “000” else ‘0’;
Subout <= Dividend(10 downto 7) - (‘0’ & Divisor);
C <= not Subout(3);
Remainder <= Dividend(9 downto 7);
Quotient <= Dividend (6 downto 0);
345
process(St, State, C)
begin
Ld1 <= ‘0’; Ld2 <= ‘0’; Sh <= ‘0’; Su <= ‘0’;
v <= ‘0’; done <= ‘0’;
case State is
when 0 =>
if St = ‘1’ then Ld1 <= ‘1’; NextState <= 1;
else NextState <= 0; end if;
when 1 =>
Ld2 <= ‘1’; NextState <= 2;
when 2 =>
if(ovf = ‘0’) then Sh <= ‘0’; v<= ‘1’; NextState <= 3;
else Sh <= ‘1’; v<= ‘0’; NextState <= 3; end if;
when 3|4|5|6|7|8 =>
if C = ‘1’ then Su <= ‘1’; NextState <= state;
else Sh <= ‘1’; NextState <= state + 1; end if;
when 9 =>
NextState <= 10;
if C = ‘1’ then Su <= ‘1’;
else Su <= ‘0’; end if;
when 10 =>
NextState <= 0; done <= ‘1’;
end case;
end process;
process(Clk, Rst)
begin
if Rst = ‘1’ then State <= 0;
elsif Clk’event and Clk = ‘1’ then
State <= NextState;
if Ld1 = ‘1’ then
Dividend <= “0000”&Bus_in(6 downto 0); end if;
if Ld2 = ‘1’ then
Divisor <= Bus_in(2 downto 0); end if;
if Su = ‘1’ then
Dividend(10 downto 7) <= Subout(3 downto 0);
Dividend(0) <= ‘1’; end if;
if Sh = ‘1’ then
Dividend <= Dividend(9 downto 0) & ‘0’; end if;
end if;
end process;
end Behavioral_20S;
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
20.T
No Counter:
Z[3:0]
"0000"
4
4
InBus
-
4
20T
4
-
Ld3
4
M
8 bit Adder
8
8
Multiplier[3:0]
8
4 bit Adder
Multiplicand[3:0]
-
Clk
Output
M
Sh
S10
Ad
St'
0
S0
S11
St
Ld1
S1
Rst
St
Ad
-
Ld2
S2
M'
Sh
20T
M
-
Sh
S6
Ld3
Ad
S4
M'
Sh
S7
-
S3
M'
Sh
M'
Sh
Sh
M
Clk
-- 20T - multiplier 4 x 4 + 4 bits
Ld4
S8
Control
Ld2
done
S9
Ld4 Ld1
Sh
Ad
Accumulator[8:0]
4
-
S12
S5
M
-
Sh
Ad
done
-- 20T - multiplier 4 x 4 + 4 bits (cont.)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity mult4X4 is
Port(Clk, St , Rst: in std_logic;
InBus: in std_logic_vector(3 downto 0);
done: out std_logic;
Output: out std_logic_vector(7 downto 0) );
end mult4X4;
case State is
when 0 =>
if St = ‘1’ then Ld1 <= ‘1’; NextState <= 1;
else NextState <= 0; end if;
when 1 =>
Ld2 <= ‘1’; NextState <= 2;
when 2 =>
Ld3 <= ‘1’; NextState <= 3;
when 3|5|7|9 =>
if M = ‘1’ then Ad <= ‘1’; NextState <= State + 1;
else Sh<= ‘1’; NextState <= State + 2; end if;
architecture Behavioral of mult4X4 is
when 4|6|8|10 =>
signal State, NextState: integer range 0 to 12;
Sh <= ‘1’; NextState <= State + 1;
signal ACC: std_logic_vector(8 downto 0);
when 11 =>
alias M: std_logic is ACC(0);
Ld4 <= ‘1’; NextState <= 12;
signal addout: std_logic_vector(4 downto 0);
when 12 =>
signal Z: std_logic_vector(3 downto 0);
done <= ‘1’; NextState <= 0;
signal adder2Output: std_logic_vector(7 downto 0);
end case;
signal Ld1, Ld2,Ld3,Ld4, Ad, Sh: std_logic;
end process;
signal Mcand: std_logic_vector(3 downto 0) ;
begin
process(Clk,Rst)
Output <= ACC(7 downto 0);
begin
adder2Output <= ACC(7 downto 0) + (“0000” & Z);
if Rst = ‘1’ then State <= 0;
addout <= (‘0’ & ACC(7 downto 4)) + Mcand;
elsif Clk’event and Clk = ‘1’ then
process(St, State,M)
if Ld1 = ‘1’ then
begin
ACC(8 downto 4) <= “00000”;
Ld1 <= ‘0’;Ld2 <= ‘0’;Ld3 <= ‘0’;Ld4 <= ‘0’;
ACC(3 downto 0) <= InBus(3 downto 0); end if;
Sh <= ‘0’;Ad <=’0’;done <= ‘0’;
if Ld2 = ‘1’ then Mcand <= InBus(3 downto 0); end if;
if Ld3 = ‘1’ then Z <= InBus(3 downto 0); end if;
if Ld4 = ‘1’ then
ACC (7 downto 0)<= adder2Output; end if;
if Ad = ‘1’ then ACC(8 downto 4) <= addout; end if;
if Sh = ‘1’ then
ACC <= ‘0’ & ACC(8 downto 1); end if;
State <= nextState;
end if;
end process;
end Behavioral;
346
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
No Counter:
20.U
-
5
20U
Z[4:0]
"000"
3
5
5
InBus
5
M
8 bit Adder
Multiplicand[2:0]
Output
Ld4
St
S0
Ld1
S1
-
Sh
Ld4 Ld1
Sh
Ad
-
M
Control
Ld2
Rst
St
Clk
Ad
M
M'
Sh
M'
Sh
M'
Sh
S9
Sh
M
M
S7
-
Sh
S5
S6
S8
Ad
S4
M'
Sh
-
Ld3
S3
20U
S10
M
-
M'
Sh
Sh
Clk
Ld2
S2
S11
8
3 bit Adder
done St'
0
S13
Ad
8
8
-
S12
Accumulator[8:0]
Multiplier[4:0]
3
-
Ld3
S14
Ad
Sh
Ad
done
-- 20U Multiplier 3 * 5 + 5 Bits
-- 20U Multiplier 3 * 5 + 5 Bits (cont.)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
case State is
when 0 =>
if St = ‘1’ then Ld1 <= ‘1’; NextState <= 1;
else NextState <= 0; end if;
when 1 =>
Ld2 <= ‘1’; NextState <= 2;
when 2 =>
Ld3 <= ‘1’; NextState <= 3;
when 3|5|7|9|11 =>
if M = ‘1’ then Ad <= ‘1’; NextState <= State + 1;
else Sh<= ‘1’; NextState <= State + 2; end if;
when 4|6|8|10|12 =>
Sh <= ‘1’; NextState <= State + 1;
when 13 =>
Ld4 <= ‘1’; NextState <= 14;
when 14 =>
done <= ‘1’; NextState <= 0;
end case;
end process;
process(Clk,Rst)
begin
if Rst = ‘1’ then State <= 0;
elsif Clk’event and Clk = ‘1’ then
if Ld1 = ‘1’ then
ACC(8 downto 5) <= “0000”;
ACC(4 downto 0) <= InBus(4 downto 0); end if;
if Ld2 = ‘1’ then
Mcand <= InBus(2 downto 0);end if;
if Ld3 = ‘1’ then Z <= InBus(4 downto 0); end if;
if Ld4 = ‘1’ then
ACC(7 downto 0) <= adder2Output; end if;
if Ad = ‘1’ then ACC(8 downto 5) <= addout; end if;
if Sh = ‘1’ then
ACC <= ‘0’ & ACC(8 downto 1); end if;
State <= nextState;
end if;
end process;
end Behavioral;
entity mult3X5 is
Port(Clk, St ,Rst: in std_logic;
InBus: in std_logic_vector(4 downto 0);
done: out std_logic;
Output: out std_logic_vector(7 downto 0) );
end mult3X5;
architecture Behavioral of mult3X5 is
signal State, NextState: integer range 0 to 14;
signal ACC: std_logic_vector(8 downto 0);
alias M: std_logic is ACC(0);
signal addout: std_logic_vector(3 downto 0);
signal Z: std_logic_vector(4 downto 0);
signal adder2Output: std_logic_vector(7 downto 0);
signal Ld1, Ld2,Ld3,Ld4, Ad, Sh: std_logic;
signal Mcand: std_logic_vector(2 downto 0);
begin
Output <= ACC(7 downto 0);
adder2Output <= ACC(7 downto 0) + (“000” & Z);
addout <= (‘0’ & ACC(7 downto 5)) + Mcand;
process(St, State,M)
begin
Ld1 <= ‘0’; Ld2 <= ‘0’; Ld3 <= ‘0’; Ld4 <= ‘0’ ;
Sh <= ‘0’; Ad <=’0’; done <= ‘0’;
347
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
No Counter:
20.V
S10
20V
"000"
3
InBus
Z[4:0]
-
M
Ld4 Ld1
Sh
Ad
Multiplier[2:0]
8
5 bit Adder
5
Multiplicand[4:0]
Output
M
Control
Clk
-- 20V - multiplier 5 x 3 + 5 bits
Ld1
Ad
Sh
M
S4
S6
S5
Ad
Ld2
-
Ld3
S3
M'
Sh
M'
Sh
-
S2
20V
M'
Sh
M
Rst
St
St
S1
Sh
-
Ld2
S0
S7
Clk
St'
0
S9
S8
Accumulator[8:0]
done
Ld4
Ld3
8 bit Adder
3
5
-
5
-
-
Ad
Sh
done
-- 20V - multiplier 5 x 3 + 5 bits (cont.)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity mult5X3 is
Port(Clk, St ,Rst: in std_logic;
InBus: in std_logic_vector(4 downto 0);
done: out std_logic;
Output: out std_logic_vector(7 downto 0) );
end mult5X3;
architecture Behavioral of mult5X3 is
signal State, NextState: integer range 0 to 10;
signal ACC: std_logic_vector(8 downto 0);
alias M: std_logic is ACC(0);
signal addout: std_logic_vector(5 downto 0);
signal Z: std_logic_vector(4 downto 0);
signal adder2Output: std_logic_vector(7 downto 0);
signal Ld1, Ld2,Ld3,Ld4, Ad, Sh: std_logic;
signal Mcand: std_logic_vector(4 downto 0) ;
begin
Output <= ACC (7 downto 0);
adder2Output <= ACC(7 downto 0) + (“000” & Z);
addout <= (‘0’ & ACC(7 downto 3)) + Mcand;
process(St, State,M)
begin
Ld1 <= ‘0’;Ld2 <= ‘0’;Ld3 <= ‘0’;Ld4 <= ‘0’;
Sh <= ‘0’;Ad <=’0’; done <= ‘0’;
case State is
when 0 =>
if St = ‘1’ then Ld1 <= ‘1’; NextState <= 1;
else NextState <= 0; end if;
when 1 =>
Ld2 <= ‘1’; NextState <= 2;
when 2 =>
Ld3 <= ‘1’; NextState <= 3;
when 3|5|7 =>
if M = ‘1’ then Ad <= ‘1’; NextState <= State + 1;
else Sh<= ‘1’; NextState <= State + 2; end if;
when 4|6|8 =>
Sh <= ‘1’; NextState <= State + 1;
when 9 =>
Ld4 <= ‘1’; NextState <= 10;
when 10 =>
done <= ‘1’; NextState <= 0;
end case;
end process;
process(Clk,Rst)
begin
if rst = ‘1’ then state <= 0;
elsif Clk’event and Clk = ‘1’ then
if Ld1 = ‘1’ then
ACC(8 downto 3) <= “000000”;
ACC(2 downto 0) <= InBus(2 downto 0); end if;
if Ld2 = ‘1’ then Mcand <= InBus(4 downto 0); end if;
if Ld3 = ‘1’ then Z <= InBus(4 downto 0); end if;
if Ld4 = ‘1’ then
ACC(7 downto 0) <= adder2Output; end if;
if Ad = ‘1’ then ACC(8 downto 3) <= addout; end if;
if Sh = ‘1’ then ACC <= ‘0’ & ACC(8 downto 1); end if;
State <= nextState;
end if;
end process;
end Behavioral;
348
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
20.W
No Counter:
20W
6
Z[5:0]
Ld3
"00"
2
8 bit Adder
6
6
InBus
Ld4 Ld1
Sh
Ad
Accumulator[8:0]
Multiplier[5:0]
8
2 bit Adder
2
Clk
Output
Multiplicand[1:0]
M
Control
Ld2
St
Clk
S16
-
M
-
Ld4
Ld1
-
S1
Ld2
-
S2
S14
M'
Sh
20W
-
Sh
Ad
-
Sh
S5
M'
Sh
M'
Sh
S11
M
S4
M'
Sh
S12
Ad
Ld3
S3
M'
Sh
Ad
-
S7
Ad
S9
-
S8
Sh
M
S6
M'
Sh
S10
M
done
-- 20W - multiplier 2 x 6 + 6 bits
St
S15
Sh
Sh
M
St'
0
S0
S13
-
done
Rst
M
Sh
Ad
349
Ad
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity mult2X6 is
Port(Clk, St ,Rst: in std_logic;
InBus: in std_logic_vector(5 downto 0);
done: out std_logic;
Output: out std_logic_vector(7 downto 0) );
end mult2X6;
architecture Behavioral of mult2X6 is
signal State, NextState: integer range 0 to 16;
signal ACC: std_logic_vector(8 downto 0);
alias M: std_logic is ACC(0);
signal addout: std_logic_vector(2 downto 0);
signal Z: std_logic_vector(5 downto 0);
signal adder2Output: std_logic_vector(7 downto 0);
signal Ld1, Ld2,Ld3,Ld4, Ad, Sh: std_logic;
signal Mcand: std_logic_vector(1 downto 0) ;
begin
Output <= ACC(7 downto 0);
adder2Output <= ACC(7 downto 0) + (“00” & Z);
addout <= (‘0’ & ACC(7 downto 6)) + Mcand;
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 20 Design Solutions
20.W
(cont.)
-- 20W - multiplier 2 x 6 + 6 bits (cont.)
process(St, State,M)
begin
Ld1 <= ‘0’; Ld2 <= ‘0’; Ld3 <= ‘0’; Ld4 <= ‘0’;
Sh <= ‘0’; Ad <=’0’; done <= ‘0’;
case State is
when 0 =>
if St = ‘1’ then Ld1 <= ‘1’; NextState <= 1;
else NextState <= 0; end if;
when 1 =>
Ld2 <= ‘1’; NextState <= 2;
when 2 =>
Ld3 <= ‘1’; NextState <= 3;
when 3|5|7|9|11|13 =>
if M = ‘1’ then Ad <= ‘1’; NextState <= State + 1;
else Sh <= ‘1’; NextState <= State + 2; end if;
when 4|6|8|10|12|14 =>
Sh <= ‘1’; NextState <= State + 1;
when 15 =>
Ld4 <= ‘1’; NextState <= 16;
when 16 =>
done <= ‘1’; NextState <= 0;
end case;
end process;
process(Clk,Rst)
begin
if Rst = ‘1’ then State <= 0;
elsif Clk’event and Clk = ‘1’ then
if Ld1 = ‘1’ then
ACC(8 downto 6) <= “000”;
ACC(5 downto 0) <= InBus(5 downto 0);
end if;
if Ld2 = ‘1’ then Mcand <= InBus(1 downto 0); end if;
if Ld3 = ‘1’ then Z <= InBus(5 downto 0); end if;
if Ld4 = ‘1’ then ACC(7 downto 0) <= adder2Output; end if;
if Ad = ‘1’ then ACC(8 downto 6) <= addout; end if;
if Sh = ‘1’ then ACC <= ‘0’ & ACC(8 downto 1); end if;
State <= nextState;
end if;
end process;
end Behavioral;
350
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
IV. SAMPLE UNIT TESTS
NAME
(signature)
PASSWORD
DATE
READINESS TEST - UNIT 1 - FORM A
Please answer the following questions carefully without any reference to outside notes. Check your answers before you turn in your paper since an essentially perfect score is required before you go on to the
next unit.
1. Multiply in binary: 11011
× 1011
2. Convert (7813.400)9 to hexadecimal (base 16). Carry out your answer to 3 places past the “point”.
3. Add the following numbers in binary. Use 2’s complement to represent negative numbers. Use a
word length of 5 bits (including sign). Indicate if an overflow occurs.
(a) 10 + 6
(b) −12 + (−14)
(c) −3 + (−12)
(d) 12 + (−15)
4. If possible, construct an 1-4-2-3 weighted code for decimal digits. If not possible, explain why. If
possible, express 673 decimal in 1-4-2-3 code.
5. Why are binary numbers used in digital computers?
351
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
NAME_______________________________PASSWORD__________DATE______________
(signature)
READINESS TEST - UNIT 2R - FORM A
(Issue a theorem sheet with this test)
1. Using a truth table, prove that
(XY)(X′ + Z′) = XYZ′
2. Simplify each of the following expressions
(A′C + B′ + DF′)[A + C′ + B′ + DF′] =
(AC + B′)(G + F + DE)(AC + B′)′ =
(X′ + Y′Z′ + 1)(X + Y)(X + Z) =
(A + B′C + 1)(B′ + C′ + BCF) =
PQ(M′N′P′ + NR + R′S′)R′ =
3. Factor as much as possible: (Your answer should be in product-of-sums form)
Z + XYQ + XYP =
4. Find D′ if D = (F′ + G′H)E.
5. Illustrate the following theorem using a network of switches.
X + YZ = (X + Y)(X + Z)
352
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
NAME______________________________ PASSWORD___________ DATE____________
(signature)
READINESS TEST - UNIT 3R - FORM A
1. Is the following statement always true? Justify your answer.
If ab′ + [b + b′(a + bc)]′ = [a + a′(ac + b)](a + b′), then a = b′
2. Factor as much as possible to obtain a product of sums:
WYZ + W′UV + W′Y′ + WV′
3. Each time you apply a theorem, mark your paper clearly to indicate which terms were used to add or delete
other terms, or indicate which terms were combined. Simplify algebraically: (answer should be a sum of 3
terms)
(A + B’ + C’ + D’)(B + C + D)(B’ + C’ + D’)(A’ + B + C + D)
4. Simplify to obtain a sum of 3 terms:
(A ≡ B’)(CD ⊕ B’) + ABCD
353
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
NAME
(signature)
PASSWORD
DATE
READINESS TEST - UNIT 4 - FORM A
1. A switching circuit has three inputs (A, B, C) and one output (Z). If A= 0, the output Z is the
exclusive-OR of B and C. If A = 1, the output is the equivalence of B and C.
(a) Find the truth table for Z.
(b) Write the minterm expansion for Z in decimal form and in terms of A, B, C.
(c) Write the maxterm expansion for Z in decimal form and in terms of A, B, C.
2. Without using a truth table, find (a) the minterm and maxterm expansions for F in algebraic and
decimal forms, and (b) the minterm and maxterm expansions for F' in decimal form.
F(A,B,C) = A + B'C'+ BC
3. Write an equation for the following sequence (use only 3 variables for the right-hand side) : The
overflow indicator V will turn on iff X is negative, Y is positive and D is positive, or if X is positive,
Y is negative and D is negative.
4. Design a 4-bit adder/subtracter using four full adders and four exclusive-OR gates. When Su = 1, the
circuit should output A - B, otherwise it should output A + B. Remember that B' = B ⊕ 1. (Assume
that negative numbers are represented in 2’s complement).
354
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
NAME _______________________________ PASSWORD _________ DATE __________
(signature)
READINESS TEST - UNIT 5R - FORM A*
1. F(a, b, c, d, e) = Σ m(0, 1, 2, 6, 7, 8, 16, 17, 19, 20, 25, 26, 29, 31) + Σ d(3, 5, 18, 27)
(a) Find the essential prime implicants of F and indicate the minterm which makes each one
essential.
(b) Find a minimum sum-of-products expression for F.
00
00
1
01
0
11
10
20
16
17
19
18
0
1
3
2
21
23
22
11
01
10
28
4
5
7
6
29
31
30
24
12
13
15
25
27
26
14
8
9
11
10
2. F(a, b, c, d) = Σ m(7, 11, 12, 14) + Σ d(0, 10)
(a) Find all of the prime implicants of F'.
(b) Find a minimum product-of-sums for F.
Note: F' is specified in (a) and F in (b).
355
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
NAME
(signature)
PASSWORD
DATE
READINESS TEST - UNIT 6 - FORM A
1. Find two different minimum sum-of-products expresstions for F using the Quine-McCluskey procedure:
F = ∑ m(2, 4, 5, 10, 11, 13, 14, 15) + ∑ d(1, 8)
Circle the essential prime implicants in your answer and specify the minterm(s) that make each one
essential.
2. What theorem is used when combining terms in the Quine-McCluskey procedure?
Why is is unnecessary to compare two terms which have the same number of 1’s (that is, why is it
unnecessary to compare two terms in the same group)?
3. Find a minimum sum of products for G using a 4-variable Karnaugh map.
G = A'BD' + A'C'D' + A'BDE + ABD'F + AC'D'F
(A'B'CD' is a don’t care term)
356
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
NAME ________________________________ PASSWORD ________DATE __________
(signature)
READINESS TEST - UNIT 7R - FORM A
1. Find a minimum 3-level NOR circuit to realize
f(A, B, C, D) = ∑ m(0, 2, 4, 6, 7, 9, 11, 12, 13, 15) (5 gates)
Do not use gate symbols with input bubbles in your final answer.
2. (a) Design a minimum 2-level NOR-NOR circuit to realize
f(X, Y, Z, W) = Σ m(5, 13, 15)
(b) Convert the circuit from part (a) to a 2-level NAND-AND circuit. Do not use gate symbols with
input bubbles in your final answer.
3. Find a minimum 2 level NAND gate circuit to simultaneously realize
F1(A, B, C, D) = Σ m(1, 3, 5, 7, 8, 9, 13)
F2(A, B, C, D) = Σ m(1, 3, 5, 7, 8, 10, 13)
(Hint: Minimum solution has 6 gates)
357
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READINESS TEST - UNIT 9R - FORM A*
1. (a) Given the following PLA connection diagram, specify the PLA contents in table form.
A
B
C
D
F1
F 2 F3
(b) Give the logic equations realized by the PLA.
(c) What size ROM would be required to realize the equations?
2. (a) Write the logic equation for the output of an 8-to-1 MUX with control inputs B, C, D.
(b) Implement a 4-to-1 MUX having control inputs A, B using gates.
(c) Implement a 4-to-1 MUX using a 2-to-4 decoder and tri-state buffers to select one of the decoder
outputs.
3. Z(a,b,c,d,e) = a′b′cd′ + ac′de′ + a′bd′e + bde
(a) Expand the above expression about the variable a.
(b) Use the expansion in part (a) to realize the function using 2 4-variable LUTs and a 2-to-1 MUX.
Specify the LUT inputs.
(c) Show the truth table for one of the LUTs.
358
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READINESS TEST - UNIT R1R - FORM A
TIME LIMIT 60 MINUTES
1. For the following function, find the simplest sum-of-products form algebraically: (Hint: Minimum
solution has three terms.)
F = (A + B' + D)(A' + B + D)(C + D)(C' + D')
2. Find a minimum 2-level multiple output NOR-NOR realization for the two functions given by the
PLA table below. (Hint: Minimum solution has seven gates.)
w
0
1
1
1
–
1
0
x
1
–
0
0
1
–
0
y
1
0
1
–
–
1
–
z
–
0
1
0
0
–
1
f1
1
1
1
1
0
0
0
f2
0
1
1
1
1
1
0
3. Given F = A'B'C + B'C'D' + A'C'D + A'B'D + B'CD'
(a) Find the maxterm expansion in decimal notation.
(b) Find a minimum 3-level network of AND and OR gates (no particular order of gates implied).
The minimum solution has 4 gates and 8 inputs.
4. B and C are initially zero. Assume 10 ns gate delays and complete the timing diagram below.
A
1
B
0
A
C
B
C
0
10
359
20
30
40
50
60
70
80 ns
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NAME_______________________________ PASSWORD____________ DATE__________
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READINESS TEST - UNIT 10 - FORM A
1. Write a conditional signal assignment statement that represents the following network.
A
B
A
C
0
MUX
F
1
D
2. Draw a network that implements the following VHDL code:
A <= B or not C and not D;
D <= not D after 5 ns;
3. A 3-to-8 decoder can be represented by a truth table with inputs X1 X2 X3 and outputs D7 D6 D5 D4 D3
D2 D1 D0. Write a complete VHDL module that implements the decoder using an 8 words X 8 bits
ROM.
X1
X2
X3
.
D7
D6
.
.
.
D0
4. Evaluate the following expression for A = “010” and B = “110”: (TEST is of type Boolean)
TEST <= (A & B or not (B & A)) < (B & A and not A & A)
360
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READINESS TEST - UNIT 11R - FORM A
1. An M-N flip-flop behaves as follows:
If MN = 11, the flip-flop is set to Q = 0.
If MN = 01, the flip-flop is set to Q = 1.
If MN = 10, no change of state occurs.
If MN = 00, the flip-flop changes states.
Derive the characteristic (next state) equation for this flip-flop.
2. Complete the following timing diagram for a rising edge triggered D-CE flip-flop with a clear input.
3. For the latch given below,
(a) If L = W = 0, what value with P and Q assume?
(b) If L is now changed to 1, what value with P and Q assume?
(c) If W is now changed to 1, what value with P and Q assume?
(d) If W is now changed to 0, what value with P and Q assume?
(e) What restriction must be placed on L and W so that Q will always equal P′?
361
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READINESS TEST - UNIT 12R - FORM A
1. Consider the following Loadable Counter with an Asynchronous Clear. Assuming that Count (Ct) is 1
throughout-and that DCDBDA are 010-complete the timing diagram.
Clock
2. A Y-Z flip-flop behaves as follows:
If YZ = 01, the flip-flop does not change state.
If YZ = 11, the flip-flop is set to Q = 1.
If YZ = 10, the flip-flop changes state.
The input combination YZ = 00 is not allowed.
(a) Complete the table below using don't cares where possible.
(b) Realize the following next state equation for Q using a Y-Z flip-flop. Q+= Q'AB' + A'B + QB.
Find equations for Y and Z.
Q
0
0
1
1
Q+ Y
0
1
0
1
Z
3. A 3-bit counter uses three different types of flip-flops as follows:
Flip-flop A is a D flip-flop.
Flip-flop B is a T flip-flop.
Flip-flop C is a J-K flip-flop.
Design the counter so that it counts in the following sequence:
ABC = 000, 010, 100, 101, 111, 110, 011, 000, .....
362
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READINESS TEST - UNIT 13 - FORM A
1. (a) For the given circuit, construct a transition table and a state graph.
X
Z
X'
B
T
B'
Clk
A'
K
A
J
B' Clk X
X A'
(b) Complete the following timing chart. Indicate at what times Z has the correct value and specify
the correct output sequence. Initially A = B = 0.
Clock
X
A
B
Z
2. Draw a general model of a Moore circuit with m inputs, n outputs, and k D flip-flops.
363
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READINESS TEST - UNIT 14 - FORM A
1. A Mealy sequential circuit has one input and two outputs. When the fourth input is received, the
circuit outputs Z1 = 1 if the majority of the inputs are 0’s, Z2 = 1 if the majority are 1’s, and Z1 = Z2 =1
if the number of 0’s and 1’s is the same. The circuit then resets. Find a state graph and state table.
Also specify what each state in your graph corresponds to. (Any solution with 12 or fewer states is
acceptable). Hint: The outputs depend only on the total number of 0’s and 1’s received and not on the
sequence. Thus 0 1 and 1 0 should go to the same state.
2. A Moore circuit has one input and one output. The output is initially zero. The output is the same
as the input just received, unless the input sequence 1011 occurs, in which case the output remains 1
thereafter. Derive the state graph and table for the circuit.
364
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READINESS TEST - UNIT 15 - FORM A
1. State tables for circuits N1 and N2 are given below. Are the circuits equivalent? Justify your answer.
N1
S0
S1
S2
S3
S4
0
S3
S2
S0
S4
S3
1
S1
S1
S0
S1
S1
0
0
1
0
0
0
1
0
0
0
0
0
N2
A
B
C
D
0
C
A
C
B
1
D
A
D
D
0
0
0
0
1
1
0
0
0
0
2. Reduce the following Moore state table to a minimum number of states.
X1 X2
00 01 11 10 Z
A C D D F 0
B D F E A 1
C A B B A 0
D B C E F 1
E E A F C 1
F F B D C 0
3. (a) The following state table is to be realized using D flip-flops. Make a suitable state assignment
which will lead to an economical circuit. Assign 000 to S0 and 010 to S2. Show how you arrived
at your state assignment.
(b) For the assignment obtained in (a) derive the input equations for the flip-flops and the output
equation.
0 1 0 1
S0 S1 S5 0 0
S1 S1 S4 1 0
S2 S1 S2 0 1
S3 S0 S2 0 1
S4 S2 S3 1 1
S5 S1 S4 1 1
365
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READINESS TEST - UNIT 17 - FORM A
1. Draw a diagram to show the hardware that the following VHDL code represents. Use a D-CE flip-flop
and gates.
if CLK'event and CLK = '1' then
if LDA = '1' then C <= A or B;
elsif LDB = '1' then C <= B;
end if;
end if;
2. Write a VHDL process using a case statement that represents the following MUX:
1
D
I0
0
I2
1
I1
I3
D'
D
D'
D'
Z
I4
I5
I6
I7
A
B
C
3. Write a VHDL code module that implements the following state table. Assume that all state changes
occur on the rising edge of the clock. Use two processes. Use a case statement with if-then-else statements.
Next State
Present
State
X=0
X=1
Output
S0
S1
S2
S3
S0
S0
S2
S3
S2
S2
S3
S1
0
1
1
0
4. Write a VHDL process to represent a 4-bit counter that will increment on every falling edge of the
clock. The counter has an asynchronous, active low reset that overrides the clock. Specify the type of
the signal that represents the counter output.
366
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READINESS TEST - UNIT 18 - FORM A
1. This problem concerns the design of a serial adder/subtracter with accumulator for 4-bit numbers as
shown below.
SI
Sh
St
x 3 x 2 x 1 x 0 xin
Clock
Clock
Control
Circuit
Sh
0
SI
Sh
y3 y2 y1 y0
Combinational
Logic
Circuit
xout
yout
yin
sum
Full
Adder
carry
Clock
D
K
3-bit counter
Q
D
D
Q'
CE
Clock
Clock
The combinational logic circuit has an input D which determines whether addition or subtraction
will take place. When D = 1, the contents of registers X and Y are added together. When D = 0, the
contents of registers X and Y are subtracted (i.e., X – Y). The control circuit has one output (Sh) and
two inputs—a start signal St and a counter output signal K. The counter counts the number of shifts,
and outputs a signal of K = 1 when it is 111 (after 7 shifts). Assume that D is not changed during
the operation of the adder/subtracter. Assume negative numbers are represented in 1’s complement.
Subtraction should be done by adding the 1’s complement. Note that 8 shifts are required: 4 to do the
initial addition and 4 more to add on the end-around carry.
(a) Construct a state graph for the control circuit (3 states). The operation should begin when St is set
to 1. St may be 1 for one clock cycle, or it might remain 1 for many clock cycles, even after the
addition is completed. Make sure that the circuit does not begin again after it is finished! The start
signal must be changed back to 0 to reset the control circuit.
(b) Design the control unit using D flip-flops and any kinds of gates.
(c) Design the combinational logic circuit.
2. (a) Draw a block diagram for a parallel divider which is capable of dividing a positive 8-bit binary
number by a positive 4-bit binary number to give a 4-bit quotient. Use a 9-bit dividend register, a
4-bit divisor register, a subtracter-comparator block and a control block.
(b) Show the contents of the dividend register and the value of C at each clock time when 49 is divided
by 6. (C is the comparator output and should have a value of C = 1 if subtraction can take place
without a negative result).
(c) Under what conditions will overflow take place?
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READINESS TEST - UNIT 19 - FORM A
1. This problem concerns the design of a digital system which multiplies two binary numbers by the repeated addition method. The block diagram of the system is shown below. When a start signal (St) is
set to 1, the accumulator is cleared and the multiplier is loaded into a counter. The multiplicand is then
added to the accumulator and the counter is decremented until the multiplication is complete. The
control then goes to a stop state and turns on a completion signal (K). The circuit then resets when St
is changed back to 0. Draw an SM chart for the control circuit which has 3 states. Control signals are
defined as follows:
C = clear accumulator
L = load multiplier
D = decrement counter
A = add multiplicand to accumulator
Z = 1 when the count is 0
C
A
Clr
Ld
Ad
Accumulator
Clk
Adder
D
L
Ld
Dec
Control
Circuit
K
St
Clk
Z
Counter
Clk
Multiplier
Multiplicand
2 (a) Realize the following SM chart using a PLA and D flip-flops that trigger on the falling edge of the
clock pulse. Draw a block diagram and give the PLA table. (Do not simplify the equations.)
(b) Complete the timing diagram.
0
X1
X1
1
Z2
0
X2
X2
X3
Z3
1
0
S1 /
Z3
Clock
00
S 0 / Z1
0
X1 1
X3
01
State
S0
Z1
1
Z2
S 2 / Z2
10
Z3
0 X 1
2
368
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