FUNDAMENTALS OF LOGIC DESIGN
SEVENTH EDITION
Boolean Algebra
(Ch.2)
Basic Operation of Boolean Algebra:
Truth Table:
NOT (inverse, complement): Out =In’
IN
AND:
OUT
Output:
0
1
1
0
A
B
C
0
0
0
0
1
0
1
0
0
1
1
1
C=A+B
A
B
C
0
0
0
A
0
1
1
1
0
1
1
1
1
C = A ∙ B = AB
A
C
B
OR:
Input:
B
C
Combination for more complex functions:
Out = AB′ + C
AB′
C
A
B′
A
B
B′
Out
AB′
C
Out
AB′
C
Out
The same function can be realized using different implementations:
Out = AB′ + C = (A + C)(B′ + C)
A
Out
C
B′
B
ABC
B’
AB’
AB’+C
A+C
B’+C
(A+C)(B’+C)
000
1
0
0
0
1
0
001
1
0
1
1
1
1
010
0
0
0
0
0
0
011
0
0
1
1
1
1
100
1
1
1
1
1
1
101
1
1
1
1
1
1
110
0
0
0
1
0
0
111
0
0
1
1
1
1
Basic Theorems:
X+0=X
X∙1=X
X+1=1
X∙0=0
X+X=X
X∙X=X
(X′)′ = X
X + X′ = 1
X ∙ X′ = 0
Commutative Law:
X∙Y=Y∙X
X+Y =Y+X
Associative Law:
XY Z = X YZ = XYZ
X+Y +Z=X+ Y+Z =X+Y+Z
XYZ
XY
YZ
(XY)Z
X(YZ)
X+Y
Y+Z
(X+Y)+Z
X+(Y+Z)
000
0
0
0
0
0
0
0
0
001
0
0
0
0
0
1
1
1
010
0
0
0
0
1
1
1
1
011
0
1
0
0
1
1
1
1
100
0
0
0
0
1
0
1
1
101
0
0
0
0
1
1
1
1
110
1
0
0
0
1
1
1
1
111
1
1
1
1
1
1
1
1
XY Z = X YZ = XYZ
X
Y
X
Y
Z
Z
X+Y +Z=X+ Y+Z =X+Y+Z
X
Y
Z
X
Y
Z
Distributive Law:
X Y + Z = XY + XZ
X + (YZ) = (X + Y)(X + Z)
=X X+Z +Y X+Z
= XX + XZ + YX + YZ
= X + XZ + YX + YZ
= X(1 + Z + Y) + YZ
= X + YZ
DeMorgan’s Law:
X + Y ′ = X ′ Y′
(XY)′ = X ′ + Y′
X1 + X 2 + ⋯ + X n
X1 X 2 X n
′
′
= X1 ′ X 2 ′ ⋯ X n ′
= X1 ′ + X2′ + ⋯ + Xn ′
FUNDAMENTALS OF LOGIC DESIGN
SEVENTH EDITION
XOR/NXOR gates,
Universal Gates
Exclusive-OR (XOR)
A
B
OUT
Check the number of ‘1’s of the inputs:
odd ones
A
B
C
OUT
A
B
OUT
0
0
0
0
1
1
1
0
1
1
1
0
A
B
C
OUT
0
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
1
Exclusive-NOR (XNOR)
A
OUT
B
even ones
A
B
C
OUT
A
B
OUT
0
0
1
0
1
0
1
0
0
1
1
1
A
B
C
OUT
0
0
0
1
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
0
1
0
1
1
1
1
0
1
1
1
1
0
NAND gate
A
OUT
B
A
A
B
OUT
0
0
1
0
1
1
1
0
1
1
1
0
OUT
B
NOR gate
A
OUT
B
A
B
OUT
A
B
OUT
0
0
1
0
1
0
1
0
0
1
1
0
The basic Boolean operations can be implemented using only
NAND or NOR gates: NAND and NOR gates are universal gates
A
A
A’
(AB)’
B
A
B
A
((AB)’)’
=AB
A’
B’
A
(A+B)’
B
A
(A’B’)’
=(A’)’+(B’)’
=A+B
A’
B
((A+B)’)’
=A+B
A’
B’
(A’+B’)’
=(A’)’(B’)’
=AB
FUNDAMENTALS OF LOGIC DESIGN
SEVENTH EDITION
minterm / sum of product
maxterm / product of sum
Karnaugh Maps
(Ch.4, Ch.5)
Row index
ABC
Minterms
Maxterms
0
000
𝐴′ 𝐵′ 𝐶 ′ = 𝑚0
𝐴 + 𝐵 + 𝐶 = 𝑀0
1
001
𝐴′ 𝐵′ 𝐶 = 𝑚1
𝐴 + 𝐵 + 𝐶′ = 𝑀1
2
010
𝐴′ 𝐵𝐶′ = 𝑚2
𝐴 + 𝐵′ + 𝐶 = 𝑀2
3
011
𝐴′ 𝐵𝐶 = 𝑚3
𝐴 + 𝐵′ + 𝐶′ = 𝑀3
4
100
𝐴𝐵′𝐶′ = 𝑚4
𝐴′ + 𝐵 + 𝐶 = 𝑀4
5
101
𝐴𝐵′𝐶 = 𝑚5
𝐴′ + 𝐵 + 𝐶′ = 𝑀5
6
110
𝐴𝐵𝐶′ = 𝑚6
𝐴′ + 𝐵′ + 𝐶 = 𝑀6
7
111
𝐴𝐵𝐶 = 𝑚7
𝐴′ + 𝐵′ + 𝐶′ = 𝑀7
Sum of product: 𝑓1 𝐴, 𝐵, 𝐶 = 𝐴′ 𝐵𝐶 + 𝐴𝐵′ 𝐶 ′ + 𝐴𝐵′ 𝐶 + 𝐴𝐵𝐶
= 𝑚3 + 𝑚4 + 𝑚5 + 𝑚7
=
𝑚 (3,4,5,7)
Product of sum: 𝑓2 𝐴, 𝐵, 𝐶 = (𝐴 + 𝐵 + 𝐶′)(𝐴 + 𝐵′ + 𝐶)(𝐴′ + 𝐵 + 𝐶)(𝐴′ + 𝐵 + 𝐶 ′ )
= 𝑀1 𝑀2 𝑀3 𝑀5
=
𝑀 (1,2,3,5)
Transfer Minterm to Maxterm by DeMorgan’s law:
𝑓(𝐴, 𝐵, 𝐶) = 𝐴’𝐵𝐶 + 𝐴𝐵’𝐶’ + 𝐴𝐵’𝐶 + 𝐴𝐵𝐶’ + 𝐴𝐵𝐶
= 𝑚3 + 𝑚4 + 𝑚5 + 𝑚6 + 𝑚7
= 𝑚 (3,4,5,6,7)
Row
ABC
Minterms
Maxterms
index
𝑓’ 𝐴, 𝐵, 𝐶 = 𝐴’𝐵’𝐶’ + 𝐴’𝐵’𝐶 + 𝐴’𝐵𝐶’
= 𝑚0 + 𝑚1 + 𝑚2
= 𝑚 (0,1,2)
0
000
𝐴′ 𝐵′ 𝐶 ′ = 𝑚0
𝐴 + 𝐵 + 𝐶 = 𝑀0
1
001
𝐴′ 𝐵′ 𝐶 = 𝑚1
𝐴 + 𝐵 + 𝐶′ = 𝑀1
2
010
𝐴′ 𝐵𝐶′ = 𝑚2
𝐴 + 𝐵′ + 𝐶 = 𝑀2
3
011
𝐴′ 𝐵𝐶 = 𝑚3
𝐴 + 𝐵′ + 𝐶′ = 𝑀3
4
100
𝐴𝐵′𝐶′ = 𝑚4
𝐴′ + 𝐵 + 𝐶 = 𝑀4
5
101
𝐴𝐵′𝐶 = 𝑚5
𝐴′ + 𝐵 + 𝐶′ = 𝑀5
6
110
𝐴𝐵𝐶′ = 𝑚6
𝐴′ + 𝐵′ + 𝐶 = 𝑀6
𝐴𝐵𝐶 = 𝑚7
𝐴′ + 𝐵′ + 𝐶′ = 𝑀7
𝑓(𝐴, 𝐵, 𝐶) = (𝑓’(𝐴, 𝐵, 𝐶))’
7
111
= 𝐴’𝐵’𝐶’ + 𝐴’𝐵’𝐶 + 𝐴’𝐵𝐶’ ’
= (𝐴’𝐵’𝐶’)’(𝐴’𝐵’𝐶)’(𝐴’𝐵𝐶’)’
= (𝐴 + 𝐵 + 𝐶)(𝐴 + 𝐵 + 𝐶’)(𝐴 + 𝐵’ + 𝐶)
= 𝑀0 𝑀1 𝑀2
= 𝑀 (0,1,2)
Karnaugh Maps
AB
𝑓 𝐴, 𝐵 = 𝐴′ 𝐵′ + 𝐴′ 𝐵
= 𝐴′ (𝐵′ + 𝐵)
= 𝐴′ ∙ 1
= 𝐴′
00
1
01
1
10
0
11
0
0
1
0
1
0
1
1
0
B
𝑓 𝐴, 𝐵, 𝐶 = 𝐴′ 𝐵𝐶 ′ + 𝐴′ 𝐵𝐶 + 𝐴𝐵′ 𝐶 ′ + 𝐴𝐵𝐶′
= 𝐴′ 𝐵𝐶 ′ + 𝐵𝐶 + 𝐴(𝐵′ 𝐶 ′ + 𝐵𝐶′)
= 𝐴′ 𝐵 𝐶 ′ + 𝐶 + 𝐴𝐶 ′ (𝐵′ + 𝐵)
= 𝐴′ 𝐵 + 𝐴𝐶 ′
A
A
f(A,B)
ABC
f(A,B,C)
000
0
001
0
010
1
0
1
00
0
1
011
1
01
0
0
100
1
101
0
110
1
111
0
BC
11
1
0
10
1
1
1. Neighboring terms are different in only one bit
2. 2𝑁 terms are grouped to be simplified
AB
00
01
11
10
00
1
1
1
1
01
0
0
0
0
11
0
1
1
0
10
1
1
1
1
CD
3. Each term can be reused
4. The simplification result is not unique
AB
AB
00
01
11
10
00
1
1
1
1
01
0
0
0
11
0
1
10
1
1
CD
00
01
11
10
00
1
1
1
1
0
01
0
0
0
0
1
0
11
0
1
1
0
1
1
10
1
1
1
1
CD
5. ‘don’t care’ terms are useful
AB
AB
00
01
11
10
00
1
1
1
1
0
01
0
0
x
0
1
x
11
0
x
1
x
1
1
10
1
1
1
1
00
01
11
10
00
1
1
1
1
01
0
0
x
11
0
x
10
1
1
CD
CD
FUNDAMENTALS OF LOGIC DESIGN
SEVENTH EDITION
MUX, Decoder, ROM
(Ch.9)
Multiplexer (MUX)
2-to-1 MUX
When S=1’b0, OUT=A
S=1’b1, OUT=B
A
OUT
B
S
S
AB
0
1
OUT=AS’+BS
00
0
0
01
0
1
11
1
1
10
1
0
A
B
S
OUT
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
1
0
1
1
1
1
1
B
OUT
A
S
4-to-1 MUX: OUT=AX’Y’+BX’Y+CXY’+DXY
A
B
A
OUT
C
X’
Y’
D
B
X
Y
X’
Y
C
X
X
X’
Y’
D
Y
Y’
X
Y
OUT
8-to-1 MUX: OUT=AX’Y’Z’+BX’Y’Z+CX’YZ’+DX’YZ+EXY’Z’+FXY’Z+GXYZ’+HXYZ
A
B
C
D
OUT
X Y
E
Z
F
G
H
X
Y
Decoder:
X=A’B’
A
A’
Y=A’B
Z=AB’
B
B’
A
A’
W=AB
A’
B
B
B’
X
A
A
B
X
Y
Z
W
B’
0
0
1
0
0
0
A
0
1
0
1
0
0
1
0
0
0
1
0
1
1
0
0
0
1
B
Y
Z
W
Read Only Memory (ROM):
A[2:0]=3’b000
A[2]
3’b001
A[2]
8 Word x 4-bit
ROM
A[1]
A[1]
A[0]
3’b010
3’b011
3’b100
3’b101
3’b110
3’b111
A[0]
D[3] D[2] D[1] D[0]
A[2] A[1] A[0] D[3] D[2] D[1] D[0]
0
0
0
1
0
1
0
0
0
1
1
1
0
0
0
1
0
0
0
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
1
1
0
1
0
0
0
0
1
1
0
1
1
1
0
1
1
1
0
0
0
1
D[3]
D[2]
D[1]
D[0]
FUNDAMENTALS OF LOGIC DESIGN
SEVENTH EDITION
CMOS based logic gates
(Appendix A)
NOT : Out =In’
Truth Table:
IN
OUT
Input:
Output:
0
1
1
0
‘1’= VDD, ‘0’=GND
VDD
VDD
Weak drive for ‘1’;
Leakage current when output ‘0’;
OUT
OUT
IN
IN
GND
GND
VDD
IN=‘0’
VDD
OUT=‘1’
IN=‘1’
OUT=‘0’
GND
GND
VDD
Complementary Metal-Oxide-Semiconductor
(CMOS)
IN
OUT
GND
NAND
NOR
VDD
M1
VDD
M2
M1
OUT
A
M3
B
M4
A
M2
OUT
B
GND
GND
M2
M3
M4
OUT
A
GND GND On
On
Off
Off
VDD
GND VDD
Off
On
Off
On
VDD
GND On
Off
On
VDD
VDD
Off
On
A
B
M1
Off
M4
M3
M2
M3
M4
OUT
GND GND On
On
Off
Off
VDD
VDD
GND VDD
Off
On
On
Off
GND
Off
VDD
VDD
GND On
Off
Off
On
GND
On
GND
VDD
VDD
Off
On
On
GND
B
M1
Off
3-input NOR
3-input NAND
VDD
VDD
A
OUT
B
A
C
B
OUT
C
GND
GND
Input
gate
delay
Output
FUNDAMENTALS OF LOGIC DESIGN
SEVENTH EDITION
Binary Number Systems, 1
(Ch1)
Number System and Conversion
Digital circuit usually presented in binary system, ‘1’ or ‘0’ correspond to ‘on’
or ‘off’ states of the circuit. (‘high’ or ‘low’ voltages)
Decimal (base 10) number:
953.7810 = 9 × 102 + 5 × 101 + 3 × 100 + 7 × 10−1 + 8 × 10−2
Binary (base 2) number:
1011.112 = 1 × 23 + 0 × 22 + 1 × 21 + 1 × 20 + 1 × 2−1 + 1 × 2−2
Convert 5310 to binary:
5310
53 = 2 × 26 + 1
26 = 2 × 13 + 0
13 = 2 × 6 + 1
6=2×3+0
3=2×1+1
1=2×0+1
=2 2 2 2 2 2 0 +1 +1 +0 +1 +0 +1
5310 = 1 × 25 + 1 × 24 + 0 × 23 + 1 × 22 + 0 × 21 + 1 × 20 = 1101012
2
Convert 0.62510 to binary:
0.625 × 2 = 1.25 = 1 + 0.25
0.25 × 2 = 0.5 = 0 + 0.5
0.5 × 2 = 1 = 1 + 0
0.62510 = 1 × 2−1 + 0 × 2−2 + 1 × 2−3 = 0.1012
Convert 5.710 to binary:
510
5=2×2+1
2=2×1+0
1=2×0+1
= 1 × 22 + 0 × 21 + 1 × 20 = 1012
0.7 × 2 = 1.4 = 1 + 0.4
0.4 × 2 = 0.8 = 0 + 0.8
0.8 × 2 = 1.6 = 1 + 0.6
0.6 × 2 = 1.2 = 1 + 0.2
1 × 2−1 + 0 × 2−2 + 1 × 2−3 + 1 × 2−4 = 0.10112 = 0.687510
5.710 − 101.10112 = 5.710 − 5.687510 = 0.012510
Quantization Error (Quantization Noise)
Reduce quantization error by increasing quantization bits:
0.7 × 2 = 1.4 = 1 + 0.4
0.4 × 2 = 0.8 = 0 + 0.8
0.8 × 2 = 1.6 = 1 + 0.6
0.6 × 2 = 1.2 = 1 + 0.2
0.2 × 2 = 0.4 = 0 + 0.4
0.4 × 2 = 0.8 = 0 + 0.8
0.8 × 2 = 1.6 = 1 + 0.6
0.6 × 2 = 1.2 = 1 + 0.2
1 × 2−1 + 0 × 2−2 + 1 × 2−3 + 1 × 2−4 + 0 × 2−5 + 0 × 2−6 + 1 × 2−7 + 1 × 2−8
= 0.101100112 = 0.6992187510
5.710 − 101.101100112 = 5.710 − 5.6992187510 = 0.0007812510
0.7 × 2 = 1.4 = 1 + 0.4
0.4 × 2 = 0.8 = 0 + 0.8
0.8 × 2 = 1.6 = 1 + 0.6
0.6 × 2 = 1.2 = 1 + 0.2
0.2 × 2 = 0.4 = 0 + 0.4
0.4 × 2 = 0.8 = 0 + 0.8
0.8 × 2 = 1.6 = 1 + 0.6
0.6 × 2 = 1.2 = 1 + 0.2
1 × 2−1 + 0 × 2−2 + 1 × 2−3 + 1 × 2−4 + 0 × 2−5 + 0 × 2−6 + 1 × 2−7 + 1 × 2−8
= 0.101100112 = 0.6992187510
0.7 − 2−1 = 0.7 − 0.5 = 0.2 > 0;
0.2 − 2−2 = 0.2 − 0.25 = −0.05 < 0;
0.2 − 2−3 = 0.2 − 0.125 = 0.075 > 0;
0.075 − 2−4 = 0.075 − 0.0625 = 0.0125 > 0;
0.0125 − 2−5 = 0.0125 − 0.03125 = −0.09375 < 0;
0.0125 − 2−6 = 0.0125 − 0.015625 = −0.003125 < 0;
0.0125 − 2−7 = 0.0125 − 0.0078125 = 0.0046875 > 0;
0.0046875 − 2−8 = 0.0046875 − 0.00390625 = 0.00078125 > 0;
′1′
′0′
′1′
′1′
′0′
′0′
′1′
′1′
FUNDAMENTALS OF LOGIC DESIGN
SEVENTH EDITION
Binary Number Systems, 2
(Ch1)
Binary Arithmetic
Addition :
0+0=0
0+1=1
1+0=1
1 + 1 = 0 add carry 1 to the next column
1310 + 1110 = 11012 + 10112 = 110002 = 2410
Subtraction :
0−0=0
0 − 1 = 1 borrow 1 from the next column
1−0=1
1−1=0
111012 − 100112 = 10102
100002 − 112 = 11012
1110012 − 10112 = 1011102
Multiplication :
0×0=0
0×1=0
1×0=0
1×1=1
1310 × 1110 = 11012 × 10112
= 1101 × 1 + 1101 × 10 + 1101 × 1000
= 1101 + 11010 + 1101000
= 100011112
= 14310
Division:
14510 ÷ 1110
= 100100012 ÷ 10112
10010001
= 1011000 + 111001
= 1011000 + 101100 + 1101
= 1011000 + 101100 + 1011 + 10
= 10112 × 11012 + 102
= 1310 × 1110 + 210
14510 ÷ 1110 = 1310 ⋯ 210
Representation of Negative Number
The subtraction can be represented as addition with the complement value.
2’s complement:
510 − 610 = 510 + (−610 )
= 01012 + 10102 = 11112
= −110
2’s complement has advantages for dealing the overflow:
4-digit 2’s complement, presents +7~ − 8
510 + 610
= 01012 + 01102 = 10112 = −510
overflow detected, the addition of two positive values should not be negative.
−510 − 610
= 10112 + 10102 = (1)01012 = 510
overflow detected, the addition of two negative values should not be positive.
−510 − 610 + 410
= 10112 + 10102 + 01002
= 01012 + 01002 = 10012 = −710
As long as the final value is in the range of representation, overflow is allowed
during the procedure.
FUNDAMENTALS OF LOGIC DESIGN
SEVENTH EDITION
Adder
(Ch4)
𝐶𝑖𝑛
Full adder:
𝑋
𝐶𝑜𝑢𝑡
Full
adder
𝑌
𝐶𝑖𝑛
𝑆𝑢𝑚
𝑆𝑢𝑚
𝐶𝑜𝑢𝑡
Cin
XY
0
1
Cin
XY
0
1
00
0
1
00
0
0
01
1
0
01
0
1
11
0
1
11
1
1
10
1
0
10
0
1
𝑋
𝑌
𝑆𝑢𝑚 𝐶𝑜𝑢𝑡
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
′
′
𝑆𝑢𝑚 = 𝑋 ′ 𝑌𝐶𝑖𝑛
+ 𝑋𝑌 ′ 𝐶𝑖𝑛
+ 𝑋 ′ 𝑌 ′ 𝐶𝑖𝑛 + 𝑋𝑌𝐶𝑖𝑛
= 𝑋 ⊕ 𝑌⨁𝐶𝑖𝑛
𝐶𝑜𝑢𝑡 = 𝑋𝑌 + 𝑋 ′ 𝑌𝐶𝑖𝑛 + 𝑋𝑌 ′ 𝐶𝑖𝑛
= 𝑋𝑌 + (𝑋 ⊕ 𝑌)𝐶𝑖𝑛
𝑆𝑢𝑚 = (𝑋 ⊕ 𝑌)⨁𝐶𝑖𝑛
𝐶𝑜𝑢𝑡 = 𝑋𝑌 + (𝑋 ⊕ 𝑌)𝐶𝑖𝑛
𝑋
𝑆𝑢𝑚
𝑌
𝐶𝑖𝑛
𝐶𝑜𝑢𝑡
4-bit Adder:
𝑆3
𝐶𝑜𝑢𝑡
𝑆2
𝑆1
𝑆0
𝐶𝑖𝑛
4-bit adder:
𝑌3 𝑋3 𝑌2 𝑋2 𝑌1 𝑋1 𝑌0 𝑋0
𝑆3
𝐶𝑜𝑢𝑡
Full
adder
𝑌3 𝑋3
𝑆2
𝐶3
𝑆1
𝑆0
𝐶2
Full
adder
𝐶1
Full
adder
Full
adder
𝑌2 𝑋2
𝑌1 𝑋1
𝑌0 𝑋0
𝐶𝑖𝑛
Subtracter for 2’s complement:
𝐶𝑜𝑢𝑡
𝑆3
𝑆2
𝑆1
𝑆0
Full
adder
Full
adder
Full
adder
Full
adder
𝑌3 𝑋3
𝑌2 𝑋2
𝑌1 𝑋1
𝑌0 𝑋0
𝐶𝑖𝑛 = 1