Banasthali Vidyapith - Faculty of Mathematics & Computing
Course Handout: B.Tech. (AI) III SEM (July 2023 – Dec 2023)
Date 28/06/2023
Course Code: CS 207
Credit Points: 4
Course Name: Computer Organization and
Architecture
Max. Marks: 100 (CA: 40+ ESA: 60)
Course Instructor: Dr Urvashi Prakash Shukla, Assistant Professor, Computer Science.
Learning Outcomes:
After successful completion of the course, students will be able to:
 Learn concepts and design of digital logic circuits.
 Understand the architecture of a computer system and its components: control unit, arithmetic
and logical (ALU) unit, input/output, and memory unit.
 Learn pipelining and microprogramming techniques in the design of the central processing unit
of a computer system.
Syllabus
Section A
Computer Codes: weighted and non-weighted, self-complementing codes. Logic Gates and Boolean
Algebra: basic and universal gates, laws, canonical forms, simplification, k-map. Combinational
Circuits: adder, subtractor, decoder, encoder, multiplexer, de-multiplexer, comparator, parity
generator and checker.
Sequential Circuits: synchronous and asynchronous, latches and flip flops, timing diagrams, analysis
and design of clocked sequential circuits, state reduction and assignment.
Section B
Registers and Counters: synchronous and asynchronous, shift registers, serial adder. Computer
Organization and Design: instruction formats, instruction set, instruction cycle, input-output
interrupts, interrupt cycle.
Micro Programmed Control: control memory, address sequencing, design of control unit. Central
Processing Unit: general register organization, stack organization, addressing modes, CISC and RISC
characteristics
Section C
Pipeline and Vector Processing: parallel processing, pipelining, arithmetic pipeline, instruction
pipeline, RISC pipeline, data control and hazards, vector processing.
Memory Organization: memory hierarchy, characteristics, RAM and ROM chips, associative memory,
cache memory - features, the principle of locality, address mapping- direct, associative, set-associative,
cache performance, cache coherence.
Input - Output Organization: interface, modes of transfer – programmed I/O, interrupt initiated,
DMA, I/O and multi-processor
Suggested Books:
S1 Mano, M. M. (2017). Digital logic and computer design. Pearson Education India.
S2 Mano, M. M. (2003). Computer system architecture. Prentice-Hall of India.
S3 Stallings, W. (2003). Computer organization and architecture: designing for performance. Pearson
Education India.
S4 Mano, M. M., & Ciletti, M. (2013). Digital design: with an introduction to the Verilog HDL. Pearson
Suggested E-Learning Resources:
E1. Computer organization and architecture: designing for performance. Pearson Education India.
http://williamstallings.com/ComputerOrganization/
E2. The Computing Technology Inside Your Smartphone https://www.edx.org/course/computingtechnology-inside- smartphone-cornellx-engri1210x-0
E3. Computer Organizations and Architecture https://nptel.ac.in/courses/106103068/
Evaluation Scheme:
Component
Home assignment I *
Marks
10
Submission Date
28 August 2023
Periodical test I
Home Assignment II *
10
10
8-11 September 2023 *
11 October 2023
Periodical test II
Semester Examination
*Subject to change
10
60
4-8 November 2023*
2-18 December 2023*
Syllabus
Topics shall be allotted in the
class by 12 August 2023
Course Covered in Section A
Topics shall be allotted in the
class by 25 September 2023
Course Covered in Section B
Whole Syllabus
Lecture-Wise Plan:
Lecture Topic to be covered
References
Computer Codes: weighted and non-weighted, self-complementing codes. Logic S1/S4/E2
1-3
Gates
4-6
Boolean Algebra: basic
simplification, k-map.
and universal gates,
laws, canonical forms, S1/S4/E2
7-10
Combinational Circuits: adder, subtractor, decoder, encoder, multiplexer, de- S1/S4/E2
multiplexer, comparator, parity generator and checker.
11-14
Sequential Circuits: synchronous and asynchronous, latches and flip flops,
S1/S4/E2
15-18
Timing diagrams, analysis and design of clocked sequential circuits, state
reduction and assignment.
S1/S4/E2
19-22
Registers and Counters: synchronous and asynchronous, shift registers, serial S7/S4/E2
adder. Computer
23-28
Organization and Design: instruction formats, instruction set, instruction cycle, S7/S4/E1
input-output interrupts, interrupt cycle.
29-31
Micro Programmed Control: control memory, address sequencing, design of
control unit.
S7/S4/E1
32-35
36-39
Central Processing Unit: general register organization, stack organization, S7/S4/E1
addressing modes, CISC and RISC characteristics
Pipeline and Vector Processing: parallel processing, pipelining, arithmetic S7/S4/E1
pipeline, instruction pipeline, RISC pipeline, data control and hazards, vector
processing
40-44
Memory Organization: memory hierarchy, characteristics, RAM and ROM chips, S4/S2
associative memory, cache memory - features, the principle of locality, address
mapping- direct, associative, set-associative, cache performance, cache
coherence
45-46
Input - Output Organization: interface, modes of transfer – programmed I/O
S4/S2
47-50
Interrupt initiated, DMA, I/O and multi-processor with Revision
S4/S2
(Dr Urvashi Prakash Shukla)