EE695K VLSI Interconnect
S-Domain Analysis
s-Domain Circuit Analysis
Time domain
(t domain)
Linear
Circuit
Differential
equation
Complex frequency
domain (s domain)
Laplace Transform
L
Laplace Transform
L
Classical
techniques
Response
waveform
Prepared by CK
Transformed
Circuit
Algebraic
equation
Algebraic
techniques
Inverse Transform
L-1
Response
transform
1
EE695K VLSI Interconnect
Kirchhoff’s Laws in s-Domain
t domain
s domain
i2 (t )
Kirchhoff’s current law (KCL)
i1 (t )
i3 (t )
i4 (t )
i1 (t ) + i2 (t ) − i3 (t ) + i4 (t ) = 0
I1 ( s ) + I 2 ( s ) − I 3 ( s ) + I 4 ( s ) = 0
+ v2 (t ) −
Kirchhoff’s voltage law (KVL)
+ v4 (t ) −
+
v1 (t )
+
v3 (t )
+
v5 (t )
−
−
−
− V1 (s) + V2 ( s) + V3 (s) = 0
− v1 (t ) + v2 (t ) + v3 (t ) = 0
Signal Sources in s Domain
t domain
s domain
i(t )
+
v(t )
v (t ) = vS (t )
i(t ) = depends _
on circuit
vS (t )
L
V (s)
_
+
Prepared by CK
V ( s ) = VS ( s )
I ( s) = depends
on circuit
I (s)
_
i(t ) = iS (t )
v (t )
v(t ) = depends +
on circuit
VS (s)
_
i(t )
Current Source:
Voltage Source:
+
_
+
Voltage Source:
I (s )
_
iS (t )
L
V (s )
+
Current Source:
I S (s)
I ( s) = VS ( s)
V ( s) = depends
on circuit
2
EE695K VLSI Interconnect
Time and s-Domain Element Models
Impedance and Voltage Source for Initial Conditions
iR (t )
+
Resistor:
+
vR (t )
vR (t ) = RiR (t )
R
L
_
VR (s)
I L (s)
+
di (t )
vL (t ) = L L
dt
L
L
iC (t )
+
1 t
vC (t ) = ∫iC (τ )dτ
vC (t )
C 0
_
+ vC (0)
Ls
VL (s )
_
_
+
I C (s)
L
VC (s)
_
VR (s ) = RI R ( s)
VL ( s) = LsI L ( s ) −
Li L (0)
LiL (0)
Capacitor:
+
C
Resistor:
Inductor:
+
vL (t )
_
Capacitor:
R
_
iL (t )
Inductor:
s-Domain
I R (s )
1
_
+
Time Domain
1 Cs VC (s ) =
I C (s) +
Cs
v C ( 0)
vC ( 0 )
s
s
Impedance and Voltage Source for Initial
Conditions
• Impedance Z(s)
Z (s ) =
voltage transform
current tr ansform
with all initial conditions set to zero
• Impedance of the three passive elements
Z R (s) =
VR ( s )
=R
I R (s )
V L ( s)
= Ls
I L (s)
wi th iL (0) = 0
VC ( s) 1
=
I C ( s ) Cs
wi th vC ( 0 ) = 0
Z L (s) =
Z C ( s) =
Prepared by CK
3
EE695K VLSI Interconnect
Time and s-Domain Element Models
Admittance and Current Source for Initial Conditions
Time Domain
iR (t )
+
Resistor:
+
vR (t )
1
iR (t ) = vR (t )
R
R
L
_
VR (s)
+
1 t
iL (t ) = ∫vL (τ )dτ
vL (t )
L 0
_
+ iL (0)
L
VL (s )
Ls
_
I C (s)
+
dv (t )
iC (t ) = C C
dt
vC (t )
_
Inductor:
+
L
+
C
L
VC (s)
_ 1 Cs
1
VR ( s )
R
I R (s ) =
I L (s)
iC (t )
Capacitor:
Resistor:
R
_
iL (t )
Inductor:
s-Domain
I R (s )
I L (s) =
i L ( 0)
s
1
VL ( s ) +
Ls
iL ( 0 )
s
Capacitor:
I C (s ) = CsVC ( s ) −
CvC (0)
CvC (0)
Admittance and Current Source for Initial
Conditions
• Admittance Y(s)
Y (s ) =
current tr ansform
1
=
voltage transform Z ( s )
with all initial conditions set to zero
• Admittance of the three passive elements
YR (s ) =
Prepared by CK
I R (s) 1
=
VR ( s) R
YL ( s ) =
I L (s) 1
=
VL ( s ) Ls
wi th iL (0) = 0
YC ( s ) =
IC (s)
= Cs
VC ( s )
wi th vC ( 0 ) = 0
4
EE695K VLSI Interconnect
Example: Solve for Current Waveform i(t)
R
_
+
L
i(t )
L
VA
s
_
+
V Au (t )
R
+ VR (s) −
I (s)
Ls
_
+
+
VL (s)
LiL (0) _
VA
+ VR (s ) + VL ( s) = 0
s
Resistor: VR (s ) = RI ( s )
Inductor: VL ( s ) = LsI (s ) − LiL (0)
V
− A + RI (s ) + LsI (s ) − LiL (0) = 0
s
VA L
i (0 )
I (s ) =
+ L
s( s + R L) s + R L
By KVL: −
V A R VA R
i (0 )
−
+ L
s
s+ R L s+ R L
R
− t
V V − R t
Inverse Transform: i(t ) =  A − A e L + iL (0)e L u (t )

R R
=
forced response
natural response
Series Equivalence and Voltage Division
I1 ( s)
I (s )
Rest
of
Circuit
+ V1 ( s ) −
Z1
+
V (s)
−
V1 ( s) = Z1 ( s ) I1 ( s) = Z1 ( s) I ( s )
+
Z2 V2 ( s ) I 2 ( s )
−
V2 ( s ) = Z 2 ( s) I 2 ( s ) = Z 2 ( s) I ( s )
KVL: V (s ) = V1 (s ) + V2 ( s)
= (Z1 ( s ) + Z 2 ( s ))I ( s )
I (s )
Rest
of
Circuit
Prepared by CK
+
V (s) Z
EQ
−
Z EQ = Z1 + Z 2
Z EQ (s ) = Z1 (s ) + Z 2 ( s)
V1 ( s ) =
Z1 ( s )
V (s )
Z EQ ( s )
V2 ( s ) =
Z 2 (s)
V (s )
Z EQ ( s )
5
EE695K VLSI Interconnect
Parallel Equivalence and Current Division
I1 ( s ) = Y1 ( s )V ( s )
I (s )
Rest
of
Circuit
+
I1 ( s)
V (s) Y1
−
I 2 ( s ) = Y2 ( s )V ( s )
I 2 (s)
Y2
KCL: I (s ) = I1 (s ) + I 2 ( s)
= (Y1 (s ) + Y2 (s ))V ( s )
YEQ ( s) = Y1 ( s) + Y2 ( s)
I (s )
Rest
of
Circuit
+
V (s) Y
EQ
−
YEQ = Y1 + Y2
I1 ( s) =
Y1 (s )
I (s )
YEQ ( s)
I 2 (s) =
Y2 ( s )
I ( s)
YEQ ( s )
Example:
Equivalence Impedance and Admittance
A
L
Inductor current = 0 at t = 0
capacitor voltage = 0
C v2 (t ) Find equivalent impedance at A and B
_
Solve for v2(t)
1
1
RCs + 1
YEQ1 (s ) =
= + Cs =
Z EQ1 ( s) R
R
+
v1 (t )
R
_
+
B
L
A
Z EQ ( s) = Ls + Z EQ1 (s ) = Ls +
Ls
RLCs 2 + Ls + R
RCs + 1
1
V2 ( s )
Z EQ1 ( s)
Cs _
V2 ( s ) =
V1 ( s )
Z EQ
=
+
V1 (s )
_
+
B
Z EQ ZREQ1
Z EQ
Z EQ1
=
Prepared by CK
R
RCs + 1
R
V1 ( s)
RCLs + Ls + R
2
6
EE695K VLSI Interconnect
General Techniques for s-Domain Circuit
Analysis
• Node Voltage Analysis (in s-domain)
–
–
–
–
Use Kirchhoff’s Current Law (KCL)
Get equations of node voltages
Use current sources for initial conditions
Voltage source
current source
• Mesh Current Analysis (in s-domain)
–
–
–
–
Use Kirchhoff’s Voltage Law (KVL)
Get equations of currents in the mesh
Use voltage sources for initial conditions
Current source
voltage source
(Works only for “Planar” circuits)
Formulating Node-Voltage Equations
Step 0: Transform the circuit into the s domain using current
sources to represent capacitor and inductor initial conditions
Step 1: Select a reference node. Identify a node voltage at each
of the non-reference nodes and a current with every element
in the circuit
Step 2: Write KCL connection constraints in terms of the
element currents at the non-reference nodes
Step 3: Use the element admittances and the fundamental
property of node voltages to express the element currents in
terms of the node voltages
Step 4: Substitute the device constraints from Step 3 into the
KCL connection constraints from Step 2 and arrange the
resulting equations in a standard form
Prepared by CK
7
EE695K VLSI Interconnect
Example: Formulating Node-Voltage Equations
L
iS (t )
R
C
Step 0: Transform the circuit into the s domain using
current sources to represent capacitor and
inductor initial conditions
Step 1: Identify N-1=2 node voltages and a current
with each element
t domain
V A (s)
I 2 (s)
I S (s)
Reference
node
Step 2: Apply KCL at nodes A and B:
i (0)
Node A : IS (s ) − L
− I1 ( s) − I 2 ( s) = 0
L
s
iL (0)
i (0)
Node B : CvC (0) + L
+ I1 (s) − I 3 ( s) = 0
s
s
Step 3: Express element equations in terms of node
Ls
VB (s)
voltages
1
I1 ( s ) I 3 ( s )
[VA (s ) − VB (s )]
I1 (s ) = YL ( s)[
VA ( s) − VB ( s)]=
Ls
1
R
Cs CvC (0) I 2 ( s) = YR ( s)VA ( s) = GV A (s ) where G = 1 R
I 3 (s ) = YC ( s)VB (s ) = CsVB ( s)
s domain
Formulating Node-Voltage Equations (Cont’d)
Step 2: Apply KCL at nodes A and B:
i (0)
Node A : IS (s ) − L
− I1 ( s) − I 2 ( s) = 0
s
i (0)
Node B : CvC (0) + L
+ I1 (s) − I 3 ( s) = 0
s
Step 3: Express element equations in terms of node voltages
1
I1 (s) = YL (s )[
VA (s ) − VB (s)]= [
VA ( s) − VB (s )]
Ls
I 2 ( s) = YR (s )VA ( s) = GV A ( s) where G = 1 R
I 3 (s) = YC ( s)VB ( s) = CsVB (s )
Step 4: Substitute eqns. in Step 3 into eqns. in Step 2 and collect
common terms to yield node-voltage eqns.
1 
i (0)

1 
Node A : G +
V A ( s) −  VB (s ) = I S (s) − L
Ls 
s

 Ls 
i (0)
1 
1

Node B : −  V A ( s) +  + Cs VB ( s) = CvC (0) + L
Ls
Ls
s
 


Prepared by CK
8
EE695K VLSI Interconnect
Solving s-Domain Circuit Equations
• Circuit Determinant: ∆( s) =
G + 1 Ls
− 1 Ls
− 1 Ls Cs + 1 Ls
= (G + 1 Ls )(Cs + 1 Ls) − (1 Ls )2
GLCs 2 + Cs + G
Ls
Depends on circuit element parameters: L, C, G=1/R,
not on driving force and initial conditions
=
• Solve for node A using Cramer’s rule:
I S ( s ) + iL (0) s
− 1 Ls
VA ( s) =
=
∆ A ( s) iL (0) s + CvC (0) Cs + 1 Ls
=
∆(s)
∆( s )
( LCs 2 + 1) I S ( s) − LCsiL (0) + CvC (0)
+
GLCs 2 + Cs + G
GLCs 2 + Cs + G
Zero State
when initial condition
sources are turned off
Zero input
when input sources
are turned off
Solving s-Domain Circuit Eqns. (Cont’d)
• Solve for node B using Cramer’s rule:
G + 1 Ls
VB (s) =
=
− 1 Ls
∆ B (s)
=
∆(s)
iL (0) s + CvC (0)
∆( s )
I S (s)
GLiL (0) + (GLs + 1)CvC (0)
+
2
GLCs + Cs + G
GLCs 2 + Cs + G
Zero State
Prepared by CK
I S (s) − iL (0) s
Zero input
9
EE695K VLSI Interconnect
Network Functions
Network function =
Zero - state Response Transform
Input Signal Transform
• Driving-point function relates the voltage and
current at a given pair of terminals called a port
V (s )
1
Z (s ) =
=
I (s ) Y ( s)
• Transfer function relates an input and response at
different ports in the circuit
V ( s)
TV (s ) = Voltage Transfer Function = 2
V1 (s )
I 2 ( s)
TI ( s) = Current Transfer Function =
V1
I1 (s )
I ( s)
In
TY (s ) = Transfer Admittance = 2
V1 ( s)
V ( s)
V1
TZ ( s) = Transfer Impedance = 2
I1 (s)
_
+
_
+
In
I (s)
+
Circuit
in the
zero-state
V (s)
−
Circuit Output
in the
V1 or I1
V or I
zero-state 2 2
Input
I2
+
V2
−
TV (s)
Out
I1 TI (s )
In
Out
I2
TY (s )
+
V2
−
I1 TZ (s)
Out
In
Out
Calculating Network Functions
Z1
V1 ( s)
+
Z2 V2 ( s )
−
_
+
I 2 (s )
I1 ( s)
Prepared by CK
Y1
Y2
• Driving-point impedance
Z EQ (s ) = Z1 (s ) + Z 2 ( s)
• Voltage transfer function:

 Z 2 (s )
V2 ( s ) = 
V1 ( s)
Z1 (s ) + Z 2 ( s) 
V ( s)
Z 2 ( s)
TV (s ) = 2
=
V1 ( s) Z 1 ( s) + Z 2 (s )
• Driving-point admittance
YEQ (s ) = Y1 (s ) + Y2 ( s)
• Voltage transfer function:
 Y2 (s ) 
I 2 (s ) = 
Y1 ( s)
Y1 ( s) + Y2 ( s) 
I (s )
Y2 ( s)
TI ( s) = 2
=
I1 (s ) Y1 ( s) + Y2 (s )
10
EE695K VLSI Interconnect
Impulse Response and Step Response
• Input-output relationship in s-domain
Input
Y (s) = T (s) X ( s)
X (s)
• When input signal is an impulse x(t ) = δ(t )
Y (s ) = T (s ) ×1 = T (s )
T(s)
Circuit
Output
Y (s)
– Impulse response equals network function
– H(s) = impulse response transform
– h(t) = impulse response waveform
• When input signal is a step x(t ) = u (t )
– G(s) = step response transform
– g(t) = step response waveform
G ( s) =
T ( s ) H ( s)
=
s
s
t
g (s ) = ∫h(τ )dτ ,
0
Prepared by CK
(=) means equal almost everywhere,
dg (t )
excludes those points at which g(t)
h(t )(=)
dt
has a discontinuity
11