Applied Thermal Engineering 219 (2023) 119370
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Applied Thermal Engineering
journal homepage: www.elsevier.com/locate/apthermeng
Research Paper
A combined solution of thermoelectric coolers and microchannels for
multi-chip heat dissipation with precise temperature uniformity control
Bo Cong a, b, Yanmei Kong a, *, Yuxin Ye a, Ruiwen Liu a, Xiangbin Du a, Lihang Yu a, b, Shiqi Jia a, b,
Zhiguo Qu c, *, Binbin Jiao a, *
a
b
c
Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China
University of Chinese Academy of Sciences, Beijing 100049, China
School of Energy and Power Engineering, Xi’an Jiaotong University, Xian 710049, China
A R T I C L E I N F O
A B S T R A C T
Keywords:
Multi-chip temperature uniformity
Thermoelectric cooler
Thermal test chip
Microchannel heat sink
Effective thermal management with precise temperature uniformity is necessary to improve the performance and
stability of multi-chip devices such as active phased array antennas, semiconductor laser radar systems, and light
emitting diode (LED) arrays. This study proposes a combined solution for multi-chip devices heat dissipation that
integrates thermoelectric coolers (TECs) and microchannel heat sink to tune the temperature of each chip
dynamically by controlling multiple TEC currents independently. The equivalent variable thermal resistance of
the TEC can be dynamically adjusted under different TEC currents, thereby realizing the equivalent thermal
resistance value of TECs change on the heat dissipation path of different chips and the precise temperature
control and continuity at desired temperature range. A simplified thermal resistance network of multi-chip is
established to illustrate the dynamic control mechanism of multi-chip temperature uniformity based on the
variable thermal resistance. Not only the heat dissipation and temperature control of single chip under different
operating conditions (TEC current, flow rate, and heat flux), but also the temperature uniformity control of multichip is studied. The combined cooling scheme is compared and analyzed with the microchannel cooling. The
results show that this combined cooling scheme can achieve precise temperature control of multiple chips with
maximum temperature difference less than 0.3 ◦ C and temperature standard deviation less than 0.07 ◦ C, which is
far less than the maximum temperature difference of 7.89 ◦ C and temperature standard deviation of 3.55 ◦ C
when the heat flux is 50 W/cm2. This represents a feasible solution for the realization of precise temperature
uniformity and dynamic temperature control in multi-chip devices.
1. Introduction
The miniaturization and increased integration of multi-chip elec­
tronic devices causes high heat flux and temperature nonuniformity [1].
Multi-chip electronic devices that are sensitive to temperature nonuni­
formity include active phased array antennas, semiconductor laser radar
devices, LED arrays. The power amplifier chip in the transmit/receive
(T/R) components of active phased array antennas are sensitive to
temperature, which affects their gain [2]. Thus, T/R modules require
accurate phase control to guarantee the stability of an antenna, and the
average temperature of two T/R modules should not exceed 10 ◦ C [3]. In
laser diodes (LDs), the wavelength is affected by temperature and
changes at a rate of 0.2–0.3 nm/◦ C [4]. Similarly, if an LED array has a
nonuniform temperature distribution, then the luminous flux will be
different for each LED [5]. Thus, effective thermal management is
required to improve the reliability and efficiency of multi-chip elec­
tronic devices.
Microchannel cooling is a promising technique that could satisfy the
heat dissipation requirements of high heat flux devices [6]. However,
large increases in the temperature of the cooling fluid along the direc­
tion of flow can affect the temperature uniformity of multi-chip elec­
tronic devices [7]. Constructal-theory networks have the potential to
improve the flow uniformity of coolants and the temperature uniformity
of multi-chip devices [8]. Various microchannel shapes and configura­
tions have been proposed to improve temperature uniformity in multichip devices. For example, H-type bifurcation structure [9], density-
Abbreviations: TEC, Thermalelectric cooler; TTC, Thermal test chip.
* Corresponding authors.
E-mail addresses: kongyanmei@ime.ac.cn (Y. Kong), zgqu@mail.xjtu.edu.cn (Z. Qu), jiaobinb@ime.ac.cn (B. Jiao).
https://doi.org/10.1016/j.applthermaleng.2022.119370
Received 15 June 2022; Received in revised form 12 September 2022; Accepted 20 September 2022
Available online 30 September 2022
1359-4311/© 2022 Elsevier Ltd. All rights reserved.
B. Cong et al.
Applied Thermal Engineering 219 (2023) 119370
Table 1
Results of previous studies investigating the effect of microchannel structures on multi-chip heat dissipation and temperature uniformity.
Study
Research method
Simulation
Experiment
[9]
[10]
[1]
[11]
[12]
[13]
[14]
√
√
√
×
√
√
√
√
×
√
√
√
√
×
Microchannel structure
No. chips
Heat flux (W/cm2)
Numerical results (◦ C)
ΔTmax
σT
ΔTmax
σT
H-type bifurcation
Density-based Topology
Fractal tree-like
Hierarchical Manifold
Leaf vein-shape
Spider web-like
Staggered fins
16
36
3
9
32
32
25
500
10
×
<75
100
150/100
125
<1
×
1.3
×
×
×
1.8
×
0.378
0.75
×
1.8
1.81
×
8.8
×
1.7
＜3
×
×
×
×
×
0.954
×
2.03
1.58
×
based topology optimization [10], fractal tree-like structures [1], hier­
archical manifolds [11], leaf vein-shaped structures [12], spider weblike structures [13], and staggered fins [14] have been investigated to
optimize microchannel designs for multi-chip heat dissipation, and the
details are shown in Table 1. The results of these studies show that the
temperature uniformity of multi-chip can be improved by optimizing the
microchannel structures, but the processing technology deviation, the
actual working environment and thermal interface material different
will affect the temperature uniformity of multi-chip devices. In addition,
the optimization of the microchannel structures is a passive enhance­
ment of the temperature uniformity in multi-chip devices, which cannot
realize the dynamic active adjustment of the high precision temperature
uniformity in multi-chip devices. Therefore, it is necessary to adopt
active control method to improve the temperature uniformity of multichip devices.
In order to realize the active control of temperature uniformity of
chip, Laguna et al. confirmed that a cooling array with self-adaptive
microvalves can proactively improve the temperature uniformity of
chip and reduce the pumping power [15]. Li et al. reported the selfadaptive microchannel cooling with the thermal-sensitive nano­
composite hydrogel, and the self-adaptive cooling is achieved by intel­
ligently adjusting the coolant through the heat load variation caused by
the thermal-sensitive property of the hydrogel [16]. Yan et al. investi­
gated the adaptive cooling of single and multiple hotspots with different
embedding positions and numbers of hydrogels in fractal micro­
channels, which can reduce the temperature of hotspots and improve the
temperature uniformity of multiple hotspots [3 17]. Owing to the shape
memory effect of shape memory alloy (SMA), the cooling capacity of
microchannel heat sink can be matched intelligently without external
control [18]. In the previous studies, the dynamic active temperature
control of chip is mainly achieved by embedding the structures or ma­
terials that can be deformed by temperature in microchannel. Although
these methods can achieve active temperature uniformity control of
multi-chip, the control capability is effective and the manufacturing
process is complex.
Thermoelectric cooler (TEC) is an active cooler that allows heat to
dissipate from a surface via the Peltier effect, which can precisely con­
trol the temperature of chip by adjusting the current of TEC. The applied
current causes charged carriers (electrons or holes) in the material, to
diffuse from the cold side to the hot side of TEC [19]. Therefore, the
external input current can pump heat away from the cold side to the hot
side. It is necessary to adopt an effective heat dissipation scheme to cool
the hot side of TEC. Different combined cooling methods were proposed
to realize chip cooling and temperature control. Compared with AHS
(air-cooled heat sink) + TEC cooling scheme, WMHS (water-cooled
microchannel heat sink) + TEC cooling scheme has a better cooling
performance by Lin et al, and they found that the hot side of a TEC can be
effectively cooled by a water-cooled microchannel in the combined
cooling solution using TEC and microchannels [20]. This can improve
the cooling capacity of the TEC and the overall cooling performance of
the combined system when the hot side is thermally regulated by liquid
cooling systems [21–23]. Based on the TEC cooling performance
changes with current, the stringent temperature control required by
Experimental results (◦ C)
some optoelectronic components can be provided by TEC, so as to sta­
bilize the temperature-dependent wave-lengths in laser beams [24,25].
In the research of chip temperature control by the combined cooling of
TEC and microchannels, Hu et al. compared the dynamic performance
under different operating conditions, including TEC with and without
temperature control and water cooling [26]. They achieved temperature
variations of less than 1.5 ◦ C with temperature control and water cool­
ing. Sullivan et al. [27] found that smaller TECs may be better at cooling
localized hotspots and mitigating the temperature gradient across a
chip. Therefore, the dynamic thermal management of multi-chip device
can also be achieved by using a combined cooling scheme of multi-TEC
and microchannel, and the multi-TEC can provide the on-demand
cooling of each chip. Although the total thermal resistance of the
package when the combined cooling scheme of microchannels and TEC
is used, the limited cooling capacity and thicker thermoelectric elements
(usually greater than 1 mm) of commercial TECs means that it is difficult
to achieve high heat flux chip cooling. Therefore, in order to improve the
cooling capacity of commercial TEC, a microchannel heat sink with
higher heat dissipation capacity can be selected to conduct thermal
management on the hot side of the TEC. Advance in the fabrication
technique with micro-electromechanical systems (MEMS) technology
has made it possible to fabricate micro-scale TEC, and the micro-scale
can reduce the thermal and electrical contact resistances. Chowdhury
et al. demonstrated the viability of refrigeration technology using
superlattice-based thin-film thermoelectric for a hotspot with a high
heat flux (1300 W/cm2) [28].
Previous studies have shown that combined cooling solution using
TECs and microchannels are an effective cooling and precise tempera­
ture control method for a single-chip. However, there are few studies
have applied this method to multi-chip devices, where temperature
different of multiple chips remain a significant concern. Therefore,
based on the potential of TECs to independently reduce hotspots to an
acceptable value [29], this study proposes a method of cooling multichip devices using a combined cooling system of TECs and micro­
channels, and explain the dynamic control mechanism of chip temper­
ature in terms of variable thermal resistance. By adjusting the cooling
current of each TEC in the combined cooling, the variable thermal
resistance value of the corresponding TEC can be adjusted, so as to
realize the change of thermal resistance value on different chip cooling
paths, and finally achieve the high precision temperature uniformity of
multi-chip. So, each TEC will act as an active temperature control device
and separately control heat dissipation for one chip with the aim of
achieving a uniform temperature distribution across a multi-chip device.
A microchannel cold plate will act as a heat sink on the hot side of TECs
to improve their cooling capacity. In this paper, thermal test chip (TTC)
will be used as thermal simulator chip to evaluate the thermo-hydraulic
performance of the combined system at different heat fluxes, TEC cur­
rents, and coolant flow rates. Heat dissipation and temperature control
are investigated for a single TTC, with the goal of achieving heat dissi­
pation with precise temperature uniformity control for multiple TTCs.
2
B. Cong et al.
Applied Thermal Engineering 219 (2023) 119370
discharged from the fluid outlet after passing through the hierarchical
multi-level bifurcation system (blue and red regions in Fig. 1(a)). This
reduces the drop in pressure and improves the uniformity of the flow by
reducing the length of microchannels [11].
Fig. 1(b) shows the thermal resistance network of the proposed
model with the combined cooling. The heat of the chip is conducted to
the cold side of the TEC through the thermal interface material, and the
corresponding interface thermal resistance is θa. The TECs operate based
on the Peltier effect; that is, heat generated by the chip is absorbed by
the cold side and emitted by the hot side as current passes through the
TEC. Then, the heat on the hot side of TEC is conducted downward to the
wall of the microchannels through the thermal interface material (the
corresponding interface thermal resistance is θb), and is absorbed by the
cooling medium and flows out from the outlet of microchannel heat sink.
The cooling capacity of a TEC depends on the current passing through it,
so a TEC can be considered as a variable thermal resistance (θthv) driven
by the equivalent current sources of the cold and hot sides. Based on the
Peltier and Seebeck effects, θthv can be used to convert electric power to
heat, thus promoting or hindering heat transfer [30]. TECs are a type of
heat engine driven by an external input current [31], so θthv is not strictly
a thermal resistance, but can be considered as a peculiar thermal resis­
tance with a negative value [32]. The different chips correspond to the
different heat dissipation paths in the thermal resistance network. Each
TEC cools one chip separately, and the equivalent thermal resistance of
the corresponding TEC can be changed by changing the current of TEC,
thereby realizing the heat dissipation with precise temperature unifor­
mity control for multi-chip.
In the thermal resistance network, the theoretical equations for the
TECs are [33]:
Fig. 1. (a) Structure of proposed multi-chip combined cooling system with
temperature uniformity control based on TECs and microchannels. (b) Simpli­
fied thermal resistance network diagram of proposed system with four chips.
1
Itec R2 − ktec (Th − Tc )
2
(1)
1
Qh = SItec Th + Itec R2 − ktec (Th − Tc )
2
(2)
2
Ptec = Qh − Qc = SItec (Th − Tc ) + Itec
R
(3)
Qc = SItec Tc −
2. A combined cooling system with temperature uniformity
control for a multi-chip test module
This section describes the concept of a combined cooling system with
temperature uniformity control for a multi-chip test module for a multichip device, and proposes a simplified thermal resistance network,
which can be used to understand the required temperature uniformity
control mechanisms. A multi-layer test module was used to study the
proposed combined cooling system under different experimental con­
ditions, and details of its design, fabrication, and assembly are provided.
The Seebeck coefficient (S), thermal conductivity (ktec), and elec­
trical resistance (R) are physical characteristics of the TECs, and Itec and
Ptec are the current passing through TEC and the power consumed by the
TEC, respectively. In addition, Th and Tc are the temperature of the hot
and cold side of the TEC, respectively.
According to the temperature node analysis of TEC cold side by en­
ergy conservation, Eq. (4) can be obtained [34].
2.1. Concept and thermal resistance network
A combined cooling scheme of microchannels and TECs for multichip device was proposed in this paper. The microchannel structure
and liquid separation structure of microchannel heat sink adopt multilevel bifurcation structure to reduce pressure loss and improve the
flow uniformity of coolant. The microchannel heat sink effectively dis­
sipates heat from the hot side of the TEC to increase the maximum
cooling capacity of the TEC. The current of each TEC is independently
controlled to achieve the on-demand cooling of each chip, thereby the
total thermal resistance on the cooling path of different chips can be
dynamically adjusted to achieve the high precise temperature unifor­
mity of multi-chip.
Fig. 1(a) shows the structure of the combined cooling system with
temperature uniformity control for a multi-chip device. Multiple TECs
are combined with a microchannel cold plate to achieve combined
cooling of a multi-chip device. Each chip is attached to the cold side of a
TEC, and the hot side of the TEC is attached to the microchannel cold
plate using a thermal interface material (TIM). Each TEC realizes the
active control of chip temperature, and the microchannel cold plate
realizes heat dissipation of each TEC hot side. The microchannel cold
plate contains multiple arrays of microchannel heat sink units, and each
heat sink unit includes a bank of high-aspect-ratio microchannels.
Coolant is delivered to the microchannels from the fluid inlet, and is
Tc − Th 1 2
Tc − Th
− Itec R + SItec Tc =
2
θth
θthv
(4)
Here, θth is the basic thermal resistance of TEC.
The temperature of TEC cold side can be expressed as:
Tc = Tj − θa Q
(5)
where Tj is the junction temperature of chip.
Combining Eqs. (3), (4) and (5), the variable thermal resistance of
TEC can be expressed as:
(
/2
)
Ptec Itec
− R θth
(
[
)]
θthv =
(6)
(Ptec − R) + 0.5SItec R − S2 Tj − θa Q θth
For a given TEC, the variable thermal resistance will vary with Ptec,
Itec and Tj.
In addition, the total thermal resistance (θ0) of the microchannel heat
sink can be expressed by the following equation:
θ0 =
Qh1 + Qh2 + ⋯ + Qhi + ⋯ + Qhn
Tch − Tin
where Qhi is the heat rejected from the hot side of TECi.
3
(7)
B. Cong et al.
Applied Thermal Engineering 219 (2023) 119370
Fig. 2. (a) Three-dimensional diagram showing structure of combined cooling system. (b) Coolant flow path. (c) Coolant flow in a single microchannel array unit. (d)
Microchannel cold plate.
As shown in Fig. 1, heat flux of multi-chip is parallel connection in
the microchannel heat sink. The assumption is that heat from different
chips will flow along the microchannel cold plate and is absorbed by
coolant, until heat flux converges to a region internal to heat sink, with a
characteristic temperature (Tch) [35]. In the TECs and microchannels
combined cooling system, the multi-chip temperature is determined by
self-heating effect and thermal coupling effect. The thermal coupling
between different chips can be calculated by thermal resistance matrix.
The thermal resistance matrix model is based on the principle of linear
superposition, and the temperature rise of chip i is obtained by super­
position the temperature rise for chip i when each chip acts alone. The
thermal resistance matrix with n chips [θj,in]n,n and the temperature of n
chips [Tj]n can be expressed as the following equations [35,36].
θik =
Tik − Tin
Qhk
⎛
[
θj,in
]n,n
θ11
⎜ θ21
⎜
=⎜
⎜ θ31
⎝ ⋮
θn1
many factors, such as thermal interface material differences, thermal
coupling effect, and machining deviations. In Eq. (6), the variable
thermal resistance will vary with Ptec, Itec and Tj for a given TEC type.
Therefore, the value of θthv is dynamically adjusted by independently
controlling the corresponding TEC current to change Ptec, Tc, Th, Qc and
Qh, so the thermal resistance of a chip can be adjusted independently to
achieve precise temperature uniformity across a multi-chip device in the
combined cooling.
2.2. Design, fabrication, and assembly of the test module
The design of a combined cooling structure based on TECs and
microchannel cold plate is shown in Fig. 2(a); in includes a chip layer,
TEC layer, microchannel cold plate layer, slot plate layer, and coolant
distributor layer. Fig. 2(b) shows the coolant flow path in the coolant
distributor, slot plate, and microchannel cold plate layer. The chip in
this study was a 1 × 1 × 0.4 mm3 (L × W × H) TTC, which can char­
acterize the thermal behavior of power devices [37]. The TTC, with
integrated silicon resistor strips and temperature-sensitive diode (TSD),
was manufactured using a standard complementary metal­
–oxidesemiconductor (CMOS) process, with the TSD located at the
center of device. The commercially available commercial TECs selected
for this study were type TES1-00708, which contain seven pairs of P–N
semiconductor columns, and have an overall size of 5 × 5 × 3 mm3 (L ×
W × H). The microchannel cold plate (Fig. 2(d)) was deep reactive ion
etched (DRIE) into 500 µm-thick silicon via the Bosch process, and the
microchannels were 50 µm wide and 350 µm deep. The 5 mm-thick slot
plate and 8 mm-thick coolant distributor were made by processing
polymethyl methacrylate (PMMA) sheets.
To assemble the multi-layer structure, thermal grease (GK-920) with
a thermal conductivity (k1) of 2 W/m⋅k was used to bond TTCi to the
center of the cold side of TECi, and the hot side of TECi to the top of the
microchannel array unit (where i denotes the ith component). Lasermachined graphic polyimide film double-sided adhesive (Kapton) 100
µm thick was used to seal the bond between the coolant distributor and
the slot plate, and the slot plate and the microchannel cold plate. In
addition, a 3 mm-thick TEC fixture was used to match the bonding po­
sitions and fix the TECs, and a 0.5 mm-thick printed circuit board (PCB)
was used to match the bond attaching positions of the TTCs and provide
(8)
θ12
θ22
θ32
⋮
θn2
θ13
θ23
θ33
⋮
θn3
⋯
⋯
…
θik
⋯
⎞
θn1
θn2 ⎟
⎟
θn3 ⎟
⎟
⋮ ⎠
θnn
⎞
⎞
⎛
Tj1
Qh1
⎟
⎜ ⎟
⎜
[ ]n ⎜ Tj2 ⎟ [ ]n,n ⎜ Qh2 ⎟
⎟
⎟
⎜
Tj = ⎜
⎜ Tj3 ⎟ = θj,in *⎜ Qh3 ⎟ + Tin
⎝ ⋮ ⎠
⎝ ⋮ ⎠
Tj4
Qhn
(9)
⎛
(10)
where θik (k = i) is the total thermal resistance along the heat transfer
path of chip i when there isn’t thermal coupling effect, θik (k ∕
= i) rep­
resents as the coupling thermal resistance from the chip k to i. Therefore,
the temperature of chip i can be calculated by Eq. (11).
Tji = θi1 Qh1 + θi2 Qh2 + ⋯ + θii Qhi + ⋯ + θin Qhn
(11)
where θii can be calculated by Eq. (12).
θii = θai + θthv,i + θbi +
Tch − Tin
Qhi
(12)
The temperature uniformity of multi-chip devices can be affected by
4
B. Cong et al.
Applied Thermal Engineering 219 (2023) 119370
Fig. 3. (a) Microscope image showing the structure of the 1 × 1 × 0.4 mm3 TTC. (b) Structure of TTCi-on-TECi assembly. (c) Test module after multi-layer assembly.
(d) Location and distribution of TTCs.
Fig. 4. (a) Schematic diagram of the experimental flow loop. (b) experimental photo of the flow loop.
an electrical connection to the heating resistors and TSDs in the TTCs.
The assembled test module is shown in Fig. 3(c).
3.1. Experimental setup
An open fluid loop (Fig. 4) was constructed to evaluate the temper­
ature of the TTCs, and the cooling and pumping power of the combined
cooling system. The TTC temperature Tttc was measured by using a 64bit standard temperature signal acquisition module, and the TECs
were driven by direct current (DC) power (RIGOL DP832). Deionized
water was used as the coolant, and an infusion pump (Y-600, XYHY)
transported it from a large volume reservoir to the liquid inlet of the test
module. The temperature of the coolant at the inlet was 23 ◦ C. T-type
thermocouples were used to measure the temperature of the coolant at
the inlet and outlet of the test module, and a differential manometer
(DPG409-050DWU, OMEGA) was used to measure the change in
pressure.
3. Experimental details
The experimental test platform was built to characterize the heat
dissipation and temperature uniformity control ability of the test mod­
ule. The uncertainty of the experimental instruments was recorded to
evaluate possible causes of deviation in the experimental data. Ac­
cording to the study of Lin et al., the current of TEC is most important
effect of the factors on the cooling performance compared with the flow
rate of coolant, inlet temperature of coolant, ambient temperature [20].
Therefore, this study mainly investigates the chip temperature change,
thermal resistance change, and temperature control ability from the
perspective of TEC current, and discusses the feasibility of controlling
the temperature uniformity of multi-chip devices.
3.2. Data reduction
The collected data included TTC temperature, TEC current, DC
power, and pressure drop, and they were monitored until a steady value
5
B. Cong et al.
Applied Thermal Engineering 219 (2023) 119370
Table 2
The datasheet parameters and calculation parameters of
TES1-00708.
Parameters
Value
Dimension (mm)
Th0 (K)
ΔTmax (K)
Imax (A)
Vmax (V)
Qc,max (W)
θth (K/W)
S (V/K)
R (Ω)
5×5×3
303.13
63
0.8
0.82
0.38
102 (Itec = 0 A)
0.0027
1.035
Table 4
Values of ΔTmax and σT for the four TECs under different cases of cooling.
ΔTmax ( C)
◦
σt (◦ C)
θ=
Coolant temperature ( C)
Pressure drop (kPa)
◦
Volumetric flow rate (ml/
min)
Power (W)
Case 3
Case 4
7.89
3.55
11.22
4.84
9.09
3.96
0.15
0.07
1 d1
k1 A
(18)
The measurement uncertainty and working range of each instrument
is listed in Table 3. The uncertainties were obtained from the manu­
facturers’ specifications, except for the TSDs. Before testing, the TTCs
were placed in an oven (ESPEC, SH-242) and multi-point temperature
calibration was used to improve the accuracy of the output voltage
signal of the TSDs. The temperature accuracy of the TTCs was ±0.1 K,
which was conservatively estimated by considering the accuracy of the
oven and the fluctuation in the output signal of the calibrated TSDs. In
this paper, the temperature of the TTCs was above 286 K, so the un­
certainty in the TTC temperature was less than 0.07 % ((|0.1 K| + |− 0.1
K|) / (286 K) × 100 %) [41]. According to the uncertainty analysis
method by Moffat [42], the uncertainty of q can be calculated by the
following formula, and the uncertainty of q is about ±0.21 %.
√̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
)2 (
)2
(
δq
δVttc
δIttc
(19)
=
+
q
Vttc
Ittc
Instrument
Range
Uncertainty
Thermocouple
Differential
manometer
Infusion pump
− 50–200
0–350
±1 ◦ C
±0.1 %
0–1000
±0.5 %
Power supply
0–195
0.05 % +20
mV
0.2 % +5 mA
was achieved. The TTC temperature was controlled and kept below
125 ◦ C based on the maximum permitted temperature of silicon-based
devices [38,39]. The TTC temperature was obtained by monitoring the
calibrated TSD output voltage.
The parameters in datasheet provided by manufacturers of TECs are
mainly include ΔTmax, Imax, Vmax and Qmax, among which ΔTmax is the
maximum temperature difference between the hot and cold side at a
given hot side temperature Th0 and Qc is 0, Imax and Vmax are the input
current and voltage at ΔT = ΔTmax, and Qc,max is the maximum amount
of heat that can be absorbed at cold side at I = Imax and ΔT = 0. Table 2
shows the parameters of the TES1-00708. The following equations can
be used to calculated the physical characteristics of TEC from datasheet
[40].
S=
Vmax
Th0
(13)
R=
(Th0 − ΔTmax )Vmax
Th0 Imax
(14)
4. Results and discussion
First, the heat dissipation and temperature control performance of
the proposed combined cooling system were investigated using a single
TTC (TTC1). Then, the potential thermal coupling of a multi-chip device
was investigated using multiple TTCs (TTC1, TTC2, TTC3, and TTC4).
Finally, combined cooling with temperature uniformity control for
multiple TTCs was studied. The location distribution of TTCs is shown in
the Fig. 3(d) (see Table 4).
4.1. Combined cooling with temperature control for a single thermal test
chip
As shown in Fig. 5(a), the TTC1 temperature Tttc1, f, and TEC1 current
Itec1 are measured and analyzed. The temperature is mainly affected by
the TEC current, and is less affected by the flow rate. This is because the
TEC and thermal interface materials have high thermal resistances and
the microchannel cooling is indirect cooling, so increasing flow rate
doesn’t significantly reduce the TTC temperature. At a constant Itec1, Tttc1
hardly change when f exceeds 160 ml/min, which indicates that the heat
from hot side of TEC1 is efficiently transferred to the microchannel heat
sink. Therefore, the flow rate of coolant is fixed at 160 ml/min in the
subsequent analysis. Tttc1 decreases as Itec1 increased, but Tttc1 at Itec1 =
1.2 A is higher than that at Itec1 = 0.9 A. The TEC operates on the basis of
the Peltier effect by dumping heat from the hot side to the cold side
when the applied current flows through it [43]. There is also Joule
heating occurs within the TEC, and it directly proportional to the square
value of the applied current passing through it, so the Joule heating
exceeds the Peltier cooling at Itec1 = 1.2 A. Thus, the optimum TEC
cooling current Iopt occurs between 0.9 and 1.2 A at 50 W/cm2, and the
optimal cooling current corresponds to the maximum cooling capacity of
TEC in the combined cooling.
From Fig. 5(b), it is clear that the optimum cooling current for TEC1
is approximately 1.1 A, and the corresponding minimum TTC1 temper­
ature is 43.15 ◦ C. When Itec1 is greater than 1.1 A, the TTC1 temperature
increases as Itec1 increased. The Peltier effect is not obvious when Itec1 =
The Q applied to each TTC was obtained by multiplying the TTC
current Ittc by the voltage at each end Vttc; that is,
Q = Ittc Vttc
(15)
Q
At
(16)
q=
Case 2
3.3. Uncertainty
Table 3
Uncertainty and working range of experimental instruments.
Parameter
Case 1
where At is the surface area of each TTC (1 × 1 mm2).
To evaluate the temperature uniformity of multiple TTCs, the stan­
dard deviation of the temperature (σt) of multiple TTCs is calculated
using the equation:
√̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
n
1∑
(17)
σt =
(Ti − T)2
n i=1
Here, Ti is the temperature of TTCi and T is the average temperature
of multiple TTCs.
The thermal resistance (θa and θb) of the thermal interface layer can
be calculated by Eq. (18). The thickness of the interface layer is about
0.1 mm (d1).
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Applied Thermal Engineering 219 (2023) 119370
Fig. 5. Combined cooling for TTC1 at 50 W/cm2. (a) TTC1 temperature against flow rate at different TEC1 currents. (b) TTC1 temperature and TEC1 power against
TEC1 current. (c) TTC1 temperature change and temperature management efficiency against TEC1 current. (d) The variable thermal resistance against TEC1 current.
0.1 A, the TTC1 temperature decreases slightly because the TEC1 power
Ptec1 is close to 0 W (TTC1 heat load is 0.5 W). Fig. 5(c) shows that the
temperature change ΔTd and management gains ηt varies with the cur­
rent at 160 ml/min. The TEC temperature management gains is defined
as the ratio of ΔTd to Ptec at the corresponding Itec. The ηt decreases as Itec
increases, and the ΔTd by a maximum of 36.64 ◦ C at Itec1 = 1.1 compared
with the temperature at Itec1 = 0 A. The TEC has higher ηt when Itec1 is
low because the Joule heating is small. This indicates that the low
applied current can reduce the effect of Joule heating and save the
cooling power consumption. Fig. 5(d) shows the variation trend of θthv
with TEC current, and the calculation formula is shown in Eq. (6). In this
experiment, limited by the lower heat dissipation capability of TES100708 and the thicker thermoelectric element (about 2 mm), TEC has
a larger thermal resistance. Owing to the higher thermal resistance of
TEC compared with other thermal resistance (interface thermal resis­
tance, microchannel heat sink thermal resistance), the temperature of
TTC will change significantly at different Itec. θthv decreases significantly
when the Itec is small, which is due to the change of the internal heat
transfer mechanism of the TEC after passing current. θthv slowly rises
after reaching the minimum value (56.66 K/W) at Itec1 = 1 A, since the
Joule heat term is a power function, the proportion of Joule heat term in
the heat exchange increases as the current increases. The difference
between the experimental results and the calculated results is due to the
Fig. 6. TTC1 temperature against heat flux for different TEC1 currents at a flow
rate of 160 ml/min.
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Applied Thermal Engineering 219 (2023) 119370
Fig. 7. Optimum TEC1 cooling capacity with combined cooling at different heat fluxes. (a) Optimum TEC1 cooling current and cooling power. (b) TTC1 temperature
at Itec1 = 0 A and Itec1 = Iopt.
TEC module parameters (S, R and θa) are taken as constants. Actually, S
and R depend on the temperature, and the thermal interface material
may have small bubbles and the thickness is more or less deviated from
0.1 mm. In theory, θthv can be negative at low heat load. Based on the
change of TEC equivalent thermal resistance, the chip temperature can
be precisely regulated under different heat load. Therefore, the high
precise temperature uniformity of multi-chip can be achieved by regu­
lating the equivalent thermal resistance of TEC at different Itec.
cold side is much less than heat load at high heat flux.
Fig. 7(a) shows the optimum TEC1 cooling current and correspond­
ing optimum cooling power (Popt) under different heat fluxes at a flow
rate of 160 ml/min. The optimum TEC1 cooling current and cooling
power gradually increase as the heat flux increases, which may be
because the temperature difference between the hot and cold sides of
TEC1 is greater when the heat flux is higher. Fig. 7(b) shows Tttc1 at a
flow rate of 160 ml/min when Itec1 is 0 A and Iopt. As the heat flux in­
creases, ΔTd gradually increases because the TEC1 optimum cooling
power increases. The combined cooling system reduces Tttc1 by 39.86 ◦ C
at a heat flux of 70 W/cm2 when Itec1 is Iopt. Therefore, the temperature
uniformity of multi-chip can be achieved by independently controlling
different TEC currents in the combined cooling system, even if there are
large temperature difference among multi-chip.
4.1.1. Performance analysis at different heat fluxes
Tttc1 against heat flux at different Itec1 and a flow rate of 160 ml/min
is shown in Fig. 6. The relationship between temperature and heat flux is
approximately linear under the different Itec1. The linear relation can be
beneficial to predict the temperature of chip under different heat flux,
which can prevent the chip temperature from being too high and help to
select the appropriate TEC current. In order to further study the rela­
tionship between chip temperature and heat flux when Itec is low. The
temperature curve for a TEC1 current of 0.1 A approaches the temper­
ature curve for a TEC1 current of 0 A because the heat absorbed by the
4.2. Combined cooling with temperature control for multiple thermal test
chips
TECs can achieve independent temperature control for each TTC in
Fig. 8. Temperature and thermal resistance distribution of four TTCs at a flow rate of 160 ml/min when the heat flux at TTC1 is varied. (a) Temperature distribution
of four TTCs. (b) Thermal resistance distribution of four TTCs.
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Applied Thermal Engineering 219 (2023) 119370
Fig. 9. Combined cooling with temperature uniformity control for two TTCs at a flow rate of 160 ml/min. (a) Temperature and power distributions for TTC1 (60 W/
cm2) and TTC3 (40 W/cm2). (b) Temperature uniformity control for TTC1 (60 W/cm2) and TTC3 (40 W/cm2). (c) Temperature and power distribution for TTC1 (55
W/cm2) and TTC3 (40 W/cm2). (d) Temperature uniformity control for TTC1 (55 W/cm2) and TTC3 (40 W/cm2).
the combined cooling system so, owing to the structural symmetry of the
test module, two and four TTCs are used to study cooling with tem­
perature control uniformity.
from Fig. 8(b), which is due to the high base thermal resistance of TEC.
Therefore, the influence of thermal coupling on the temperature uni­
formity control of multi-chip can be ignored.
⎛
⎞
θ11 0 0 0
[ ]4,4 ⎜ θ21 0 0 0 ⎟
⎟
θj,in
=⎜
(20)
⎝ θ31 0 0 0 ⎠
θ41 0 0 0
4.2.1. Thermal coupling for multiple thermal test chips
There may be thermal coupling between chips in multi-chip devices,
which will affect the independent temperature control for each chip. In
this paper, TTC1, TTC2, TTC3, and TTC4 are selected to analyze thermal
coupling in the test module. Fig. 8(a) shows the temperature curves of
the four TTCs when a heat flux of 0–80 W/cm2 is applied to TTC1 alone,
and all the TECs are turned off. The results show that thermal coupling is
related to the distance between the TTCs. The TTC2 temperature is
affected by heat conduction from TTC1, and the TTC2 temperature in­
creases by 3.8 ◦ C when there is a heat flux of 80 W/cm2 at TTC1. The
different positions of multi-chip have different heat dissipation paths,
and the thermal coupling of adjacent chips may affect the temperature
uniformity of multi-chip devices. The corresponding thermal resistance
matrix is shown in Eq. (20) when the power is applied only to TTC1, and
the thermal resistance θ21, θ31, and θ41 represents as the coupling ther­
mal resistance from the TTC1 to TTC2, TTC3, and TTC4, respectively. The
thermal resistance can be calculated by Eq. (8). Obviously, the coupling
thermal resistance is much less than the total thermal resistance of TTC1
4.2.2. Combined cooling with temperature uniformity control for two
thermal test chips
Owing to their very small thermal coupling, TTC1 and TTC3 are
selected to investigate the combined cooling system with temperature
uniformity control for two TTCs. The current of TEC1 and TEC3 is
regulated independently at a constant flow rate (160 ml/min) in the
combined cooling system, thereby the temperature of TTC1 and TTC3 is
controlled independently.
Fig. 9(a) shows the Tttc1 and Tttc3 at heat fluxes of 60 and 40 W/cm2,
respectively, and Ptec1 and Ptec3 at different Itec. Ptec1 and Ptec3 are slightly
different at the same current, which may be due to deviation in the TIM
and TEC characteristic parameters. Temperature uniformity across TTC1
and TTC3 is achieved by increasing Itec1 to decrease Tttc1, which can
reduce the equivalent thermal resistance of TEC1. As shown in Fig. 9(b),
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Applied Thermal Engineering 219 (2023) 119370
Fig. 10. Temperature of four TTCs against heat flux under (a) case 1 and (b) case 2 cooling. (c) Temperature standard deviation curves for TTCs in (a) and (b). (d)
Temperature of four TTCs under different types of cooling. Case 1, microchannel cooling (without TECs); case 2, combined cooling (Itec = 0 A, the four TECs are
switched off); case 3, combined cooling (Itec = Iopt, the four TECs are working at optimum cooling currents); and case 4, combined cooling (Itec3 = Iopt, the other three
TECs are working) with temperature uniformity control. The four TECs are TEC1, TEC2, TEC3, and TEC4.
the difference in temperature between TTC1 and TTC3 is kept below
0.3 ◦ C by adjusting the TEC1 current. Precise temperature uniformity
(ΔTmax < 0.3 ◦ C) across TTC1 and TTC3 is achieved by adjusting Itec1
when the Tttc1 exceeds 55.14 ◦ C, because Tttc1 is 55.14 ◦ C when TEC1
reaches the optimum cooling capacity.
As shown in Fig. 9(c), compared with Fig. 9(a), the difference in
temperature between TTC1 and TTC3 reduces because the heat flux of
TTC1 is decreased to 55 W/cm2. Fig. 9(d) shows that increasing Itec1 can
bring the temperature difference between TTC1 and TTC3 to 0.3 ◦ C when
Tttc3 exceeds 49.98 ◦ C. Therefore, the TEC optimum cooling capacity of
the combined system will limit the adjustable range of temperature
uniformity control, and the adjustable range of temperature uniformity
control is smaller when the difference in the heat flux across a multi-chip
device is bigger. Furthermore, the combined cooling system can achieve
a maximum temperature difference within 0.3 ◦ C when there are more
chips.
4.3. Comparative analysis of combined cooling and microchannel cooling
for four thermal test chips
In order to further analyze and compare the effects of combined
cooling and microchannel cooling on multi-chip heat dissipation and
temperature uniformity. Four types of cooling are considered in this
experiment: case 1, microchannel cooling (Four TTCs are bonded to the
microchannel cold plate by the thermal interface material and without
TECs); case 2, combined cooling (Itec = 0 A, the four TECs are switched
off); case 3, combined cooling (Itec = Iopt, the four TECs are working at
optimum cooling currents); and case 4, combined cooling (Itec3 = Iopt, the
other three TECs are working) with temperature uniformity control.
Fig. 10(a) shows the temperature curves for four TTCs with case 1
cooling. The temperature across the four TTCs became less uniform as
the heat flux increases. The maximum temperature difference is
31.25 ◦ C at 150 W/cm2, which may be attributed to the effects of flow
maldistribution and the thermal interface materials. As shown in Fig. 10
(b), the maximum temperature difference between the four TTCs with
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Applied Thermal Engineering 219 (2023) 119370
case 2 cooling gradually increases as the heat flux increases, from
3.62 ◦ C at 20 W/cm2 to 13.07 ◦ C at 80 W/cm2. Due to the high thermal
resistance of the TEC and the effect of the two-layer interface materials,
the temperature of TTC3 exceeds 125 ◦ C when the heat flux is 80 W/cm2.
Fig. 10(c) shows the temperature standard deviation curves, σt,1 and σ t,2,
for the TTCs shown in Fig. 10(a) and (b), respectively. When the heat
flux exceeds 50 W/cm2, the small variations in σt,2 may be attributed to
the lower heat dissipation capacity resulting from the longer heat
dissipation path and the greater thermal resistance in combined cooling
system.
Fig. 10(d) shows the temperatures of the four TTCs with each type of
cooling when the heat flux is 50 W/cm2. Tttc3 as the adjustment target
temperature of other TTCs. After modulating the three remaining TEC
currents in case 4, the maximum temperature difference and tempera­
ture standard deviation of the four TTCs are 0.15 ◦ C and 0.07 ◦ C,
respectively. The small cooling capacity of the commercial TECs meant
that, at a heat flux of 50 W/cm2, combined cooling does not significantly
improve the performance compared to microchannel cooling alone.
However, precise temperature uniformity control can be achieved for
multi-chip devices using a combined cooling system to regulate the
equivalent thermal resistance of different chip heat dissipation paths.
The details of the maximum temperature difference and temperature
standard deviation for the four TTCs under the different cases of cooling
are shown in Table 3, and the corresponding heat flux is 50 W/cm2.
Compared with the data in Table 1 of improving the temperature uni­
formity of multi-chip by using the optimized microchannel structure, the
combined cooling based on TECs and microchannels has higher tem­
perature uniformity, simple operation method and high control
precision.
superlattice-based thin-film TECs integrated with microchannels.
Declaration of Competing Interest
The authors declare that they have no known competing financial
interests or personal relationships that could have appeared to influence
the work reported in this paper.
Data availability
Data will be made available on request.
Acknowledgements
This work was supported by the National Key R&D Program of China
(grant number 2020YFB2008900). We also thank Suzhou Rich Sensor
Science & Technology Co., Ltd for providing the thermal test chip and
technical support.
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