ASIC RTL Guideline
<<Principles_of_VLSI_RTL_Design.pdf>>
How can an RTL designer make later stages (Simulation, Synthesis, Place&Route, Timing closure and
DFT) of an IC design smoother? How essential is an RTL designer’s role in delivering a quality chip to the
market at the right time and what precautions he needs to take to deliver quality RTL?
1. RTL designer should code simulation friendly RTL
a. Avoid a RTL coding styles that results in pre and post simulation mismatches.
2. The RTL coded should be timing analysis friendly
a. Avoid a coding style that results in inferring unintentional latches as latches are hard to
analyze by the trimming analysis tool.
b. Avoid combinational loops.
always @(in1, in2)
if(in1)
out = in2
else
out = out
3. Makes sure that RTL coded is CDC friendly.
a. It is very important for an RTL engineer to list all the CDC paths in the design and have
appropriate synchronization circuit in place to handle cock crossing.
b. There are various synchronization methods such as double synchronization,
synchronized common enable & FIFO. It is again a RTL designer who decides which
method to use for synchronization based on type of the signal crossing clock domain.
4. DFT friendly RTL help DFT team to catch all possible manufacturing faults using stuck at fault
methodology.
a. An ATPG (automation test pattern generator) tool endeavor to see if any design nets are
stuck at '0' or '1'.
b. ATPG can only access/drive any given nets in the design either through inputs of the IC
or through scan flops and observe them through an output ports or scan flops so, it is
RTL designer responsibility to ensure that all the nets in the design are controllable and
observable.
c. Don't ever code combinational loops as they make nets unobservable.
5. Timing exception friendly RTL helps STA tools to have better understanding of all types of timing
exceptions paths (false and multicycle paths) exists in design.
a. Only an RTL designer can know which timing paths are false and multicycle paths so, it is
his responsibility to define all the timing exception paths in SDC file.