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Hardware Modeling Using Verilog
Assignment- Week 2
TYPE OF QUESTION: MCQ/MSQ/SA
Number of questions: 8
Total mark: 8 X 1 = 8
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QUESTION 1:
Which of the following statements is/are false for Verilog modules?
a. A module can contain one or more definitions of other modules.
b. If a module X is instantiated 4 times within another module Y, only one copy of X
is created, which is linked 4 times.
c. A module can be instantiated within another module any number of times.
d. If a module X is instantiated 4 times within another module, 4 copies of X are
created.
Correct Answer: a, b
Detailed Solution:
In Verilog, module definitions must be disjoint, and one module cannot be defined within
another. Also there is no concept of calling or linking a module from other modules. When a
module is instantiated k times, k copies of the module are created in the design. Options (a)
and (b) are false statements here.
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QUESTION 2:
What does the statement “assign f = (a | b) & (c | d)” signify?
a.
b.
c.
d.
A gate level netlist consisting of two OR gates, and one AND gate.
A behavioral description of the function f.
A structural description of the function f.
None of these.
Correct Answer: b
Detailed Solution:
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The “assign” statement only specifies a function; it does not specify the gates or the netlist to
be used for implementation. It basically specifies the behavioral description of the function.
Hence, only option (b) is correct.
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QUESTION 3:
Which of the following is/are true for register type variables?
a.
b.
c.
d.
They always map to a hardware register after synthesis.
They can be used in an expression on the RHS of an “assign” statement.
They may also be used to model a combinational circuit.
None of these.
Correct Answer: b, c
Detailed Solution:
A register type variable may either map to a storage cell during synthesis, or it may also be used
to realize a pure combinational circuit.
In an “assign” statement, both “net” and “register” type variables may be used in the
expression on the right hand side.
Hence, the options (b) and (c) are true.
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QUESTION 4:
For the following Verilog code segment, what will be the number of bits in “sum” as deduced
during synthesis?
wire [6:0] data1, data2;
reg [7:0] dummy;
integer sum;
sum = (data1 + data2) + dummy;
a.
b.
c.
d.
7
8
9
None of these
Correct Answer: c
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Detailed Solution:
Both data1 and data2 are 7-bit variables. When “data1” and “data2” are added, the result can
be of 8 bits. When this result is added to “dummy” (which is an 8-bit variable), the result can be
of 9 bits. The synthesis tool will make this calculation and assign 9 bits to “sum”. Hence, the
correct option is (c).
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QUESTION 5:
For the following Verilog code segment, if the initial value of IR is 2D00 023A (in hexadecimal),
what will be the value of “memaddr” in decimal?
wire [31:0] IR;
wire [7:0] opcode;
wire [23:0] address;
wire [23:0] memaddr;
assign opcode = IR[31:24];
assign address = IR[23:0];
assign memaddr = address + 100;
a.
b.
c.
d.
685
670
723
None of these
Correct Answer: b
Detailed Solution:
address = 00023A (in hex) = 570 (in decimal)
memaddr = 570 + 100 = 670
Thus, the value of “memaddr” in decimal will be 670. So, option (b) is correct.
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QUESTION 6:
Consider the following Verilog module.
module ALU (data1, data2, cond, result);
input [7:0] data1, data2;
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input [2:0] cond;
output reg [7:0] result;
always @(data1 or data2 or cond)
begin
if (cond == 3’b000) result = data1;
else if (cond == 3’b001) result = data2;
else if (cond == 3’b010) result = data1 +
else if (cond == 3’b011) result = data1 else if (cond == 3’b101) result = data1 &
else if (cond == 3’b110) result = data1 |
else if (cond == 3’b111) result = 0;
end
endmodule
data2;
data2;
data2;
data2;
What will happen when the module is synthesized?
a. A combinational circuit will be generated.
b. A sequential circuit with storage elements will be generated.
c. If the synthesizer supports adder and subtractor blocks, a combinational circuit
will be generated.
d. None of these.
Correct Answer: b
Detailed Solution:
In the “if” construct, we do not assign values to “result” for all possible values of “cond”. For
instance, (cond == 3’b100 )is not checked. This will result in storage elements to be generated
for “result”. Hence, the correct option is (b).
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QUESTION 7:
Consider the following Verilog code segment:
wire [5:0] A, B;
wire C;
assign C = ^A;
If the values of A and B are 5’b10011 and 5’b01110 respectively, what will be the value of
{A[3:1], 2{C}, B[2:0]}?
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a.
b.
c.
d.
00100110
00111110
01111110
None of these
Correct Answer: b
Detailed Solution:
Here, A[3:1] = 001
C = 1 (bitwise XOR of all the bits in A)
B[2:0] = 110
Hence, {A[3:1], 2{C}, B[2:0]} = 001 11 110
The correct answer is (b).
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QUESTION 8:
When does the $monitor statement in a Verilog test bench print the specified values?
a.
b.
c.
d.
At the start of the simulation.
When the $monitor statement is first encountered.
Whenever the value of any of the specified variables change.
None of the above.
Correct Answer: c
Detailed Solution:
The $display statement prints the value whenever it is executed. In contrast, the $monitor
statement prints the values whenever the value/state of at least one of the parameters is
modified. Hence, the correct answer is (c).
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