Uploaded by Brady Mitchelmore

Final Cheat Sheet

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·5
ENMI Vaee
Minterm
means
Maxterm
means
fall-adder
ont
Half-udder
/rosene
AB
1su
I
A
·
B
8.
8
A*B
=
0
b
)
cont=AB
9
·
I
Decoder
JK
I
Multiplexer
Latch/ Ff
DR
I
Latch/FF
SR
FF
T
FF
VHDL Models
①
Behavioral
② Structural
③ Dataflow
Look
-
-
-
design
based
describe
how
described
by
ahead
on
is
truth
table
baitfrom
simpler
logical expression
carry
or
of
(if,
behaviour
modules
digital
else
(gates)
(2, 1, &)
circuit
I
Flip Flops are triggered
by posing edges
Latches
by
adder
are
inputs
Gr An. Bu
=
Pr
An & Bu
=
(n Gn Pn(n
=
+
-
1
-
triggered
conditional:
and -> masking
or
Branch
combining
for
Unconditional:
inverting
Jump
Instruction
32-bitconstant
If
MSB
of
addi
① Fetch:
is
cement,Ope
I,
-
Cycle
-& Decode:
③
instructions
fetching
[PC]
->
Cyclel
(4
[AR]
decode
Execution:
->
③ Clean Up!
Instruction
Clem
opera
·
the
caller-calls
Callee
-
Program Memory
-
DR
-
IR
operand
opcode to operand
including registers to buses for
execute based
buffers
the
factto
then returns to
function
called
memory
I
on
next
(Ju
Functions
·
all
tion
program
->
instructions, getopcode
-
Ifstatement:
from
[Address (bus]
-
etewetejusans wherei
caller
↑
ra
return
=
->
address
PC
program
=
conta
If-else statement:
Args
while
returns
t
statement!
Arrays
elements
e memory
For Loop:
base
address
stored
->
I
②
①
Fetch
read
Instruct
operand
&
Compute memory
Instruction Fetch
①
② Instruction Decode
③ Execution (ALU)
address
S
④ Memory
&
from
⑥ read data
memory I write
backto
③
Extend
L
immidiate
register
file
-
⑮
Register
Access
Writeback
sequentially
in
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