1. Briefly describe COWOS technology
Chip-on-Wafer-on-Substrate (CoWoS) is a two-point-five dimensional integrated
circuit (2.5D IC) through-silicon via (TSV) interposer-based packaging technology designed
by TSMC for high-performance applications.
CoWoS is a 2.5D wafer-level multi-chip packaging technology that incorporates
multiple dies side-by-side on a silicon interposer in order to achieve better interconnect
density and performance. Individual chips are bonded through micro-bumps on a silicon
interposer forming a chip-on-wafer (CoW). The CoW is then subsequently thinned such that
the TSV perforations are exposed. This is followed C4 bumps formation and singulation. A
CoWoS package is completed through bonding to a package substrate.
2. Briefly describe INFO technology
In InFO(integrated Fan-Out) technology, copper interconnects formed after the exposure of
on-chip aluminum pads, known as post-passivation interconnects (PPI), allow signals to fan
out to regions larger than the silicon die shadow.
InFO-WLP provides distinct advantages over flip-chip ball grid array (FC-BGA) packaging.
First, I/O's can be redistributed to the fan-out region outside of the silicon die shadow for
increased pin count at the package level. Second, passive devices such as inductors and
capacitors can be formed over molding compound for lower substrate loss and higher
electrical performance. Third, a smaller form factor leads to better thermal behavior and
hence a lower operating temperature for the same power budget, or alternatively, faster
circuit operation for the same temperature profile as FC-BGA
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InFO_PoP
InFO_PoP, the industry's 1st 3D wafer level fan-out package, features high density RDL and TIV to
integrate mobile AP w/ DRAM package stacking for mobile application. Comparing to FC_PoP,
InFO_PoP has a thinner profile and better electrical and thermal performances because of no
organic substrate and C4 bump.
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InFO_oS
InFO_oS leverages InFO technology and features higher density 2/2µm RDL line width/space
to integrate multiple advanced logic chiplets for 5G networking application. It enables hybrid
pad pitches on SoC with minimum 40µm I/O pitch, minimum 130µm C4 Cu bump pitch and > 2X
reticle size InFO on >65 x 65mm substrates. Production ramped in Q4'17. Expect to integrate
more chips as our customers continue to accelerate the adoption of chiplet packaging scheme
for their next generation products.
3. Briefly describe Si FinFET technology
最初的電晶體結構是矩形的，源極、汲極和閘極這 3 個結構之間的接觸面，都是一個平
面。後來，隨著製程技術不斷提升，晶體管中閘極的寬度越來越小。
當這個閘極低於 20 nm 時，對電流就會失控，源極的電流會穿透閘極，直接到達汲極。
相當於晶片的「漏電」，讓晶片發熱量急劇上升。
1999 年，胡正明教授發明「FinFET 電晶體技術」，解決當時電晶體漏電問題。胡正明
教授的 FinFET 解決方案就是「改變結構」。改造電晶體的結構，把源極和汲極做成「直
立」的樣子，然後讓閘極包圍住源極和汲極，相當於增加了閘極和源極、汲極的接觸面
積，加強閘極的控制能力，避免漏電現象。因為這種結構長得像「魚鰭」，所以也被叫做
鰭片結構。