VLSI LAB (18EC614)
Important Questions for Both Internal and External Examination
Combinational Circuits Using:
(a) Gate level Model ,
(b) Dataflow model and
(c) Behavioural Models
1.
2.
3.
4.
5.
6.
Basic Logic Gates
8-bit Adder
Boolean Expression
8x1 MUX
3x8 Decoder
8x3 Encoder
Sequential Circuits Using Behavioural Model ONLY
7.
8.
9.
10.
D-Flip Flop
8-bit Register
SISO, SIPO, PISO, PIPO
FSM: Sequence Detector
a. Mealy Machine with Overlapping
b. Mealy Machine with Non-Overlapping
c. Moore Machine with Overlapping
d. Moore Machine with Non-Overlapping
Layout Model
11. NMOS Characteristics & Layout
12. CMOS Inverter Characteristics & Layout
13. NAND Gate Layout