ASSIGNMENT-3
1. What are the different topologies of Single stage Amplifier? Differentiate them.
Single-stage amplifiers are amplifiers that consist of a single active device (such as a
transistor) and provide amplification of the input signal. The most common topologies
of single-stage amplifiers are as follows:
Common-Emitter (CE) Amplifier:
The common-emitter amplifier is a widely used configuration in transistor amplifiers.
In this topology, the input signal is applied to the base terminal, the output is taken
from the collector terminal, and the emitter terminal is common to both input and
output. The CE amplifier provides high voltage gain and medium current gain. It has a
high input impedance and a relatively low output impedance. The CE amplifier is
suitable for applications where high voltage gain and moderate power gain are
required.
Common-Base (CB) Amplifier:
The common-base amplifier has the input applied to the emitter terminal, the output is
taken from the collector terminal, and the base terminal is common to both input and
output. The CB amplifier provides high current gain and low voltage gain. It has a
low input impedance and a relatively high output impedance. The CB amplifier is
commonly used in RF (Radio Frequency) applications where low input impedance
and high current gain are required.
Common-Collector (CC) Amplifier:
The common-collector amplifier, also known as the emitter follower, has the input
applied to the base terminal, the output is taken from the emitter terminal, and the
collector terminal is common to both input and output. The CC amplifier provides a
voltage gain slightly less than unity (less than 1), but it provides high current gain. It
has a high input impedance and a low output impedance. The CC amplifier is often
used as a buffer stage between different stages of amplification to provide impedance
matching and isolation.
Differentiating the topologies:
Input and Output Configurations: In the CE amplifier, the input is applied to the base
terminal and the output is taken from the collector terminal. In the CB amplifier, the
input is applied to the emitter terminal and the output is taken from the collector
terminal. In the CC amplifier, the input is applied to the base terminal and the output
is taken from the emitter terminal.
Voltage and Current Gain: The CE amplifier provides high voltage gain and medium
current gain. The CB amplifier provides high current gain and low voltage gain. The
CC amplifier provides a voltage gain slightly less than unity (less than 1), but it
provides high current gain.
Input and Output Impedance: The CE amplifier has a high input impedance and a
relatively low output impedance. The CB amplifier has a low input impedance and a
relatively high output impedance. The CC amplifier has a high input impedance and a
low output impedance.
Applications: The CE amplifier is suitable for applications where high voltage gain
and moderate power gain are required. The CB amplifier is commonly used in RF
applications where low input impedance and high current gain are required. The CC
amplifier is often used as a buffer stage between different stages of amplification to
provide impedance matching and isolation.
2. Draw a neat circuit diagram of Common Source, Common gate Amplifier &
Source Follower and explain its operation.
3. Explain a clocked flip-flop Logic circuit.
In the clocked R-S flip-flop the Q output will be unaffected by any change in R or S
as long as the clock (C) is “0” (low). That is, during the “read” phase of the clock
cycle the contents of memory cannot be changed. When the clock input goes to “1”
(high), designating the “write” phase of the clock cycle, the Q output will change
depending upon the values of R and S.
4. Draw and explain a CMOS logic circuit for NAND gate.
It consists of two P-channel MOSFETs, Q1 and Q2, connected in parallel and two Nchannel MOSFETs, Q3 and Q4 connected in series.
P-channel MOSFET is ON when its gate voltage is negative with respect to its source
whereas N-channel MOSFET is ON when its gate voltage is positive with respect to
its source.
when both inputs are low. Here, the gates of both P-channel MOSFETs are negative
with respect to their sources, since the sources are connected to +VDD. Thus, Q1 and
Q2 are both ON. Since the gate – to – source voltages of Q3 and Q4 (N-channel
MOSFETs) are both 0V, those MOSFETs are OFF. The output is therefore connected
to +VDD (HIGH) through Q1 and Q2 and is disconnected from ground.
when A = 0 and B = +VDD. In this case, Q1 is on because VGS1 = −VDD and Q4 is
ON because VGS4 = +VDD. MOSFETs Q2 and Q3 are off because their gate-tosource voltages are 0 V. Since Q1 is ON and Q3 is OFF, the output is connected to
+VDD and it is disconnected from ground. When A = +VDD and B = 0V, the situation
is similar (not shown) ; the output is connected to +VDD through Q2 and it is
disconnected from ground because Q4 is OFF. Finally, when both inputs are high (A =
B = +VDD), MOSFETs Q1 and Q2 are both OFF and Q3 and Q4 are both ON. Thus,
the output is connected to the ground through Q3 and Q4 and it is disconnected from
+VDD.
5. Write a brief note on typical design flow for designing VLSI IC circuits.
Steps of the VLSI Design Flow
The VLSI (Very Large Scale Integration) design flow is a series of steps used to create
a complex integrated circuit (IC) or system-on-chip (SoC). The following steps are
commonly included in the VLSI design flow:
1. Specification and Architecture
This is the initial stage where the requirements for the IC or SoC are defined,
including the functionality, performance, power consumption, and area constraints.
2. Design Entry
This involves creating a high-level design representation of the IC or SoC using a
hardware description language (HDL) such as Verilog or VHDL.
3. Functional Verification
This step involves verifying that the high-level design meets the specifications by
simulating it using a hardware simulator.
4. Synthesis
In this step, the high-level design is translated into a gate-level netlist, which is a
collection of logic gates and flip-flops that implement the design.
5. Design Optimization
The gate-level netlist is optimized for various design constraints such as power
consumption, timing, and area.
6. Physical Design
This step involves placing the gates and routing the interconnections to meet the
timing and area constraints.
7. Design Rule Check (DRC)
The physical design is checked against a set of design rules to ensure it is
manufacturable.
8. Layout Verification
The physical design is verified using simulations to ensure that it meets the
specifications.
9. Tape-out
Once the physical design is verified, the final design is sent to the fabrication facility
for manufacturing.
10. Testing
After the IC or SoC is fabricated, it is tested to ensure that it meets the specifications.
6. Explain Data flow modelling with an example.
Dataflow modeling provides the means of describing combinational circuits by their
function rather than by their gate structure. Dataflow modeling uses a number of
operators that act on operands to produce the desired results. Dataflow modeling uses
continuous assignments and the keyword assign. A continuous assignment is a
statement that assigns a value to a net. The datatype net is used in Verilog HDL to
represent a physical connection between circuit elements. The value assigned to the
net is specified by an expression that uses operands and operators.
Dataflow description of 2-to-1 line multiplexer
module mux2x1_df (A,B,select,OUT);
input A,B,select;
output OUT;
assign OUT=select ? A:B;
endmodule
7. Explain Behavioural modelling with an example.
Behavioral modeling represents digital circuits at a functional and algorithmic level. It
is used mostly to describe sequential circuits, but can be used to describe
combinational circuits. Here the behavioral modeling concept will be presented for
combinational circuits. Behavioral description use the keyword always followed by a
list of procedural assignment statements. The target output of procedural assignment
statement must be of the reg data type.
Behavioral description of 2-to-1 line multiplexer
module mux2x1_bh (A,B,select,OUT);
input A,B,select;
output OUT;
reg OUT;
always @(select or A or B)
if (select==1) OUT=A;
else OUT=B;
endmodule
8. Explain Data types of Verilog HDL.
Bit (reg, wire):
Represents a single binary digit (0 or 1).
Syntax: reg for variables that can be assigned values, wire for variables that can only
be used for signal connections.
Example: reg [0:0] my_bit;
Vector (reg, wire):
Represents a multi-bit vector, where each bit can be individually accessed.
Syntax: reg [n:0] or wire [n:0], where n specifies the width of the vector.
Example: wire [7:0] my_vector;
Integer (int, integer):
Represents signed or unsigned integer values.
Syntax: int or integer.
Example: integer count;
Real (real):
Represents floating-point numbers.
Syntax: real.
Example: real temperature;
Parameter (parameter):
Represents a constant value that can be used to configure or parameterize the design.
Syntax: parameter.
Example: parameter DATA_WIDTH = 8;
Enumerated (enum):
Represents a set of named values, providing a convenient way to define a set of states
or modes.
Syntax: enum.
Example: enum { IDLE, START, STOP } state;
state = START;
Struct (struct):
Represents a user-defined composite data type that combines multiple variables into a
single unit.
Syntax: struct.
Example: struct {
reg [7:0] data;
reg [3:0] flags;
} my_struct;
Arrays (reg, wire):
Represents a collection of multiple elements of the same data type.
Syntax: reg [n:0] array_size; or wire [n:0] array_size;, where n specifies the width of
each element.
Example: reg [7:0] memory[1023:0];
9. What do you mean by port, module, array, parameter, module instantiation in
Verilog HDL?
In Verilog HDL, a port refers to the interface of a module that enables
communication between the module and its surrounding environment. Ports define the
inputs, outputs, and bidirectional signals of a module.
module MyModule(input A, output B);
// ...
endmodule
A module is a basic building block in Verilog HDL that represents a hardware
component or a unit of functionality within a digital system. Modules encapsulate a
collection of statements, variables, and ports that define the behavior and
interconnections of the hardware component. Modules can be instantiated and
interconnected to form complex digital systems.
module MyModule(input A, output B);
// Logic implementation
endmodule
In Verilog HDL, an array represents a collection of multiple elements of the same
data type. Arrays allow you to conveniently store and manipulate multiple values in a
compact manner. Arrays can be declared using the square bracket ([]) notation,
specifying the range or size of the array.
reg [7:0] myArray [0:3];
// Declaration of a 4-element array of 8-bit registers
A parameter is a constant value in Verilog HDL that can be used to configure or
parameterize a design. Parameters enable flexibility in modifying certain
characteristics of a design without modifying the source code directly. Parameters are
typically declared at the module level using the parameter keyword.
module MyModule #(parameter WIDTH = 8) (input [WIDTH-1:0] A, output B);
// ...
endmodule
Module instantiation refers to the process of creating instances of a module within
another module or at the top level of a design. Module instantiation allows you to
reuse existing module designs and connect them together to form a larger system.
Instances of a module are created by using the module name followed by an instance
name and optional port connections.What is differential Amplifier? Explain its
different operational modes with neat diagram.
MyModule inst1 (.A(inputA), .B(outputB));
// Instantiation of a module named MyModule with port connections
10. What is CMRR?
CMRR stands for Common-Mode Rejection Ratio. It is a parameter used to measure
the ability of an amplifier or a differential circuit to reject common-mode signals.
Common-mode signals are those that are present at both input terminals of the
amplifier with the same magnitude and phase.
CMRR is defined as the ratio of the differential-mode voltage gain to the commonmode voltage gain. It quantifies how effectively the amplifier or circuit can amplify
the desired differential signals while attenuating or rejecting the unwanted commonmode signals. A higher CMRR value indicates better rejection of common-mode
signals and is desirable in applications where the differential signals of interest are
relatively small compared to the common-mode signals. It is often expressed in
decibels (dB) and can vary depending on the specific amplifier or circuit design.
CMRR is an important parameter in applications such as instrumentation amplifiers,
differential amplifiers, and communication systems, where the accurate amplification
of differential signals and rejection of common-mode noise are crucial for signal
integrity and fidelity.
11. What are the applications of differential amplifier?
Instrumentation Amplifiers: Differential amplifiers are commonly used in
instrumentation systems for precise measurements. They provide high common-mode
rejection, low noise, and high accuracy, making them suitable for amplifying small
differential signals in sensor and measurement applications.
Operational Amplifiers (Op-Amps): Differential amplifiers form the core of
operational amplifiers, which are widely used in analog signal processing, active
filters, and amplification circuits. Op-amps with differential inputs provide high gain,
low distortion, and good linearity.
Differential Communication Systems: Differential amplifiers play a key role in
differential signaling schemes used in communication systems. By transmitting data
as the difference between two voltages, these amplifiers help improve noise immunity
and common-mode rejection in high-speed communication interfaces like RS-485,
Ethernet, and USB.
Audio Amplifiers: Differential amplifiers find application in audio amplification
systems. They can be used to amplify audio signals with high fidelity and low
distortion. Differential amplifiers help in canceling out common-mode noise and
improving the signal-to-noise ratio in audio applications.
Balanced Modulators/Demodulators: Differential amplifiers are utilized in
balanced modulator and demodulator circuits, which are essential in communication
systems for frequency and phase modulation. They enable the generation and
recovery of modulated signals while suppressing undesired interference.
Automatic Gain Control (AGC) Circuits: Differential amplifiers are employed in
AGC circuits that adjust the gain of an amplifier to maintain a consistent output signal
level. Differential amplifiers in AGC circuits help maintain the desired signal level
while rejecting variations in the common-mode signal.
Differential Input ADCs: Differential amplifiers are used as front-end amplifiers in
differential input analog-to-digital converters (ADCs). They amplify and condition the
differential analog input signal before it is digitized by the ADC, providing better
accuracy and noise rejection.
12. Explain Current Mirror with a neat diagram.
Consider the above current mirror circuit using MOSFET, the MOSFET transistor M1 is in the
saturation region as the VDS ≤ VGS. For the case of MOSFET M2, it will also remain in saturation
mode as long as the output voltage is greater than the saturation voltage. Therefore the input
current across the M1 will control directly the output current of M2.
MOSFET device function like this, the drain current reflects the function of the gate to source
and drain to gate voltage.
So, the formula can be written using the below function,
ID = f (VGS, VDG)
Due to this, the input current in the MOSFET M1, is mirrored to the drain current. In the image,
the input current is provided by the bias resistor.
If the drain to gate voltage VDG is 0 for the MOSFET M1, the drain current of M1 will be
ID = f (VGS, VDG=0)
Therefore, f (VGS, 0) = IIN Thus, IIN sets the value of VGS.. The same gate to source voltage is
reflected across the M2. So, if the M2 biased using zero
VDG and provided transistors M1 and M2 share identical properties and exact matching, then
the
IOUT = f (VGS, VDG=0) is true.
So the output current is mirrored as the input current, IOUT = IIN
The drain-to-source voltage can be further introduced as VDS=VDG + VGS. With this changeover,
the Shichman-Hodges model can provide the approximate answer of the f(VGS,VDG):
The function can be expressed as
13. Explain Cascode Mirror with a neat diagram.
14. What is op-amp? What are its different operation modes? List some of its
applications.
15. Explain Two stage op-amp.
16. What are output offset voltage, input offset current, input offset voltage?
17. What is slew rate.
18. Write short notes on Gilbert Multiplier Cell or Variable Transconductance technique.
19. List some applications of Multiplier ICs.
20. Find the gain of the op amp shown in the figure. Assume the power supply is VDD =
1.8 V and a purely capacitive load. Assume the process parameters for the 0.18 μm
process as given.
Given: ID8 = 20 μA; ID1 = ID2 = ID3 = ID4 = 100 μA; ID5 = 200 μA; ID6 = ID7 = 300 μA
gm1 = gm2 = 2.60 mA/V and gm7 = 3.12 mA/V.