EEE 2019 – PRINCIPLES OF ELECRICITY I
MODEL SOLUTIONS TO FINAL EXAMINATION - 2013/2014 ACADEMIC YEAR
DATE OF EXAMINATION: 25TH JULY, 2014
Question 6: [Solution]
a)
i)
The diode will conduct during positive half-cycles of the input to yield an output vout as
shown below.
vin
vout
short cct
15V
0
15V


T
2
T
vin
t
i
15V
vout
2kΩ

0

T
2
15V
T
t
[3 marks]
ii)
The dc level is determined by finding the average of the output waveform vout over a full
period, i.e.,
T
Vdc  Vavg 
iii)
1
1
vout dt 

T 0
T
T 2
 V
p
sin t  dt 
0
Vp

 Vdc 
,
15

 4.77 V
[3 marks]
The peak-inverse-voltage (PIV) is the voltage across the diode when it is reverse biased.
Thus the PIV is found as follows:
vin
 PIV 
15V
0
15V

T
2
T
t
vin

I 0

2kΩ
vout

Applying KVL to the cct yields, PIV  Vpin  IR  15  0 ,  PIV  15 V
[4 marks]
b) When the ideal diode is replaced with a germanium diode the following is obtained:
i)
The sketch of the output vout is as shown below:
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
s. cct
0.3V
vout



i
vin
vout
2kΩ

ii)
14.7V
T
2
0

T
t
[3 marks]
The dc level is determined by finding the average of the output waveform vout over a full
period, i.e.,
Vdc  Vavg
1

T
T 2
 V
p
 VD sin t  dt 
Vp  VD

0
 Vdc 
,
15  0.3

 4.679 V
[3 marks]
iii)
PIV is obtained by applying KVL to the circuit below:
vin
PIV 
 

15V
0
15V
T
2


vin
t
T
0.3V
vout
2kΩ


I 0
Thus, PIV  Vpin  IR  VD  15  0  0.3 ,  PIV  15.3 V
[4 marks]
[Total 20 marks]
Question 7: [Solution]
a) For the given RC circuit:
1
R
S
2

V1 

t 0

 V2
C
v t 

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R
S
2

t 0

 V2
i
C
v t 

Dept. of EEE, School of Engg, UNZA.
i)
At t  0 the steady-state voltage across the capacitor is V1 , which is the initial voltage to
the new circuit arrangement. Since V2  V1 , the current flows as shown above to charge
the capacitor to V2 .
Thus, applying KVL to the new circuit arrangement yields,
V2  Ri  v ; but i  C
dv
dv
, it follows that , V2  RC  v
dt
dt
[1 mark]

v  V2
dv
,

dt
RC
Rearranging the equation and integrating both sides over the given limits yields,

v t 
V1
t dt
dv
 
0 RC
v  V2
 ln  v  V2 
 ln  v  t   V2   ln V1  V2   
v t 
V1

t t
,
RC 0
 v  t   V2 
t
t
.
 0 , that is, ln 

RC
RC
 V1  V2 
[2 marks]
Taking exponential of both sides yields,
 v  t   VS

 V1  VS
 t RC
,  v  t   V2  V1  V2  et RC ,
e

 v  t   V2  V1  V2  et RC , being the step response voltage.
ii)
[2 marks]
Recall that the current through the capacitor is ,
iC
dv
. Given also that V1  0 , it follows that  v  t   V2 1  et RC  . Thus, [2 marks]
dt
i C
CV2 t RC
dv
d
,
 C V2 1  et RC   
e
dt
dt
RC
 i t  
V2 t RC
e
u t 
R
[3 marks]
b) The given voltage pulse written in terms of step functions is of the form,
v t 
10
0
2
5
t
v  t   10u  t  2   10u  t  5
[4 marks]
c) The output of each block of the regulated power supply is as shown below.
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t
t
t
Full-wave
rectifier
Transformer
[1 mark]
t
Voltage
regulator
Capacitor
filter
[2 marks]
t
t
[2 marks]
[1 mark]
[Total 20 marks]
Question 8: [Solution]
a) For the given circuit
 

vs 
I


vin
220V rms



D3
0.3V

D2
0.3V

D4

RL 
vout
2kΩ

vin  vsec  120V rms
i)
The secondary voltage is given as 120V rms . Thus, the peak voltage is calculated as
follows: Vpsec  Vrms
 2   120  2   169.71 V .
[2 marks]
Since germanium diodes are used in the bridge cct, the dc output is given by
Vdc  Vavg
2

T
 
T 2
0

V
 2VD sin t  dt 
 psec

 Vdc 
ii)

2 Vpsec  2VD

2 169.71  2  0.3 

 107.66 V
[2 marks]
The PIV rating of each diode is found as follows:
PIV  Vpsec  VD  169.71  0.3  169.41V ,
iii)
,

PIV  169.41V
[4 marks]
The maximum diode current during conduction is
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Dept. of EEE, School of Engg, UNZA.
I
Vp out 
RL

Vpsec  2VD
RL

169.71  2  0.3 169.11

 0.0846 ,
2 103
2 103
 I  84.6 mA
[4 marks]
b) Given the diode limiting circuit
vi
0
16V

T
2
T
vi
t

vo

VBIAS

4V

Circuit
Input waveform.
i)

R
16V
An ideal diode will not conduct when vi  VBIAS  4 V , hence no current will flow and all
the input voltage appears at the output, see waveform below.
vo
16V
4V
0
T
2
T
t
16V
ii)
[4 marks]
When the diode is replaced a silicon diode of inherent barrier voltage VD  0.7 V .
Thus, the diode will not conduct when vi  VBIAS  VD   4  0.7  3.3 V . Hence no
current will flow and the entire input voltage appears at the output as shown below.
vo
16V
3.3V
0
T
2
T
t
[4 marks]
16V
[Total 20 marks]
END OF EEE 2019 EXAM MODEL SOLUTIONS
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