TECHNICAL HANDBOOK
1678MCC
Rel. 4.3
OPTICAL MULTIBAND PLATFORM
VOL. 1/1
3AG24163BEAA – Ed. 03
3AG24163BEAA – Ed. 03
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
DESIGN SPECIFICATION
TABLE OF CONTENTS
LIST OF FIGURES AND TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
HANDBOOK GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
- 1
-
HANDBOOK STRUCTURE AND CONFIGURATION CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Handbook Applicability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Customer Documentation 1678 Metro Core Connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 1.3.1 Customer Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 1.3.2 Service Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 1.4 Handbook Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 1.5 Target Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 1.6 Handbook Change History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
17
17
18
18
20
21
21
22
- 2 COMPLIANCE WITH EUROPEAN NORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 2.1 Electromagnetic Compatibility (EMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 2.2 Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
23
23
- 3 SAFETY NORMS AND LABELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
- 4 OTHER NORMS AND LABELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 4.1 Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 4.1.1 General Norms – Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 4.1.2 General Norms – Turn–up & Commissioning, Operation . . . . . . . . . . . . . . . . . . . . . . . . . .
- 4.1.3 General Norms – Maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 4.2 Electrostatic Dischargers (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 4.3 Suggestions, Notes and Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 4.4 Labels affixed to the Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
25
25
25
25
26
27
27
- 5 LIST OF ABBREVIATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
- 6
-
44
44
44
44
45
GENERAL ON ALCATEL–LUCENT CUSTOMER DOCUMENTATION . . . . . . . . . . . . . . . . . . . .
6.1 Products, Product-releases, Versions and Customer Documentation . . . . . . . . . . . . . .
6.2 Handbook supply to Customers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Aims of Standard Customer Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 Handbook Updating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
03
080325
R4.3.1
B. WILKE
B. HANNEMANN
02
080304
R4.3.1
B. WILKE
B. HANNEMANN
01
071207
R4.3
B. WILKE
B. HANNEMANN
ED
DATE
CHANGE NOTE
APPRAISAL AUTHORITY
ORIGINATOR
1678MCC REL. 4.3
TECHNICAL HANDBOOK
ED
03
3AG 24163 BEAA PCZZA
531
1 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
- 6.4.1 Changes introduced in the same Product Release (same Handbook Part Number) . .
- 6.4.2 Notes for Handbooks relevant to Software Applications . . . . . . . . . . . . . . . . . . . . . . . . . .
- 6.4.3 Changes due to new Product Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 6.5 Documentation supply on CD–ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 6.5.1 Contents, Creation and Production of a CD–ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 6.5.2 Use of the CD–ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 6.5.3 CD–ROM Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
45
45
46
46
46
46
- 7 REGISTERED TRADEMARKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
49
- 8
-
GENERAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1 Introduction to the Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3 1678MCC Main Shelf Equipment View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4 Insertion of the Equipment into the Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 8.4.1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 8.4.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 8.4.3 Network Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 8.5 1678MCC Management Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 8.5.1 Craft Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 8.5.2 TL1 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1AA 00014 0004 (9007) A4 – ALICE 04.10
- 9
-
51
51
54
57
60
60
63
65
68
69
71
RACK CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1 Configuration Possibilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2 Rack Configuration for SONET markets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3 LAN Switches (LSX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4 Dispersion Compensation Unit (DCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5 Housekeeping Monitoring Unit (HMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
73
73
75
76
77
78
- 10 PHYSICAL CONFIGURATION OF THE MAIN SHELF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 10.1 1678MCC Main Shelf (SR78) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 10.1.1 Equipment Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 10.1.2 Configuration Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 10.2 Part List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 10.3 Units Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
79
80
83
85
95
103
- 11 PHYSICAL CONFIGURATION OF THE LO EXTENSION SHELF . . . . . . . . . . . . . . . . . . . . . . . .
- 11.1 Lower Order Extension Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 11.1.1 Equipment Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 11.1.2 Configuration Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 11.1.3 Connection to the Main Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 11.2 Part List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 11.3 Units Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
126
127
128
130
134
136
140
- 12 PHYSICAL CONFIGURATION OF THE OED SHELVES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 12.1 1670SM Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 12.1.1 Shelf Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 12.1.2 Basic Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 12.1.3 Basic Function of the Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 12.1.4 I/O Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 12.1.5 System Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 12.1.6 Connection to the Main Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 12.1.7 Part List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
146
147
147
148
149
149
150
155
158
ED
03
3AG 24163 BEAA PCZZA
531
2 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
- 12.1.8 Units Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 12.2 1662SMC Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 12.2.1 Shelf Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 12.2.2 1662SMC: Basic Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 12.2.3 Basic Function of the Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 12.2.4 System Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 12.2.5 Part List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 12.2.6 Units Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
163
179
179
179
180
181
185
189
- 13 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.1.1 Centralized Common Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.1.2 Equipment Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.1.3 Traffic Ports boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.1.4 Lower Order Extension Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.2 Subsystems and involved Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.3 Connections Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.3.1 High Order SDH/SONET/OTN Cross Connect Subsystem . . . . . . . . . . . . . . . . . . . . . . .
- 13.3.2 20/40G Lower Order Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.3.3 160G Lower Order Partsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.3.4 Transmission Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.3.5 Connection Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.4 Signal Management Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.4.2 SDH functional Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.4.3 ITU–T/ETSI SDH Functional Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.4.4 Matrix Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.5 Controller Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.5.2 FLC and SLC Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.5.3 External Communication and Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.6 Synchronization Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.7 Protection Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.7.1 EPS Protection Main Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.7.2 EPS Protection 1670SM Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.7.3 EPS Protection 1662SMC Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.7.4 Network Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.7.5 Restoration – Support of the GMPLS Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.8 Performance Monitoring Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.8.2 Monitoring Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.9 External Interfaces Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.10 Power Supply Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.10.1 1678MCC Main Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.10.2 OEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.11 Equipment Alarms and Tests Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.11.1 Battery Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.11.2 RUM, RUTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.11.3 RUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.11.4 Fuse Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.11.5 Test Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.12 Station Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.12.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.12.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
198
198
198
200
200
204
205
208
208
209
212
213
214
217
217
217
218
223
224
224
225
230
236
239
240
241
245
247
274
301
301
302
303
304
304
309
312
312
312
312
313
313
314
314
314
ED
03
3AG 24163 BEAA PCZZA
531
3 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
- 13.12.3 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.12.4 Control of the (NG)TRU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.12.5 NGTRU Alarm Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.12.6 Hardware Aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.12.7 Supported Customer individual Housekeeping contacts . . . . . . . . . . . . . . . . . . . . . . . .
- 13.12.8 Housekeeping Monitoring Unit (HMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.13 Remote Inventory Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.14 OED Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.14.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.14.2 System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.14.3 Mechanical OED Integration Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.14.4 SW OED Integration Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.14.5 Kinds of OEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.14.6 OED Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.15 1678MCC Network Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.16 Data Application and Layer 2 Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.16.1 4/8/16xGigabit Ethernet Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.16.2 4x10 Gigabit Ethernet Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 13.16.3 ISA–ES64 Data Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
315
315
316
316
319
319
321
322
322
322
322
323
323
326
327
328
328
328
329
- 14 UNITS DESCRIPTIONS MAIN SHELF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.2 First Level Controller and Control & General Interface (FLCCONGI) . . . . . . . . . . . . . .
- 14.2.1 First Level Controller Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.2.2 Control and General Interface Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.2.3 DCC Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.2.4 External Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.2.5 Reset Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.3 First Level Controller and Service Interface (FLCSERV) . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.3.1 Equipment Controller Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.3.2 Service and General Interface Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.3.3 DCC Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.3.4 External Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.3.5 Reset Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.4 Power Supply and Filter Board (PSF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.4.1 Main Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.4.2 Electrical Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.5 Bus Termination Board (BUSTERM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.5.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.5.2 Power Supply Control and Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.6 Matrix 640 Gbit/s Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.6.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.6.2 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.7 Matrix 320/160 Gbit/s Enhanced Board (MX320 / MX160) . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.8 Lower Order Adaptation and Matrix 40G and 20G (LAX40 and LAX20) . . . . . . . . . . . .
- 14.8.1 Lower Order Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.8.2 Lower Order Adaption Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.9 STM–64 traffic Port Boards with not pluggable MSA Modules . . . . . . . . . . . . . . . . . . . .
- 14.9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.9.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.9.3 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.10 STM–64 traffic Port Boards with pluggable XFP MSA Modules . . . . . . . . . . . . . . . . . .
- 14.10.1 4xSTM–64 XFP Port Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.10.2 2xSTM–64 XFP Port Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
330
330
334
335
336
336
336
338
339
340
340
340
340
342
343
343
343
346
346
347
348
348
349
357
358
358
358
361
361
361
363
367
367
368
ED
03
3AG 24163 BEAA PCZZA
531
4 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
- 14.10.3 Timing Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.11 STM–16 traffic Port Board (P16S16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.11.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.11.3 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.12 STM–16 Traffic Port Board (P4S16, P8S16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.13 16xSTM–1/4 Traffic Port Board (P16S1–4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.13.2 Functional and Physical Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.14 16xSTM–1 Traffic Port Board (P16S1S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.14.2 Functional and Physical Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.15 4/8/16xGigabit Ethernet Port Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.15.2 HW Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.15.3 Link Capacity Adjustment Scheme (LCAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.15.4 Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.16 2x/4x10 Gigabit Ethernet Port Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.16.2 HW Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.16.3 Ethernet Virtual Private Line (EVPL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.16.5 Power Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.17 ES64 Server Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.17.2 HW Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.17.4 Power Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.18 FAN Unit (FAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.18.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.18.2 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.18.3 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.18.4 FAN Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 14.18.5 FAN Unit in SONET Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
369
370
370
370
370
373
374
374
374
375
375
375
376
376
376
376
377
382
382
382
383
384
386
387
387
387
388
389
391
391
392
392
392
392
- 15 UNITS DESCRIPTIONS LOWER ORDER EXTENSION SHELF . . . . . . . . . . . . . . . . . . . . . . . . .
- 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 15.2 Lower Order Adaptation Board 20G (LA20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 15.2.1 Lower Order Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 15.2.2 Lower Order Adaption Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 15.3 Lower Order Matrix 160 Gbit/s Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 15.3.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 15.3.2 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 15.4 Alarm Board (ALM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 15.4.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 15.5 Power Supply and Filter Board (PSF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 15.6 Bus Termination Board (BUSTERM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
395
395
396
396
396
399
399
400
401
401
404
404
- 16 UNITS DESCRIPTIONS OED SHELF 1670SM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 16.2 STM-1 Electrical I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 16.2.1 4xSTM-1Electrical I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 16.2.2 16xSTM-1Electrical I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 16.3 STM-1 Optical I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
405
405
406
406
410
412
ED
03
3AG 24163 BEAA PCZZA
531
5 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
- 16.3.1 4xSTM-1Optical I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 16.3.2 16xSTM-1 Optical I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 16.4 I/O Port Board STM-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 16.5 I/O Port Board 4xSTM-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 16.5.2 STM-4 Optical Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 16.6 4x140 Mbit/s Port Board (P4E4N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 16.6.1 2x140 Mbit/s Access Board (A2S1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 16.6.2 140 Mbit/s Electrical Module (ICMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 16.7 High Speed Port Protection Using HPROT and HPROT16 Boards . . . . . . . . . . . . . . . . .
- 16.8 Optical Link Enhanced (HCLINKE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 16.9 Bus Termination (BTERM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 16.10 Control and General Interface Board (CONGIHC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 16.11 Matrix Board (HCMATRIX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 16.12 FANs Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
412
416
417
419
420
421
423
423
425
428
430
431
434
438
- 17 UNITS DESCRIPTIONS OED SHELF 1662SMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 17.2 63x2 Mbit/s Access Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 17.3 Low Speed Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 17.4 63x2 Mbit/s Port Board (P63E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 17.5 63x2 Mbit/s / G703 / ISDN–PRA Port Board (P63E1N) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 17.6 CONGI Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 17.7 SYNTH16 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 17.7.1 FAN Unit for FAN Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
441
441
442
444
445
448
453
457
465
- 18 TECHNICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 18.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 18.2 Electrical Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 18.2.1 Electrical Transmission Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 18.2.2 Electrical Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 18.3 Optical Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 18.3.1 STM–N Optical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 18.3.2 Optical Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 18.4 Power Supply Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 18.5 Alarm Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 18.5.1 Units Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 18.5.2 Centralized Equipment Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 18.5.3 Trouble–shooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 18.6 Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 18.6.1 1678MCC Rack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 18.6.2 OED Rack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 18.6.3 1678MCC Main Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 18.6.4 1678MCC Main Shelf (SONET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 18.6.5 1670SM Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 18.6.6 1662SMC Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 18.7 Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 18.7.1 Waste from Electrical and Electronic Equipment (WEEE) . . . . . . . . . . . . . . . . . . . . . . . .
- 18.7.2 Acoustical noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 18.7.3 Climatic for Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 18.7.4 Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 18.7.5 Transportation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 18.7.6 EMI/EMC Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
469
469
473
473
474
475
475
488
493
494
494
494
494
495
495
495
495
496
496
496
497
497
497
498
500
502
503
DISMANTLING & RECYCLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
504
ED
03
3AG 24163 BEAA PCZZA
531
6 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
- 19 DISMANTLING & RECYCLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 19.1 WEEE general Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 19.2 How to disassembly equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 19.2.1 Tools necessary for Disassembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 19.2.2 Shelf Disassembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 19.2.3 Unit Disassembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 19.2.4 Hazardous Materials and Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 19.3 ECO Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ED
506
506
507
507
508
515
525
527
03
3AG 24163 BEAA PCZZA
531
7 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
LIST OF FIGURES AND TABLES
Table 1. Handbook related to the specific product hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2. Handbooks related to the specific product SW management and local product control . .
Table 3. Handbooks common to Alcatel–Lucent Network Elements using 1320CT platform . . . . . .
Table 4. Safety Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5. Customer Documentation on CD–ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6. Handbooks related to Service activities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7. Label references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 1. Subrack label (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2. Subrack label (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3. Subrack label (3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4. Labels on units with standard cover plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5. Modules label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6. Internal label for Printed Board Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7. Back panels internal label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 8. Label specifying item not on catalogue (P/N and serial number) . . . . . . . . . . . . . . . . . . . . .
Figure 9. Label specifying item on catalogue (P/N and serial number) . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10. Item identification labels – item on catalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11. Label identifying the equipment (example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12. CE Label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13. WEEE Label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8. List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14. 1678MCC scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 15. 1678MCC SDH/SONET Multiplexing Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 16. 1678MCC Main Shelf – Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 17. 1678MCC Main Shelf – Side View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 18. 1678MCC Main Shelf – Board View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19. Terminal multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 20. Add/Drop Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 21. ”HUB” STM–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 22. Point–to–point links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 23. Linear drop–insert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 24. Ring structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 25. Meshed topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 26. Management Interfaces of 1678MCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 27. Example of network management architecture via Craft Terminal . . . . . . . . . . . . . . . . . .
Figure 28. Example of network management architecture via TL1 interface . . . . . . . . . . . . . . . . . . .
Figure 29. Schematic 1678MCC Main Rack Configurations with Main and OED Shelves . . . . . . . .
Figure 30. Schematic 1678MCC Rack Configurations with LO Extension Shelf . . . . . . . . . . . . . . . .
Figure 31. Schematic OED Rack Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 32. Schematic SONET Rack Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 33. General LAN Cabling for multirack configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9. Main Rack Configurations with DCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10. OED Rack Configurations with DCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 34. Dispersion Compensation Unit (DCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 35. Housekeeping Monitoring Unit (HMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 36. 1678MCC Main Shelf Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 37. 1678MCC Equipment front view (slot position) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11. 1678MCC Equipment: slot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 12. Pluggable Optical and Electrical Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 13. 1678MCC Equipment: slot configuration explanation notes . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 38. Main Shelf: Supported I/O boards – Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 39. Main Shelf: Supported I/O boards – Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ED
18
18
19
19
19
20
27
28
29
30
31
32
32
33
33
34
34
34
35
35
36
52
55
57
58
59
63
63
64
65
65
66
67
68
70
71
73
74
74
75
76
77
77
77
78
80
84
86
87
88
90
91
03
3AG 24163 BEAA PCZZA
531
8 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Figure 40. Basic configuration of 1678MCC Main Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 41. Allowed Equipment Configuration (Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14. Main parts list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15. Accessories list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16. Parts list: explanatory notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 42. 4xGE, 4xSTM–16 optical port board – front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 43. 8xGE, 8xSTM–16 optical port board – front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 44. LAC40, 16xGE,16xSTM–16,16xSTM–4/1, 16xSTM–1E port board – front view . . . . . .
Figure 45. 1xSTM–64 (S64M) optical port board – front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 46. 2xSTM–64 (P2S64M) optical port board – front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 47. 4xSTM–64 (P4S64M) optical port board – front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 48. 1xSTM–64 (L–642M) optical port board – front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 49. 1xSTM–64 (V–642M) optical port board – front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 50. 1xSTM–64 (U–642M) optical port board – front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 51. Connector assignment of L–642M, V–642M an U–642M boards . . . . . . . . . . . . . . . . . . .
Figure 52. 2xSTM–64 XFP/XFP–E – Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 53. 4xSTM–64 XFP/XFP–E – Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 54. 2x10GE LAN – Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 55. 4x10GE LAN – Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 56. ES64SC – Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 57. First Level Controller and Service Interfaces board – front view . . . . . . . . . . . . . . . . . . . .
Figure 58. First Level Controller and Control&General Interfaces board – front view . . . . . . . . . . . .
Figure 59. Matrix board – front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 60. Lower Order Matrix board – front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 61. Power Supply and Filter board – front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 62. FANs unit – front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 63. Optical SFP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 64. Electrical SFP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 65. Optical XFP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 66. Optical XFP–E Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 67. Lower Order Extension Shelf Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 68. Lower Order Extension Shelf Equipment front view (slot position) . . . . . . . . . . . . . . . . . .
Table 17. 1678MCC LO Shelf Equipment: slot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18. Pluggable Optical Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19. 1678MCC LO Shelf Equipment: slot configuration explanation notes . . . . . . . . . . . . . . . .
Figure 69. Lower Order Extension Shelf: Supported Adaptation Board . . . . . . . . . . . . . . . . . . . . . . .
Figure 70. Basic configuration of LO Extension Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 71. Configuration of the 160G LO extension Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 72. Connection of 160G LO Extension Shelf with the Main Shelf . . . . . . . . . . . . . . . . . . . . . .
Figure 73. VC–4 mapping on LA20 Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 20. Main parts list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 21. Accessories list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 22. Parts list: explanatory notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 74. Lower Order Adaptation 20G board – front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 75. Alarm board – front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 76. LO Centerstage Matrix Board – front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 77. Power Supply and Filter board – front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 78. FANs unit – front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 79. 1670SM Shelf Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 23. Basic Equipment of the 1670SM Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 80. 1670SM: Relation Port/Access Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 24. 1670SM: General Configuration Rules for the I/O Boards . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 25. 1670SM: Slot relation Port/Access Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 26. 1670SM: Position of the Port Boards in the Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ED
93
94
96
100
101
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
123
124
124
125
125
127
129
130
130
130
131
132
133
134
135
137
138
139
141
142
143
144
145
147
148
150
151
151
152
03
3AG 24163 BEAA PCZZA
531
9 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Table 27. 1670SM: Interface specific Configuration Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 81. 1670SM: Flexible Shelf equipped with 16xSTM–1e EPS protected and other I/O Boards . .
153
Table 28. 1670SM: Allowed mix of I/O Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 82. Assignment of I/O Boards to the Link Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 83. Example for a Connection Main Shelf /1670SM (4 links, 1+1 MSP full protected) . . . . . 156
Figure 84. Example for a Connection Main Shelf /1670SM (4 links, unprotected) . . . . . . . . . . . . . . . 157
Table 29. Main part list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 30. Accessories list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 31. Parts list: explanatory notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 85. 4x140/STM-1 Switchable E/O Port Board or 4xSTM-4 Port Board – Front View . . . . . . 164
Figure 86. 4xSTM-1 E/16xSTM-1 E/O Port Board – Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 87. 16xSTM–1 COMPACT optical Port Board – front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 88. 2x140Mbit/s/STM-1/STM-4 Access Board Optical – Front View . . . . . . . . . . . . . . . . . . . . 167
Figure 89. 4xSTM–1 Electrical 75 Ohm Access Board – Front View . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 90. 16xSTM-1 Electrical 75 Ohm Access Board – Front View . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 91. 12xSTM-1 COMPACT optical Access Board – Front View . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 92. High-Speed Protection Board – Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 93. Bus Termination Board – Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 94. HiCap Matrix Board – Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 95. Optical Link Enhanced Board – Front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 96. Control and Generic Interface Board – Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 97. FANs Subrack Cover – Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 98. Shelf ID Connector for 1670SM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 99. Electrical pluggable module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 100. STM–4 Optical Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 101. Optical SFP module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 102. 1662SMC Shelf: Face Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 32. 1662SMC: Basic Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 103. 1662SMC: I/O Boards. Relation Access/Port Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 33. 1662SMC: Relation Access / Port Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 34. 1662SMC: Configuration Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 104. 1662SMC Equipment: Unprotected Configuration with 2Mbit/s . . . . . . . . . . . . . . . . . . . . 182
Figure 105. 1662SMC Equipment: Protected Configuration with 2Mbit/s . . . . . . . . . . . . . . . . . . . . . . 182
Figure 106. Connection Main Shelf/1662SMC (1+1MSP protected) . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 107. Connection Main Shelf/1662SMC (unprotected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 35. Main part list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 36. Accessories list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 37. Parts list: explanatory notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 108. 63 x 2 Mbit/s Port Board – Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 109. Control and General Interface – Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 110. SYNTH16 Board – Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 111. 63 x 2 Mbit/s Access Board – Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 112. Low Speed Protection Board – Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 113. FANs Subrack Cover – Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 114. STM-16 optical SFP module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 115. Shelf ID Connector for 1662SMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 116. 1678MCC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 38. Subsystems and involved boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 117. Low Order Matrix Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 118. Physical Matrix View with MX640 and LAX40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 119. Logical Matrix View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 120. 1678MCC Main Shelf with 160G Lower Order Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 39. Point–to–point connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
ED
03
3AG 24163 BEAA PCZZA
531
10 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Figure 121. Types of connections managed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 122. SDH payload subsystem functional model: physical position of functional blocks . . . .
Figure 123. Port board implementation and corresponding ITU–T G.783 functional model . . . . . .
Figure 124. Matrix board implementation: payload processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 125. Physical LAN Topology of Main shelf only configuration . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 126. Physical LAN Topology of Main shelf with single 1670SM OED configuration . . . . . . .
Figure 127. Physical LAN Topology of Main shelf with single 1662SMC OED configuration . . . . . .
Figure 128. Physical LAN Topology of Main shelf with single LO extension shelf . . . . . . . . . . . . . . .
Figure 129. Physical LAN Topology of Multi Rack Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 130. Example of a routing domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 131. OSI protocol stack (layer 1 - 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 132. Multiple Rings on 1678MCC as Transit NE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 133. Multiple Rings on 1678MCC as Gateway NE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 134. SETS function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 40. EPS Protection Scheme parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 135. MSP Linear 1+1 single and dual ended protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 136. MSP Linear 1:N Dual–Ended protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 41. SNCP configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 137. Typical ring network with SNCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 138. Failure examples in SNCP ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 139. Drop and Continue D/C A INS A and D/C A INS B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 140. Drop and Continue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 141. Drop and Continue – 1st and 2nd failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 142. 2F MS SPRING Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 143. Effect of a BRIDGE “B side” operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 144. Effect of a BRIDGE “A side” operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 145. Effect of SWITCH “B side” operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 146. Effect of SWITCH “A side” operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 147. Line break recovering operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 148. 2F MS–SPRING example of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 149. Squelching on isolated Node connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 150. MS SPRING Drop and Continue, Insert Continues (protected) . . . . . . . . . . . . . . . . . . . .
Figure 151. Collapsed dual node interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 152. Collapsed dual node interconnection – 1st and 2nd failure . . . . . . . . . . . . . . . . . . . . . . .
Figure 153. Collapsed single node ring interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 154. Collapsed single node ring interconnection –1st failure . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 155. Collapsed single node ring interconnection –2nd failure . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 156. Network Interfaces UNI /NNI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 157. G.ASTN architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 158. TNE reference model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 159. GMRE: SW Top level architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 160. DCC Protection Mechanism In–Fibre / In–Band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 161. DCC Protection Mechanism In–Band / Out of–Band . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 162. SNCP Ring Closure in a GMRE Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 163. Multicast connections (example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 42. External Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 164. Step–up Converter – Location of Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 165. 1678MCC Power Supply with 3-wire FPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 166. 1678MCC Power Supply with 2-wire FPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 167. Power distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 168. OED Shelf Power Supply with 3-wire FPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 169. OED Shelf Power Supply with 2-wire FPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 170. Station Alarm System Architecture – Physical View . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 171. Rack Lamp Interfaces including GP Contacts of 1678MCC Shelf . . . . . . . . . . . . . . . . . .
ED
216
217
218
223
225
227
228
228
229
231
232
234
235
236
241
249
251
252
253
254
256
257
258
260
261
261
262
262
263
265
266
267
269
270
271
272
273
276
278
281
282
287
288
292
296
303
305
306
307
308
310
311
315
317
03
3AG 24163 BEAA PCZZA
531
11 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Figure 172. Rack Lamp Interfaces including GP Contacts of LO Extension Shelf . . . . . . . . . . . . . . .
Figure 173. Rack Lamp Interfaces including GP Contacts of 1670SM Shelf . . . . . . . . . . . . . . . . . . .
Figure 174. Rack Lamp Interfaces including GP Contacts of 1662SMC Shelf . . . . . . . . . . . . . . . . . .
Table 43. Rack Lamp Colors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 175. Schematic Drawing of HMU Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 176. Remote Inventory Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 177. Schematic drawing of OED Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 178. Layout of the 1670SM Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 179. 1662SMC Shelf: Face Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 180. OED Synchronization for ETSI application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 44. Units involved in 1678MCC Main Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 45. Electrical Modules involved in 1678MCC Main Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 46. Optical Modules involved in 1678MCC Main Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 181. Block Diagram and external Interfaces of FLCCONGI enhanced . . . . . . . . . . . . . . . . . .
Figure 182. Block Diagram and external Interfaces of FLCSERV(A) enhanced . . . . . . . . . . . . . . . .
Figure 183. PSF Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 184. BUSTERM Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 185. Matrix Board Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 186. Payload Subsystem Logical Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 187. Payload Subsystem Physical Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 188. Power Subsystem Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 47. Power characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 189. CRU, On– and Off– Board Connections in SDH Applications . . . . . . . . . . . . . . . . . . . . .
Figure 190. CRU, On– and Off– Board Connections in SONET Applications . . . . . . . . . . . . . . . . . .
Figure 191. PQ2/SCM Control Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 192. LAX40 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 193. LAX40 (LAX20) Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 194. Equipping Options of STM–64 Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 195. STM–64 Board Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 196. STM–64 Board Payload Subsystem Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 197. STM–64 Board Power Supply Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 198. STM–64 Board Timing and Clock Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 199. Functional Blocks of the 4xSTM–64 Port Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 200. Functional Blocks of the 2xSTM–64 Port Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 201. STM–64 XFP Board Timing and Clock Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 202. STM–16 board Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 203. STM–16 Board Payload Subsystem Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 204. STM–16 Board Power Supply Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 205. STM–16 Board Timing and Clock Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 206. GE Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 207. Ethernet Virtual Private Line Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 208. 10GE LAN Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 209. Power Subsystem Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 210. ISA ES64 Trunks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 211. Block Diagram of the ES64 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 212. Power Subsystem Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 213. FAN Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 48. Units involved in 1678MCC LO Extension Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 49. Optical Modules involved in 1678MCC LO Extension Shelf . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 214. LA20 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 215. LA20 Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 216. LO Centerstage Matrix Board Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 217. ALM Board Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 50. Units involved in 1670SM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ED
317
318
318
319
320
321
322
324
325
326
330
332
332
334
339
345
347
349
349
350
351
352
353
354
356
358
360
362
364
365
365
366
368
369
369
371
372
372
373
378
383
384
386
387
388
390
393
395
395
397
398
399
403
405
03
3AG 24163 BEAA PCZZA
531
12 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Table 51. Pluggable Modules involved in 1670SM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 218. Block Diagram 4xSTM-1 Electrical I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 219. Block Diagram Access Board 4xSTM-1 Electrical (A4ES1) . . . . . . . . . . . . . . . . . . . . . . .
Figure 220. Relation between Port Boards/Access Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 221. Block Diagram 16xSTM-1 Electrical I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 222. Block Diagram 4xSTM-1 Optical I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 223. Block Diagram Access Board 2xSTM-1 Optical (A2S1) . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 224. Block Diagram STM-1 Optical Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 225. Relation between Port Boards/Access Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 226. Block Diagram Optical STM-4 I/O Port Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 227. Block Diagram Access Board 2xSTM-4 Optical (A2S4) . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 228. Block Diagram STM-4 Optical Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 229. P4E4N Port Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 230. A2S1 Access Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 231. ICMI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 232. Block Diagram HPROT Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 233. BTERM Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 52. Interfaces on the Boards CONGIHC A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 234. CONGIHC Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 235. HCMATRIX Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 236. FANs Unit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 53. Units involved in 1662SMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 237. 63x2 Access Board – Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 238. LSPROT Board – Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 239. 63x2 Mbit/s Board – Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 240. 63x2 Mbit/s G.703/ISDN–PRA, Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 241. Functional Diagram of the NT ISDN–PRA Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 54. CONGI A and CONGI B interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 55. Rack lamps signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 242. CONGI – Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 243. SYNTH16 – Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 244. FANs Shelf 19” General Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 245. FANs Unit for FAN Shelf 19” Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 56. Parameters specified for STM–1 optical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 57. Parameters specified for STM–4 optical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 58. Parameters specified for STM–16 optical interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 59. Parameters specified for STM–64 optical interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 60. Parameters specified for STM–64 optical interface – P1L1–2D2 long–haul application .
Figure 246. Long Haul Application (L–64.2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 247. Very Long Haul Application (V–64.2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 248. Ultra Long Haul Application (U–64.2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 61. Parameters specified for STM–64 optical interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 62. Parameters specified for 1000B–SX Optical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 63. Parameters specified for 1000B–LX Optical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 64. Parameters specified for 10GE–SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 65. Parameters specified for 10GE–LR,–ER,–ZR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 66. Hazard level classification of different optical interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 67. Incorporated laser sources characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 68. Relation between Alarm severity terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 249. Climatogram for Class 3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 69. Climate parameters for environmental class 3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 250. Climatogram for Class 1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 70. Climate parameters for environmental class 1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 71. Climatic conditions for environmental classes 2.1/2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ED
405
407
409
410
411
413
414
415
416
418
419
420
422
423
424
425
430
431
432
437
439
441
443
444
447
451
452
453
454
456
464
466
467
476
477
478
479
480
481
481
482
483
484
485
486
487
488
489
494
499
499
501
501
503
03
3AG 24163 BEAA PCZZA
531
13 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Figure 251. Shelf Front and Rear View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 252. Handle Removal and Disassembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 253. Rear Cover Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 254. Back Panel Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 255. Upper and Lower Guides Plane Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 256. Side Wall Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 257. Optical Fiber Duct, Guides and Contact Spring Removal . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 258. Side Coverplate Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 259. Levers Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 260. Optical Connectors Support Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 261. Side Coverplate and Contact Spring Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 262. Internal Connectors Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 263. Dissipator Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 264. Modules Removal from Dissipator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 265. Daughter Board Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 266. Gold Connector Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 267. Internal Cables Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 268. Connector metal Support Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 72. List of hazardous materials and components present in the equipment . . . . . . . . . . . . . .
Table 73. Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ED
508
509
510
511
512
513
514
515
516
517
518
519
520
521
521
522
523
524
525
528
03
3AG 24163 BEAA PCZZA
531
14 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1AA 00014 0004 (9007) A4 – ALICE 04.10
ED
03
15 / 531
HANDBOOK GUIDE
3AG 24163 BEAA PCZZA
531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ED
03
3AG 24163 BEAA PCZZA
531
16 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1 HANDBOOK STRUCTURE AND CONFIGURATION CHECK
1.1 General Information
NOTICE
Strict compliance with the instructions and procedures specified in the product documentation (refer
to product release note for the complete list of applicable manuals) is the precondition of the
enforceability of such warranty claims against Alcatel–Lucent.
Warranty claims which result from non-compliance with the defined procedures, cannot be enforced
against Alcatel–Lucent.
NOTICE
The product specification and/or performance levels contained in this document are for information
purposes only and are subject to change without notice.
They do not represent any obligation on the part of Alcatel–Lucent.
COPYRIGHT
NOTIFICATION
The technical information of this manual is the property of Alcatel–Lucent and must not be copied,
reproduced or disclosed to a third party without written consent.
1.2 Handbook Applicability
1AA 00014 0004 (9007) A4 – ALICE 04.10
This handbook refers to the Multiband Multiservice Connect 1678 Metro Core Connect (MCC) Release 4.2
which belongs to the Alcatel–Lucent Intelligent Optical Networks (ION) product family.
In general the system is referred to as MCC only.
ED
03
3AG 24163 BEAA PCZZA
531
17 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1.3 Customer Documentation 1678 Metro Core Connect
The list of handbooks given here below is valid on the issue date of this Handbook and
can be changed without any obligation for ALCATEL–LUCENT to update it in this
Handbook.
Some of the handbooks listed here below may not be available on the issue date of this
Handbook.
The Documentation is splitted in:
–
–
Customer Documentation
Service Documentation.
1.3.1 Customer Documentation
The standard Customer Documentation is available in English and consists of the following handbooks:
Table 1. Handbook related to the specific product hardware
REF.
PART
NUMBER
HANDBOOK
1678MCC Rel.4.3 Technical Handbook
THIS
HDBK
3AG 24163 BEAA
[1]
Provides information regarding Equipment Description.
Table 2. Handbooks related to the specific product SW management and local product control
REF.
PART
NUMBER
HANDBOOK
1678MCC Rel. 4.3 CT Basic Operator’s Handbook
[2]
3AG 24164 BEAA
Provides general information, installation and operational procedures for the 1678MCC Craft
Terminal
1678MCC Rel.4.3 CT Operator’s Handbook
3AG 24165 BEAA
[3]
Provides 1678MCC screens and operational procedures.
1678MCC Rel. 4.3 Operator’s Troubleshooting and Maintenance
Handbook
3AG 24197 BEAA
1AA 00014 0004 (9007) A4 – ALICE 04.10
[4]
Provides trouble shooting in case of alarms coming from the 1678MCC and contains
maintenance procedures for operators.
ED
03
3AG 24163 BEAA PCZZA
531
18 / 531
Table 3. Handbooks common to Alcatel–Lucent Network Elements using 1320CT platform
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
REF.
PART
NUMBER
HANDBOOK
1330AS Rel. 6.5 Operator’s Handbook
[5]
3AL 88876 AAAA
Provides detailed information and operational procedures regarding the alarm Surveillance
software embedded in the 1320CT software package.
ELB Rel. 2.X Operator’s Handbook
[6]
3AL 88877 AAAA
Provides detailed information and operational procedures regarding the Event Log
Management software embedded in the 1320CT software package.
CLI User Guide GMRE
3AG 24193 BEAA
[7]
Describes the usage of the Command Line Interface.
Table 4. Safety Instructions
REF.
PART
NUMBER
CD–ROM TITLE
Safety Instructions 1678MCC
3AG 24198 AAAA
[8]
Contains all common Safety Instructions.
Table 5. Customer Documentation on CD–ROM
Note: refer to para. 6.5 on page 46.
REF.
PART
NUMBER
CD–ROM TITLE
1678MCC Rel. 4.3 CD–ROM–Customer Documentation
3AG 24399 BDAA
[9]
1AA 00014 0004 (9007) A4 – ALICE 04.10
Contains, in electronic format, the following handbooks: REF. [1] to REF. [8] .
ED
03
3AG 24163 BEAA PCZZA
531
19 / 531
1.3.2 Service Documentation
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The standard Service Documentation is available in English and consists of the following handbooks:
Table 6. Handbooks related to Service activities
REF.
PART
NUMBER
HANDBOOK
Commissioning Procedure
3AG 24167 BAAA
[10]
Describes the tests to be performed in the commissioning phase for the 1678MCC.
Commissioning Protocol
3AG 24168 BAAA
[11]
Form to fill out after commissioning procedure.
Installation & Start–Up Manual FLC Software
3AG 24169 BEAA
[12]
Defines the installation procedure of FLC software.
Maintenance Handbook
[13]
3AG 24323 BEAA
Provides information regarding ISUs, routine and corrective maintenance, replacement of
boards, matrix upgrade etc.
Network Configuration Guide GMRE
[14]
3AG 24194 BEAA
This document covers the configuration of homogeneous GMRE networks consisting of
1678MCC.
Installation Handbook
[15]
3AG 24191 AAAA
Provides information regarding Equipment Installation, according to A–Installation
Engineering Dept. rules.
1678MCC Installation Guide Rel 2.0
3AL 89572 CAAA
[16]
Defines the installation modality for the 1678MCC equipment.
1678MCC Rack Rel 4.0 Technical Handbook
[17]
3AL 81824 AAAA
Provides information on description, composition, installation, turn–on and maintenance of the
MCC rack.
System Installation Handbook Optinex Rack
[18]
3AL 38270 AAAA
Provides information on description, composition, installation, turn–on and maintenance of the
Optinex rack.
1AA 00014 0004 (9007) A4 – ALICE 04.10
1670SM Installation Guide Rel.4.3
3AL 89790 CAAA
[19]
Defines the installation modality for the 1670SM equipment.
ED
03
3AG 24163 BEAA PCZZA
531
20 / 531
1.4 Handbook Structure
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
This handbook is divided into the following main topics as described in the table of contents:
HANDBOOK GUIDE:
It contains general information on safety norms, EMC and type of labels
that might be affixed to the equipment.
Furthermore, it describes the handbook structure and the customer
documentation. The abbreviation list is supplied too.
DESCRIPTION:
It contains all the equipment’s general and detailed system features
including its application in the telecommunication network.
Furthermore, it supplies the equipment description and specifications
(i.e., system, mechanical, electrical and/or optical).
DISMANTLING &
RECYCLING:
It contains information for shelves/units dismantling and recycling and
list of hazardous materials.
APPENDICES:
Section included (but not necessarily utilized) to describe possible
alternative unit.
ANNEXES:
Section envisaged (but not necessarily included) containing additional
documentation or general information on other topics not inherent to
the chapters making up the handbook.
MAINTENANCE:
Maintenance related information are described separately in the
’Maintenance Handbook’.
(*)
(*)
If the equipment is software integrated and man–machine interfaced (through a PC, Work Station
or other external processing/displaying system) the operation and maintenance carried out WITH
SUCH SYSTEM is detailed in the Operator’s Handbooks (refer to para. 1.3 on page 18).
1.5 Target Audience
This handbook is intended to provide a system overview as well as more detailed information on single
sub–systems and equipment. Therefore, this is the handbook to start with.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Especially, before reading any of the other handbooks it is recommended to read at least the following
chapters of the Description part for gaining a system overview:
–
General
–
Physical Configuration of the Main Shelf
–
Physical Configuration of the LO extension Shelf
–
Physical Configuration of the OED Shelves
ED
03
3AG 24163 BEAA PCZZA
531
21 / 531
1.6 Handbook Change History
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Ed.03:
Created in March, 2008. This is the third released issue of this handbook for product release 4.3. The main
updates since Ed. 02 are:
–
SLSks51271: need TH update for support of new FLC AB variant
Added FLCCONGI (max DCC–M) and FLCSERVICE (max DCC–M) to Main part list (see
Table 14. on page 96).
Ed.02:
Created in March, 2008. This is the second released issue of this handbook for product release 4.3. The
main updates since Ed. 01 are:
–
SLSks49776: DTAG: L–64.2M Path penalty out of spec:
Added attenuator to figures on page 113 and 481, and to legend of table on page 479.
–
SLSks50678: Remove R2 feature descriptions not supported in R3 and R4
Removed EOW and AUX sections from chapter 18.2.1 on page 473.
Removed PM on AU–PJE from chapter 13.8.1 on page 301.
–
SLSks50944: Need Handbook update for HOT and WTR w/ 1:N MSP:
Corrected text on page 249.
–
Added/ corrected support of Jumbo Frames for GbE (page 376), 10GbE (page 382) and ES64 boards
(page 387)
Corrected “DWA” values of modules
Added SGEZX module for GbE (to SGELX/ SFP–LX.)
–
–
Ed. 01:
Ed.01 created in December, 2007 is the first officially released edition of this handbook, associated to
product release 4.3. This edition based on 3AG 24163 BDAA PCZZA Ed.01.
Changes to 3AG 24163 BDAA PCZZA Ed.01:
1AA 00014 0004 (9007) A4 – ALICE 04.10
–
–
–
–
–
–
–
–
ED
ES64
Update of GMRE chapter and new features
MSP 1:N for STM–1 electrical
DCC enhancements
GE Services
Added Compound Links into GMRE glossary
Multicast connections
SLSks50382: EOW und AOX in TH und FL
03
3AG 24163 BEAA PCZZA
531
22 / 531
2 COMPLIANCE WITH EUROPEAN NORMS
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
2.1 Electromagnetic Compatibility (EMC)
The CE markings printed on the product denote compliancy with the following directives:
•
89/336/EEC of May 3rd, 1989 (EMC directives), amended:
–
by the 92/31/EEC Directive issued on April 28th, 1992
–
by the 93/68/EEC Directive issued on July 22nd, 1993
Compliancy to above Directives is declared, when the equipment is installed as for the manufacturer
handbooks, according to the following European Norm:
•
EN 300 386 (V1.3.1) environment ”Telecommunication center”
WARNING
This is a class A product of EN 55022. In domestic, residential and light industry environments, this
product may cause radio interference in which case the user may be required to take adequate
measures.
2.2 Safety
1AA 00014 0004 (9007) A4 – ALICE 04.10
Compliancy to Safety Norms is declared in that the equipment satisfies standardized norms:
ED
•
IEC 60950–1 ed. 2001
for electrical safety
•
EN 60950–1 ed. 2001
for electrical safety
•
EN 60825–1 ed. 1994 + A11 ed. 1996 + A2 ed. 2001
for optical safety
•
IEC 60825–1 ed. 1993 + A2 ed. 2001 (1999)
for optical safety
•
EN 60825–2 ed. 2000
for optical safety
•
IEC 60825–2 ed. 2000
for optical safety
03
3AG 24163 BEAA PCZZA
531
23 / 531
3 SAFETY NORMS AND LABELS
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Refer to the Safety Instructions, 3AG 24198 AAAA, to obtain the following information:
–
General Safety Rules
–
Labels
–
Several Dangerous Conditions
ED
03
3AG 24163 BEAA PCZZA
531
24 / 531
4 OTHER NORMS AND LABELS
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
4.1 Electromagnetic Compatibility
The equipment’s EMC norms depend on the type of installation being carried out (cable termination,
grounding, etc.) and on the operating conditions (equipment, setting options of the electrical/electronic
units, presence of dummy covers, etc.).
•
Before starting any installation, turn–up & commissioning, operation & maintenance work refer
to the relevant Handbooks and chapters.
The norms set down to guarantee EMC compatibility, are distinguished inside this handbook
by the symbol and term:
•
ATTENTION
EMC NORMS.
4.1.1 General Norms – Installation
•
All connections (towards the external source of the equipment) made with shielded cables use
only cables and connectors suggested in this technical handbook or in the relevant Plant
Documentation, or those specified in the Customer’s ”Installation Norms” (or similar
documents).
Shielded cables must be suitably terminated.
Install filters outside the equipment as required.
Ground connect the equipment utilizing a conductor with proper diameter and impedance.
Mount shields (if utilized), previously positioned during the installation phase, but not before
having cleaned and decreased it.
Before inserting the shielded unit proceed to clean and decrease all peripheral surfaces
(contact springs and connection points, etc.).
Screw fasten the units to the subrack.
To correctly install EMC compatible equipment follow the instructions given.
•
•
•
•
•
•
•
4.1.2 General Norms – Turn–up & Commissioning, Operation
•
•
Preset the electrical units as required to guarantee EMC compatibility.
Check that the equipment is operating with all the shields properly positioned (dummy covers,
ESD connector protections, etc.).
To properly use EMC compatible equipment observe the information given.
•
4.1.3 General Norms – Maintenance
•
Before inserting the shielded unit, which will replace the faulty or modified unit, proceed to clean
and decrease all peripheral surfaces (contact springs and connection points, etc.).
Clean the dummy covers of the spare units as well.
Screw fasten the units to the subrack.
1AA 00014 0004 (9007) A4 – ALICE 04.10
•
•
ED
03
3AG 24163 BEAA PCZZA
531
25 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
4.2 Electrostatic Dischargers (ESD)
Before removing the ESD protections from the monitors, connectors etc., observe the precautionary
measures stated. Make sure that the ESD protections have been replaced and after having terminated
the maintenance and monitoring operations.
Most electronic devices are sensitive to electrostatic dischargers, to this concern the following warning
labels have been affixed:
Observe the precautionary measures stated when having to touch the electronic parts during the
installation/maintenance phases.
Workers are supplied with antistatic protection devices consisting of:
ELASTICIZED BAND
1AA 00014 0004 (9007) A4 – ALICE 04.10
COILED CORD
ED
•
an elasticized band worn around the wrist;
•
a coiled cord connected to the elasticized band and to the stud on the subrack.
03
3AG 24163 BEAA PCZZA
531
26 / 531
4.3 Suggestions, Notes and Cautions
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Suggestions and special notes are marked by the following symbol:
Suggestion or note....
Cautions to avoid possible equipment damage are marked by the following symbol:
TITLE...
(caution to avoid equipment damage)
statement....
4.4 Labels affixed to the Equipment
This chapter indicates the positions and the information contained on the identification and serial labels
affixed to the equipment.
Figure 1. on page 28 through Figure 7. on page 33 illustrate the most common positions of the labels on
the units, modules and subracks.
Figure 8. on page 33 through Figure 11. on page 34 illustrate the information (e.g., identification and
serial No.) printed on the labels.
The table below relates the reference numbers stated on the figures to the labels used.
Labelling depicted hereafter is for indicative purposes and could be changed without any notice.
Table 7. Label references
1AA 00014 0004 (9007) A4 – ALICE 04.10
Ref. No.
Name of Label
1
label specifying item not on catalogue (P/N and serial number)
Refer to Figure 8. on page 33.
2
label specifying item on catalogue (P/N and serial number)
Refer to Figure 9. on page 34.
3
item identification label – item on catalog
Refer to Figure 10. on page 34.
4
label identifying the equipment
Refer to Figure 11. on page 34.
5
label identifying compliancy with CE and WEEE Directives.
Refer to Figure 12. on page 35 and Figure 13. on page 35.
On contract basis, customized labels can be affixed to the equipment.
Standard labels can be affixed to any position on the equipment, as required by the Customer.
However, for each of the above are applied the rules defined by each individual Customer.
ED
03
3AG 24163 BEAA PCZZA
531
27 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1AA 00014 0004 (9007) A4 – ALICE 04.10
ED
4
Figure 1. Subrack label (1)
2
Note: the above reference numbers are detailed on Table 7. on page 27.
03
531
5
3AG 24163 BEAA PCZZA
ABCD
28 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1AA 00014 0004 (9007) A4 – ALICE 04.10
ED
Figure 2. Subrack label (2)
2
3AG 24163 BEAA PCZZA
531
Note: the above reference numbers are detailed on Table 7. on page 27.
03
ABC
29 / 531
NB.1
ABC
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
2
NB.1: the label is present on the support side.
Note: the above reference numbers are detailed on Table 7. on page 27.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 3. Subrack label (3)
ED
03
3AG 24163 BEAA PCZZA
531
30 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1AA 00014 0004 (9007) A4 – ALICE 04.10
ED
xxxxxx
xxxxxxxxx
xxxxxx
2
Figure 4. Labels on units with standard cover plate
3
3AG 24163 BEAA PCZZA
531
Note: the above reference numbers are detailed on Table 7. on page 27.
03
ABC
31 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
2
ABC
Note: the above reference numbers are detailed on Table 7. on page 27.
Figure 5. Modules label
NB.1
ABC
1AA 00014 0004 (9007) A4 – ALICE 04.10
1
NB.1: the label is present on the PCB component side.
Note: the above reference numbers are detailed on Table 7. on page 27.
Figure 6. Internal label for Printed Board Assembly
ED
03
3AG 24163 BEAA PCZZA
531
32 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
NB.1
ABC
1
NB. 1: the label is present on PCB components side or rear side on the empty spaces.
Note: the above reference numbers are detailed on Table 7. on page 27.
Figure 7. Back panels internal label
FACTORY P/N + CS
FACTORY SERIAL NUMBER
1AA 00014 0004 (9007) A4 – ALICE 04.10
SERIAL NUMBER BAR CODE
(format 128; Module = 0,166; EN 799; Subset B/C)
Figure 8. Label specifying item not on catalogue (P/N and serial number)
ED
03
3AG 24163 BEAA PCZZA
531
33 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ANV ITEM PART NUMBER + space + ICS
ANV ITEM PART NUMBER + ICS BAR CODE
(format ALFA 39 (+ * start, stop); Module = 0,166; Ratio = 2)
ALCATEL FACTORY PART
NUMBER + SPACE + CS
ACRONYM
SERIAL NUMBER BAR CODE
(format ALFA 39 (+ * start, stop); Module = 0,166; Ratio = 2)
SERIAL NUMBER
Figure 9. Label specifying item on catalogue (P/N and serial number)
FREQUENCY
(Optional)
ACRONYM
ANV ITEM PART NUMBER
Figure 10. Item identification labels – item on catalog
1AA 00014 0004 (9007) A4 – ALICE 04.10
EQUIPMENT NAME
Figure 11. Label identifying the equipment (example)
ED
03
3AG 24163 BEAA PCZZA
531
34 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1AA 00014 0004 (9007) A4 – ALICE 04.10
ED
03
Figure 12. CE Label
Figure 13. WEEE Label
35 / 531
Warning: CE and WEEE symbols can be in the same label or in different position of the
equipment.
3AG 24163 BEAA PCZZA
531
5 LIST OF ABBREVIATIONS
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Table 8. List of Abbreviations
ABBREVIATION
ED
MEANING
ABIL
Enabling
ABN
Abnormal condition
AC
Alternate Current
ADM
Add/Drop Multiplexer
AIS
Alarm Indication Signal
ALM
Alarm Board
ALS
Automatic Laser Shutdown
AND
Alarm on both station batteries
ANSI
American National Standards International
APD
Avalanche Photodiode
APS
Automatic Protection Switching
ASIC
Application Specific Integrated Circuit
ASON
Automatically Switched Optical Network
ASTN
Automatically Switched Transport Network
ATM
Asynchronous Transfer Mode
ATTD
Attended (alarm storing)
AU
Administrative Unit
AU4
Administrative Unit – level 4
AUG
Administrative Unit Group
AUOH
AU Pointer
AUX
Auxiliary
BATT
Battery
BER
Bit Error Rate
BGP
Border Gateway Protocol
BIP
Bit Interleaved Parity
BNC
Bayonet Not Coupling
BTERM
Bus Termination Board (1670SM)
BUSTERM
Bus Termination Board (Main Shelf)
CE
European Conformity
CLNP
ConnectionLess Network Protocol
CMI
Code Mark Inversion
CO
Central Office
COAX
Coaxial
03
3AG 24163 BEAA PCZZA
531
36 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ABBREVIATION
ED
MEANING
CONGIHC
Control and General Interface Board (High Capacity) in 1670SM
COPS
Common Open Policy Server
CORBA
Common Object Request Broker Architecture
CPE
Customer Premises Equipment
CPLD
Complex Programmable Logic Device
CPI
Incoming Parallel Contacts
CPO
Outgoing Parallel Contacts
CPU
Central Processing Unit
CT
Craft Terminal
DC
Direct Current
DCC
Data Communication Channel
DCCM
DCC on Multiplex Section (D4–D12)
DCCP
DCC on Path Overhead
DCCR
DCC on Regenerator Section (D1–D3)
D&C
Drop and Continue
DCM
Dispersion Compensation Module
DCN
Data Communication Network
DCR
DCC Router
DCU
Dispersion Compensation Unit
DDF
Digital Distribution Frame
DXC
Digital Cross Connect
EBU
European Broadcasting Union
EC
Equipment Controller
ECC
Embedded Control Channel
ECT
Equipment Craft Terminal
EIDEC
Enhanced IDE Controller
EM
Embedded Module (FLC)
EMI/EMC
Electromagnetic interference / Electromagnetic compatibility
EOW
Engineering Order Wire
EPS
Equipment Protection Switching
EQUICO
Equipment Controller
ES
End System
ESD
Electrostatic Discharges
ETSI
European Telecommunication Standards Institute
F
Interface F (for Craft Terminal) or Fuse
FC/PC
Type of optical connector
FCS
Frame Check Sequence
03
3AG 24163 BEAA PCZZA
531
37 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ABBREVIATION
ED
MEANING
FEBE
Far End Block Error
FEC
Forward Error Correction
FEPROM
Flesh Electrically Erasable Programmable Read Only Memory
FERF
Far End Receive Failure
FLC
First Level Controller
FLCCONGI
First Level Controller+Control and General Interface Board
FLCSERV
FLCSERVICE (First Level Controller + SERVICE Board)
FPE
Functional Protection Earth
FPGA
Field Programmable Gate Array
GA
Gate Array
G.ASTN
GMPLS Automatically Switched Transport Network
GE
Gigabit Ethernet
GBOS
Generic Basic Operating System
GFP
Generic Frame Procedure
gGOS
Performance improved version of GBOS
GMPLS
Generalized Multiprotocol Label Switching
GMRE
GMPLS Routing Engine
GND
Ground
GNE
Gateway Network Element
GRE
Generic Routing Encapsulation
GUI
Graphical User Interface
HDB3
High Density Bipolar Code Order
HDBK
Handbook
HK
Housekeeping
HMU
Housekeeping Monitoring Unit
HO
High Order
HOA
High Order Adaptation
HOI
High Order Interface
HPC
High Order Path Connection
HPOM
High Order Path Overhead Monitoring
HPROT
High Speed Protection Board
HPT
Higher Order Path Termination
HSUT
High order Supervisory Unequipped Termination
HW
Hardware
I
Intra-Office
ICS
Item Change Status
ID
Identification signals
03
3AG 24163 BEAA PCZZA
531
38 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ABBREVIATION
ED
MEANING
IEC
International Electrotechnical Commission
IEEE
Institute of Electrical and Electronic Engineers
IETF
Internet Engineering Task Force
ILM
Integrated Laser Modulator
IN
Input
I–NNI
Internal Network–to–Network Interface
IND
Indicative alarm
INT
Internal Local Alarms
ION
Intelligent Optical Network
I/O
Input/Output
IP
Internet Protocol
IPCC
IP Control Channel
IS
Intermediate System
ISA
Integrated Service Adapter
ISO
International Organization for Standardization
ISPB
Intra Shelf Processor Bus
ISU
In Service Upgrade
ITU–T
Information Telecommunication Union – Telecommunication Sector
JE1 – JE2 – JE3
Joint Engineering
L–
Long Haul
L1
Level 1 IS
L2
Level 2 IS
LA20
LO Adaptation Board 20G
LAC40
Lower Order Matrix Link 40G
LAN
Local Area Network
LAPD
Link access Procedure on D channel
LAX40
LO Adaption and Matrix Board 40G
LAX20
LO Adaption and Matrix Board 20G
LC
Type of optical connector
LCAS
Link Capacity Adjustment Scheme
LDSSHUT
Command for ALS
LED
Light Emission Diode
LIU
Line Interface Unit
LMP
Link Management Protocol
LO
Low Order
LOF
Loss Of Alignment
LOI
Low Order Interface
03
3AG 24163 BEAA PCZZA
531
39 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ABBREVIATION
ED
MEANING
LOM
Loss Of Multiframe
LOP
Loss Of Pointer
LOPP
Low Order Pointer Processing
LOS
Loss Of Signal
LPA
Lower Order Path Adaption
LPC
Lower Order Path Connection
LPM
Loop–back Line Side (remote)
LPOM
Lower Order Path Monitoring
LPT
Lower order Path Termination or Loopback equipment side
LPT
Link Path Through (Gigabit Ethernet service)
LSUT
Lower order Supervisory Unequipped Termination
LSX
LAN Switch
LX160
LO Centerstage Matrix 160GBIT/S
MAC
Media Access Controller
MCC
Metro Core Connect
MCF
Message Communication Function
MHDLC
Multi High–Level Data Link Controller
MLM
Multi Longitudinal Mode
MMF
Multimode Fiber
MPLS
Multi Protocol Label Switching
MS
Multiplex Section
MSA
Multiplex Section Adaptation
MSOH
Multiplex Section OverHead
MSP
Multiplex Section Protection
MS–SPRING
Multiplex Section Shared Protection Ring
MST
Multiplex Section Termination
MTU
Maximum Transfer Unit
MX640
Matrix Board 640GBIT/S
MX320
Matrix Board 320GBIT/S
MX160
Matrix Board 160GBIT/S
NAD
Network Access Domain
NCA
Network Control Adapter
NCI
NE Control Interface
NE
Network Element
NGTRU
New Generation Top Rack Unit
NM
Network Management
NMI
Network Management Interface
03
3AG 24163 BEAA PCZZA
531
40 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ABBREVIATION
ED
MEANING
NMS
Network Management System
NNI
Network to Network Interface
NP
Network Processor (Restoration Manager 1354NP)
NPE
Network Protection Element
NPOS
Network Protection Operating System
NRZ
No Return to Zero
NURG
Not Urgent Alarm
OBPS
On Board Power Supply
ODF
Optical Distribution Frame
OED
Optical Edge Device
OFA
Optical Fiber Amplifier
OH
OverHead
OH–BUS
Dedicated housekeeping stream
OIF
Optical Internetworking Forum
OMSG
Optical Multiservice Gateway and Cross–Connect
OMSN
Optical Multiservice Node
OOF
Out Of Frame
ORALIM
OR’ing of station power supply alarm
OS
Operation System
OSI
Open Systems Interconnection
OTH
Optical Transport Hierarchy
OTN
Optical Transport Network
O–UNI
Optical User–Network Interface
OUT
Output
PC
Personal Computer
PCB
Printed Circuit Board
PCI
Peripheral Component Interconnect
PDH
Plesiochronous Digital Hierarchy
PFAIL
Power Supply Failure
PI
Physical Interface
PJE
Pointer Justification Event
P/N
Part Number
POH
Path Overhead
PPI
Plesiochronous Physical interface
ppm
parts per million
PPS
Path Protection Switching
PWALM
Power Supply Alarm
03
3AG 24163 BEAA PCZZA
531
41 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ABBREVIATION
ED
MEANING
PWANDOR
ANDOR/3 failure
Q2/QB2
TMN interface with B2 protocol; interface towards PDH equip.
Q3/QB3
TMN Interface with B3 protocol; interface towards TMN
RA
Rack Alarm
RAI
Remote Alarm Indication
RAM
Random Access Memory
RCK
Received Clock
RDI
Remote Defect Indication
RECC
Recommendation
REI
Remote Error Indication
REL
Release
RL
Rack Lamp
RMS
Root Mean Square
RNURG
Not urgent Alarm command. Lights up the relative rack red LED
RS
Regenerator Section
RSOH
Regenerator Section OverHead
RST
Regenerator Section Termination
RURG
Urgent Alarm command. Lights up the relative rack red LED
Rx
Reception
S
Short Haul
S–LAG
Static Link Aggregation Group
SBR
Source Based Restoration
SC
Shelf Controller
SC
Type of optical connector
SDH
Synchronous Digital Hierarchy
SEC
SDH Equipment Clock
SEMF
Synchronous Equipment Management Function
SETG
Synchronous Equipment Timing Generation
SETS
Synchronous Equipment Timing Source
SFF
Small Form Factor (not pluggable)
SFP
Small Form Pluggable
SGI
Service and General Interface
SLC
Second Level Controller
SLM
Single Longitudinal Mode
SM
Single Mode/Synchronous Multiplex
SNC–P
Subnetwork Connection Protection
SOH
Section OverHead
03
3AG 24163 BEAA PCZZA
531
42 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ABBREVIATION
ED
MEANING
SONET
Synchronous Optical Network
S/P
Serial/Parallel Converter
SPC
Soft Permanent Connection
SPI
Synchronous Physical Interface
SQ
Squelch
SSF
Server Signal Fail
SSM
Synchronization Status Message
SSU
System Startup and Supervision
STM–N
Synchronous Transport Module
SW
Software
TANC
Remote alarm due to failure of all power supply units
TD
Layout drawing
TDM
Time Division Multiplexing
TMN
Telecommunication Management Network
TOR
Remote alarm indicating loss of one of the station batteries
TORC
Remote alarm due to a faulty/missing power supply unit
TRIB
Tributary
TSD
Trail Signal Degrade
TSF
Trail Signal Fail
TTF
Transport Terminal Function
TX
Transmission
U–
Ultra Long Haul
UNI
User to Network Interface
URG
Urgent
V–
Very Long Haul
VCG
Virtual Concatenation Group
VCXO/VCO
Voltage controlled oscillator
VC–x
Virtual Container
VECE
Virtual Equipment Control Element
VLAN
Virtual LAN
VMMF
Virtual Machine Management Function
WAN
Wide Access Network
WEEE
Waste of Electrical and Electronic Equipment
XFP
10 Gigabit Small Form Factor Pluggable Module
XFP–E
XFP Extended
03
3AG 24163 BEAA PCZZA
531
43 / 531
6 GENERAL ON ALCATEL–LUCENT CUSTOMER DOCUMENTATION
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
6.1 Products, Product-releases, Versions and Customer Documentation
A Product is defined by the network hierarchical level where it can be inserted and by the whole of
performance and services for which it is meant.
A Product evolves through successive Product Releases. A Product Release is a version of a Product
with a defined set of features at a given time.
A Product Release can have further development steps, named Versions, that are defined to improve or
add some features (mainly software) with respect to the previous version, or for bug fixing purposes.
Versions are defined by adding Change Levels (CL) to a Product Release or even more detailed by
adding Patch Levels (P) to a Change Level.
A Product Release has its own standard Customer Documentation consisting of a set of handbooks and
the related CD–ROM.
A new Version of a Product Release may or may not produce a change in the status of the Customer
Documentation set, as described in para. 6.4 on page 45.
6.2 Handbook supply to Customers
Handbooks are not automatically delivered together with the equipment they refer to.
The number of handbooks per type to be supplied must be decided at contract level.
6.3 Aims of Standard Customer Documentation
Standard Customer Documentation, referred to hereafter, must be always meant as plant-independent.
Plant-dependent documentation, if envisaged by the contract, is subjected to commercial criteria as far
as contents, formats and supply conditions are concerned (plant-dependent documentation is not
described here).
Standard hardware and software documentation is meant to give the Customer personnel the possibility
and the information necessary for installing, commissioning, operating and maintaining the equipment
according to Alcatel–Lucent Laboratory design choices.
In particular: the contents of the handbooks associated to the software applications focus on the
explanation of the man-machine interface and of the operating procedures allowed by it; maintenance is
described down to faulty PCB location and replacement.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Consequently, no supply to the Customers of design documentation (like PCB hardware design and
production documents and files, software source programs, programming tools, etc.) is envisaged.
The handbooks concerning hardware (usually the ”Technical Handbook”) and software (usually the
”Operator’s Handbook”) are kept separate in that any product changes do not necessarily concern their
contents.
For example, only the Technical Handbook might be revised because of hardware configuration changes
(e.g., replacing a unit with one having different part number but the same function).
On the other hand, the Operator’s Handbook is updated because of a new software version but which does
not concern the Technical Handbook as long as it does not imply hardware modifications.
However, both types of handbooks can be updated to improve contents, correct mistakes, etc..
ED
03
3AG 24163 BEAA PCZZA
531
44 / 531
6.4 Handbook Updating
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The Customer handbooks associated to the Product Release are listed in para. 1.3 on page 18.
Each handbook is identified by:
–
–
–
–
the name of the Product Release;
the handbook name;
the handbook part number;
the handbook edition (usually first edition=01);
6.4.1 Changes introduced in the same Product Release (same Handbook Part Number)
Changes of the handbook cause the edition number increase (e.g. from Ed.01 to Ed.02). Version character
can be used for draft or proposal editions (e.g. Ed. 01A).
6.4.1.1 Supplying updated Handbooks to Customers
Supplying updated handbooks to Customers who have already received previous issues is submitted to
commercial criteria.
By updated handbook delivery it is meant the supply of a complete copy of the handbook’s new issue .
6.4.2 Notes for Handbooks relevant to Software Applications
Handbooks relevant to software applications (typically the Operator’s Handbooks) are usually only
modified, if the new software Version distributed to Customers implies man–machine interface changes.
Particularly, screen prints are not updated just because they contain a name of a former Product Release.
They are updated only, if the screen content has changed.
6.4.3 Changes due to new Product Version
1AA 00014 0004 (9007) A4 – ALICE 04.10
A new product version changes the handbook part number and the edition starts from 01.
In this case the modified parts of the handbook are not listed.
ED
03
3AG 24163 BEAA PCZZA
531
45 / 531
6.5 Documentation supply on CD–ROM
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
In the following ’CD–ROM’ means ’Customer Documentation on CD–ROM’.
6.5.1 Contents, Creation and Production of a CD–ROM
In most cases, a CD–ROM contains the documentation of one Product Release and for a certain language.
A CD–ROM is obtained collecting various handbooks and documents in .pdf format. Bookmarks and
hyperlinks make the navigation easier. No additional information is added to each handbook, so that the
documentation present in the CD–ROMs is exactly the same the Customer would receive on paper.
The files processed in this way are added to files/images for managing purpose and a master CD–ROM
is recorded.
Suitable checks are made in order to have a virus–free product.
6.5.2 Use of the CD–ROM
The CD–ROM can be used both in PC and Unix WS environments.
The CD–ROM starts automatically with autorun and hyperlinks from the opened Index document permit
to visualize the handbooks.
In order to open the .pdf documents Adobe Acrobat Reader Version 4.0 (minimum) must have been
installed on the platform.
The CD–ROM does not contain the Adobe Acrobat Reader program. The Customer is in charge of getting
and installing it.
ReadMe info is present on the CD–ROM to this purpose.
Then the Customer is able to read the handbooks on the PC/WS screen, using the navigation and zooming
tools included, and to print selected parts of the documentation on a local printer.
6.5.3 CD–ROM Identification
1AA 00014 0004 (9007) A4 – ALICE 04.10
Each CD–ROM is identified:
ED
1)
by the following external identifiers, that are printed on the CD–ROM upper surface:
–
the name of the Product Release
–
a writing indicating the language(s)
–
the CD–ROM part number
–
the CD–ROM edition (usually first edition=01)
2)
and, internally, by the list of the source handbooks and documents (part numbers and editions)
by whose collection and processing the CD–ROM itself has been created.
03
3AG 24163 BEAA PCZZA
531
46 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
7 REGISTERED TRADEMARKS
–
–
–
–
ED
HP is a registered trademark of the Hewlett–Packard Corporation
UNIX is a registered trademark of UNIX System Laboratories, AT&T
Sun, SunOS, SPARC, NeWSprint and Solaris are registered trademarks of Sun Microsystems, Inc.
All other names, products and services mentioned are trademarks of their respective holders.
03
3AG 24163 BEAA PCZZA
531
47 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ED
03
3AG 24163 BEAA PCZZA
531
48 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1AA 00014 0004 (9007) A4 – ALICE 04.10
ED
03
49 / 531
DESCRIPTIONS
3AG 24163 BEAA PCZZA
531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ED
03
3AG 24163 BEAA PCZZA
531
50 / 531
8 GENERAL
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
8.1 Introduction to the Equipment
The 1678 Metro Core Connect (MCC) is a new generation Optical Multiband Platform for Broadband
(SDH/Sonet), Wideband (SDH/Sonet), OTN and L2 (Ethernet) functionalities, each portion flexibly
configurable in size. Starting with a switching capacity of 640 Gbit/s in one single shelf, the architecture
allows scaling to bigger capacities in each direction thanks to its modular design and advanced technology.
The system has been designed to address all the variety of applications from metro to backbone networks
supporting ring–based functionalities as well as advanced mesh topologies based on GMPLS/ASON
dynamic control plane (refer to Figure 14. on page 52).
Telecom Operators and Service Providers look for prompt solutions to face the challenges of today’s
telecommunication market. New revenue opportunities from broadband services can be supported by
limited budgets for new network infrastructures. By leveraging an SDH/SONET infrastructure capable to
evolve, carriers can reach the objective of enabling broadband services while keeping network and
operation costs to a minimum level.
An ideal transport solution for metro–core and core networks has to satisfy the following requirements:
•
Simplify and optimize the network: less network elements capable of better aggregating and
consolidating huge multi–protocol traffic streams towards the core.
•
Minimize costs: compact equipment with high switching capacity and high density interfaces
to lower CAPEX and OPEX with respect to more complex multi–node architectures.
•
Enable broadband services: support Gigabit Ethernet and data layer management features
to enable Packet–based services cost–effectively.
•
Future proof: easy to support Optical Transport Network (OTN) architectures, lambda
switching and GMPLS control plane.
The 1678 Metro Core Connect of the Intelligent Optical Multi–Service Nodes (OMSN) family was designed
to meet all those challenges.
The 1678 MCC is an Intelligent Optical Multi–Band Node with an outstanding broadband density of
640 Gbit/s or 4096 x 4096 STM–1 equivalents in a single shelf, with a wideband (VC12/VT1.5) matrix up
to 40 Gbit/s, Gigabit Ethernet, ASON/GMPLS and OTN extension features.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The system is highly scalable both in broadband and wideband direction: the architecture is ready for
possible future evolution up to 160 Gbit/s for the wideband switching and up to 5 Tbit/s for the broadband
one.
ED
03
3AG 24163 BEAA PCZZA
531
51 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1AA 00014 0004 (9007) A4 – ALICE 04.10
ED
Optical Core
Metro Core
10G/2.5G
STM 1/4/16
Metro Access
03
10GE
G.709
Submarine
10G
1678 MCC
1GE
–
Figure 14. 1678MCC scenario
IP Backbone
3AG 24163 BEAA PCZZA
531
52 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The 1678MCC equipment allows for a seamless evolution of the existing SDH/SONET infrastructure
towards OTN and packet base services, offering a single–shelf solution with unsurpassed compactness
and capacity, providing telecom operators with both near–term and long–term benefits:
ED
•
Compact and Capable
640 Gbit/s worth traffic capacity in one single shelf. Minimum footprint with up to 3.8 Tbit/s
switching in one 600x600 rack. High density interfaces, such as 16 x STM–16 or 4 x STM–64
in one slot.
•
Wideband Grooming Point
Fully flexible, non–blocking 256 x 256 STM–1 equivalents, 20G or 40G LO single board matrix
(VC/11/12/3), 1+1 EPS protected. Each copy of the LO matrix is plugged into one 40G slot of
the main shelf.
From R4.1 on a 160 Gbit/s (1024 x 1024 STM–1 equivalents) LO matrix is introduced. This LO
matrix is located in an own shelf named LO Extension Shelf.
•
Multiservice Broadband enabler
Standardized Gigabit Ethernet transport and aggregation for packet–based services.
•
Family I/O edge devices
Full range of wideband interfaces (E1, E3, E/FE/GE, STM1–el., STM1–opt., STM–4/16/64) are
supported in Optical Edge Devices (OEDs), as 1662SMC and 1670SM. Multi–shelf
configurations are managed as single network element.
•
Grow as you want
Next generation plug–in optical interfaces. Scalable wideband LO fully non blocking extension.
•
Cost–effective
Reduced CAPEX and OPEX thanks to network and office simplification. Pay–as–you–grow
service capacity increments up to 4096 STM–1 equivalents, including Lower Order
aggregation. Support of both SDH and SONET transport technologies.
•
Future–proof
Hardware platform ready for VC–4/ODU–k switching and GMPLS/ASON control plane
management to support OTN and meshed architectures.
03
3AG 24163 BEAA PCZZA
531
53 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
8.2 General Description
All kind of broadband (STM–1/4/16/64, 1GE, 10GE), wideband (E1, E3, STM1) and Optical G.709 (OTM1,
OTM2, colored) interfaces are integrated with a family concept to support traditional TDM, data aware,
long haul SAN and transparent services.
The 1678MCC can operate in any mesh, ring, restoration or hub and spoke topology, because of its
superior blocking free cross–connect architecture and its fast–speed control plane. It can be used as a
Multi–Terminal, Multi–Ring closure node, Restoration–Crossconnect or as a Gateway between different
layers.
The HO switching functionalities are implemented in a 640 Gbit/s Matrix board that can be extended in
future. The matrix supports any mixture of AU–4 and AU–3 cross connections. In future the available signal
rates are extended to ODU1 and ODU2 (ITU–T G.709).
Moreover a LO matrix is available with a capacity of 40 Gbit/s for cross connecting at VC–3/VC–12 level.
In future it will also support VC11. This function allows the perfect control of VC–4 and VC–3 pipes filling
in the SDH frame, maximizing flexibility.
When the LO matrix is used in conjunction with an I/O shelf containing the LO interfaces, the 1678MCC
becomes a next generation wideband cross–connect. The architecture is prepared to scale the LO
capacity beyond 40G in service operation.
From R4.1 on a LO matrix with a capacity up to 160 Gbit/s is available.
The same LO matrix board implements the AU3–TU3 conversion function: this enables the usage of
1678MCC in a mixed SDH/SONET traffic environment.
Figure 15. on page 49 shows the SDH/SONET multiplexing schemes of the 1678MCC.
The plug–in boards can be of the following types:
–
–
–
–
–
–
STM–64 port (1x/2x/4x):
Intraoffice, Short, Long, Very Long and Ultra Long Haul interfaces
STM–16 port (4x/8x/16x):
Short and Long Haul interfaces
STM–4 port (16x):
Short and Long Haul interfaces
STM–1 port (16x):
Short and Long Haul interfaces; electrical interfaces
Gigabit Ethernet (4x/8x/16x):
SX and LX interfaces
10 Gigabit Ethernet
10G–SR, 10G–LR and 10G–ER interfaces
Additional plug–in boards are supported in OED shelves 1670SM and 1662SMX:
–
–
–
–
STM–4 port (4x):
Short and Long Haul interfaces
STM–1e port (4x/16x)
140Mbit/s port
2Mbit/s port
1AA 00014 0004 (9007) A4 – ALICE 04.10
For future applications the following OTH interfaces will be supported:
–
–
–
–
OTM–0.1
OTM–0.2
2.5 Gbit/s UNI (STM–16/CBR 2.5 Gbit/s)
9.95 Gbit/s UNI (STM–64/CBR 9.95 Gbit/s)
These interfaces are not shown in Figure 15. (SDH/SONET multiplexing schemes).
ED
03
3AG 24163 BEAA PCZZA
531
54 / 531
x1
STM–256
AUG256
AU3–768c
VC4–256c
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
x4
STM–64
x1
OC192
STM–16
AUG64
C4–64
STS–192c SPE
AUG16
10GE
VC4–16c
AU3–48c
C4–16c
STS–48c SPE
OC48
STM–4
VC4–64c
AU3–192c
x4
x1
C4–256c
STS–768c SPE
x4
x1
AUG4
VC4–4c
AU3–12c
C4–4c
STS–12c SPE
OC12
x4
STM–1
x1
x1
x1
AUG1
AU3–3c
x1
VC–4
C4
x3
STS–3c SPE
OC3
EC3
x3
STM–0
x1
x1
TUG–3
AU3
TU–3
VC–3
C3
VC–3
STS1–SPE
OC1 (optical)
EC1 (electrical)
x7
(DS3) GE
x7
x1
TUG–2
TU–2
VT–Group
x3
TU–12
1678MCC matrix connectivity supported for this signal rate
VC–2
C2
VT6
DS2
VC–12
C12
VT2
2Mbit/s
VC–11
C11
x4
TU–11
supported (monitoring or payload mapping or interface type)
VT1.5
planned
OTH capability not shown.
1GE with configurable virtual concatenation and LCAS.
10GE with configurable virtual concatenation, LCAS, EPL and EVPL.
GE
140Mbit/s
GE
SPE
STS
VT
DS1
Gigabit Ethernet
Synchronous Payload Envelope
Synchronous Transport Signal
Virtual Tributary
Figure 15. 1678MCC SDH/SONET Multiplexing Schemes
Some additional units are devoted to central functions:
–
–
1AA 00014 0004 (9007) A4 – ALICE 04.10
–
–
–
–
Equipment Controller units
HO SDH/SONET/OTN Matrix + Clock Reference units
•
MX640, MX320 and MX160 for ETSI applications
•
MX640GA and MX320GA for ANSI applications
LO Matrix
Power supply filter boards
FAN cooling units
Service and Control&General interfaces boards
According to the network topology, single ended and dual ended MSP (Multiplex Section Protection) 1+1
and 1:N can be implemented between any STM–n interfaces.
SNCP (Sub Network Connection Protection) inherent (SNCP/I) as well as non–intrusive (SNCP/N) is also
provided at all VC–4, VC–3 and VC–12 levels (future: VC11 as well).
The SDH ports belonging to a protection group (MSP or SNCP) can be flexibly selected by craft terminal
or management system, regardless of their position in the shelf.
MS–SPRing protection is supported in a 2F or 4F schema, at STM–16 or STM–64 level.
The 1678 MCC supports non–intrusive Path Overhead Monitoring (POM) of the Higher Order and Lower
Order VCs. For LO VCs only Monitoring before matrix is supported.
ED
03
3AG 24163 BEAA PCZZA
531
55 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Supervisory Unequipped Trail (SUT) functions on 100% is only supported for Higher Order VCs. Tandem
Connection Monitoring and Termination capabilities can be supported in future.
All STM–1, STM–4 and STM–16 optical interfaces are realized with SFP plug–in technology, giving small
size, cheapness and huge flexibility. XFP modules can be used for STM–64 and 10GE interfaces.
For Very Long Haul (VLH) and Ultra Long Haul (ULH) at STM–64 boards the optical amplifiers and
pre–amplifiers are integrated on the relevant boards.
The synchronization function, located on the SDH/SONET matrix board, synchronizes the 1678 MCC and
provides generation and distribution of a reference clock. The clock can be locked to an external 2 MHz,
2 Mbit/s or 1.5 Mbit/s source, to any STM–N traffic port or to the internal oscillator. The SSM
(Synchronization Status Message) quality and priority algorithms are also supported (not for 1.5 Mbit/s).
The Equipment Controller and Service Controller boards provide configuration, alarm status and
performance monitoring data. A software download facility (Local and Remote) is available in order to
update the complete software of the control subsystem. The system can be managed either by a CMISE
Craft Terminal running on a Personal Computer attached to the F–interface, by the Network Management
System through the Q–interface or by a TL1 command line interface.
1AA 00014 0004 (9007) A4 – ALICE 04.10
A DC/DC converter, located on each board, guarantees power supply throughout the system. The
distribution of the DC/DC converters guarantees inherently power supply hardware protection.
ED
03
3AG 24163 BEAA PCZZA
531
56 / 531
8.3 1678MCC Main Shelf Equipment View
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
In the following figures are shown the 1678MCC Main Shelf Equipment photos:
•
Figure 16. on page 57 shows a view of equipment with cover;
•
Figure 17. on page 58 shows a lateral view of equipment with cover;
•
Figure 18. on page 59 shows a view of the 1678MCC main shelf with relevant units (common
and traffic ports board).
Figure 16. 1678MCC Main Shelf – Front View
ED
03
3AG 24163 BEAA PCZZA
531
57 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1AA 00014 0004 (9007) A4 – ALICE 04.10
ED
03
Figure 17. 1678MCC Main Shelf – Side View
3AG 24163 BEAA PCZZA
531
58 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1AA 00014 0004 (9007) A4 – ALICE 04.10
ED
03
Figure 18. 1678MCC Main Shelf – Board View
3AG 24163 BEAA PCZZA
531
59 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
8.4 Insertion of the Equipment into the Network
The 1678MCC equipment belongs to the Alcatel–Lucent OMSN family product, compliant with the
Synchronous Digital Hierarchy (SDH) defined by the ITU–T Recs. and compliant with SONET defined by
the ANSI Recs.
The 1678MCC can be used for transmission over any type of fiber.
The equipment 1678MCC can be utilized in interurban, regional and metropolitan networks configured for
standard plesiochronous or synchronous systems.
The product can be suitably employed on linear, ring and hub networks and on protected or unprotected
line links.
The equipment applications depends on the different types of networks available.
The main applications are described in the following paragraph.
8.4.1 Applications
The 1678MCC is designed with enough flexibility to find application in many segments of a carrier’s
network. Because the system can be minimally configured with a matrix, common control and interface
boards, yet also be fully populated with a mix of interface types, the same system can be used either near
the network edge or even in core applications.
A number of the most important network applications are listed below:
•
•
•
•
•
•
•
•
•
Metro–Core Cross–Connect (VC–4/3/12/11)
Core Cross–Connect (VC–4nc/VC–4; AU–3nc/AU–3)
Optical Gateway Cross–Connect (SDH/SONET/OTH)
Gateway in Trans–National networks
Gateway in Submarine Landing station
Gateway for Carrier – Carrier stations
Hub and Spoke node in Core Data networks
Service Connect for Mobile Core Networks
ASON / GMPLS node for Core ISP networks
Optimized Site Architectures
All kind of network topologies like hub and spoke, ring or mesh networks are supported by 1678MCC,
converging the different layers of transmission.
Most carriers’ networks contain points of presence or central offices in physical locations dictated by traffic
demand or collocation with other carriers. Typically, these offices form interconnection points between:
•
ring or hub based access and metro structures that collect and aggregate traffic coming from
the network edge, often carrying as well LO as HO traffic parts;
ring or mesh based transport structures, interconnecting different metro areas directly or via a
metro core / core network (mostly HO structured).
•
1AA 00014 0004 (9007) A4 – ALICE 04.10
Historically, sites therefore required a number of network elements (LO/HO OMSNs, LO/HO DXCs) in
order to satisfy the different applications. Today only one 1678MCC is necessary to perform this task, such
ensuring a very cost–effective node solution.
In addition to this office modernization effect, there are other possibilities to reduce the required node
functionality and size (and with that the node cost) by choosing appropriate layered network topologies.
This should be done in such a way that transit traffic is avoided in client layers and switched or
cross–connected in server layers instead.
ED
03
3AG 24163 BEAA PCZZA
531
60 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
One example for such an network concept is the change from hierarchical IP/MPLS over DWDM networks
to a flat (fully meshed on the MPLS layer) architecture, with an intermediate SDH layer which provides an
1:1 mapping of MPLS LSPs into SDH VCs. These than can be groomed and cross–connected throughout
their way in the network at lower cost as it would be if they had to be handled in real IP/MPLS nodes at
each location.
The 1678MCC with its data functionalities is best suited and prepared for these applications.
Aggregation
Whether there is a need for traffic aggregation or cross–connecting – the 1678MCC provides the optimized
solution. Usually in the metro area many customers create low bit–rate access traffic using various
services to reach their partners and service providers somewhere else.
The 1678MCC fits in ideally as an advanced wideband multi–service cross–connect which bridges the
required distances and concentrates the required capacities in one single network element by using
SDH/SONET and OTH technology. Comprising the wide range of interfaces from 2 Mbit/s to 10 Gbit/s by
using extension shelves, even the OTH boundary transition in core networks is effectively possible.
Thus, thanks to its flexible architecture and SW build–up it is possible not only to converge SDH and
SONET but also OTH on a common platform taking the benefits of aggregation over all layers.
Data Interfaces
The growth of data applications adds the requirement for associated interfaces like 1 Gigabit Ethernet
(1GE) or 10GE.
The 1678MCC supports optical 1/10 Gbit/s Ethernet data interfaces that enable easy to handle and cost
effective connectivity towards data aware networks with Routers and Servers.
Following applications are supported:
•
•
•
Point to Point EoS (Ethernet over SDH/Sonet)
Point to Multi–Point EoS (with L2 extension)
LSR (Label Switch Router) in core data networks
GASON / GMPLS Support
The overall forecasted growth of data applications adds requirements for dynamics and interoperability,
not only for the service but also for the management of the transport entity. Automatic Switched Optical
Networks (ASON) as the concept and Generalized Multi Protocol Label Switching (GMPLS) as the
protocol are today’s buzzwords in this aspect.
The traditional trend of centralized management of transmission networks is enhanced with the
introduction of a dynamic, decentralized control plane paying tribute to the new demand. By introducing
such a concept to the optical transmission, a new era arises.
1AA 00014 0004 (9007) A4 – ALICE 04.10
This era will lead to:
ED
•
Restorable mesh networks.
Those are either already implemented or under implementation. Automation is used here to
achieve a kind of ’automatic redialing’ performed by the network in case of failures. Based on
this technology a much finer service differentiation can be provided compared to today’s
protected networks.
•
Interoperability on control level.
Actually each vendor has a different manager for his equipment and in a multi vendor domain
there is always an issue to provide end–to–end connectivity and supervision.
03
3AG 24163 BEAA PCZZA
531
61 / 531
By using standard protocols between devices of different vendors, a end–to–end provisioning
can be achieved by actually performing only one provisioning action at the source of a
connection.
New services with close protocol interaction (ASON) between Data and Transmission
equipment. Here the service node (e.g. a router) can derive according to bandwidth and QoS
requirements whether additional transport capacity is needed or if sufficient capacity is readily
available.
Automatic switching from user side may be introduced concurrently to above steps depending
on prosperous business models. Ethernet over SDH may push for a control plane
interoperability between data and transmission to actually control and maintain the overall
network. Bandwidth on Demand (BonD) can become a service once interoperability between
nodes and technologies are resolved.
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
•
•
Alcatel–Lucent is also tackling one of the key issues operators see when dealing with GMPLS, that is its
operational manageability. Yet, this seems to be one of the key factors that have so far prevented
widespread adoption of the technology.
Here comes Alcatel–Lucent distinctive story: thanks to huge and unparalleled experience accumulated
in transport network management, including the intricacies of large backbone real time restoration
systems, Alcatel–Lucent is in a position to design, implement and deploy a managed GMPLS solution that
allows tracking in real time the circuit and bandwidth allocation within the network keeping continuous
control of network resource usage.
Also, to ease deployment and customization with the new technology, Alcatel–Lucent solution allows
partitioning of each NE between different control planes, allowing a smooth transition from the current
technology paradigm to the next.
”Lambda” aware Networking
The 1678MCC has built in networking capabilities according to the new Optical Transport Hierarchy (OTH)
which allows effective and cost efficient networking on a coarser granularity than traditional SDH/SONET
+networks. Even if OTH signals are digital signals and as such independent from the physical medium they
currently are transported or processed, often it is referred to as ”Lambda” networking, as DWDM
technology is part of the OTH concept and as the transport entities are in the order of magnitude of a
complete wavelength (today 2.5 & 10 Gbit/s, in future also 40 Gbit/s).
Three major network applications can be fulfilled by the 1678MCC on the OTH layers:
•
a gateway functionality between SDH and OTH networks with the appropriate mapping
functionalities (e.g. STM–16 in ODU1, or STM–64 in ODU2);
a pure ODU cross–connect functionality between OTH interfaces;
a ”modem” functionality which allows both, complete STM–N signals and already ODU
structured OTH signals, to be transported over non–OTH–aware SDH networks (using virtual
concatenated SDH VCs as transport entity).
•
•
Optical Edge Device (OED) Integration
1AA 00014 0004 (9007) A4 – ALICE 04.10
Optical Edge Devices (OEDs) will be used in 1678 Metro Core Connect to provide additional I/O ports,
which are not supported in the 1678MCC main shelf at all, or where implementation in the OED allows
a better usage of the HO matrix capacity in the 1678MCC main shelf.
The OED integration feature covers the complete integration of OEDs, consisting of the mechanical OED
integration and the SW OED integration.
ED
03
3AG 24163 BEAA PCZZA
531
62 / 531
8.4.2 Configuration
•
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Terminal multiplexer (refer to Figure 19. on page 63)
The multiplexer is provided with an STM–1 / STM–4 / STM–16 / STM–64 station interface
(possibly stand–by too) to be connected to a Digital Electronic Cross–Connect or to a higher
hierarchical line system.
SDH
PDH PORTS
SDH PORT
NE
SDH PORT
(SPARE)
Figure 19. Terminal multiplexer
•
Add/Drop Multiplexer (refer to Figure 20. on page 63)
The multiplexer can be programmed to drop (insert) signals from (into) the STM–1 / STM–4 /
STM–16 / STM–64 stream.
Part of the signal pass–through between the line sides, defined A and B in Figure 20. on page
63.
Side A
SDH PORT
SDH PORT
NE
Side B
SDH PORT
(SPARE)
SDH PORT
(SPARE)
SDH, PDH PORTS
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 20. Add/Drop Multiplexer
ED
03
3AG 24163 BEAA PCZZA
531
63 / 531
•
”HUB” STM–N (refer to Figure 21. on page 64)
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The multiplexer permits to drop/insert STM–N tributaries into a multiple stream and then branch
them off in HUB structures.
SDH PORT
SDH PORT
NE
SDH PORT
(SPARE)
SDH PORT
(SPARE)
SDH PORT
Figure 21. ”HUB” STM–1
•
Mixed Configuration
1AA 00014 0004 (9007) A4 – ALICE 04.10
The NE can handle in the same node all the previously configuration thus performing a mixed
configuration.
ED
03
3AG 24163 BEAA PCZZA
531
64 / 531
8.4.3 Network Topologies
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
For each of the above network applications different network topologies may be used.
The most important network topologies are:
•
•
•
•
–
Point to Point
Linear
Ring and multiring topology
Meshed topology
Point–to–point link (refer to Figure 22. on page 65)
In this case the NE can be connected to another NE through the line.
SDH PORT
SDH
PDH PORTS
SDH PORT
NE
SDH
PDH PORTS
NE
SDH PORT
SPARE
SDH PORT
SPARE
Figure 22. Point–to–point links
–
Linear Drop–insert (refer to Figure 23. on page 65)
The NE can be programmed to drop (insert) PDH and SDH ports from (into) the STM–1, STM–4,
STM–16, STM–64 stream or terminate PDH ports.
SDH PORT
NE
SDH PORT
NE
SPARE
SDH PORT
NE
SPARE
NE
SPARE
PDH PORTS
PDH PORTS
1AA 00014 0004 (9007) A4 – ALICE 04.10
SDH AND PDH
PORTS
SDH AND PDH
PORTS
Figure 23. Linear drop–insert
ED
03
3AG 24163 BEAA PCZZA
531
65 / 531
–
Ring structure (refer to Figure 24. on page 66)
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The drop–insert function permits to realize ring structures.
The VC can be automatically rerouted if the optical splice breaks down or one of the equipment nodes
fails.
SDH AND PDH
PORTS
STM–64
NE
STM–64
RING1
SDH AND PDH
PORTS
NE
SDH AND PDH
NE
SDH AND PDH
PORTS
STM–64
PORTS
STM–64
NE
STM–1
STM–1
PDH
PORTS
SDH AND PDH
PORTS
NE
SDH AND PDH
PORTS
NE
RING2
STM–1
STM–1
NE
1AA 00014 0004 (9007) A4 – ALICE 04.10
SDH AND PDH
PORTS
Figure 24. Ring structure
ED
03
3AG 24163 BEAA PCZZA
531
66 / 531
–
Meshed Topology (refer to Figure 25. on page 67)
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The Meshed topology may be used in case of collection of traffic in peripheral nodes or customer
premises sites. The 1+1 line protection may be used to protect against line failure and, in some
cases, node failure could be protected using dual hub topology too. For this type of network
topologies the mini digital cross connect system is very useful and SNCP/I is used.
PDH PORT
NE
STM–N
STM–N
SDH AND PDH
PORTS
PDH PORT
PDH PORT
STM–1
NE
RING1
STM–N
NE
NE
STM–1
NE
STM–N
PDH PORT
NE
STM–N
SDH AND PDH
PORTS
STM–N
PDH PORT
NE
STM–N
STM–N
NE
STM–N
NE
RING2
NE
PDH PORT
SDH AND PDH
PORTS
STM–N
NE
STM–N
1AA 00014 0004 (9007) A4 – ALICE 04.10
PDH PORT
Figure 25. Meshed topology
ED
03
3AG 24163 BEAA PCZZA
531
67 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
8.5 1678MCC Management Interfaces
With the extensive introduction of SDH and WDM in the transport network, centralized and integrated
network management is mandatory for Network Operators to realize the potential cost saving and required
Quality of service.
Figure 26. shows the 1678MCC Management Interfaces. A CMISE Interface, based on Q3 or
RFC 1006, for communication with the Craft Terminal (CT) and other Network Managers, like 1353SH
(Element Management System) or 1354RM/1354NP (Domain Management) is existing.
Furthermore the 1678MCC can be managed over a TL1 interface.
TL1
CT
TL1
CMISE–IF
TL1 Adapter
CMISE–IF
1678MCC
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 26. Management Interfaces of 1678MCC
ED
03
3AG 24163 BEAA PCZZA
531
68 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
8.5.1 Craft Terminal
The Craft Terminal is a project in charge of the local management of single network elements.
Multiple NE management up to 32 Network elements is possible, obtaining a remote Craft Terminal
application. This number is defined in order not to overload the network.
The Craft Terminal uses a state–of–the–art platform for providing an advanced and integrated
Management. It is ALMAP, the Alcatel Management Platform.
The Craft Terminal is based on EML core, a project that extends ALMAP in order to provide a common
set of functions for projects which realize an Alcatel–Lucent network management system. This project
is common with the 1353SH (Element Management Level ), permitting the same approach for the NE
management (commonality of views and commands).
Examples of network management architecture are reported in Figure 27. on page 70.
The SDH/SONET Equipment provides two types of physical interfaces for management functions: the F
interface and the QB3 interface. To these interfaces can be connected the manager computer, that can
be:
•
a CRAFT TERMINAL (CT). It is generally a personal computer (PC), connected through the F
interface for local management.
•
OPERATION SYSTEM (OS). Workstations utilized for the TMN (Telecommunications
Management Network). They are connected through the QB3 interface, for network
management.
The management can be realized in local or remote mode:
•
in the local mode the managed equipment are directly connected to the computer via F
interface
•
in the remote mode the managed equipment are indirectly connected via the OSI Networking
which can include both DCCM / DCCR protocol or Ethernet LAN (Local Area Network)
•
in the remote mode the managed equipment are indirectly connected via an IP network using
a tunnel over IP.
1AA 00014 0004 (9007) A4 – ALICE 04.10
For more detailed information refer to CT Basic Operator’s handbook.
ED
03
3AG 24163 BEAA PCZZA
531
69 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
LAN
OPERATIONS
SYSTEM
NE
GATEWAY
LAN
LAN
BRIDGES /
ROUTERS
DCN
OPERATIONS
SYSTEM
LAN
BRIDGES /
ROUTERS
LAN
QB3
N.E
GATEWAY
DCC/LAN
QB3
CRAFT
TERMINAL
F
N.E
GATEWAY
F
N.E
GATEWAY
F
DCC/LAN
DCC/LAN
DCC/LAN
F
NE
NE
NE
Craft
Terminal
F
NE
DCC/LAN
DCC/LAN
DCC/LAN
F
F
N.E
N.E
N.E
F
DCN : Data Communication Network
N.E. : Network Element (MSN, ADM, CROSS CONNECT; etc)
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 27. Example of network management architecture via Craft Terminal
ED
03
3AG 24163 BEAA PCZZA
531
70 / 531
8.5.2 TL1 Interface
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
For ANSI market application the 1678 provides a TL1 NE management interface. The basic characteristics
of the TL1 interface are compliant to applicable Bellcore standards.
The TL1 interface is implemented by a new software layer TL1.
The TL1 interface will be used by operator personnel for daily work from remote locations and network
element (NE) local maintenance. The TL1 interface will further be used by Network Management for Alarm
Supervision and Path Provisioning.
The TL1 interface is a command line interface. The operator starts a Telnet session via LAN and can
control the system using TL1 commands.
LAN
TL1
interface
NE
GATEWAY
LAN
LAN
BRIDGES /
ROUTERS
DCN
OPERATIONS
SYSTEM
LAN
BRIDGES /
ROUTERS
LAN
QB3
N.E
GATEWAY
DCC/LAN
QB3
CRAFT
TERMINAL
F
N.E
GATEWAY
DCC/LAN
F
N.E
GATEWAY
F
DCC/LAN
DCC/LAN
F
NE
NE
F
NE
NE
DCC/LAN
DCC/LAN
DCC/LAN
F
F
N.E
N.E
N.E
F
DCN : Data Communication Network
N.E. : Network Element (MSN, ADM, CROSS CONNECT; etc)
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 28. Example of network management architecture via TL1 interface
ED
03
3AG 24163 BEAA PCZZA
531
71 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ED
03
3AG 24163 BEAA PCZZA
531
72 / 531
9 RACK CONFIGURATIONS
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
9.1 Configuration Possibilities
The 1678MCC cross connect consists of one or more racks. The minimum configuration is one main rack
equipped with the main shelf. This configuration can be extended with additional shelves an racks.
There are four kinds of shelves:
–
–
–
–
Main shelf
Lower Order extension shelf
1670SM OED
1662SMC OED
These shelves can be mounted in two different racks. The main shelf and the LO extension shelf can only
be mounted in a main rack. The OED shelves can be mounted inside the main rack in combination with
the main shelf or in a separate rack, named OED rack.
The several rack configurations are shown from Figure 29. to Figure 31.
Figure 29. shows the combination possibilities of main shelf and OED shelves inside the main rack.
Figure 30. shows the combination possibilities with the LO extension shelf.
Figure 31. shows the configuration possibilities of the OED shelves inside the OED rack.
For more details about the shelves installation in the racks refer to the “Installation Handbook”.
NGTRU
HMU
NGTRU
HMU
Cable Space
NGTRU
NGTRU
NGTRU
NGTRU
HMU
HMU
HMU
DCU
HMU
DCU
Cable Space
1662SMC
Main
Shelf
1670SM
Main
Shelf
FAN
Main
Shelf
Main
Shelf
Cable Space
FAN
Main
Shelf
DCU
Main
Shelf
Cable Space
Main
Shelf
DCU
Top access
Main
Shelf
1670SM
DCU
1662SMC
FAN
FAN
Bottom access
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 29. Schematic 1678MCC Main Rack Configurations with Main and OED Shelves
ED
03
3AG 24163 BEAA PCZZA
531
73 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Configuration inside the main rack
Rack for system extension *
NGTRU
NGTRU
HMU
HMU
Main
Shelf
LO
Shelf
Storage Box
LO
Shelf
LAN
* The extension rack can be mounted at right, left or back side of an existing main rack.
Figure 30. Schematic 1678MCC Rack Configurations with LO Extension Shelf
TRU
HMU
TRU
HMU
1662SMC
1662SMC
FAN
FAN
TRU
HMU
TRU
HMU
1670SM
FAN
LAN
DCU
Top access
HMU/DCU
1670SM
FAN
1670SM
1662SMC
FAN
LAN
TRU
1662SMC
FAN
1670SM
TRU
HMU
DCU
FAN
FAN
1662SMC
1662SMC
FAN
FAN
LAN
LAN
1662SMC
1670SM
FAN
FAN
Top/Bottom
access
Bottom access
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 31. Schematic OED Rack Configurations
ED
03
3AG 24163 BEAA PCZZA
531
74 / 531
9.2 Rack Configuration for SONET markets
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The following special features exits:
–
–
One main shelf or,
Main shelf plus LO extension shelf (customer specific racks are used)
–
Lower FAN unit with dust filter,
–
Special shelf with support for dust filter,
–
Modified NGTRU to provide ANSI complaint battery inputs,
–
No HMU is used.
This is possible in case of single shelf per rack only. In this case a dedicated alarm cable is needed
to interface NGTRU with main shelf.
Figure 32. shows a schematic SONET rack configurations.
NGTRU
NGTRU
Main
Shelf
Main
Shelf
LO
Shelf
Top/Bottom access
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 32. Schematic SONET Rack Configurations
ED
03
3AG 24163 BEAA PCZZA
531
75 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
9.3 LAN Switches (LSX)
For multirack configurations consisting of a 1678MCC main rack and several OED racks a pair of Ethernet
LAN switches are needed to interconnect the internal control plane.
The two LAN switches will be mounted at the bottom of one OED rack (refer to Figure 33. ). For more details refer to the “Installation Handbook”.
OED Rack
Main Rack
OED Rack
LAN A
LAN B
TRU
NGTRU
TRU
1678 MMC
1662SMC
1670 SM
1670 SM
1670 SM
LO Shelf
LAN A
LAN B
Q3B to LAN A
Q3B to LAN B
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 33. General LAN Cabling for multirack configurations
ED
03
3AG 24163 BEAA PCZZA
531
76 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
9.4 Dispersion Compensation Unit (DCU)
This chapter describes the mechanical integration of up to four Dispersion Compensation Units (DCUs)
into both rack types (Main–/OED–Rack). In consequence of using V/U–64.2 boards the insertion of one
or two Dispersions Compensation Modules (DCMs) is required. Up to two DCMs can be housed per DCU
shelf (refer to Figure 34. ). The DCM is a pure passive component without any control functions. The Dispersion Compensation Module is designed for SMF operating in extended C–band. It is capable of compensating the dispersion of standard single mode fiber (SMF) over a wide wavelength range, from 1529nm
to 1569nm. For more details please refer to chapter 18.3.1.2 and 18.3.1.3.
The following tables show the several configuration possibilities in the Main and in the OED rack.
For more details about the concrete rack configurations with DCUs refer to the “Installation Handbook”.
Table 9. Main Rack Configurations with DCU
Main Rack
HMU
1678MCC
1670SM
1662SMC
# of DCU
1
1
1
0
1*
1
1
0
1
2
1
2
0
0
4
* Only by bottom access. No DCU is possible by top access .
Table 10. OED Rack Configurations with DCU
OED Rack
HMU
1670SM
1662SMX
LANs
# of DCU
1
1
1
0
2
1
0
2
2
4
1*
2
0
0
1*
* Only one HMU or one DCU is possible.
DCM
DCM
1AA 00014 0004 (9007) A4 – ALICE 04.10
Front cover
Figure 34. Dispersion Compensation Unit (DCU)
ED
03
3AG 24163 BEAA PCZZA
531
77 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
9.5 Housekeeping Monitoring Unit (HMU)
The HMU (refer to Figure 35. on page 78) is meant to be a collector and distributor for system internal and
housekeeping signals. The HMU can be used in all racks being equipped with a 1678MCC, a 1670SM or
a 1662SMC shelf.
All supported combinations of HMUs with other equipment inside main rack and OED rack are shown in
Figure 29. and Figure 31.
Regarding the 1678MCC, main purpose of the HMU is to make the converter alarms of the up to six step–
up converters located inside the NGTRU available to the system(s). Also the “Push Button” to reset system
alarm lamps and the customer access via a D–SUB connector to the GPI and GPO interfaces will be supported.
Regarding the 1670SM, only the “Push Button” will be used.
For the 1662SMC, beside the “Push Button” also the FAN alarms of the 1662SMC will be supported.
Reset push button
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 35. Housekeeping Monitoring Unit (HMU)
ED
03
3AG 24163 BEAA PCZZA
531
78 / 531
10 PHYSICAL CONFIGURATION OF THE MAIN SHELF
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
This chapter illustrates the physical structure, layout and composition, coding and partition of the main
shelf equipment.
The Equipment shelf front view is illustrated in Figure 36. on page 80 and Figure 37. on page 84.
The Main part codes and partition are listed in Table 14. on page 96.
The Accessory codes and partition are listed in Table 15. on page 100.
The Explanatory notes of part list are reported in Table 16. on page 101.
For the units front view refer to para. 10.3 on page 103.
These paragraphs illustrate the interconnection points that can be accessed on the units front panel and
the alarm/status LEDs together with the relevant legend and meaning.
Notes:
The Personal Computer (Craft Terminal) utilized for Initial Turn-on and Maintenance operations is
not listed as an item of the equipment, but it can be supplied by Alcatel–Lucent.
Refer to Operator’s Handbook for PC hardware configuration.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Table 14. on page 96 contains the units of current equipment release. Units belonging to previous
equipment releases/versions (e.g. for configuration updating) are not here listed but still supported,
if compatible with the current one (for eventual units belonging to previous equipment
releases/versions refer to the relevant Technical Handbook).
ED
03
3AG 24163 BEAA PCZZA
531
79 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
10.1 1678MCC Main Shelf (SR78)
The mechanical design of the 1678MCC is based on a 21” ETSI compatible shelf, consistent with the
1678MCC Rack equipment practice. This rack can house one 1678MCC shelf, or one 1678MCC shelf plus
an additional OED shelf.
The mechanical dimensions of the shelf (named SR78) is the following:
–
–
–
533 mm (Wide)
674 mm (High) or 684 mm (with dust filter)
294 mm (Deep)
The deep with cover is max. 300 mm.
The mechanical design provides EMI/EMC performances, in compliance with ETSI standard 300 386–1
“Telecommunication Center”.
The 1678MCC main shelf is a single row shelf (refer to Figure 36. ):
Subrack n
PSF
Traffic Ports
FLCCONGI
MATRIX* (Copy B)
Traffic Ports
MATRIX* (Copy A)
FLCSERV
PSF
FAN Unit
FAN Unit
Subrack n+1
Subrack n+2
21"−96TE
Matrix*:
MX160
MX320
MX640
Figure 36. 1678MCC Main Shelf Layout
The 1678MCC main shelf (SR78) has a symmetrical layout. There are no dedicated slots for expansions
towards other shelves.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The 1678MCC has got 16 port slots, each supporting up to 40 Gbit/s (256 STM–1 equivalent) throughput.
So the maximum throughput supportable by 1678MCC is 640 Gbit/s (4096 STM–1 equivalent).
The 16 port slots are provided by a 2.5 Gbit/s backpanel.
ED
03
3AG 24163 BEAA PCZZA
531
80 / 531
Three types of slots are distinguished:
•
Port slot (16 slots, each 4.5TE wide), containing any type of the following Traffic Port boards:
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
16 x STM–1/4 optical board
16 x STM–1 board
16 x STM–16 optical board
8 x STM–16 optical board
4 x STM–16 optical board
1 x STM–64 optical board
2 x STM–64 optical board
4 x STM–64 optical board
2 x STM–64 optical board
4 x STM–64 optical board
16 x GE Port board
8 x GE Port board
4 x GE Port board
2 x 10 Gigabit Ethernet Port
4 x 10 Gigabit Ethernet Port
Lower Order Matrix board 40G
Lower Order Matrix board 20G
Lower Order Matrix Link 40G
ISA–ES64 Server Board
(P16S1–4)
(P16S1S)
(P16S16)
(P8S16)
(P4S16)
(S64M)
(P2S64M)
(P4S64M)
(P2S64X)
(P4S64X)
(P16GE)
(P8GE)
(P4GE)
(P2XGE)
(P4XGE)
(LAX40)
(LAX20)
(LAC40)
(ES64SC)
The maximum quantity of each interface per shelf is:
•
•
•
•
•
•
•
Higher Order Matrix slot (2 slots, each 8TE wide), containing the following boards (1+1):
–
–
–
–
–
•
(MX640)
(MX640GA)
(MX320)
(MX320GA)
(MX160)
First Level Controller and
Service Interfaces
(FLCSERV)
First Level Controller and
Service Interfaces ANSI
(FLCSERVA)
First Level Controller and
Control&General Interfaces
(FLCCONGI)
–
Power Supply Filter (1+1)
(PSF)
–
Bus Termination (two boards)
(BUSTERM)
–
–
1AA 00014 0004 (9007) A4 – ALICE 04.10
640 Gbit/s Matrix board
640 Gbit/s Matrix board ANSI
320 Gbit/s Matrix board
320 Gbit/s Matrix board ANSI
160 Gbit/s Matrix board
Control and Common parts slot (2 slots, each 4TE wide), containing the following boards:
–
ED
256 x STM–1 optical interfaces
256 x STM–4 optical interfaces
256 x STM–16 optical interfaces
64 x STM–64 optical interfaces
256 x GE optical interfaces
64 x 10GE optical interfaces
03
3AG 24163 BEAA PCZZA
531
81 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Note:
FLC, PSF and BUSTERM are located in the same slot. This slot is divided into three subslots (refer
to Figure 37. on page 84). The BUSTERM board is not visible on the shelf front panel. It is positioned
behind the FLC board.
The FAN Subsystem consists of two subracks and contains the following boards:
–
FANs unit
(FAN)
The FLCSERVICE supports the following functionalities:
•
•
•
•
•
•
•
Flash Memory device
First Level Controller spare
connectors for Auxiliary AUX/EOW Channels (not supported by the software)
External Synchronization Interface
Q3 and F interfaces
phone jack and phone expansion
DCC
The FLCCONGI supports the following functionalities:
•
•
•
•
•
Flash Memory device
First Level Controller main
External connectors for Housekeeping, Remote Alarms, Rack Alarms
Q3 and F interfaces
DCC
The Matrix boards supports the following functionalities:
•
•
•
•
Cross–connection
Synchronization (CRU)
Shelf Controller
1+1 EPS protection scheme, when two Matrix boards are present
The Power Supply Filter board (PSF) supports the following functionality:
•
distribution of Power Supply after filtering process
The Bus Termination board (BUSTERM) supports the following functionality:
•
electrical termination to the buses routed on the backplane
These two boards are not visible on shelf front–panel. They are two small board included in the shelf
and one BUSTERM is placed behind the FLCSERV board and the other BUSTERM is placed behind
the FLCCONGI board.
The FAN unit (FAN) supports the following functionality:
1AA 00014 0004 (9007) A4 – ALICE 04.10
•
cooling of the equipment
Due to the high level of integration reached with this equipment, the two FAN units located at the top
and at the bottom of the shelf have always to be equipped.
The two FAN units are physically integrated in the 1678MCC shelf, without the need of external
connection cables.
Note:
The slots which are not equipped have to be closed by a dummy plate for EMC reasons.
ED
03
3AG 24163 BEAA PCZZA
531
82 / 531
10.1.1 Equipment Front View
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The 1678MCC equipment has a symmetrical layout (refer to Figure 37. on page 84).
The following types of slots are distinguished:
•
slot 1
•
slots 2 ÷ 9 and
slots 12 ÷ 19 :
:
First Level Controller “spare” + Service Interfaces board
(FLCSERV, FLCSERVA)
Traffic Port boards, ES64 data board, Lower Order Adaptation/Matrix and
Lower Order Matrix Link 40G
•
slot 10 and 11 :
High Order Matrix (A and B) boards
(MX640, MX640GA, MX320, MX320GA, MX160)
•
slot 20
First Level Controller “main” + Control&General Interfaces board
(FLCCONGI)
•
slot 21 and 22 :
Bus Termination boards
(BUSTERM)
•
slot 24 and 25 :
Power Supply and Filter boards
(PSF)
:
Note:
Slot 21 and slot 22 are positioned behind slot 1 and slot 20 respectively, so the BUSTERM
boards are not visible on the shelf front panel.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The two FANs have no slot number, because they are modelled as separate subracks (subrack n and n+2).
ED
03
3AG 24163 BEAA PCZZA
531
83 / 531
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
FAN (Subrack n)
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
24
1
2
3
4
5
6
7
8
ÄÄÄÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄ
ÄÄÄÄ
ÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄÄ
ÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄ
ÄÄÄÄ
ÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄÄ
ÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄÄ
ÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄÄ
ÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄÄ
ÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄÄ
ÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄ
ÄÄÄÄ
ÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄÄÄÄÄ
9
21
25
20
12 13 14 15 16 17 18 19
10
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
11
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
22
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
1AA 00014 0004 (9007) A4 – ALICE 04.10
FAN (Subrack n+2)
Figure 37. 1678MCC Equipment front view (slot position)
ED
03
3AG 24163 BEAA PCZZA
531
84 / 531
10.1.2 Configuration Rules
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
10.1.2.1 Capacity Count in HO Matrix
From R3.2 (SKY20–01G) onwards the following handling on I/O boards with pluggable modules is
implemented:
The HO matrix capacity is counted on configured port level (not on board level), while cards without
direct interfaces (e.g. LAX20/40) are not counted. But all LO shelf LAC40 ports are taken in account!
10.1.2.2 Restrictions
There are the following two restrictions in term of matrix size and power consumption:
Please note, that the number of configurable modules (e.g. on 16xSTM–16 boards)
depends on your matrix size! The matrix size defines the max. number of modules. There
are restrictions in case of smaller matrix size:
–
–
MX320 = 2048 STM–1 equ.
MX160 = 1024 STM–1 equ.
Note:
Refer to the CT Operator’s Handbook chapter ’Create, modify or delete modules of an I/O board’ for
the detailed procedure.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The max. number of boards is limited because of the power consumption of around
140 W per board. The maximum shelf load (of around 1.5 kW for the sum of all 16 I/O slots)
mustn’t be violated.
ED
03
3AG 24163 BEAA PCZZA
531
85 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
10.1.2.3 Allowed or basic Equipment Configuration
Table 11. on page 86 presents for each slot, the allowed equipment types and the basic equipment type
(the acronyms of the units are shown).
Table 11. describes the configuration for allowed and basic boards in the 1678MCC main shelf.
Table 12. describes the configuration of the Pluggable Modules in the STM–64, STM–16, STM–1/4 and
the GE boards front panels allowed for 1678MCC main shelf.
Table 11. 1678MCC Equipment: slot configuration
1678MCC shelf
Slots
Basic Configuration
Allowed Equipment
1
FLCSERV/FLCSERVA
––
1
SDH High Speed ports:
P4S64M
P2S64M
P4S64X
P2S64X
S64M
P16S16
P8S16
2
2÷9
and
12 ÷ 19
P4S16
P16S1S4
P16S1S
P16GE
P8GE
P4GE
P2XGE
P4XGE
no basic configuration
Layer 2 Switch 20G board:
ES64SC
LO Matrix boards:
LAX40
LAX20
1AA 00014 0004 (9007) A4 – ALICE 04.10
note
14
3
LO Matrix Link 40G boards:
LAC40
––
13
4
10
MX640, MX640GA,
MX320, MX320GA, MX160
(main)
11
MX640, MX640GA,
MX320, MX320GA, MX160
(spare)
––
4
20
FLCCONGI
––
5
21, 22
BUSTERM
––
6
24, 25
PSF
––
7
subrack n, n+2
FAN
––
8
Refer to explanatory notes on Table 13. on page 88.
ED
03
3AG 24163 BEAA PCZZA
531
86 / 531
Figure 38. on page 90 and Figure 39. on page 91 shows the supported basic boards and allowed I/O and
LO matrix boards and the STM–N optical/electrical modules managed in the 1678MCC main shelf.
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Table 12. Pluggable Optical and Electrical Modules
Slot
Allowed Equipment
note
P16S1S board
J1 ÷ J16
STM–1 electrical module:
SES1
9
STM–N optical modules:
SS11
SL11
SL12
9
J1 ÷ J16
P16S1S4 board
J1 ÷ J16
STM–1 electrical module:
SES1
9
STM–N optical modules:
SS11
SL11
SL12
SS41
SL41
SL42
9
J1 ÷ J16
P4S16, P8S16, P16S16
J1 ÷ J4
J1 ÷ J8
J1 ÷ J16
STM–N optical modules:
STM–N colored modules:
SI161
SS161
SL161
SL162
CWP (1470 – 1610 nm)
CWA (1470 – 1610 nm)
DWA (CH 620 – CH 170)
10
LAC40 boards
J1 ÷ J16
STM–N optical modules:
SI161
10
P4GE, P8GE, P16GE boards
J1 ÷ J4...16
Optical modules:
SGESX
SGELX
SGEZX
10
P2S64X, P4S64X boards
J1 ÷ J2
J1 ÷ J4
STM–N optical modules:
XS642E
XS642B
XI641
XP1L12D2
11
P2XGE, P4XGE boards
1AA 00014 0004 (9007) A4 – ALICE 04.10
J1 ÷ J16
STM–N optical modules:
XGES
XS642B
XI641
12
Refer to explanatory notes on Table 13. on page 88.
ED
03
3AG 24163 BEAA PCZZA
531
87 / 531
Table 13. 1678MCC Equipment: slot configuration explanation notes
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Note Explanation
1
1AA 00014 0004 (9007) A4 – ALICE 04.10
2
ED
It is 4TE.
It is dedicated to First Level Controller ”spare” function and Service interfaces.
Equipment Controller 1+1 EPS protection scheme is supported. When this board is “active”
manages the F interface.
All these boards are 4.5TE.
For S64M: This port board can combine with different non exchangeable MSA modules.
The following board types result from this:
–
1 x S–64.2 Port (S–64.2M)
–
1 x L–64.2 Port (L–64.2M)
–
1 x I–64.1 Port (I–64.1M)
–
1 x V–64.2 Port (V–64.2M)
–
1 x U–64.2 Port (U–64.2M)
For P2S64M: This port board can combine with different non exchangeable MSA modules.
The following board types result from this:
–
2 x S64.2 Port (P2S64M)
–
2 x I64.1 Port (P2I64M)
For P4S64M: This port board can combine with different non exchangeable MSA modules.
The following board types result from this:
–
4 x S64.2 Port (P4S64)
–
4 x I64.1 Port (P4I64)
For P2S64X/P4S64X: This port boards can combine with different pluggable XFP/XFP–E
modules. The following XFP/XFP–E modules are supported:
–
OPTO TRX XFP S–64.2B Ext.
–
OPTO TRX S–64.2B XFP
–
OPTO TRX I–64.1 XFP –5/70C
–
OPTO TRX XFP P1L1–2D2 (80 km)
For P16S16: up to sixteen Short, Long Haul and colored STM–16 standard ITU–T optical
interfaces are provided.
For P8S16: up to eight Short, Long Haul and colored STM–16 standard ITU–T optical interfaces are provided.
For P4S16: up to four Short, Long Haul and colored STM–16 standard ITU–T optical interfaces are provided.
For P16S1S4: up to sixteen electrical STM–1 and/or optical STM–1 and/or STM–4 standard ITU–T interfaces are provided.
For P16S1S: up to sixteen optical STM–1 and/or electrical STM–1 standard ITU–T interfaces are provided.
For P4/8/16GE: up to four/eight/sixteen Gb Ethernet SFP modules are provided.
For P2XGE/P4XGE: up to four of the following modules are provided per board:
–
OPTO TRX 10G BASE–S
–
OPTO TRX S–64.2B XFP
–
OPTO TRX I–64.1 XFP –5/70C
3
It is 4.5TE. Both boards provide to 1+1 EPS protection scheme (mandatory).
LAX A and LAX B have to be located as pair in the following slot numbers:
slot#2 and #3 or slot#4 and#5 and so on until slot#18 and #19.
4
It is 8TE. Both boards provide to 1+1 EPS protection scheme (mandatory).
5
It is 4TE.
It is dedicated to First Level Controller “main” function and Control&General interfaces.
First Level Controller 1+1 EPS protection scheme is supported. When this board is “active”
manages the F interface.
03
3AG 24163 BEAA PCZZA
531
88 / 531
Note Explanation
7
These two small boards are located behind FLCSERV and FLCCONGI boards.
They are not visible on the front view.
They are both mandatory.
8
They are both mandatory, one under and one above the shelf.
9
Up to sixteen optical/electrical SFP modules can be plugged in the P16S1S4 and P16S1S
port board. A mix of different modules is allowed. In case of P16S1S4 a mix of STM–1e/o
and STM–4 is only allowed in groups of four.
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
6
10
11
12
13
1AA 00014 0004 (9007) A4 – ALICE 04.10
14
ED
Each optical SFP module can be plugged in anyone of the up to sixteen front panel slots of
the relevant port boards.
Each optical XFP/XFP–E module can be plugged in anyone of the up to four front panel
slots of the relevant port boards. A mix of different modules is allowed.
Each optical XFP module can be plugged in anyone of the up to four front panel slots of the
relevant port boards. A mix of different modules is allowed.
This board is used to connect the 1678MCC main shelf with the LO extension shelf.
Max. 5 (4+1) LAC40 boards are necessary to connect a fully equipped 160G LO extension
shelf. The board can be equipped with up to sixteen SI161 SFP modules.
This board is used to support Layer 2 switch functionality.
03
3AG 24163 BEAA PCZZA
531
89 / 531
Main Shelf: Supported I/O boards
Port boards
I/O Interfaces
Connectors
1 slot
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1
4xSTM–64 MSA PORT
4xSTM–64
2
SC/PC
S64.2b
3
I–64.1
no mix possible,
modules not pluggable
(FC/PC)
P4S64
.
4
P4I64
1 slot
2xSTM–64 MSA PORT
2xSTM–64
1
S–64.2b
SC/PC
I–64.1
no mix possible,
modules not pluggable
2
P2S64M
.
(FC/PC)
P2I64M
1
4xSTM–64 XFP PORT
XFP(–E)
1 slot
4xSTM–64
2
S64.2b
XFP(–E)
I–64.1
LC
3
XFP(–E)
P1L1–2D2
4
any mix of XFP/XFP–E modules
possible; modules are pluggable
XFP(–E)
P4S64X
1 slot
2xSTM–64
2xSTM–64
2xSTM–64 XFP PORT
1
S–64.2b
XFP(–E)
LC
I–64.1
P1L1–2D2
2
XFP(–E)
any mix of XFP/XFP–E modules
possible; modules are pluggable
P2S64X
1 slot
1xSTM–64
1xSTM–64
S–64.2b
1
L–64.2b
S–64.2M
L–64.2M
I–64.1M
I–64.1
SC/PC
(FC/PC)
1 slot
1xSTM–64
1xSTM–64
refere to
Figure 51.
on page 113
external part
V–64.2
DCU
U–64.2
1
V–64.2M
U–64.2M
1 slot
(4/8)16xSTM–16
1
I–16.1
S–16.1
L–16.1
L–16.2
CWP
CWA
DWA
2
.
.
(4/8)16
SFP
SFP
. (4/8)16xSTM–16
.
(P4S16)
SFP
LC
(P8S16)
P16S16
any mix of SFP modules allowed
1 slot
1
LAC40
2
I–16.1
.
.
SFP
SFP
.
.
16xSTM–16
LC
16
1AA 00014 0004 (9007) A4 – ALICE 04.10
SFP
LAC40
* only on customer request
Figure 38. Main Shelf: Supported I/O boards – Part 1
ED
03
3AG 24163 BEAA PCZZA
531
90 / 531
Main Shelf: Supported I/O boards (continuation)
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
I/O Interfaces
Port boards
Connectors
1 slot
1
16xSTM–1/4
2
S–4.1, L–4.1, L–4.2
S–1.1, L–1.1, L–1.2, SES1
a mix of SFP modules allowed,
but only in groups of four
.
.
SFP
SFP
.
.
16xSTM–1/4
LC
16
SFP
P16S1S4
1 slot
1
16xSTM–1
2
S–1.1, L–1.1, L–1.2, SES1
a mix of SFP modules allowed,
but only in groups of four
.
.
16
SFP
SFP
.
.
16xSTM–1
SFP
P16S1S
LC
1 slot
1
(4/8)16xGE
2
SGELX
SGESX
SGEZX
any mix of SFP modules allowed
.
.
SFP
SFP
.
.
(4/8)16
SFP
(4/8)16xGE
LC
(P4GE)
(P8GE)
P16GE
1 slot
2x10GE XFP PORT
10G BASE–S
1
2
S–64.2b (10G BASE–E)
XFP
XFP
2x10GE
LC
I–64.1 (10G BASE–L)
P2XGE
1
4x10GE XFP PORT
10G BASE–S
S–64.2b (10G BASE–E)
1 slot
XFP
2
XFP
3
XFP
I–64.1 (10G BASE–L)
4x10GE
LC
4
XFP
P4XGE
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 39. Main Shelf: Supported I/O boards – Part 2
ED
03
3AG 24163 BEAA PCZZA
531
91 / 531
10.1.2.4 Examples of Equipment Configuration
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The figures on next pages show some examples of allowed equipment configuration.
Figure 40. on page 93 shows the typical basic configuration of 1678MCC main shelf (without Traffic Port
boards):
•
•
•
•
•
•
•
•
•
slot 1
: FLCSERV / FLCSERVA board
slot 2 ÷ 9
: reserved to traffic port boards, ES64 and LO matrix
slot 10 and slot 11 : two MX(160/320/320GA/640/640GA) boards
slot 12 ÷ 19
: reserved to traffic port boards, ES64 and LO matrix
slot 20
: FLCCONGI board (CT interface)
slot 21 and slot 22 : two BUSTERM boards (small board)
slot 24 and slot 25 : two PSF boards
two FAN units (subrack n, n+2)
dummy plates for all other slots unequipped
Figure 41. on page 94 shows an example of the following configuration:
1AA 00014 0004 (9007) A4 – ALICE 04.10
•
•
•
•
•
•
•
•
•
ED
basic configuration
slot 2 ÷ 5
: four 16 x STM–16 boards
slot 7 and slot 8
: two 1 x STM–64 boards (short haul)
slot 9
: a 4 x STM–64 board (short haul)
slot 12 and slot 13 : two 16 x STM–1/4 boards
slot 14
: a 4 x STM–64 board (short haul)
slot 15 and slot 16 : two 2 x STM–64 boards (short haul)
slot 18
: a 4 x STM–64 board (intraoffice)
dummy plates for all other slots unequipped
03
3AG 24163 BEAA PCZZA
531
92 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1AA 00014 0004 (9007) A4 – ALICE 04.10
ED
03
24
FLCSERVICE
1
21
BUSTERM
PSF
2
3
4
5
6
7
8
9
FAN (subrack n)
11
Matrix Copy B
10
FAN (subrack n+2)
12 13 14 15 16 17 18 19
3AG 24163 BEAA PCZZA
531
Figure 40. Basic configuration of 1678MCC Main Shelf
Matrix Copy A
PSF
25
FLCCONGI
20
22
BUSTERM
93 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1AA 00014 0004 (9007) A4 – ALICE 04.10
ED
03
PSF
2
3
4
5
6 7
dummy plate
S642M
8
S642M
P4S64
11
Matrix Copy B
10
Matrix Copy A
12 13 14 15 16 17 18 19
P16S1–4
P16S1–4
PSF
25
20
22
BUSTERM
FAN (subrack n)
9
FAN (subrack n+2)
3AG 24163 BEAA PCZZA
531
Figure 41. Allowed Equipment Configuration (Example)
P16S16
P16S16
P16S16
P16S16
P4S64
P2S64
P2S64
dummy plate
P4I64
dummy plate
FLCCONGI
24
FLCSERVICE
1
21
BUSTERM
94 / 531
10.2 Part List
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The Part List is subdivided in three tables, specifically:
•
in Table 14. on page 96 is shown the Main part list
•
in Table 15. on page 100 is shown the Accessory list
•
in Table 16. on page 101 is shown the Explanatory notes of previous lists
Furthermore, for any item the position and the maximum quantity that can be allocated inside the
equipment are indicated too.
Such tables report the following information:
ED
•
Description: name of items
•
Acronym: it is used to identified units and modules on the Craft Terminal applications
•
ANV Part/Number
•
Max Q.ty: maximum quantity of items in the 1678MCC equipment
•
Slot: position of the units inside the 1678MCC equipment (refer to Figure 37. on page 84)
•
Notes: are listed a set of explanatory notes.
03
3AG 24163 BEAA PCZZA
531
95 / 531
Table 14. Main parts list
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
DESCRIPTION
ACRONYM
ANV P/N
Max.
Q.ty
SLOT
NOTE
1
––
1
1
––
1
––
28
2
24, 25
3
MECHANICAL STRUCTURE
MCC RACK WITH NGTRU
––
1678MCC SHELF
SR78
HOUSEKEEPING MONITORING UNIT
HMU
3AL 81673 AA––
3AL 81673 AB––
3AL 81224 AA––
3AL 81224 AB––
3AG 24234 AA––
2
29
POWER SUPPLY
POWER SUPPLY AND FILTERS
PSF
3AL 81502 AA––
COMMON PARTS (CONTROLLER)
FLCCONGI ENH.
FLCCONGI
3AG 24102 AA––
FLCCONGI ENH. (max DCC–M)
FLCCONGI
3AG 24102 AB––
FLCSERVICE ENH.
FLCSERV
3AG 24103 AA––
FLCSERVICE ENH. (max DCC–M)
FLCSERV
3AG 24103 AB––
FLCSERVICE ENH. ANSI
FLCSERVA
3AG 24332 AB––
20
1
4
1
SWITCHING MATRIX
MATRIX 640 GBIT/S
MATRIX 640 GBIT/S ANSI
MATRIX 320 GBIT/S
MATRIX 320 GBIT/S ANSI
MATRIX 160 GBIT/S
LOWER ORDER ADAPTATION/MATRIX
40G
LOWER ORDER ADAPTATION/MATRIX
20G
Lower Order Matrix Link 40G
MX640
3AL 81429 AA––
MX640GA
3AG24334 AA––
MX320
3AG 24173 AA––
MX320GA
3AG 24336 AA––
MX160
3AG 24174 AA––
LAX40
3AG 24104 AA––
LAX20
LAC40
3AG 24186 AA––
3AG 24186 AB––
3AG 24327 AA––
10, 11
5
2
2÷9
and
12 ÷ 19
5
6
35
SPARE PARTS
TERMINATION BUS
1AA 00014 0004 (9007) A4 – ALICE 04.10
SFP EXTRACTOR
ED
BUSTERM
––
3AL 81209 AA––
3AL 81209 AB––
3AL 81728 AA––
2
1
––
7
8
03
3AG 24163 BEAA PCZZA
531
96 / 531
DESCRIPTION
ACRONYM
ANV P/N
Max.
Q.ty
SLOT
NOTE
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
TRAFFIC PORTS
16xSTM–1 PORT /SFP (OC–3)
P16S1S
3AG 24183 AA––
9
16xSTM–1/4 PORT /SFP (OC–3/OC–12)
10
P16S1S4
3AL 89540 AA––
16xSTM–16 PORT /SFP (OC–48)
P16S16
3AL 81295 AA––
8xSTM–16 PORT /SFP (OC–48)
P8S16
3AG 24175 AA––
4xSTM–16 PORT /SFP (OC–48)
P4S16
3AG 24176 AA––
4xSTM–64 I–64.1 PORT FC/PC (OC–192)
P4I64
4xSTM–64 S–64.2 PORT FC/PC (OC–192)
P4S64
4xSTM–64 XFP PORT (OC–192)
P4S64X
2xSTM–64 I–64.1 PORT FC/PC (OC–192)
P2I64M
2xSTM–64 S–64.2 PORT FC/PC (OC–192)
P2S64M
2xSTM–64 XFP PORT (OC–192)
P2S64X
1xSTM–64 V–64.2 PORT FC/MU (OC–192)
V–642M
1xSTM–64 U–64.2 PORT FC/PC (OC–192)
U–642M
1xSTM–64 I–64.1 PORT FC/PC (OC–192)
I–641M
1xSTM–64 S–64.2 PORT FC/PC (OC–192)
S–642M
1xSTM–64 L–64.2 PORT FC/PC (OC–192)
L–642M
3AL 81292 AA––
3AL 81292 AB––
3AL 81692 AE––
3AL 81692 AF––
3AG 24161 AA––
3AG 24161 AB––
3AG 24177 AA––
3AG 24177 AB––
3AL 81692 AC––
3AL 81692 AD––
3AL 24214 AA––
3AL 24214 BA––
3AL 89997 AA––
16xGE/FC PORT
P16GEFC
3AL 89996 AA––
3AL 89996 AB––
3AG 24179 AA––
3AG 24179 AB––
3AL 81692 AA––
3AL 81692 AB––
3AL 89995 AA––
3AL 89995 AB––
3AL 81904 AA––
8xGE/FC PORT
P8GEFC
3AG 24181 AB––
4xGE/FC PORT
P4GEFC
3AG 24182 AB––
2x10GE XFP PORT
P2XGE
3AG 24476 AA––
4x10GE XFP PORT
P4XGE
3AG 24339 AA––
11
16
2÷9
and
12 ÷ 19
––
16
2÷9
and
12 ÷ 19
––
2÷9
and
12 ÷ 19
40
––
DATA APPLICATION
1AA 00014 0004 (9007) A4 – ALICE 04.10
ISA–ES PACKET AGGREGATOR 20G
(SERVER CARD)
ED
ES64SC
3AG 24371 AA––
2
03
3AG 24163 BEAA PCZZA
531
97 / 531
DESCRIPTION
ACRONYM
ANV P/N
Max.
Q.ty
SLOT
NOTE
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
STM–N ELECTRICAL/OPTICAL MODULES
OPTO TRX SFP STM–1EL PLUG–IN
OPTO TRX SFP S–1.1 PLUG–IN
OPTO TRX SFP S–1.1 DDM PLUG–IN
OPTO TRX SFP L–1.1 PLUG–IN
OPTO TRX SFP L–1.1 DDM PLUG–IN
OPTO TRX SFP L–1.2 PLUG–IN
OPTO TRX SFP L–1.2 DDM PLUG–IN
OPTO TRX SFP S–4.1 PLUG–IN
OPTO TRX SFP S–4.1 DDM PLUG–IN
OPTO TRX SFP L–4.1 PLUG–IN
OPTO TRX SFP L–4.1 DDM PLUG–IN
OPTO TRX SFP L–4.2 PLUG–IN
OPTO TRX SFP L–4.2 DDM PLUG–IN
OPTO TRX SFP S–16.1 PLUG–IN
OPTO TRX SFP S–16.1 PLUG–IN
OPTO TRX SFP S–16.1 DDM PLUG–IN
OPTO TRX SFP L–16.1 PLUG–IN
OPTO TRX SFP L–16.1 DDM PLUG–IN
OPTO TRX SFP L–16.2 PLUG–IN
1AA 00014 0004 (9007) A4 – ALICE 04.10
OPTO TRX SFP L–16.2 DDM PLUG–IN
SES1
SS–1.1
SL–1.1
SL–1.2
SS–4.1
SL–4.1
SL–4.2
SI–16.1
SS–16.1
SL–16.1
SL–16.2
1AB 21017 0001
1AB 19467 0001
1AB 19467 0004
1AB 19467 0002
1AB 19467 0005
1AB 19467 0003
1AB 19467 0006
1AB 19636 0001
1AB 19636 0004
1AB 19636 0003
1AB 19636 0006
256
––
256
––
12
1AB 19636 0002
1AB 19636 0007
1AB 19637 0013
1AB 19637 0001
1AB 19637 0006
1AB 19637 0004
1AB 19637 0008
1AB 19637 0003
1AB 19637 0009
Opto Transc. Module 1470nm
CWP
1AB 19634 0001
Opto Transc. Module 1490nm
CWP
1AB 19634 0002
Opto Transc. Module 1510nm
CWP
1AB 19634 0003
Opto Transc. Module 1530nm
CWP
1AB 19634 0004
Opto Transc. Module 1550nm
CWP
1AB 19634 0005
Opto Transc. Module 1570nm
CWP
1AB 19634 0006
Opto Transc. Module 1590nm
CWP
1AB 19634 0007
Opto Transc. Module 1610nm
CWP
1AB 19634 0008
Opto Tr. Module 1470nm APD
CWA
1AB 19635 0001
Opto Tr. Module 1490nm APD
CWA
1AB 19635 0002
Opto Tr. Module 1510nm APD
CWA
1AB 19635 0003
Opto Tr. Module 1530nm APD
CWA
1AB 19635 0004
Opto Tr. Module 1550nm APD
CWA
1AB 19635 0005
Opto Tr. Module 1570nm APD
CWA
1AB 19635 0006
Opto Tr. Module 1590nm APD
CWA
1AB 19635 0007
Opto Tr. Module 1610nm APD
CWA
1AB 19635 0008
ED
12, 27
12
03
3AG 24163 BEAA PCZZA
531
98 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
DESCRIPTION
Opto TRX SFP DWDM CH620...CH170
OPTO TRX 1.25 GBE SFP–LX
OPTO TRX 1.25 GBE SFP–LX DDM
OPTO TRX 1.25 GBE SFP–SX
OPTO TRX 1.25 GBE SFP–SX DDM
OPTO TRX 1.25 GBE SFP–ZX DDM
ANV P/N
DWA
1AB 23141 0001
to
1AB 23141 0046
SGELX
SGESX
1AB 18728 0031
XGES
1AB 21454 0002
OPTO TRX I–64.1 XFP
XI641
OPTO TRX XFP S–64.2B EXT
XS642E
ED
XP1L12D2
NOTE
37
256
––
12
1AB 18728 0033
OPTO TRX XFP 10GBASE–S
XS642B
SLOT
1AB 18728 0002
1AB 18728 0042
OPTO TRX S–64.2B XFP
Max.
Q.ty
1AB 18728 0001
SGEZX
OPTO TRX XFP P1L1–2D2
1AA 00014 0004 (9007) A4 – ALICE 04.10
ACRONYM
3AG 24273 AA––
1AB 21454 0001
3AG 24274 AA––
1AB 21728 0001
3AL 81887 AA––
24
64
36
––
26
3AG 24488 AA––
1AB 21728 0002
03
3AG 24163 BEAA PCZZA
531
99 / 531
Table 15. Accessories list
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
DESCRIPTION
ACRONYM
Max.
Q.ty
SLOT
SOFTWARE
NOTE
13
EQUIPMENT ACCESSORIES
1678MCC FAN UNIT
FAN
3AL 81205 AA––
3AL 81205 AB––
14
2
34
1678MCC DUST FILTER UNIT
––
3AG 24350 AA––
1
31
1678MCC DUST FILTER
––
3AG 24354 AA––
1
32
1678MCC INSTALLATION KIT
––
3AL 89584 AA––
1
15
1678MCC INSTALLATION KIT
––
3AG 24367 AA––
1
30
DUMMY PLATE W=22.5 mm
––
3AN 52174 AA––
16
16
2 MB/S AUX CHANNEL 75 Ω KIT
––
3AL 38432 AA––
1
2 MB/S AUX CHANNEL 120 Ω KIT
––
3AL 38433 AA––
1
SDH SYNC ADAPTER 75 Ω UNBAL KIT
––
3AL 89586 AA––
1
––
SDH SYNC ADAPTER 120 Ω BAL KIT
––
3AL 89587 AA––
1
––
CRAFT TERMINAL CABLE KIT
––
3AL 89585 AA––
1
17
NGTRU
3AL 81656 AA––
1
33
––
3AN 51536 AA––
4
18
STPUP
NGBYP
3AL 89590 AA––
3AL 38414 AA––
6
6
19
21
FAN UNIT PROTECTION
––
3AL94613 AA––
1
14
SFP DUMMY PLUG KIT
INSTALLATION KIT NGTRU
ESD KIT
EARTHQUAKE KIT
ACCESSORY KIT 1678MCC
XFPE DUMMY PLUG
LOW LOSS SMF C + BAND DCM 40 km –
MU
LOW LOSS SMF C + BAND DCM 80 km –
MU
KIT DCU TRAY 1678MCC RACK
––
––
––
––
––
––
3AL89857 AA––
3AL 38423 AA––
3AL 37973 AA––
3AL 91637 AA––
3AG 24268 AA––
3AL 24271 AA––
16
1
1
1
1
20
––
22
23
––
24
––
1AB 21083 0008
NGTRU
NGTRU DUMMY COVER
DC/DC CONVERTER STEP–UP 2000 W
NGTRU BYPASS
LAN SWITCH LS–DC
INSTALLATION KIT LAN SWITCH
1AA 00014 0004 (9007) A4 – ALICE 04.10
ANV P/N
ED
––
––
––
––
25
––
1AB 21083 0012
––
3AL 91853 AA––
LS–DC
––
3AL 74705 AA––
3AL 74705 AB––
3AG 24223 AA––
––
2
––
38
2
––
39
03
3AG 24163 BEAA PCZZA
531
100 / 531
Table 16. Parts list: explanatory notes
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Note Explanation
ED
1
This item contains the NGTRU equipment (without converters and dummy covers) and the
complete set of parts of the rack to host 1678MCC equipment.
2
It is the equipment shelf.
3
These items are mandatory and they are provisioned in 1+1 configuration: the boards perform
the filtering and the distribution of the power supply for the 1678MCC equipment.
4
The two boards are used in an 1+1 protected FLC configuration (master and slave): one is the
FLC active and the other is the FLC in stand–by to perform the equipment controller functionalities.
5
Two MX boards are used in an 1+1 protected EPS configuration: the boards perform connection and cross–connection functionalities and moreover synchronization functionalities.
6
The both LAX boards have to be located as pair in the following slot numbers:
slot#2 and #3 or slot#4 and#5 and so on until slot#18 and #19.
7
This is a spare part item; the 1678MCC shelf (SR78) already included it.
8
This is a spare part item; the 1678MCC shelf (SR78) already included it. It is necessary for
STM–N Optical Module extraction.
9
It provides to process up to sixteen STM–1 electrical and optical SFP modules: Any mix of
different SFP modules is possible.
10
It provides to process up to sixteen STM–1e/o and/or STM–4 SFP modules: a mix of different
SFP modules is possible, but only in groups of four.
11
It provides to process up to sixteen STM–16 SFP modules: Any mix of different SFP modules
is possible.
12
Up to 16 of these modules are hosted in PORT board.
13
Details concerning the software P/N are given in the Operator’s Handbook.
14
These items are mandatory. Maintenance intervals are described in the ’Maintenance Handbook’.
15
It contains the cables and all the accessories (connectors, caps, screws, etc.) concerning
Power Supply and Auxiliary systems (except Sync. and 2 Mbit/s Aux. systems).
16
It is essential to insert the relevant dummy plates on the space left by all Traffic Port boards
NOT supplied, in order to obtain the EMI/EMC performances.
17
It contains the cable to connect the Craft Terminal to the “Active” Equipment Controller
(FLCCONGI or FLCSERV boards). Its length is 3 m.
18
It is essential to insert the relevant dummy covers on the space left by all DC/DC Step–up
Converters (or NGTRU Bypass) NOT supplied in the NGTRU equipment, in order to obtain
the EMI/EMC performances.
19
These items are hosted in the NGTRU equipment in 1+1 configuration to supply the
1678MCC equipment.
20
It contains the SFP dummy plugs to insert into the free cavities of P16S16 and P16S1–4
boards.
21
When this item is used in alternative to the DC/DC Step–up Converter, only 8 Traffic Ports are
provisional in the 1678MCC equipment (four into slots 2 ÷ 9 and four into slots 12 ÷ 19).
22
Part of MCC rack
03
3AG 24163 BEAA PCZZA
531
101 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Note Explanation
ED
23
If earthquake proof is required.
24
One per unplugged XFP–E module necessary.
25
Dispersion Compensation Module for STM–64 (U–64.2 and V–64.2); refer also Figure 51.
Two DCMs can be mounted in one Dispersion Compensation Unit (DCU).
26
Up to 4 of these modules are hosted in PORT board. Any mix of different XFP modules is possible.
27
Electrical SFP modules have to be inserted in the leftmost and rightmost board of the shelf
(slot 2 or slot 19)!
28
Only necessary in case of supported feature: Station Alarms
29
Shelf supports FANs with dust filter.
30
Installation Kit 1678MCC for ANSI market.
31
Dust filter support.
32
The Kit includes three dust filter.
33
This is a spare part item; the 1678MCC rack already included it.
34
Version for ANSI market.
35
Link board for the connection of the LO extension shelf. In case of a full equipped 160G LO
extension shelf 5 (4+1) LAC40 are necessary.
36
Number of modules depends on number of used boards.
37
Up to 16 of these modules are hosted in PORT board.
1AB 23141 0003 is CH600, 1AB 23141 0004 is CH590 and so on up to 1AB 23141 0043 is
CH200
38
LAN switches are necessary for multirack configurations.
39
One Kit per LAN switch.
40
Always 1:1 protected. One working and one protecting board.
03
3AG 24163 BEAA PCZZA
531
102 / 531
10.3 Units Front View
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
This paragraph shows the access points (LEDs, switches etc.) present on each units together with legend
and meaning.
Figure 44. on page 106 through Figure 62. on page 123 illustrate units front view available in the 1678MCC
Equipment.
Figure 63. on page 124 to Figure 66. on page 125 show the pluggable modules available in the 1678MCC
Equipment.
Note: The unit dimensions in all figures are not the real ones.
ED
03
3AG 24163 BEAA PCZZA
531
103 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
SLOTS
P4S16
2 to 9 and 12 to 19
P4GE
2 to 9 and 12 to 19
(2)
(3)
(4)
(5)
LEGENDA:
(1) Bicolor LED:
Red – local unit alarm
Green – in service unit
1AA 00014 0004 (9007) A4 – ALICE 04.10
(2)to (5) STM–16 optical channel
(from ch. #1 to ch. #4)
(1)
Note: the cavities must be equipped with up to four STM–16 or GE optical SFP module plug–in (refer to
Figure 63. on page 124); in the free cavities must be inserted the relevant SFP dummy plugs.
Figure 42. 4xGE, 4xSTM–16 optical port board – front view
ED
03
3AG 24163 BEAA PCZZA
531
104 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
SLOTS
P8S16
2 to 9 and 12 to 19
P8GE
2 to 9 and 12 to 19
(2)
(3)
(8)
(9)
LEGENDA:
(1) Bicolor LED:
Red – local unit alarm
Green – in service unit
1AA 00014 0004 (9007) A4 – ALICE 04.10
(2)to (9) STM–16 optical channel
(from ch. #1 to ch. #8)
(1)
Note: the cavities must be equipped with up to eight STM–16 or GE optical SFP module plug–in (refer to
Figure 63. on page 124); in the free cavities must be inserted the relevant SFP dummy plugs.
Figure 43. 8xGE, 8xSTM–16 optical port board – front view
ED
03
3AG 24163 BEAA PCZZA
531
105 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
SLOTS
P16S16
2 to 9 and 12 to 19
P16S1S4
2 to 9 and 12 to 19
(2)
P16S1S
2 to 9 and 12 to 19
P16GE
2 to 9 and 12 to 19
LAC40
2 to 9 and 12 to 19
(3)
(16)
LEGENDA:
(17)
(1) Bicolor LED:
Red – local unit alarm
Green – in service unit
1AA 00014 0004 (9007) A4 – ALICE 04.10
(2)to (17) STM–16 optical channel
(from ch. #1 to ch. #16)
(1)
Note: the cavities must be equipped with up to sixteen STM–1e, STM–1, STM–4, STM–16 or GE SFP module
plug–in (refer to Figure 63. on page 124); in the free cavities must be inserted the relevant SFP dummy plugs.
Figure 44. LAC40, 16xGE,16xSTM–16,16xSTM–4/1, 16xSTM–1E port board – front view
ED
03
3AG 24163 BEAA PCZZA
531
106 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
SC/PC
ACRONYM
SLOTS
I–64.1M
2 to 9 and 12 to 19
S–64.2M
2 to 9 and 12 to 19
(1)
It is also available with following connector:
FC/PC
OUTPUT
INPUT
LEGENDA:
(1) Channel #1
(2) Bicolor LED
Red – local unit alarm
Green – in service unit
1AA 00014 0004 (9007) A4 – ALICE 04.10
(2)
Figure 45. 1xSTM–64 (S64M) optical port board – front view
ED
03
3AG 24163 BEAA PCZZA
531
107 / 531
SC/PC
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
SLOTS
P2I64M
2 to 9 and 12 to 19
P2S64M
2 to 9 and 12 to 19
It is also available with following connector:
FC/PC
(1)
(2)
OUTPUT
INPUT
LEGENDA:
(1) Channel #1
(2) Channel #2
(3) Bicolor LED:
Red – local unit alarm
Green – in service unit
1AA 00014 0004 (9007) A4 – ALICE 04.10
(3)
Figure 46. 2xSTM–64 (P2S64M) optical port board – front view
ED
03
3AG 24163 BEAA PCZZA
531
108 / 531
SC/PC
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
SLOTS
P4I64
2 to 9 and 12 to 19
P4S64
2 to 9 and 12 to 19
It is also available with following connector:
FC/PC
(1)
(2)
OUTPUT
INPUT
(3)
LEGENDA:
(1) Channel #1
(2) Channel #2
(3) Channel #3
(4) Channel #4
(4)
(5) Bicolor LED
Red – local unit alarm
Green – in service unit
1AA 00014 0004 (9007) A4 – ALICE 04.10
(5)
Figure 47. 4xSTM–64 (P4S64M) optical port board – front view
ED
03
3AG 24163 BEAA PCZZA
531
109 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
L–642M
SLOTS
2 to 9 and 12 to 19
(1)
(2)
LEGENDA:
(1) Output Booster, Input L64 *
(2) Input Booster, Output L64 *
(3) Bicolor LED:
Red – local unit alarm
Green – in service unit
* Connector assignment refere to Figure 51. on page 113.
1AA 00014 0004 (9007) A4 – ALICE 04.10
(3)
Figure 48. 1xSTM–64 (L–642M) optical port board – front view
ED
03
3AG 24163 BEAA PCZZA
531
110 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
V–642M
SLOTS
2 to 9 and 12 to 19
(1)
(2)
LEGENDA:
(1) Input Preamplifier, Output Preamplifier *
(2) Input Laser Module, Output Laser Module *
(3) Bicolor LED:
Red – local unit alarm
Green – in service unit
1AA 00014 0004 (9007) A4 – ALICE 04.10
* Connector assignment refere to Figure 51. on page 113.
(3)
Figure 49. 1xSTM–64 (V–642M) optical port board – front view
ED
03
3AG 24163 BEAA PCZZA
531
111 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
U–642M
SLOTS
2 to 9 and 12 to 19
(1)
(2)
LEGENDA:
(3)
(1) Output Booster, Input Preamplifier *
(2) Input Booster, Output Preamplifier *
(3) Input Laser Module, Output Laser Module *
(4) Bicolor LED
Red – local unit alarm
Green – in service unit
(4)
1AA 00014 0004 (9007) A4 – ALICE 04.10
* Connector assignment refere to Figure 51. on page 113.
Figure 50. 1xSTM–64 (U–642M) optical port board – front view
ED
03
3AG 24163 BEAA PCZZA
531
112 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Connector
on Board variant:
ABxx AAxx
SC
FC
IN L–64
OUT Booster
IN Booster
SC
80 KM
OUT L–64
FC
Attenuator
L–64
Connector
on Board variant:
IN Preamp
10dB
120 KM
OUT Preamp
AAxx
FC
MU
Connectors
IN ILM
in
out
DCM
80 km
OUT ILM
V–64
LC
Connector
on Board variant:
160 KM
IN Preamp
OUT Booster
ABxx
SC
AAxx
FC
IN Booster
SC
FC
IN ILM
LC
OUT Preamp
LC
OUT ILM
MU
Connectors
in
out
DCM
80 km
MU
Connectors
out
in
DCM
40 km
U–64
1AA 00014 0004 (9007) A4 – ALICE 04.10
Note: This connector assignment is valid for all realization variants xxAB of this boards.
Figure 51. Connector assignment of L–642M, V–642M an U–642M boards
ED
03
3AG 24163 BEAA PCZZA
531
113 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
SLOTS
P2S64X
2 to 9 and 12 to 19
(2)
(3)
LEGENDA:
(1) Bicolor LED:
Red – local unit alarm
Green – in service unit
(2) Slot with XFP module
(3) Slot with XFP–E module
any mix of XFP and XFP–E modules is possible
(1)
1AA 00014 0004 (9007) A4 – ALICE 04.10
Note:
For XFP module refere to Figure 65. on page 125 and for
XFP–E module refere to Figure 66. on page 125.
Figure 52. 2xSTM–64 XFP/XFP–E – Front View
ED
03
3AG 24163 BEAA PCZZA
531
114 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
SLOTS
P4S64X
2 to 9 and 12 to 19
(2)
(3)
(4)
(5)
LEGENDA:
(1) Bicolor LED:
Red – local unit alarm
Green – in service unit
(2) to (3) Slot with XFP modules + adapter
(4) to (5) Slot with XFP–E modules
any mix of XFP and XFP–E modules is possible
(1)
1AA 00014 0004 (9007) A4 – ALICE 04.10
Note:
For XFP module refere to Figure 65. on page 125 and for
XFP–E module refere to Figure 66. on page 125.
Figure 53. 4xSTM–64 XFP/XFP–E – Front View
ED
03
3AG 24163 BEAA PCZZA
531
115 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
SLOTS
P2XGE
2 to 9 and 12 to 19
XFP1
XFP2
(4)
(5)
(2)
(3)
LEGENDA:
(1) Bicolor LED:
Red – local unit alarm
Green – in service unit
(2) to (3) Slots for XFP modules
(4) LED for XFP module (2)
(5) LED for XFP module (3)
(1)
1AA 00014 0004 (9007) A4 – ALICE 04.10
Note:
For XFP module refere to Figure 65. on page 125.
Figure 54. 2x10GE LAN – Front View
ED
03
3AG 24163 BEAA PCZZA
531
116 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
SLOTS
P4XGE
2 to 9 and 12 to 19
XFP1
XFP2
XFP3
XFP4
(6)
(7)
(8)
(9)
(2)
(3)
(4)
LEGENDA:
(1) Bicolor LED:
Red – local unit alarm
Green – in service unit
(5)
(2) to (5) Slots for XFP modules
(6) LED for XFP module (2)
(7) LED for XFP module (3)
(8) LED for XFP module (4)
(9) LED for XFP module (5)
(1)
1AA 00014 0004 (9007) A4 – ALICE 04.10
Note:
For XFP module refere to Figure 65. on page 125.
Figure 55. 4x10GE LAN – Front View
ED
03
3AG 24163 BEAA PCZZA
531
117 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
SLOTS
ES64SC
2 to 9 and 12 to 19
LEGENDA:
(3)
(1) Reset command key
(2) Debug Interface
(2)
(3) LAN Interface
1AA 00014 0004 (9007) A4 – ALICE 04.10
(4) Multicolor LED:
Red – local unit alarm
Green – in service unit
Yellow – in stand–by unit
(1)
(4)
Figure 56. ES64SC – Front View
ED
03
3AG 24163 BEAA PCZZA
531
118 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
SLOT
FLCSERV
FLCSERVA
1
(12)
(11)
(18)
(19)
First Level Controler SPARE
(9)
(20)
(21)
(13)
LEGENDA:
(1)
(2)
(3)
(4)
(5)
(6)
Reset command key
Personal Computer Connector (F interface)
Synchronization Interface
Red LED – Urgent alarm (Critical or Major)
Red LED – Not Urgent alarm (Minor)
Yellow LED – Alarm storing (Attended)
(7)
(8)
(9)
(10)
(11)
Yellow LED – Abnormal condition
Yellow LED – Indicative alarm (Warning)
Line Seizure Key
Alarm storing push–botton (Attended)
Green LED – When on it means active unit
IN
2
1
OUT
(22)
(1)
(10)
(3)
(15)
(12) Multicolor LED
Red – local unit alarm
Green – in service unit
Yellow – in stand–by unit
(16)
(2)
(13) Auxiliary Channels (not supported)
(14) EC and OAM Debug (internal use only)
(14)
(15) LAN Interface for ext. LAN switch
(multi rack configuration)
(4)
(5)
(6)
(7)
(8)
(16) LAN Interface for internal LAN cabling to OED/LO shelf
(single rack configuration)
(17) Future CT Interface (not used)
1AA 00014 0004 (9007) A4 – ALICE 04.10
(18) Yellow LED
(19) Green LED
(17)
EOW Line Status (not supported)
(20) Telephone Jack
(21) 4 Wire Telephone Extension
(22) 2 Mbit/s Auxiliary Channels
adhesive silk–screen printingfront–plate
Figure 57. First Level Controller and Service Interfaces board – front view
ED
03
3AG 24163 BEAA PCZZA
531
119 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
SLOT
FLCCONGI
20
(12)
(11)
First Level Controller MAIN
(9)
(13)
(1)
(10)
LEGENDA:
(1)
(2)
(3)
(4)
(5)
(6)
Reset command key
Personal Computer Connector (F interface)
Synchronization Interface
Red LED – Urgent alarm (Critical or Major)
Red LED – Not Urgent alarm (Minor)
Yellow LED – Alarm storing (Attended)
(7)
(8)
(9)
(10)
(11)
Yellow LED – Abnormal condition
Yellow LED – Indicative alarm (Warning)
Rack Lamps
Alarm storing push–botton (Attended)
Green LED – When on it means active unit
(3)
(15)
(16)
(2)
(12) Multicolor LED
(14)
Red – local unit alarm
Green – in service unit
Yellow – in stand–by unit
(17)
(4)
(5)
(6)
(7)
(8)
(13) Housekeeping and Remote Alarms
(14) EC and OAM Debug (internal use only)
(15) LAN Interface for ext. LAN switch
(multi rack configuration)
1AA 00014 0004 (9007) A4 – ALICE 04.10
(16) LAN Interface for internal LAN cabling to OED/LO shelf
(single rack configuration)
(17) Future CT Interface (not used)
adhesive silk–screen printing front–plate
Figure 58. First Level Controller and Control&General Interfaces board – front view
ED
03
3AG 24163 BEAA PCZZA
531
120 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
SLOTS
MX640
10, 11
MX640GA
10, 11
MX320
10, 11
MX320GA
10, 11
MX160
10, 11
slot 10: MATRIX /A – main
slot 11: MATRIX /B – spare
(4)
(3)
(1)
LEGENDA:
(5)
(1) Debug Interface – for internal use only
(2) Multicolor LED:
Red – local unit alarm
Green – in service unit
Yellow – in stand–by unit (spare–EPS schema)
1AA 00014 0004 (9007) A4 – ALICE 04.10
(3) LAN Interface
(4) LAN Interface
(5) Reset command key
(2)
adhesive silk–screen printing front–plate
Figure 59. Matrix board – front view
ED
03
3AG 24163 BEAA PCZZA
531
121 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
SLOTS
LAX40
2 to 9 and 12 to 19
LAX20
2 to 9 and 12 to 19
slot 2 and 3; 4 and 5 ...18 and 19
(1)
(2)
LEGENDA:
(1) Reset command key
(3)
(2) Debug Interface
(3) LAN Interface – not used
1AA 00014 0004 (9007) A4 – ALICE 04.10
(4) Multicolor LED:
Red – local unit alarm
Green – in service unit
Yellow – in stand–by unit (spare–EPS schema)
(4)
Figure 60. Lower Order Matrix board – front view
ED
03
3AG 24163 BEAA PCZZA
531
122 / 531
ACRONYM
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
PSF
SLOTS
24, 25
(3)
LEGENDA:
(1)
Bicolor LED:
Red – local unit alarm
Green – in service unit
(2) Equipment and boards Lamp Test key
(3) Input Power Supply
(2)
(1)
Figure 61. Power Supply and Filter board – front view
ACRONYM
SUBRACKs
FAN
n, n+2
(2)
(3)
(1)
LEGENDA:
(1) Bicolor LED:
Red – local unit alarm
Green – in service unit
1AA 00014 0004 (9007) A4 – ALICE 04.10
(2) WARNING label: moving mechanical parts
(3) WARNING label: windage (air suction)
Figure 62. FANs unit – front view
ED
03
3AG 24163 BEAA PCZZA
531
123 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
MODULE
ACRONYM
SI161
EQUIPPED
on CARDS
LAC40
SI161
SS161
SL161
SL162
CWP
CWA
DWA
P4S16
P8S16
P16S16
SS41
SL41
SL42
SS11
SL11
SL12
P16S1S4
SGELX
SGESX
SGEZX
P4GE
P8GE
P16GE
TRX STM–16 SFP module
TRX STM–1/4 SFP module
Gigabit Ethernet optical module
Output
Input
Optical cables
Figure 63. Optical SFP Module
MODULE
ACRONYM
SES1
EQUIPPED
on CARDS
P16S1S
P16S1S4
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 64. Electrical SFP Module
ED
03
3AG 24163 BEAA PCZZA
531
124 / 531
MODULE
ACRONYM
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
XS642B
XI641
XP1L12D2
XGES
EQUIPPED
on CARDS
P4S64X / P2XGE / P4XGE
P4S64X / P2XGE / P4XGE
P4S64X
P2XGE / P4XGE
Input
TRX S–64.2B XFP module
TRX I–64.1 XFP module
TRX P1L1–2D2 XFP module
TRX 10G BASE–S XFP module
Output
Figure 65. Optical XFP Module
MODULE
ACRONYM
EQUIPPED
on CARDS
XS642E
P2S64X
P4S64X
Output
TRX XFP S–64.2B Ext.
Input
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 66. Optical XFP–E Module
ED
03
3AG 24163 BEAA PCZZA
531
125 / 531
11 PHYSICAL CONFIGURATION OF THE LO EXTENSION SHELF
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
This chapter illustrates the physical structure, layout and composition, coding and partition of the lower
order extension shelf equipment.
The Equipment shelf front view is illustrated in Figure 67. on page 127 and on page 129.
The Main part codes and partition are listed in Table 20. on page 137.
The Accessory codes and partition are listed in Table 21. on page 138.
The Explanatory notes of part list are reported in Table 22. on page 139.
For the units front view refer to para. 11.3 on page 140.
These paragraphs illustrate the interconnection points that can be accessed on the units front panel and
the alarm/status LEDs together with the relevant legend and meaning.
Notes:
The Personal Computer (Craft Terminal) utilized for Initial Turn-on and Maintenance operations is
not listed as an item of the equipment, but it can be supplied by Alcatel–Lucent.
Refer to Operator’s Handbook for PC hardware configuration.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Table 20. on page 137 contains the units of current equipment release. Units belonging to previous
equipment releases/versions (e.g. for configuration updating) are not here listed but still supported,
if compatible with the current one (for eventual units belonging to previous equipment
releases/versions refer to the relevant Technical Handbook).
ED
03
3AG 24163 BEAA PCZZA
531
126 / 531
11.1 Lower Order Extension Shelf
The lower order extension shelf is a single row shelf (refer to Figure 67. ). It has got 16 slots for the Lower
order Adaptation 20G boards.
Subrack n
PSF
Subrack n+1
ALM
LO CS MATRIX* (Copy B)
LO ES Slots
LO CS MATRIX* (Copy A)
PSF
FAN Unit
Dummy Plate
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The lower order extension shelf is from mechanical point of view the same as the 1678MCC main shelf
(refer to chapter 10.1 on page 80).
LO ES Slots
FAN Unit
Matrix*:
Subrack n+2
LX160
Figure 67. Lower Order Extension Shelf Layout
Three types of slots are distinguished:
•
LO ES Slot (16 slots, each 4.5TE wide), containing the Lower Order Adaptation 20G boards
(LA20).
•
Centerstage Matrix slot (2 slots, each 8TE wide), containing the LO Centerstage Matrix
160GBIT/S boards (LX160; 1+1):
•
Control and Common parts slot (2 slots, each 4TE wide), containing the following boards:
–
–
–
Alarm Board
Power Supply Filter (1+1)
Bus Termination (two boards)
(ALM)
(PSF)
(BUSTERM)
Note: ALM, PSF and BUSTERM are located in the same slot. This slot is divided into three subslots (refer
to Figure 37. on page 84). The BUSTERM board is not visible on the shelf front panel. It is positioned
behind the dummy plate (slot 1) and the ALM board (slot 20).
1AA 00014 0004 (9007) A4 – ALICE 04.10
The ALM board provides housekeeping, remote alarm and rack lamp interfaces. The ALM board
functionality is a subset of the FLCCONGI board.
The FAN Subsystem consists of two subracks and contains the following boards:
–
ED
FANs unit
(FAN)
03
3AG 24163 BEAA PCZZA
531
127 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The Matrix board (LX160) supports the following functionalities:
•
•
•
•
Cross–connection
Synchronization
Shelf Controller
1+1 EPS protection scheme, when two Matrix boards are present (default)
The Power Supply Filter board (PSF) supports the following functionality:
•
distribution of Power Supply after filtering process
The Bus Termination board (BUSTERM) supports the following functionality:
•
electrical termination to the buses routed on the backplane
These two boards are not visible on shelf front–panel. They are two small boards included in the shelf
and are placed behind the dummy plate (slot 1) and the ALM board (slot 20).
The FAN unit (FAN) supports the following functionality:
•
cooling of the equipment
Due to the high level of integration reached with this equipment, the two FAN units located at the top
and at the bottom of the shelf have always to be equipped.
The two FAN units are physically integrated in the lower order extension shelf, without the need of
external connection cables.
Note: The slots which are not equipped have to be closed by a dummy plate for EMC reasons.
11.1.1 Equipment Front View
1AA 00014 0004 (9007) A4 – ALICE 04.10
The lower order extension shelf equipment has a symmetrical layout (refer to Figure 68. on page 129).
The following types of slots are distinguished:
•
slot 1
•
slots 2 ÷ 9 and
12 ÷ 19 :
:
empty (closed with dummy plate)
Lower Order Adaptation 20G boards
slot 2 and 19 are reserved for LA20 protection boards
•
slot 10 and 11 :
LO Centerstage Matrix 160GBIT/S boards
(LX160)
•
slot 20
Alarm board
(ALM)
•
slot 21 and 22 :
Bus Termination boards
(BUSTERM)
•
slot 24 and 25 :
Power Supply and Filter boards
(PSF)
:
Note:
Slot 21 and slot 22 are positioned behind slot 1 and slot 20 respectively, so the BUSTERM
boards are not visible on the shelf front panel.
The two FANs have no slot number, because they are modelled as separate subracks (subrack n and n+2).
ED
03
3AG 24163 BEAA PCZZA
531
128 / 531
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
FAN (Subrack n)
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
24
1
2
3
4
5
6
7
8
ÄÄÄÄÄÄÄ
ÄÄÄÄ
ÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄÄ
ÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄÄ
ÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄÄ
ÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄÄ
ÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄÄ
ÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄ
ÄÄÄÄ
ÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄÄ
ÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄÄ
ÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄÄ
ÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄÄÄÄÄ
ÄÄÄÄ
ÄÄÄ
ÄÄÄÄÄÄÄ
9
21
25
20
12 13 14 15 16 17 18 19
10
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
11
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
22
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
1AA 00014 0004 (9007) A4 – ALICE 04.10
FAN (Subrack n+2)
Figure 68. Lower Order Extension Shelf Equipment front view (slot position)
ED
03
3AG 24163 BEAA PCZZA
531
129 / 531
11.1.2 Configuration Rules
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
11.1.2.1 Allowed or basic Equipment Configuration
Table 17. presents for each slot, the allowed equipment types and the basic equipment type (the acronyms
of the units are shown).
Note: Up to now a switching matrix capacity of max. 160G is supported.
That means, max. eight LA20 working boards can be equipped.
Table 17. 1678MCC LO Shelf Equipment: slot configuration
1678MCC shelf
Slots
Basic Configuration
Allowed Equipment
1
Empty (dummy plate)
––
1
3÷5
Spare (dummy plate)
––
9
LA20
––
2
Protection LA20
––
3
Spare (dummy plate)
––
9
10
LX160 (main)
––
11
LX160 (spare)
––
20
ALM
––
5
21, 22
BUSTERM
––
6
24, 25
PSF
––
7
subrack n, n+2
FAN
––
8
6÷9
and
12 ÷ 15
2, 19
16 ÷ 18
note
4
Refer to explanatory notes on Table 19.
Table 18. Pluggable Optical Modules
LA20 boards
J1 ÷ J8
Note
STM–N optical modules: SI161
10
Table 19. 1678MCC LO Shelf Equipment: slot configuration explanation notes
1AA 00014 0004 (9007) A4 – ALICE 04.10
Note Explanation
1
It is 4TE.
2
All these boards are 4.5TE.
Up to eight LA20 boards can be equipped. Working LA20 boards are always inserted in the
inner slots of their half (starting from slot 9 and 12).
3
These slots are mandatory for protection LA20 boards.
4
It is 8TE. Both boards provide to 1+1 EPS protection scheme (mandatory).
5
6
ED
It is 4TE.
This slot is dedicated to ALM board. The ALM board is always unprotected.
BUSTERM#1 is located behind the dummy plate of slot1 and BUSTERM#2 behind the
ALM board. They are not visible on the front view.
03
3AG 24163 BEAA PCZZA
531
130 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Note Explanation
7
They are both mandatory.
8
They are both mandatory, one under and one above the shelf.
9
It is 4.5TE. These slots are reserved for future applications (LO matrix > 160G)
10
Up to eight optical SFP modules (I–16.1) can be plugged in the LA20 board.
Lower Order Extension Shelf: Supported Lower Order Adaptation Board
Board
Interfaces
Connectors
1 slot
Lower Order Adaptation 20G
1
I–16.1
2
.
.
8
SFP
SFP
.
.
LA20
LC
SFP
Figure 69. Lower Order Extension Shelf: Supported Adaptation Board
11.1.2.2 Examples of Equipment Configuration
The figures on next pages show some examples of allowed equipment configuration.
Figure 70. on page 132 shows the typical basic configuration of LO extension shelf (without LO adaptation
20G boards):
•
•
•
•
•
•
•
•
•
slot 1
: empty
slot 2 ÷ 9
: reserved to LO adaptation 20G boards
slot 10 and slot 11 : two LX160 boards
slot 12 ÷ 19
: reserved to LO adaptation 20G boards
slot 20
: ALM board
slot 21 and slot 22 : two BUSTERM boards (small board)
slot 24 and slot 25 : two PSF boards
two FAN units (subrack n, n+2)
dummy plates for all other slots unequipped
Figure 71. on page 133 shows the configuration of the 160G LO extension shelf:
1AA 00014 0004 (9007) A4 – ALICE 04.10
•
•
•
•
•
•
ED
basic configuration
slot 6 ÷ 9
: four LA20 boards
slot 2
: LA20 protection board
slot 12 ÷ 15
: four LA20 boards
slot 19
: LA20 protection board
dummy plates for all other slots unequipped
03
3AG 24163 BEAA PCZZA
531
131 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1AA 00014 0004 (9007) A4 – ALICE 04.10
ED
03
24
1
21
BUSTERM
PSF
2
3
4
5
6
7
8
9
FAN (subrack n)
11
160G LO Matrix Copy B
10
FAN (subrack n+2)
12 13 14 15 16 17 18 19
3AG 24163 BEAA PCZZA
531
Figure 70. Basic configuration of LO Extension Shelf
160G LO Matrix Copy A
PSF
25
ALM
20
22
BUSTERM
132 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1AA 00014 0004 (9007) A4 – ALICE 04.10
ED
03
PSF
2
3
dummy plate
LA20 protection
dummy plate
4
5
6 7
LA20
LA20
8
LA20
LA20
11
160G LO Matrix Copy B
12 13 14 15 16 17 18 19
LA20
LA20
LA20
LA20
dummy plate
dummy plate
PSF
25
20
22
dummy plate
LA20 protection
ALM
FAN (subrack n)
9
160G LO Matrix Copy A
10
FAN (subrack n+2)
3AG 24163 BEAA PCZZA
531
Figure 71. Configuration of the 160G LO extension Shelf
dummy plate
dummy plate
BUSTERM
24
1
21
BUSTERM
133 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
11.1.3 Connection to the Main Shelf
To connect the LO extension shelf with the 1678MCC main shelf STM–16 interfaces are used in the main
shelf. The board which supports this functionality is the Link Board LAC40. This is a special 16xSTM–16
board used only for connection to LO extension shelf.
The configuration of the Main shelf is flexible (refer to Figure 72. ):
The position of the boards in the main shelf is flexible and allows an upgrade which is independent from
the starting configuration.
A LAC40 board can be linked to a symmetric pair of LA20 boards only. The lower ports of the LAC40 (9..16)
are linked with the ports of the left half and the upper ports (1..8) are linked with the ports of the right half.
For the connection to a 160G LO extension shelf the 1678MCC main shelf contains:
–
–
Four LAC40 working boards
One LAC40 protection board
The LAC40 boards are equipped with I16.1 SFP modules.
The LO extension have to be connected to the main shelf as shown in Figure 72.
Higher Order Shelf
Lower Order Shelf
FAN
S S S
P
l l l
S o o o
F t t t
# # #
2 3 4
S
l
o
t
#
9
S
l
o
t
#
10
S
l
o
t
#
11
L
F
L I I I I I A I I
C / / / / / C / /
S O O O O O 4 OO
0
E
R
P
V
R
I
O
C
T
E
M
X
6
4
0
M
L
X I I I A
6 / / / C
4 OOO 4
0
0
S
l
o
t
#
5
S
l
o
t
#
6
S
l
o
t
#
7
S
l
o
t
#
8
FAN
C
O
P
Y
A
C
O
P
Y
B
S S S S S S S S
P
l l l l l l l l
o o o o o o o o S
t t t t t t t t F
# # # # # # # #
12 1314 15 16 1718 19
L
A
C
4
0
L
A
C
4
0
L
A I F
C / L
4 O C
C
0
O
N
G
I
S
S S S S S
P
l
l l l l l
o S o o o o o
F t t t t t
t
#
# # # # #
24
2 3 4 5 6
S
l
o
t
#
7
S
l
o
t
#
8
S
l
o
t
#
9
S
P
A
R
E
L
A
2
0
L
A
2
0
D
U
M
M
Y
L
A
2
0
S
P
A
R
E
P
R
S
B
O
l
o T T
E
t
# R
21 M
FAN
S
P
A
R
E
L
A
2
0
S
l
o
t
#
10
S
l
o
t
#
11
S S S S S S S S
P
l l l l l l l l
o o o o o o o o S
t t t t t t t t F
# # # # # # # #
12 13 14 15 16 17 18 19
L
L X
A 1
2 6
0
0
L
X
1
6
0
L
A
2
0
C
O
P
Y
A
C
O
P
Y
B
L
A
2
0
L
A
2
0
S
l
o
t
#
25
S S S
L
P P P L A
A
A A A A L
2
R R R 2 M
0
E E E 0
P
R
O B
T T
E
R
M
S
l
o
t
#
22
FAN
16
16
16
16
16
8
8
8
8
Figure 72. Connection of 160G LO Extension Shelf with the Main Shelf
The configuration of the LO extension shelf is fixed (refer to Figure 72. ):
1AA 00014 0004 (9007) A4 – ALICE 04.10
–
–
–
ED
A LA20 has to host either 8 protection or 8 working ports per board (no mixture is allowed).
For this reason 8 working boards and 2 protecting boards are used.
Working LA20 boards are configured in the inner slots of their half (starting from slot 9 and 12).
The protection boards are configured always in the outer slots of their half (slot 2 and 19).
03
3AG 24163 BEAA PCZZA
531
134 / 531
The connection main shelf/LO extension shelf is done via the following ’connection items’:
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
Optical cables.
•
On the Main Shelf side, the cables are plugged at the front of LAC40 boards.
•
On the LO extension shelf side, the cables are plugged at the front of the LA20 boards.
The connection is always 1:N MSP protected.
Note: The same modules (I16.1) have to be used in LA20 and in LAC40 boards.
The location scheme of the VC–4s on LA20 boards and the connection scheme LA20/LAC 40 is shown
in the following Figure 73. Refer also to Figure 72. for understanding this scenario. The LAC40 boards
are configured as shown in Figure 72.
Higher Order Shelf
Lower Order Extension Shelf
LAC40 Board
Protecting
LA20 Board
Port
Slot
Slot Port
1–8
9–16
7
7
2
1–8
1–8
9–16
1–8
9–16
15
15
16
16
6
7
8
9
1–8
1–8
1–8
1–8
ModVc4
Protecting
751–875
501–625
251–375
1–125
Matrix
1–8
9–16
1–8
9–16
17
17
18
18
The position of the LAC40 boards is flexible.
12
13
14
15
1–8
1–8
1–8
1–8
19
1–8
126–250
376–500
626–750
876–1000
Protecting
The position of the LA20 boards is fixed.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 73. VC–4 mapping on LA20 Boards
ED
03
3AG 24163 BEAA PCZZA
531
135 / 531
11.2 Part List
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The Part List is subdivided in three tables, specifically:
•
in Table 20. on page 137 is shown the Main part list
•
in Table 21. on page 138 is shown the Accessory list
•
in Table 22. on page 139 is shown the Explanatory notes of previous lists
Furthermore, for any item the position and the maximum quantity that can be allocated inside the
equipment are indicated too.
Such tables report the following information:
ED
•
Description: name of items
•
Acronym: it is used to identified units and modules on the Craft Terminal applications
•
ANV Part/Number
•
Max Q.ty: maximum quantity of items in the 1678MCC equipment
•
Slot: position of the units inside the 1678MCC equipment (refer to Figure 68. on page 129)
•
Notes: are listed a set of explanatory notes.
03
3AG 24163 BEAA PCZZA
531
136 / 531
Table 20. Main parts list
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
DESCRIPTION
ACRONYM
ANV P/N
Max.
Q.ty
SLOT
NOTE
MECHANICAL STRUCTURE
MCC RACK WITH NGTRU
––
1678MCC SHELF
SR78
HOUSEKEEPING MONITORING UNIT
HMU
3AL 81673 AA––
3AL 81673 AB––
3AL 81224 AA––
3AL 81224 AB––
3AG 24234 AA––
1
1
––
2
4
POWER SUPPLY
POWER SUPPLY AND FILTERS
PSF
3AL 81502 AA––
2
24, 25
5
1
20
6
2
10, 11
7
10
2÷9
and
12 ÷ 19
8
2
––
9
80
––
10
COMMON PARTS
ALARM
ALM
3AG 24262 AA––
SWITCHING MATRIX
LO CENTERSTAGE MATRIX 160 GBIT/S
LOWER ORDER ADAPTATION 20G
LX160
LA20
3AG24328 AA––
3AG 24150 AA––
SPARE PARTS
TERMINATION BUS
1AA 00014 0004 (9007) A4 – ALICE 04.10
OPTO TRX SFP I–16.1 PLUG–IN
ED
3AL 81209 AA––
3AL 81209 AB––
STM–N OPTICAL MODULES
BUSTERM
SI–161
1AB 19637 0013
03
3AG 24163 BEAA PCZZA
531
137 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Table 21. Accessories list
DESCRIPTION
ACRONYM
SLOT
SOFTWARE
NOTES
11
EQUIPMENT ACCESSORIES
1678MCC DUST FILTER UNIT
––
3AL 81205 AA––
3AL 81205 AB––
3AG 24350 AA––
1678MCC DUST FILTER
––
3AG 24354 AA––
1
––
15
1678MCC INSTALLATION KIT
––
3AL 89584 AA––
1
––
16
1678MCC INSTALLATION KIT
––
3AG 24367 AA––
1
––
17
DUMMY PLATE W=22.5 mm
––
3AN 52174 AA––
6
––
18
2 MB/S AUX CHANNEL 75 Ω KIT
––
3AL 38432 AA––
1
––
––
2 MB/S AUX CHANNEL 120 Ω KIT
––
3AL 38433 AA––
1
––
––
SDH SYNC ADAPTER 75 Ω UNBAL KIT
––
3AL 89586 AA––
1
––
––
SDH SYNC ADAPTER 120 Ω BAL KIT
––
3AL 89587 AA––
1
––
––
NGTRU
3AL 81656 AA––
1
––
19
––
3AN 51536 AA––
4
––
20
STPUP
NGBYP
3AL 89590 AA––
3AL 38414 AA––
6
6
––
––
21
22
––
––
––
––
––
––
3AL94613 AA––
3AL 38423 AA––
3AL 37973 AA––
3AL 91637 AA––
3AL 24268 AA––
3AL 91853 AA––
1
1
1
1
1
––
––
––
––
––
––
12
––
23
24
––
––
1678MCC FAN UNIT
NGTRU
NGTRU DUMMY COVER
DC/DC CONVERTER STEP–UP 2000 W
NGTRU BYPASS
FAN UNIT PROTECTION
INSTALLATION KIT NGTRU
ESD KIT
EARTHQUAKE KIT
ACCESSORY KIT 1678MCC
KIT DCU TRAY 1678MCC RACK
1AA 00014 0004 (9007) A4 – ALICE 04.10
Max.
Q.ty
ANV P/N
ED
FAN
2
––
12
1
––
14
03
3AG 24163 BEAA PCZZA
531
138 / 531
Table 22. Parts list: explanatory notes
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Note Explanation
ED
1
This item contains the NGTRU equipment (without converters and dummy covers) and the
complete set of parts of the rack to host 1678MCC equipment.
2
It is the equipment shelf.
3
Shelf supports FANs with dust filter.
4
Only necessary in case of supported feature: Station Alarms
5
These items are mandatory and they are provisioned in 1+1 configuration: the boards perform
the filtering and the distribution of the power supply for the 1678MCC equipment.
6
The ALM board provides housekeeping, remote alarm and rack lamp interfaces.
7
Two LX boards are used in an 1+1 protected EPS configuration: the boards perform connection and cross–connection functionalities.
8
Up to eight SFP modules can be equipped (I–16.1) per board.
9
This is a spare part item; the 1678MCC shelf (SR78) already included it.
10
Up to 8 of these modules are hosted in LA20 board.
11
Details concerning the software P/N are given in the Operator’s Handbook.
12
These items are mandatory. Maintenance intervals are described in the ’Maintenance Handbook’.
13
Version for ANSI market.
14
Dust filter support.
15
The Kit includes three dust filter.
16
It contains the cables and all the accessories (connectors, caps, screws, etc.) concerning
Power Supply and Auxiliary systems (except Sync. and 2 Mbit/s Aux. systems).
17
Installation Kit 1678MCC for ANSI market.
18
It is essential to insert the relevant dummy plates on the space left by all LA20 boards NOT
supplied, in order to obtain the EMI/EMC performances. The number of six dummy plates is
necessary in case of 160G LO matrix (refer to Figure 71. ).
19
This is a spare part item; the 1678MCC rack already included it.
20
It is essential to insert the relevant dummy covers on the space left by all DC/DC Step–up
Converters (or NGTRU Bypass) NOT supplied in the NGTRU equipment, in order to obtain
the EMI/EMC performances.
21
These items are hosted in the NGTRU equipment in 1+1 configuration to supply the
1678MCC equipment.
22
When this item is used in alternative to the DC/DC Step–up Converter, only 8 Traffic Ports are
provisional in the 1678MCC equipment (four into slots 2 ÷ 9 and four into slots 12 ÷ 19).
23
Part of MCC rack
24
If earthquake proof is required.
03
3AG 24163 BEAA PCZZA
531
139 / 531
11.3 Units Front View
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
This paragraph shows the access points (LEDs, switches etc.) present on each units together with legend
and meaning.
Figure 74. on page 141 through Figure 78. on page 145 illustrate units front view available in the
1678MCC Equipment.
NOTE: The unit dimensions in all figures are not the real ones.
ED
03
3AG 24163 BEAA PCZZA
531
140 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
LA20
SLOTS
2, 6 to 9, 12 to 15, 19
(2)
(3)
(8)
LEGENDA:
(9)
(1) Bicolor LED:
Red – local unit alarm
Green – in service unit
1AA 00014 0004 (9007) A4 – ALICE 04.10
(2)to (9) STM–16 optical channel
(from ch. #1 to ch. #8)
(1)
Figure 74. Lower Order Adaptation 20G board – front view
ED
03
3AG 24163 BEAA PCZZA
531
141 / 531
SLOT
ALM
20
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
(1)
(2)
(3)
(9)
LEGENDA:
1AA 00014 0004 (9007) A4 – ALICE 04.10
(1) Multicolor LED
(2)
(3)
(4)
(5)
(6)
Red – local unit alarm
Green – in service unit
Yellow – in stand–by unit
Rack Lamps
Housekeeping and Remote Alarms
Red LED – Urgent alarm (Critical or Major)
Red LED – Not Urgent alarm (Minor)
Yellow LED – Alarm storing (Attended)
(7)
(8)
(9)
(10)
Yellow LED – Abnormal condition
Yellow LED – Indicative alarm (Warning)
Alarm storing push–botton (Attended)
Future CT Interface (not used)
(10)
(4)
(5)
(6)
(7)
(8)
Figure 75. Alarm board – front view
ED
03
3AG 24163 BEAA PCZZA
531
142 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
SLOTS
LX160
10, 11
slot 10: MATRIX /A – main
slot 11: MATRIX /B – spare
(4)
(3)
(1)
LEGENDA:
(5)
(1) Debug Interface – for internal use only
(2) Multicolor LED:
Red – local unit alarm
Green – in service unit
Yellow – in stand–by unit (spare–EPS schema)
1AA 00014 0004 (9007) A4 – ALICE 04.10
(3) LAN Interface
(for connection to the corresponding HO main shelf)
(4) LAN Interface
(for connection to the corresponding HO main shelf)
(5) Reset command key
(2)
adhesive silk–screen printing front–plate
Figure 76. LO Centerstage Matrix Board – front view
ED
03
3AG 24163 BEAA PCZZA
531
143 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
PSF
SLOTS
24, 25
(3)
LEGENDA:
(1)
Bicolor LED:
Red – local unit alarm
Green – in service unit
(2) Equipment and boards Lamp Test key
(3) Input Power Supply
(2)
(1)
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 77. Power Supply and Filter board – front view
ED
03
3AG 24163 BEAA PCZZA
531
144 / 531
ACRONYM
SUBRACKs
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
FAN
n, n+2
(2)
(3)
(1)
LEGENDA:
(1) Bicolor LED:
Red – local unit alarm
Green – in service unit
(2) WARNING label: moving mechanical parts
(3) WARNING label: windage (air suction)
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 78. FANs unit – front view
ED
03
3AG 24163 BEAA PCZZA
531
145 / 531
12 PHYSICAL CONFIGURATION OF THE OED SHELVES
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
This chapter illustrates the physical structure, layout and composition, coding and partition of the OED
shelves equipment.
The Equipment shelf front view is illustrated in Figure 79.
The Main part codes and partition are listed in Table 29. on page 159 for 1670SM and Table 35. on
page 186 for 1662SMC.
The Accessory codes and partition are listed in Table 30. on page 160 for 1670SM and Table 36. on
page 187 for 1662SMC.
The Explanatory notes of part list are reported in Table 31. on page 161 for 1670SM and Table 37. on
page 188 for 1662SMC.
For the units front view refer to chapter 12.1.8
These paragraphs illustrate the interconnection points that can be accessed on the units front panel and
the alarm/status LEDs together with the relevant legend and meaning.
Notes:
The Personal Computer (Craft Terminal) utilized for Initial Turn-on and Maintenance operations is
not listed as an item of the equipment, but it can be supplied by Alcatel–Lucent.
Refer to Operator’s Handbook for PC hardware configuration.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Table 29. on page 159 contains the units of current equipment release. Units belonging to previous
equipment releases/versions (e.g. for configuration updating) are not here listed but still supported,
if compatible with the current one (for eventual units belonging to previous equipment
releases/versions refer to the relevant Technical Handbook).
ED
03
3AG 24163 BEAA PCZZA
531
146 / 531
12.1 1670SM Shelf
The 1670SM shelf is divided in three areas (refer to Figure 79. ):
–
–
–
The Access area in the upper portion of the shelf mainly devoted to the physical interfaces
The Traffic Ports area in the middle devoted to the traffic and control boards
The Link area in the lower portion of the shelf devoted to the boards for the inter-shelf communication
A separate FAN subrack is mounted at the bottom of each 1670SM.
1
2 3 4 5 6 7 8 9 10 1112131415161718 19 20
21
22
23 2425 26 27 28 2930 31 323334 35 36 3738 3940
CONGIHC copyB
empty
CONGIHC copyA
Accesscards
empty
empty
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
12.1.1 Shelf Layout
AccessArea
41
empty
PortArea
50
HCLINKE 4B
49
HCMATRIX copyB
I/O slots assigned
to VSR LINK 4
48
HCLINKE 4A
47
HCLINKE 3B
I/O slots assigned
to VSR LINK 3
BTERM
46
HCLINKE 3A
I/O slots assigned
to VSR LINK 2
44 45
HCLINKE 2B
I/O slots assigned
to VSR LINK 1
43
HCLINKE 2A
HCLINKE 1A
42
HCLINKE 1B
empty
HCMATRIX copyA
PortCards
LinkArea
SeparateFanShelf
Figure 79. 1670SM Shelf Front View
The Access area (21 slots) can contain the following boards:
–
–
–
2 slots for general service connectors such as Power, QB3 Int., Housekeeping, remote alarm, rack
lamp (CONGIHC/A and CONGIHC/B);
16 slots for traffic access modules;
3 slots empty (not used).
1AA 00014 0004 (9007) A4 – ALICE 04.10
The Traffic Ports area (20 slots) can host the following boards:
–
–
–
ED
2 slots for the matrices (master and slave)
16 slots for the traffic ports
2 slots empty (not used)
(HCMATRIX)
03
3AG 24163 BEAA PCZZA
531
147 / 531
The Link area (9 slots) can host the following boards:
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
–
1 slot for the internal bus termination (BTERM)
8 slots for the link boards (HCLINKE) used for inter-shelf connection to the main shelf.
Note:
The number of link boards depends on the number of equipped slots.
The 1670SM shelf has a capacity of 256 STM-1 equivalents.
The maximum quantity of each interface per shelf is:
–
–
–
–
64 x 140 Mbit/s interfaces
256 x STM-1 electrical interfaces
256 x STM-1 optical interfaces
64 x STM-4 optical interfaces
12.1.2 Basic Equipment
Slot
Board
Mnemonic
Comment
CONGIHC
Mandatory. “3–wire” variant
CONGIHC
Mandatory. “3–wire” variant
HCMATRIX
Mandatory
HCMATRIX
Mandatory
HCLINKE boards are used only for connection to
the Main Shelf.
Access Area
1
Control and General Interface Board copy A
2..3
Empty
4...19
Access boards or empty
20
Empty
21
Control and General Interface Board copy B
Port Area
22
Matrix Hi–Cap copy A
23
Empty
24...39
I/O port boards
40
Empty
41
Matrix Hi–Cap copy B
Link Area
42
Optical Link Enhanced board 1 copy A
HCLINKE
43
Optical Link Enhanced board 1 copy B
HCLINKE
44
Optical Link Enhanced board 2 copy A
HCLINKE
45
Optical Link Enhanced board 2 copy B
HCLINKE
47
Optical Link Enhanced board 3 copy A
HCLINKE
48
Optical Link Enhanced board 3 copy B
HCLINKE
49
Optical Link Enhanced board 4 copy A
HCLINKE
50
Optical Link Enhanced board 4 copy B
HCLINKE
46
Bus Termination Board
BTERM
Only the required HCLINKE boards are equipped
If the connection Main Shelf / 1670SM is not protected, HCLINKE boards copy B is not equipped
Mandatory
Cooling: A separate FAN shelf must be mounted at the bottom of each 1670SM shelf
1AA 00014 0004 (9007) A4 – ALICE 04.10
Table 23. Basic Equipment of the 1670SM Shelf
ED
03
3AG 24163 BEAA PCZZA
531
148 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
12.1.3 Basic Function of the Boards
CONGIHC (Control and General Interface)
–
Provides power supply interfaces and power supply distribution
(only the ’3-wire FPE’ variant 3AL 79135 AB** is used)
–
Provides the external LAN interface
A Shelf Identifier is plugged on the CONGIHC B (Q2 interface)
Access Board
–
Line Interface:
Access boards are used together with the STM-1 and 4xSTM-4 interfaces
Matrix Hi-Cap
–
The synchronization function CRU is used for frame synchronization and for clock distribution within
the shelf.
–
The Shelf Controller (SC) controls the ASICs of the shelf
–
The SC provides the redundant interface to the control system
Port Board
–
Transport, adaptation and termination functions
–
Matrix Hi-Cap selection
Link board – HCLINKE
–
The Link boards are the interfaces between 1670SM and 1678MCC Main shelf. The HCLINKE
boards are implemented in a 1+1 protected configuration. Each shelf can be equipped with max. 4+4
HCLINKE boards.
Bus Termination Board
–
Electrical Termination of the buses routed on the backpanel.
–
Power supply of the ISPB bus (management bus)
12.1.4 I/O Interfaces
The 1670SM integration offers the following interfaces:
–
–
–
–
140 Mbit/s
STM-1e
STM-1o
STM-4
1AA 00014 0004 (9007) A4 – ALICE 04.10
Mixed I/O configuration on shelf level is supported. For more details about supported STM-N interfaces
and configurations in R3 refer to chapter 12.1.5.
ED
03
3AG 24163 BEAA PCZZA
531
149 / 531
12.1.5 System Configurations
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
12.1.5.1 Supported I/O Boards, Relation Access/Port Boards
I/O Interfaces
Access Boards
Port Boards
Connectors
1 slot
1
2
4xSTM–4
S–4.1
L–4.1
proprietary
proprietary
SC/PC, FC/PC
2xSTM–4
3
L–4.2
4
any mix of I/O modules allowed
4xSTM–4
proprietary
proprietary
P4S4
A2S4
1 slot
1 slot
1
16xSTM–1o
.
.
.
4
S–1.1
L–1.1
.
.
.
any mix of SFP I/O modules allowed
16
SFP
.
.
.
SFP
LC
1 slot
5
L–1.2
SFP I/O modules are pluggable
.
.
.
16xSTM–1o
SFP
.
. 12xSTM–1o
.
SFP
P160S1
A12OS1
1 slot
1 slot
16xSTM–1e
16xSTM–1e
16xSTM–1e
1.0/2.3 – 75 Ohm
P16S1
A16S1
1 slot
1 slot
4xSTM–1e
4xSTM–1e
4xSTM–1e *
1.0/2.3 – 75 Ohm
P4ES1
A4ES1
1 slot
4x140/155Mbit/s
ICMI I/O modules are pluggable
1
ICMI
2
ICMI
2x140/155Mbit/s
3
4
1.0/2.3 – 75 Ohm
1 slot
4x140/155Mbit/s
ICMI
ICMI
P4E4
A2S1
* only on customer request
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 80. 1670SM: Relation Port/Access Boards
ED
03
3AG 24163 BEAA PCZZA
531
150 / 531
12.1.5.2 Configuration Rules for the I/O Boards
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
General I/O Configuration Rules
Table 24. 1670SM: General Configuration Rules for the I/O Boards
I/O Boards
Mixing of I/O
boards within
a Shelf
I/O Protection
HCLINKE
Boards
–
The supported I/O boards are shown in Figure 80.
Take into account that some boards require an access board
–
Each I/O slot has a capacity of 16 STM–1 eq.
–
The slot position of the access boards have to be in line with the slot position of the corresponding port
boards
The connection port/access boards is done on the backpanel. (Ref.Table 25. )
–
It is possible to equip a board only with the required I/O modules. I/O modules slots which are not
equipped must not be closed by a dummy plate.
–
The boards can be plugged in almost any mix in any slot (flexible configuration) from left to right .
The boards which are allowed to be mixed within a shelf are shown in Table 28.
–
A shelf may be equipped with combinations of all unprotected electrical boards and all
protected/unprotected optical boards.
–
A flexible shelf configuration with EPS for 16xSTM–1e is also supported (Ref. chapter 12.1.5.3)
–
The optical I/O signal can be 1+1 MSP protected or unprotected
–
A protection connection must be established in the same shelf (no protection is possible across different
shelves)
–
The HCLINKE boards are used only for the connection to the Main Shelf
–
Each HCLINKE board has a capacity of 64 STM–1equiv.
–
HCLINKE boards copy A and copy B must be neighbor boards
–
If the connections Main Shelf OEDs are not protected, the HCLINKE boards copy B are not equipped.
–
There is a fixed relationship between I/O boards and HCLINKE boards:
I/O boards
Dummy Plates
slot 24,25,26,27
slot 28,29,30,31
slot 32,33,34,35
slot 36,37,38,39
HCLINKE board
HCLINKE board
HCLINKE board
HCLINKE board
slot 42+43
slot 44+45
slot 47+48
slot 49+50
–
Only the HCLINKE boards which are necessary are equipped.
–
The I/O slots and HCLINKE slots which are not equipped must be closed by a dummy plate for EMC
reasons.
Slot Relation Port/Access Boards
1AA 00014 0004 (9007) A4 – ALICE 04.10
Table 25. 1670SM: Slot relation Port/Access Boards
I/O Board
Width
Slot relation Port/Access boards
4x140Mbit Unprotected
STM–N
1 slot
Port boards
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Access boards 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
4/16xSTM–1e unprotected
1 slot
Port boards
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Access boards 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
4/16xSTM–1e Protected
EPS N+1 (N=1+15)
1 slot
Port boards
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Access boards 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Protecting port board at the left side of the working boards
Protecting access board (HPROT/HPROT16):
depends on position of protecting
port board
16xSTM–1o Protected/
Unprotected
1 slot
Port boards
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Access boards 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
4xSTM–4 Protected/Unprotected
1 slot
Port boards
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Access boards 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
ED
03
3AG 24163 BEAA PCZZA
531
151 / 531
Slot Position of the Port Boards
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Table 26. 1670SM: Position of the Port Boards in the Shelf
I/O Board
Protection
Width
Slot positions
4x140Mbit
unprotected
1 slot
any
4xSTM–1e
unprotected
1 slot
any
4xSTM–1e
EPS N+1 (N=1...15)
1 slot
unprotected
16xSTM–1e
unprotected
1 slot
16xSTM–1e
EPS N+1 (N=1...15)
1 slot
unprotected
protecting board: at the left side of working boards
working boards 25....39
24...39 working boards
any
protecting board: at the left side of working boards
working boards 25....39
24...39 working boards
16xSTM–1o
unprotected or 1+1 MSP protected
1slot
any
4xSTM-4
unprotected or 1+1 MSP protected
1 slot
any
Interface Specific Configuration Rules
Table 27. 1670SM: Interface specific Configuration Rules
4xSTM–4
Board equipment:
– The port board and the access board are equipped with one or two I/O modules
– If only two ports are required, the access board can be omitted
– Within a board, a mix of different STM–4 I/O modules (S–4.1, L–4.1, L–4.2) is allowed
– Within a board, a mix with other I/O modules is not allowed
Replacement of IF modules:
– The I/O modules are hot pluggable
Protection:
– The I/O signal can be 1+1 MSP protected or unprotected
16xSTM–1o
Board equipment:
– It is possible to equip 1 to 16 SFP modules
– If no more than 4 ports are required, the access board can be omitted
– The SFP modules are hot pluggable
– It is possible to equip only the required ports. The ports which are not equipped need not to be covered
by a dummy plate.
Protection:
– The I/O signal can be 1+1 MSP protected or unprotected
Limitation
– Timing reference can be derived only from interfaces of group 1: SFP 1 to 6 on A12OS1 and 3,4 on
P16OS1
4/16xSTM–1e
Shelf equipment
Unprotected:
Protected:Working
Protecting
Access boards: slots 4...19
Port boards: slots: 24...39
Access boards: slots 5...19
Port boards: slots: 25...39
HPROT/HPROT16: depends on position of protection board
Port board: left side of working boards
Protection
Protection is performed at board level
4x140Mbit/s
Board equipment
– The port board and the access board can be equipped with one or two ICMI I/O modules
1AA 00014 0004 (9007) A4 – ALICE 04.10
– If only two ports are required, the access board can be omitted
– Within a board, a mix with other IF modules (e.g. STM–1e) is not allowed
–The ports slots which are not equipped need not to be covered by a dummy plate.
Protection
ED
Protection not supported
03
3AG 24163 BEAA PCZZA
531
152 / 531
12.1.5.3 Flexible Configuration with EPS for 16xSTM–1e
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
As a general rule a 1670SM shelf may be equipped with combinations of all unprotected electrical I/O
boards and all protected/unprotected optical I/O boards. This is called the ’flexible configuration’.
It is also possible to equip a ’flexible’ shelf with EPS protected 16xSTM–1e pairs.
Configuration Rules
–
–
–
–
–
The 16xSTM–1e boards with EPS are installed from the left to the right without any gap (no empty
slot allowed).
The most left board is the protection board, the related access slot is equipped with the HPROT16
board.
Other I/O boards are installed starting from the most right slot to allow extension of the EPS group.
The following boards may be equipped in a flexible shelf:
•
16xSTM–1e with or without EPS
•
4x140Mbit/s without EPS
•
all kinds of STM–N optical boards protected or unprotected
Commissioning and reconfiguration is possible via remote access.
Figure 81. shows an example of a mixed electrical/optical shelf supporting EPS for the electrical ports.
21
CONGIHC B
2 3 4 5 6 7 8 9 10 1112131415161718 19 20
empty
empty
HPRROT16
Access 16 x STM–1e
Access 16 x STM–1e
Access 16 x STM–1e
Access 16 x STM–1e
not equipped
not equipped
not equipped
not equipped
not equipped
Access 2 x 140Mb/s
Access 2 x 140Mb/s
Access 2 x STM–4
Access 2 x STM–4
Access 2 x STM–4
Access 2 x STM–4
empty
CONGIHCA
1
23 2425 26 27 28 2930 31 323334 35 36 3738 3940
41
HCMATRIX B
HCMATRIX A
22
empty
Port 16xSTM–1e
Port 16xSTM–1e
Port 16xSTM–1e
Port 16xSTM–1e
Port 16xSTM–1e
not equipped
not equipped
not equipped
not equipped
not equipped
Port 4 x 140Mbit/s
Port 4 x 140Mbit/s
Port 4 x STM–4
Port 4 x STM–4
Port 4 x STM–4
Port 4 x STM–4
empty
P W WW W
48
49
HCLINKE 4A
50
HCLINKE 4B
47
HCLINKE 3B
HCLINKE 2A
46
HCLINKE 3A
HCLINKE 1B
45
HCLINKE 2B
44
BTERM
43
HCLINKE 1A
P W W WW
42
W Working
P Protecting
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 81. 1670SM: Flexible Shelf equipped with 16xSTM–1e EPS protected and other I/O Boards
ED
03
3AG 24163 BEAA PCZZA
531
153 / 531
12.1.5.4 Allowed Mix of I/O Boards
4x140Mbit
4xSTM–4
16xSTM–1o
16xSTM–1e EPSN+1
16xSTM–1e unprot.
4xSTM–1e EPS N+1
4xSTM–1e unprot.
I/O Board Type
unprot.
x
x
–
x
1)
x
x
4xSTM–1e
unprot.
x
x
–
x
1)
x
x
4xSTM–1e
EPS N+1
–
–
x
–
–
–
–
16xSTM–1e
unprot.
x
x
–
x
1)
x
x
16xSTM–1e
(N=1..15)
EPS N+1
1)
1)
–
1)
x
1)
1)
16xSTM–1o
x
x
–
x
1)
x
x
4xSTM–4
x
x
–
x
1)
x
x
1)
1AA 00014 0004 (9007) A4 – ALICE 04.10
4x140Mb unprot.
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Table 28. 1670SM: Allowed mix of I/O Boards
ED
According to Figure 81.
03
3AG 24163 BEAA PCZZA
531
154 / 531
To connect the 1670SM with the 1678MCC main shelf no HW modification in the 1670SM is needed. The
STM-64 interface of the 1670SM is compatible with the STM-64 interface on the 1678MCC, both standard
SDH-interfaces, and are used as link interfaces. In the 1678MCC the 4xSTM-64 I–64.1 boards are used
as link board to the 1670SM. Each port can be physically connected to one HCLINKE board in the 1670SM
shelf with an optical fibre.
In 1678MCC Release 3 the links between 1670SM and 1678MCC main shelf are statically assigned. The
4 leftmost I/O-slots in the 1670SM with a capacity of 4xSTM-16 are connected in the HO matrix of the
1670SM to the leftmost HCLINKE board copy A (refer to Figure 82. ). The next 4 I/O slots to the next link
board copy A and so on. For link protections the HCLINKE boards copy B are used and the HO matrix
connections are broadcasted to both corresponding link boards.
1
2 3 4 5 6 7 8 9 10 1112131415161718 19 20
21
22
23 2425 26 27 28 2930 31 323334 35 36 3738 3940
CONGIHC copyB
empty
CONGIHC copyA
Accesscards
empty
empty
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
12.1.6 Connection to the Main Shelf
AccessArea
41
49
empty
HCMATRIX copyB
PortArea
50
HCLINKE 4B
I/O slots assigned
to VSR LINK 4
48
HCLINKE 4A
I/O slots assigned
to VSR LINK 3
47
HCLINKE 3B
HCLINKE 2B
46
BTERM
45
HCLINKE 3A
I/O slots assigned
to VSR LINK 2
44
HCLINKE 2A
I/O slots assigned
to VSR LINK 1
43
HCLINKE 1B
empty
42
HCLINKE 1A
HCMATRIX copyA
PortCards
LinkArea
Figure 82. Assignment of I/O Boards to the Link Boards
In the link area of the 1670SM the link boards copy A and B are ordered alternately, i.e. A–B–A–B.
Also the fibre connection from the HCLINKE board in the OED to one port of a 4xSTM-64 board in the main
shelf is assigned statically. The HCLINKE boards copy A in the 1670SM are connected to the ports of the
leftmost 4xSTM64 I/O board in the main shelf. If the links are protected the HCLINKE boards copy B in
the OED are connected to the second 4xSTM-64 I/O board in the main shelf.
All links are MSP protected but can optionally also be configured as unprotected.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The connection Main Shelf/1670SM is done via the following ’connection items’:
–
–
–
–
ED
Optical cables
On the Main Shelf side, the cables are plugged at the front of dedicated I/O boards 4xSTM–64
(I–64.1)
On the 1670SM side, the cables are plugged at the front of HCLINKE boards.
The connection may be unprotected or 1+1 MSP protected
03
3AG 24163 BEAA PCZZA
531
155 / 531
Figure 83. shows an example for a Main Shelf/1670SM connection 1+1 MSP protected.
Figure 84. shows an example for a Main Shelf/1670SM connection 1+1 MSP unprotected.
The number of 1670SM OEDs which can be connected to one 1678MCC main shelf is limited by the I/O
ports used as link ports in the 1678MCC main shelf.
The 1678MCC main shelf offers 16 x 4 = 64 STM–64 ports which can be used as STM–64 link ports to
an 1670SM OED. Depending on the number of link modules equipped per 1670SM OED shelf,
16...64 OED shelves can be connected to the 1678MCC main shelf with links unprotected, or 8...32 OED
shelves with links protected, respectively.
OED: 1670SM
49
HCMATRIX copyB
empty
50
HCLINKE 4B
I/O slots assigned
to VSR LINKs 4
HCLINKE 3B
48
HCLINKE 4A
I/O slots assigned
to VSR LINKs 3
I/O slots assigned
to VSR LINKs 2
I/O slots assigned
to VSR LINKs 1
empty
FAN
HCLINKE 3A
11 12 13 14 15 16 1718 19 20
46 47
45
BTERM
10
44
HCLINKE 2B
8 9
43
HCLINKE 2A
5 6 7
HCLINKE 1A
1 2 3 4
41
PSF
42
4 4
HCLINKE 1B
3 3
LAX20/40 Copy A (optional)
2 2
23 2425 26 27 28 29 30 31 32 33 34 35 36 37 38 3940
25
LAX20/40 Copy B (optional)
FLCCONGI
1
MX160/320/640 Copy A
4 x STM64 I–64.1 copy B
1
24
22
MX160/320/640 Copy B
PSF
FLCSERV
4 x STM64 I–64.1 copy A
FAN
21
CONGIHC B
Main Shelf
2 3 4 5 6 7 8 9 10 1112 1314 15 161718 19
CONGIHCA
1
HCMATRIX copyA
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Number of connected 1670SM Shelves
Capacity: 1xSTM–64 per Link
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 83. Example for a Connection Main Shelf /1670SM (4 links, 1+1 MSP full protected)
ED
03
3AG 24163 BEAA PCZZA
531
156 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1AA 00014 0004 (9007) A4 – ALICE 04.10
ED
24
1
2
3
4
5 6 7
8 9
11 12 13 14 15 16 1718 19 20
MX160/320/640 Copy B
LAX20/40 Copy A (optional)
45
I/O slots assigned
to VSR LINKs 2
46
47
HCLINKE 3A
I/O slots assigned
to VSR LINKs 3
49
I/O slots assigned
to VSR LINKs 4
50
empty
157 / 531
CONGIHC B
21
41
HCMATRIX copyB
OED: 1670SM
48
HCLINKE 4A
2 3 4 5 6 7 8 9 10 1112 1314 15 161718 19
44
HCLINKE 2A
1
43
I/O slots assigned
to VSR LINKs 1
CONGIHCA
23 2425 26 27 28 29 30 31 32 33 34 35 36 37 38 3940
empty
PSF
22
42
HCLINKE 1A
25
LAX20/40 Copy B (optional)
FLCCONGI
HCMATRIX copyA
BTERM
Main Shelf
MX160/320/640 Copy A
FAN
10
FAN
Capacity: 1xSTM–64 per Link
3AG 24163 BEAA PCZZA
531
Figure 84. Example for a Connection Main Shelf /1670SM (4 links, unprotected)
1 2 3 4
03
PSF
FLCSERV
4 x STM64 I–64.1
12.1.7 Part List
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The Part List is subdivided in three tables, specifically:
•
in Table 29. on page 159 is shown the Main part list
•
in Table 30. on page 160 is shown the Accessory list
•
in Table 31. on page 161 is shown the Explanatory notes of previous lists.
Furthermore, for any item the position and the maximum quantity that can be allocated inside the
equipment are indicated too.
Such tables report the following information:
ED
•
Description: name of items
•
Acronym: it is used to identified units and modules on the Craft Terminal applications
•
ANV Part/Number
•
Max Q.ty: maximum quantity of items in the 1670SM equipment
•
Slot: position of the board inside the 1670SM equipment (refer to Figure 79. on page 147)
•
Notes: are listed a set of explanatory notes.
03
3AG 24163 BEAA PCZZA
531
158 / 531
Table 29. Main part list
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
NAME
ACRONYM
ANV P/N
Factory P/N
Max.
Qty
SLOT
NOTE
MECHANICAL STRUCTURE
1670SM MAIN SHELF
SR70M
3AL 79245 AA––
1
––
1
ASEL FANS SUBRACK
––
3AN 52347 AA––
4
––
2
OPTINEX RACK WITH TRU
––
3AN 44815 AA––
1
––
3
IDSHELF
3AL 79242 AA––
1
––
4
SHELF IDENTIFICATION
COMMON PARTS
CONTROL & GENERAL I/F HC
CONGIHC
3AL 79135 AA––
2
1, 21
5
ASEL CONTROL & GENERAL I/F HC
3WIRE
CONGIHC
3AL 79135 AB––
2
1, 21
5
1670SM OPTICAL LINK ENH FC/PC
HCLINKE
3AL 81509 AA––
8
1670SM OPTICAL LINK ENH SC/PC
HCLINKE
3AL 81509 AB––
8
42 ÷ 45,
47 ÷ 50
42 ÷ 45,
47 ÷ 50
6
6
SWITCHING MATRIX
MATRIX HI–CAP
HCMATRIX
3AL 78938 AA––
2
22, 41
7
SPARE PARTS
TERMINATION BUS
BTERM
3AL 79076 AA––
1
46
8
EXTRACTORS KIT
––
3AL 79497 AA––
1
––
––
TRAFFIC PORTS: STM–1 (SDH)
16 x STM–1 OPTIC. / EL. PORT
16 x STM–1 OPTICAL COMPACT
PORT
4 x 140/STM–1 SWITCH. O/E PORT/1
4 x STM–1 ELECTRICAL PORT
P16S1N
3AL 79152 AA––
16
24 ÷ 39
9
P16OS1
3AL 80948 AA––
16
24 ÷ 39
10
P4E4N
3AL 79263 AA––
16
24 ÷ 39
11, 12
P4ES1N
3AL 78823 AA––
16
24 ÷ 39
25
16
24 ÷ 39
13
TRAFFIC PORTS: STM–4 (SDH)
4 x STM–4 PORT
P4S4N
3AL 79176 AA––
ACCESS BOARDS (CONNECTION MODULES)
2 x140/STM–1 OPT./EL. ADAPTER
A2S1
3AL 78818 AA––
16
4 ÷ 19
14
2 x STM–4 ACCESS
A2S4
3AL 79177 AA––
16
4 ÷ 19
15
4 x STM–1 EL
A4ES1
3AL 78835 AA––
16
4 ÷ 19
26
16 x STM–1 ELECTRICAL ACCESS
A16ES1
3AL 80492 AA––
16
4 ÷ 19
16
HIGH SPEED PROTECTION
HPROT
3AL 78849 AA––
3
4 ÷ 19
17
HPROT16
3AL 81269 AA––
3
4 ÷ 19
17
16
4 ÷ 19
18
256
––
19
256
––
20
16 x HIGH SPEED PROTECTION
12 x STM–1 OPTICAL ACCESS
A12OS1
3AL 80949 AA––
COMPACT
STM–N ELECTRICAL/OPTICAL MODULES
1AA 00014 0004 (9007) A4 – ALICE 04.10
140/155MB ELECTRICAL INTERF.
ICMI
3AL 37558 AB––
OPTO TRX SFP S–1.1 PLUG–IN
SS–1.1
1AB 19467 0001
OPTO TRX SFP L–1.1 PLUG–IN
SL–1.1
1AB 19467 0002
OPTO TRX SFP L–1.2 PLUG–IN
SL–1.2
1AB 19467 0003
ED
03
3AG 24163 BEAA PCZZA
531
159 / 531
NAME
ACRONYM
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
S–4.1 OPTICAL INTERF. FC/PC
ANV P/N
Factory P/N
Max.
Qty
SLOT
NOTE
64
––
21
Max.
Qty
SLOT
8
––
3AL 79340 AA––
S–4.1 OPTICAL INTERF. SC/PC
IS–4.1
3AL 79451 AA––
S–4.1 OPTICAL INTERF. LC
3AL 91793 AA––
L–4.1 OPTICAL INTERF. FC/PC
3AL 79452 AA––
L–4.1 OPTICAL INTERF. SC/PC
IL–4.1
3AL 79452 AB––
L–4.1 OPTICAL INTERF. LC
3AL 91794 AA––
L–4.2 OPTICAL INTERF. FC/PC
3AL 79453 AA––
L–4.2 OPTICAL INTERF. SC/PC
IL–4.2
L–4.2 OPTICAL INTERF. LC
3AL 79453 AB––
3AL 91795 AA––
Table 30. Accessories list
NAME
ACRONYM
ANV P/N
Factory P/N
NOTE
EQUIPMENT ACCESSORIES
FAN UNIT
FOR FANS SHELF 21”
ASEL FAN LEVEL 3WIRE
PROTECTION
FOR FANS SHELF 21”
DUMMY PLATE W20 (h 290)
DUMMY PLATE W40 (h 140)
1AA 00014 0004 (9007) A4 – ALICE 04.10
INSTALLATION KIT 1670SM for OPTINEX RACK
INSTALLATION KIT 1670SM for
1678MCC RACK
ED
FAN
3AL 79114 AA––
FAN
3AL 79114 AB––
––
3AN 50121 AA––
4
––
––
3AN 49397 AA––
35
––
23
––
3AN 49587 AA––
8
––
24
––
3AL 79486 AA––
1
––
––
––
3AL 81819 AA––
1
––
––
22
03
3AG 24163 BEAA PCZZA
531
160 / 531
Table 31. Parts list: explanatory notes
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Note Explanation
ED
1
It is the equipment shelf. It includes the back panel and a W10 dummy plate.
2
Placed under the 1670SM Shelf, it is mandatory and does not include its accessories (two
FAN Units and one Protection).
3
OED rack for 1670SM and 1662SMC.
4
One Shelf ID per 1670SM shelf mandatory.
5
Delivers two voltage levels to all the boards.
Provides external connectors for housekeepings, rack lamps, Q interface, LAN interface.
A mixed configuration of two types of CONGIHC (3–wire and 2–wire) in the same 1670SM equipment is not allowed.
6
Needed for connection to the 1678 main shelf.
7
Two HCMATRIX boards are used in an 1+1 protected EPS configuration; the board performs
connection and cross–connection functionalities and moreover synchronization functionalities.
8
This is a spare part item.
The 1670SM Shelf already includes it.
9
This board needs an access board (A16ES1) for 16xSTM–1 electrical connections.
10
This board manages up to sixteen STM–1 optical streams (numbered from Ch.1 to Ch.4).
It needs up to four SFP optical modules to be fully equipped and the others twelve SFP optical
modules have to be inserted on the relevant A12OS1 access board (numbered from Ch.5 to
Ch.16).
11
The port needs four (electrical or optical) modules to be fully connected. Two modules have
to be inserted on the board front panel and two on the corresponding access board 2xSTM–1
front panel (A2S1). Notice that different kind of access module (electrical and optical, also of
different characteristic and connectors) can be inserted in the port board or in the access
board.
12
Each port of this board can be configurated as 140 Mbit/s or STM–1.
13
The port needs four optical modules to be fully connected. Two modules have to be inserted
on the board front panel and two on the corresponding access board 2xSTM–4 front panel
(A2S4). Notice that different kind of access module (also of different characteristic and connectors) can be inserted in the port board or in the access board.
14
This board needs up to 2 (electrical or optical) 140Mbit/s or STM–1 modules in the front panel,
numbered from top to bottom; this board is used for the 4x140/STM–1 O/E port (P4E4N).
15
This board needs up to 2 optical STM–4 modules in the front panel, numbered from top to bottom; this board is used for the 4xSTM–4 port (P4S4N).
16
HS access board to be used for the 16xSTM–1 optical/electrical port (P16S1N). Allows the
bidirectional connection of up to 16 channels.
17
This board is used in an EPS protection scheme as access board for High Speed STM–1
electrical spare port (HPROT for P4ES1 and HPROT16 for P16S1).
18
This board is used in conjunction to the relevant 16xSTM–1 compact port (P16OS1).
It needs up to twelve SFP optical modules to be fully equipped (numbered from Ch.5 to
Ch.16).
19
Up of 2 of these modules are inserted on the following boards P4E4N and A2S1 to realize
electrical connections for a maximum of 2 STM–1 channels (one for module).
03
3AG 24163 BEAA PCZZA
531
161 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Note Explanation
ED
20
Up of to 4 of these SFP modules are inserted on P16OS1 board and up of to 12 of these modules are inserted on A12OS1 access board. They realize optical STM–1 connections.
21
Up of 2 of these modules are inserted on the boards P4S4N and A2S4 to realize optical connections for a maximum of 4 STM–4 channels (one for module). Optical modules supplied
with different connectors (SC/PC or FC/PC).
22
Accessories of FANs Subracks.
23
It is essential to insert the relevant dummy plates on the spaces left by all boards (port or access board) not supplied in order to obtain the EMI/EMC performances.
24
Dummy plate for unequipped HCLINKE board.
25
This board needs an access board (A4ES1) for 4xSTM–1 electrical connections.
26
HS access board to be used for the 4xSTM–1 electrical port (P4S1N). Allows the bidirectional
connection of up to 4 channels.
03
3AG 24163 BEAA PCZZA
531
162 / 531
12.1.8 Units Front View
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
This paragraph shows the access points (LEDs, switches etc.) present on each units together with legend
and meaning.
Figure 85. on page 164 through Figure 97. on page 176 illustrate units front view available in the 1670SM
Equipment.
Figure 101. on page 178 shows the pluggable module available in the 1670SM Equipment.
Note: The unit dimensions in all figures are not the real ones.
ED
03
3AG 24163 BEAA PCZZA
531
163 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
P4E4N
P4S4N
SLOTS
24 to 39
(1)
(2)
(1) Channel #1 (refer to Note)
(2) Channel #2 (refer to Note)
(3) Bicolor LED
Red: The system control
detected a board error,
local board alarm (INT)
Green: The board is in service
(3)
1AA 00014 0004 (9007) A4 – ALICE 04.10
NOTE:
The P4E4N board can be equipped with electrical modules (refer to Figure 99. ).
The P4S4N board can be equipped with optical modules (refer to Figure 100. ).
Figure 85. 4x140/STM-1 Switchable E/O Port Board or 4xSTM-4 Port Board – Front View
ED
03
3AG 24163 BEAA PCZZA
531
164 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
SLOTS
P4ES1
24 to 39
P16S1N
24 to 39
1AA 00014 0004 (9007) A4 – ALICE 04.10
(1)
Bicolor LED
Red: The system control
detected a board error,
local board alarm (INT)
Green: The board is in service
(1)
Figure 86. 4xSTM-1 E/16xSTM-1 E/O Port Board – Front View
ED
03
3AG 24163 BEAA PCZZA
531
165 / 531
SLOTS
P16OS1
24 to 39
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(1)
Bicolor LED
Red: The system control
detected a board error,
local board alarm (INT)
Green: The board is in service
(2) to (5) STM−1 optical channel (refer to Note)
(from channel #1 to channel #4)
(6) to (9) Laser restart key
(from channel #1 to channel #4)
(1)
1AA 00014 0004 (9007) A4 – ALICE 04.10
Note: Others twelve STM91 channels are on A12OS1 access board
(refer to Figure 91. on page 170)
The cavities must be equipped with STM91 optical SFP module
plug9in (refer to Figure 101. on page 178)
Figure 87. 16xSTM–1 COMPACT optical Port Board – front view
ED
03
3AG 24163 BEAA PCZZA
531
166 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
SLOTS
A2S1
4 to 19
A2S4
4 to 19
(1)
(2)
(1) Channel #3 (refer to Note)
(2) Channel #4 (refer to Note)
(3) Bicolor LED
Red: The system control
detected a board error,
local board alarm (INT)
Green: The board is in service
(3)
NOTE:
The A2S1 board can be equipped with electrical modules (refer to Figure 99. ).
The A2S4 board can be equipped with optical modules (refer to Figure 100. ).
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 88. 2x140Mbit/s/STM-1/STM-4 Access Board Optical – Front View
ED
03
3AG 24163 BEAA PCZZA
531
167 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
A4ES1
SLOTS
4 to 19
INPUT
OUTPUT
(1)
(2)
INPUT
OUTPUT
(3)
INPUT
OUTPUT
INPUT
(4)
OUTPUT
1AA 00014 0004 (9007) A4 – ALICE 04.10
(1) to (4)
(5)
STM91 electrical Channel
Bicolor LED:
Red:
The system control detected a board error,
local board alarm (INT)
Green: The board is in service
(5)
Figure 89. 4xSTM–1 Electrical 75 Ohm Access Board – Front View
ED
03
3AG 24163 BEAA PCZZA
531
168 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
A16ES1
SLOTS
4 to 19
INPUT
OUTPUT
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
1AA 00014 0004 (9007) A4 – ALICE 04.10
(1) to (16)
(17)
STM91 electrical Channel
Bicolor LED:
Red:
The system control detected a board error,
local board alarm (INT)
Green: The board is in service
(17)
Figure 90. 16xSTM-1 Electrical 75 Ohm Access Board – Front View
ED
03
3AG 24163 BEAA PCZZA
531
169 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
A12OS1
SLOTS
4 to 19
(1)
(14)
(2)
(15)
(3)
(16)
(4)
(17)
(5)
(18)
(6)
(19)
(7)
(20)
(8)
(1) to (12) STM91 optical channel (refer to Note)
(from channel #5 to channel #16)
(14) to (25) Laser restart key
(from channel #5 to channel #16)
(13) Bicolor LED
Red: The system control
detected a board error,
local board alarm (INT)
Green: The board is in service
(21)
(9)
(22)
(10)
(23)
(11)
(24)
(12)
(25)
1AA 00014 0004 (9007) A4 – ALICE 04.10
Note:
(13)
First four STM91 channels are on P16OS1 port board
(refer to Figure 87. on page 166)
The cavities must be equipped with STM91 optical SFP
module plug9in (refer to Figure 101. on page 178)
Figure 91. 12xSTM-1 COMPACT optical Access Board – Front View
ED
03
3AG 24163 BEAA PCZZA
531
170 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
SLOTS
HPROT
4 to 19
HPROT16
4 to 19
(1)
Bicolor LED
Red: The system control
detected a board error,
local board alarm (INT)
Green: The board is in service
(1)
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 92. High-Speed Protection Board – Front View
ED
03
3AG 24163 BEAA PCZZA
531
171 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
SLOT
BTERM
46
(1)
(1)
Bicolor LED
Red: The system control
detected a board error,
local board alarm (INT)
Green: The board is in service
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 93. Bus Termination Board – Front View
ED
03
3AG 24163 BEAA PCZZA
531
172 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
HCMATRIX
SLOTS
22 and 41
(1)
(3)
(2)
(1)
(2)
(3)
For factory and maintenance only.
Reset command key.
Multicolor LED
Red: The system control
detected a board error,
local board alarm (INT)
Green: The board is in service (main)
Yellow: The board is in stand by (spare)
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 94. HiCap Matrix Board – Front View
ED
03
3AG 24163 BEAA PCZZA
531
173 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
FC/PC
ACRONYM
SLOTS
HCLINKE
42 to 45
47 to 50
(1)
HCLINKE main: slot 42, 44, 47, 49
HCLINKE spare: slot 43, 45, 48, 50
(2)
(3)
INPUT
OUTPUT
(1)
(2)
(3)
Bicolor LED
Red: The system control
detected a board error,
local board alarm (INT)
Green: The board is in service
Laser Restart Key
Optical IN/OUT 10 GBit/s signal
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 95. Optical Link Enhanced Board – Front view
ED
03
3AG 24163 BEAA PCZZA
531
174 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
SLOTS
CONGIHC
1, 21
(1)
CONGIHC/A Slot 1
CONGIHC/B Slot 21
(8)
(1)
Power (−48/60 V)
(2)
Housekeeping and remote alarm (only used in slot 1)
(3)
Rack lamp (only used in slot 1)
(4)
Shelf Identifier block (not used in slot 1)
(5)
not used (external LAN, 10Base2)
(6)
not used (external LAN, 10Base2)
(7)
External LAN (Slot 1), 10BaseT
IP or Q interface (single LAN configuration)
Customer’s LAN (Slot 21), 10BaseT (optionally)
only Q interface (separated LAN configuration
(2)
(9)
(3)
(4)
(10)
(8)
Auxiliary housekeeping (8 + 8), connector for FAN alarm cable
(9)
not Used
(10) Internal LAN 9 10baseT (link #1) − Main LAN
(11) not used
(12) not used
(5)
(11)
(6)
(12)
(7)
(13)
(13) Internal LAN 9 10baseT (link #2) − Redundant LAN
(14) Bicolor LED
Red: The system control
detected a board error,
local board alarm (INT)
Green: The board is in service
(14)
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 96. Control and Generic Interface Board – Front View
ED
03
3AG 24163 BEAA PCZZA
531
175 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
(1) (2) (3) (4) (5)
(6)
(7)
Fans Unit #1
(8)
Fans Unit #2
LEGENDA:
(1) (2) (3) (4) (5) (6)
(1) Red LED – (NURG) – not used or not present
(2) Red LED – Urgent alarm (URG)
(3) Yellow LED – Alarm storing (ATTD)
(4) Alarm storing push–botton (Attended)
(5) Red LED – not used or not present
(6) Red LED – fans Urgent alarm (URG–V)
(7) WARNING label: windage (air suction)
(8) WARNING label: moving mechanical parts
Figure 97. FANs Subrack Cover – Front View
Rotary Switch
for ID
Connector SUB9D
159pin, male
1AA 00014 0004 (9007) A4 – ALICE 04.10
Shelf ID Connector
is connected on
CONGIHC Board B
(Slot 21)
Figure 98. Shelf ID Connector for 1670SM
ED
03
3AG 24163 BEAA PCZZA
531
176 / 531
EQUIPPED
on CARDS
ICMI
P4E4N
A2S1
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
MODULE
ACRONYM
Input
Output
Figure 99. Electrical pluggable module
MODULE
ACRONYM
IS–41
IL–41
IL–42
Optical Module FC/PC
EQUIPPED
on CARDS
P4S4N
A2S4
Input
Output
Laser Restart Key
Optical Module LC
Optical Module SC/PC
Laser Restart Key
Input
Output
Output
Input
1AA 00014 0004 (9007) A4 – ALICE 04.10
Laser Restart Key
Figure 100. STM–4 Optical Modules
ED
03
3AG 24163 BEAA PCZZA
531
177 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1AA 00014 0004 (9007) A4 – ALICE 04.10
ED
MODULE
ACRONYM
P16OS1
A12OS1
EQUIPPED
on CARDS
Optical cables
TRX STM–1 SFP module
Figure 101. Optical SFP module
SS–1.1
SL–11
SL–12
03
3AG 24163 BEAA PCZZA
531
178 / 531
12.2 1662SMC Shelf
The 1662SMC is a single row construction. The mechanical integration is such that the 1662SMC is
housed in 600x300 mm racks. Back to back and stand alone application of OED-Racks will be supported.
EMC shielding is done on shelf level. The 1662SMC shelves are indoor equipment and it is recommended
to be installed in a air conditioned location.
It must be noted that max 504x2 Mbit/s ports can be equipped in one shelf (unprotected configuration).
In the configuration with EPS max 378x2 Mbit/s ports can be equipped.
The layout of the 1662SMC shelf is shown in Figure 102.
1662SMC
6
7
8
9 10 11 12 13 14
*
15
16 17 18 19 20
Access
Access
Access
Access
CONGI
5
B
SYNTH16 copyB
3 4
Port
Port
Port
Port
Port
Port
Port
Port
2
A
SYNTH16 copyA
1
CONGI
Access
Access
Access
Access
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
12.2.1 Shelf Layout
* Slot 21 and 22 for
BUSTERM board
(behind SYNTH16)
*
Figure 102. 1662SMC Shelf: Face Layout
12.2.2 1662SMC: Basic Equipment
1AA 00014 0004 (9007) A4 – ALICE 04.10
Table 32. 1662SMC: Basic Equipment
Slot
Board
Mnemonic
Comment
1
Control & General I/F Board
CONGI
Mandatory
2 ... 5
Access boards 63x2Mbit/s
A63x2E1A/B
6
Compact STM–16 copy A
SYNTH16
7 ... 14
Port boards 63x2Mbit/s
P63E1/N/N–M4
15
Compact STM–16 copy B
SYNTH16
16 ... 19
Access boards 63x2Mbit/s
A63x2E1A/B
20
Control & General I/F Board
CONGI
Mandatory
21, 22
Termination Bus 1662
T_BUS
Mandatory
Cooling
A separate FAN subrack is mounted at the bottom of each 1662SMC
ED
Mandatory
Mandatory
03
3AG 24163 BEAA PCZZA
531
179 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
12.2.3 Basic Function of the Boards
CONGI (Control and General Interface)
–
Provides power supply interfaces and power supply distribution
–
Provides the external LAN interface
A Shelf Identifier is plugged on the CONGI in slot 20 (Q2 interface)
SYNTH16
SYNTH16 board includes:
–
SDH matrix
The matrix implements the Cross-Connect functions. The full non blocking matrix allows
cross-connections of up to 96x96 STM-1 equivalents at High Order level and up to 64x64 STM-1
equivalents at Low Order level between all traffic ports.
–
Clock reference and
–
Equipment control functions.
BUSTERM (Termination Bus)
–
Provides voltage logical reference to all Control and Auxiliary buses
The board is mandatory and is located behind the SYNTH16 board (not visible in front view)
Access board
–
Line Interface:
Access boards are used together with the 2 Mbit/s interfaces
–
Protection board (LPROT)
Port board
–
Transport, adaptation and termination functions
–
Matrix selection
I/O Interfaces
1AA 00014 0004 (9007) A4 – ALICE 04.10
The 1662SMC integration of this Release supports only 2 Mbit/s interfaces.
ED
03
3AG 24163 BEAA PCZZA
531
180 / 531
12.2.4 System Configurations
Interface
Port Boards
Access Boards
1 slot
63
1 slot
63
Port standard
Port with retiming
function
HM 75Ohm or 120Ohm
with retiming
function
1 slot
1 slot
63x2Mbit/s
....
Port with retiming
function
1 slot
63x2Mbit/s
Standard
1
Access K20
Standard
63x2Mbit/s
63
63 x 2Mbit/s
HM 120Ohm
1 slot
....
Access standard
1 slot
63x2Mbit/s
K20
1
63 x 2Mbit/s
Standard
63x2Mbit/s
....
63 x 2Mbit/s
HM 75Ohm or 120Ohm
Standard
1
Access K20
63x2Mbit/s
....
Port standard
63x2Mbit/s
....
63 x 2Mbit/s
Access standard
63
Connectors
1 slot
....
....
1
63x2Mbit/s
....
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
12.2.4.1 Supported I/O Boards, relation Access/Port Boards
HM 120Ohm
with retiming
function
K20
2 slot
1 x STM–16
SYNTH16
S–16.1
FC/PC
SC/PC
Used only for the connection to the Main Shelf
Figure 103. 1662SMC: I/O Boards. Relation Access/Port Boards
12.2.4.2 Relation Access Board/Port Board
1AA 00014 0004 (9007) A4 – ALICE 04.10
Table 33. 1662SMC: Relation Access / Port Boards
ED
Slot Access Board
2
3
4
5
16
17
18
19
Slot Port Board
7
8
9
10
11
12
13
14
03
3AG 24163 BEAA PCZZA
531
181 / 531
12.2.4.3 Configuration Rules
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Table 34. 1662SMC: Configuration Rules
–
Capacity of the Shelf: 16 STM–1eq.
(Actually needed capacity in the 1678MCC application R3: 8 STM–1equiv.)
–
Max. number of 1662SMC which can be attached to the Main Shelf: 32
This number is limited by the max. capacity of the LO matrix: 256STM–1 eq.
–
Only 2Mbit/s boards are supported
–
Each slot has a capacity of 2 STM–1eq.
–
The 2Mbit/s I/O interfaces consists of port and access boards.
–
The 2 Mbit/s port and access boards are available in different versions as shown in Figure 103.
–
EPS 1:n (n=1...3). One or two protection groups are possible
–
The protection access board LPROT may be located in slots 2 to 5, resp. 18 to 21. The protection I/O
port board have to be inserted in a slot at the most left of the protected port boards group. (for
relation of access and port board ref. Table 33. )
Dummy Plates
–
The slots which are not equipped must be closed by a dummy plate for EMC reasons
Connection to
the Main Shelf
–
The connection to the Main Shelf is done via the SYNTH16 (S–16.1) boards: the connection cables
are plugged at the front of the SYNTH16
–
Capacity of the SYNTH16 board: 16 STM–1eq.
Capacity
I/O Boards
I/O Protection
Face Layout of the Shelf equipped with 2Mbit/s I/O Boards
9
10 11 12 13 14
15
B
SYNTH16 copyB
8
WW W W W W W W
WW W W
16 17 18 19 20
Access 63 x 2Mb/s
Access 63 x 2Mb/s
Access 63 x 2Mb/s
Access 63 x 2Mb/s
CONGI copyB
7
2Mb/s
2Mb/s
2Mb/s
2Mb/s
2Mb/s
2Mb/s
2Mb/s
2Mb/s
6
x
x
x
x
x
x
x
x
5
63
63
63
63
63
63
63
63
4
Port
Port
Port
Port
Port
Port
Port
Port
3
A
SYNTH16 copyA
2
CONGI copyA
Access 63 x 2Mb/s
Access 63 x 2Mb/s
Access 63 x 2Mb/s
Access 63 x 2Mb/s
1
W W WW
Figure 104. 1662SMC Equipment: Unprotected Configuration with 2Mbit/s
6
7
8
9
10 11 12 13 14
15
16 17 18 19 20
LPROT
Access 63 x 2Mb/s
Access 63 x 2Mb/s
Access 63 x 2Mb/s
CONGI copyB
5
B
SYNTH16 copyB
4
A
SYNTH16 copyA
3
prot. Port 63 x 2Mb/s
Port 63 x 2Mb/s
Port 63 x 2Mb/s
Port 63 x 2Mb/s
prot. Port 63 x 2Mb/s
Port 63 x 2Mb/s
Port 63 x 2Mb/s
Port 63 x 2Mb/s
2
CONGI copyA
LPROT
Access 63 x 2Mb/s
Access 63 x 2Mb/s
Access 63 x 2Mb/s
1
W: Working
1AA 00014 0004 (9007) A4 – ALICE 04.10
P: Protection
P W WW
P W W W P WW W
P W WW
Figure 105. 1662SMC Equipment: Protected Configuration with 2Mbit/s
ED
03
3AG 24163 BEAA PCZZA
531
182 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
12.2.4.4 Connection to the Main shelf
In deviation to the 1670SM where the link capacity is STM-64, the capacity for each link for the 1662SMC
is STM-16. As link board in the 1662SMC the STM-16 I/O board (SYNTH16) is used which is connected
with fibres to one port of the 16xSTM-16 I/O board in the main shelf of the 1678MCC.
The link can be configured in a flexible way, i.e. the STM-16 ports can be chosen in an arbitrary way.
The links are MSP protected. Two (SYNTH16) boards using a STM-16 interface in the 1662SMC are
connected with two fibres to two different STM-16 ports on possibly different 16xSTM-16 boards in the
1678MCC (refer to Figure 106. ).
The synchronization between OED and main-shelf is done via the STM-16 links. No additional cabling is
required. The clock source can be either selected from an I/O port at the OED and the synchronization
is transmitted over the link to the main-shelf which selects the link as clock source, or vice versa. The
STM-16 links allow a complete SSM handling for synchronization.
The connection main shelf/1662SMC is done via the following ’connection items’:
–
–
–
–
Optical cables.
On the Main Shelf side, the cables are plugged at the front of dedicated I/O boards 16xSTM-16
(S–16.1)
On the 1662SMC side, the cables are plugged at the front of the SYNTH 16 boards (S–16.1).
The connection may be unprotected or 1+1 MSP protected.
Figure 106. shows an example for a Main Shelf/1662SMC connection 1+1 MSP protected.
Figure 107. shows an example for a Main Shelf/1662SMC connection 1+1 MSP unprotected.
Main Shelf
PWI
LAX40 copyB
LAX40 copyA
FLCCONGI
11 12 13 14 15 16 17 18 19 20
FAN
1 2 3 4 5
7 8 9 10 11 12 1314
Access
Access
Access
Access
CONGI copyB
9 10
Port
Port
Port
Port
Port
Port
Port
Port
SYNTH16 copyBB(S–16.1)
8
MX160/320/640 Copy B
..
..
1662SMC
CONGI copyA
Access
Access
Access
Access
SYNTH16 copyAA(S–16.1)
1 2 3 4 5
..
..
25
MX160/320/640 Copy A
FLCSERV
24
16xSTM–16 S–16.1 copyA
16xSTM–16 S–16.1 copyB
PWI
FAN
16 17 18 19 20
1AA 00014 0004 (9007) A4 – ALICE 04.10
Capacity: 1xSTM–16 per Link
Figure 106. Connection Main Shelf/1662SMC (1+1MSP protected)
ED
03
3AG 24163 BEAA PCZZA
531
183 / 531
Main Shelf
PWI
LAX40 copyB
LAX40 copyA
FLCCONGI
11 12 13 14 15 16 17 18 19 20
FAN
1 2 3 4 5
7 8 9 10 11 1213 14
Access
Access
Access
Access
CONGI copyB
9 10
Port
Port
Port
Port
Port
Port
Port
Port
SYNTH16 copyBB(S–16.1)
8
MX160/320/640 Copy B
..
.
1662SMC
CONGI copyA
Access
Access
Access
Access
SYNTH16 copyAA(S–16.1)
1 2 3 4 5
25
MX160/320/640 Copy A
FLCSERV
24
16xSTM–16 S–16.1 copyA
PWI
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
FAN
16 17 18 19 20
Capacity: 1xSTM–16 per Link
Figure 107. Connection Main Shelf/1662SMC (unprotected)
Number of connected 1662SMC Shelves
The number of OEDs which can be connected to one 1678MCC main shelf is limited by the I/O ports used
as link ports in the 1678MCC main shelf. For 1662SMC OEDs, an additional limit is given by the LO matrix
capacity offered by the 1678MCC main shelf (max. 160G).
For the 1662SMC integration the 1678MCC main shelf offers 16x16 = 256 STM–16 ports which can be
used as STM–16 link ports. Theoretically 256 1662SMC OEDs could be connected unprotected or
128 OEDs with a protected link. Because the 1662SMC OEDs are integrated to reuse the LO I/O ports
(2Mbit/s), the number of OEDs is restricted by the LO matrix capacity of the main shelf. In this release the
LO matrix capacity is max. 160G (1024 STM–1 equivalents).
1AA 00014 0004 (9007) A4 – ALICE 04.10
Because the 1662SMC uses only STM–8 capacity in the STM–16 link up to 128 1662SMC can be
connected to the main shelf to use 100% of the LO matrix capacity.
ED
03
3AG 24163 BEAA PCZZA
531
184 / 531
12.2.5 Part List
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The Part List is subdivided in three tables, specifically:
•
in Table 35. on page 186 is shown the Main part list
•
in Table 36. on page 187 is shown the Accessory list
•
in Table 37. on page 188 is shown the Explanatory notes of previous lists.
Furthermore, for any item the position and the maximum quantity that can be allocated inside the
equipment are indicated too.
Such tables report the following information:
ED
•
Description: name of items
•
Acronym: it is used to identified units and modules on the Craft Terminal applications
•
ANV Part/Number
•
Max Q.ty: maximum quantity of items in the 1662SMC equipment
•
Slot: position of the board inside the 1662SMC equipment (refer to Figure 102. on page 179)
•
Notes: are listed a set of explanatory notes
03
3AG 24163 BEAA PCZZA
531
185 / 531
Table 35. Main part list
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
NAME
ACRONYM
ANV P/N
Factory P/N
Max.
Qty
SLOT
NOTE
MECHANICAL STRUCTURE
1662SMC SHELF
SR62C
3AL 98009 AB––
1
––
1
FANS SHELF 19”
––
3AL 79773 AA––
1
––
2
OPTINEX RACK WITH TRU
––
3AN 44815 AA––
1
––
3
T_BUS
3AL 79088 AC––
2
21, 22
4
IDSHELF
3AL 79242 AA––
1
––
5
TERMINATION BUS/2
SHELF IDENTIFICATION
COMMON PARTS
CONTROL AND GENERAL I/F
COMPACT ADM 16
CONGI
3AL 78830 AD––
2
1, 20
6
SYNTH16
3AL 98038 AC––
3AL 98038 AD––
2
6, 15
7
1
––
8
SPARE PARTS
EXTRACTORS KIT
––
3AL 79497 AA––
TRAFFIC PORTS: LOW SPEED (PDH)
63x2 MBIT/S PORT
P63E1
3AL 79092 AA––
9
8
7 ÷ 14
63x2 MBIT/S G703/ISDN–PRA–FS
P63E1N
3AL 79092 AC––
PORT
LS (LOW SPEED) ACCESS BOARDS (CONNECTION MODULES)
63x2 MBIT/S PROT. 75 OHM HM
A63E1A
3AL 98029 AA––
63x2 MBIT/S PROT. 120 OHM HM
A63E1B
3AL 98035 AA––
63x2 MBIT/S PROT. 120 OHM HM K20
A63E1B
3AL 98051 AA––
LOW SPEED PROTECTION
LPROT
3AL 98026 AA––
8
2 ÷ 5,
16 ÷ 19
10
11
11, 12
2
2 ÷ 5,
16 ÷ 19
13
2
––
14
STM–N OPTICAL MODULES
1AA 00014 0004 (9007) A4 – ALICE 04.10
OPTO TRX SFP S–16.1 PLUG–IN
ED
SS–161
1AB 19637 0001
03
3AG 24163 BEAA PCZZA
531
186 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Table 36. Accessories list
NAME
ACRONYM
Max.
Qty
SLOT
NOTE
EQUIPMENT ACCESSORIES
FAN UNIT
FOR FANS SHELF 19”
METALLIC FAN GRID
INSTALLATION KIT FAN SHELF
1662SMC for OPTINEX RACK
INSTALLATION KIT FAN SHELF
1662SMC for 1678MCC RACK
INSTALLATION KIT 1662SMC for OPTINEX RACK
INSTALLATION KIT 1662SMC for
1678MCC RACK
1662SMC 19/21” ADAPTER
1662SMC FIBER INSTALLATION KIT
21”
2MB/S CABLING TOOLS
1AA 00014 0004 (9007) A4 – ALICE 04.10
ANV P/N
Factory P/N
ED
FAN
3AL 79772 AA––
4
––
15
––
3AL 81812 AA––
1
––
16
––
3AL 80807 AA––
1
––
––
––
3AG 24277 AA––
1
––
––
––
3AL 79463 AA––
1
––
––
––
3AL 91636 AA––
1
––
––
––
3AL 98097 AA––
1
––
17
––
3AL 98198 AA––
1
––
––
––
3AL 98162 AA––
1
––
––
03
3AG 24163 BEAA PCZZA
531
187 / 531
Table 37. Parts list: explanatory notes
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Note Explanation
ED
1
It is the equipment shelf. It includes the back panel.
2
Placed under the 1662SMC Shelf, it is mandatory and does not include its accessories (two
FAN Units and one Protection).
3
OED rack for 1670SM and 1662SMC.
4
Mandatory board, it is used to provide voltage logical reference to all control and auxiliary
busses.
5
One Shelf ID per 1662SMC shelf mandatory.
6
Delivers two voltage levels to all the boards. Only the CONGI in slot1 provides external connectors for housekeeping, rack lamps, Q interface, LAN interface. Both CONGI boards (slot1
and 20) deliver remote alarms.
7
Needed for connection to the 1678 main shelf. The board provides: 1xSTM–16 line interface,
equipment controller, shelf controller, matrix and synchronization function (1+1 protected EPS
configuration).
8
Tool used to extract the connectors.
9
To be used with access board A63E1. Each access board A63E1 are needed to fully connect
the port channels.
10
The board supports the NT functionality, performance monitoring and retiming on 2 Mbit/s
ISDN–PRA.
11
Protected LS access board. Allow bidirectional connection of up to 63x2 Mbit/s channels. To
be used in EPS protection configurations.
12
LS access board complaint with ITU K20 norms.
13
To be used in EPS protection schemes as access board for the LS electrical port (63x2 Mbit/
s).
14
Optical SFP module used on the SYNTH16 board.
15
Two FAN units for each 1662SMC shelf are necessary in the FAN shelf.
16
Metallic FAN grid.
17
Mechanical adapter utilized to insert the subrack in an 21” rack.
03
3AG 24163 BEAA PCZZA
531
188 / 531
12.2.6 Units Front View
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
This paragraph shows the access points (LEDs, switches etc.) present on each units together with legend
and meaning.
Figure 108. on page 190 through Figure 113. on page 195 illustrate units front view available in the
1662SMC Equipment.
Figure 114. on page 196 shows the pluggable module available in the 1662SMC Equipment.
Note: The unit dimensions in all figures are not the real ones.
ED
03
3AG 24163 BEAA PCZZA
531
189 / 531
P63E1
7 to 14
P63E1N–M4
7 to 14
1AA 00014 0004 (9007) A4 – ALICE 04.10
(1) Multicolor LED
Red led – local unit alarm
Green led – in service unit
Orange led –unit in Stand–by (EPS schema)
xxxxxx
SLOTS
3AL XXXXX AA
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
(1)
Figure 108. 63 x 2 Mbit/s Port Board – Front View
ED
03
3AG 24163 BEAA PCZZA
531
190 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
SLOTS
CONGI
1, 20
(1)
(2)
(3)
(4)
(1) Power
(5)
(2) Housekeeping and remote alarm
(3) Rack lamps (not used on CONGI in slot 20)
(4) QMD (Q2) (Fan alarm on CONGI in Slot 1)
(Shelf ID on CONGI in Slot 20)
(6)
1AA 00014 0004 (9007) A4 – ALICE 04.10
(7) Bicolor LED:
Red led – local unit alarm
Green led – in service unit
xxxxxx
(6) RJ45 for Q3 10 base T (not used on CONGI in slot 20)
3AL XXXXX AA
(5) I/O BNC for Q3 10 base 2 (not used on CONGI in slot 20)
(7)
Figure 109. Control and General Interface – Front View
ED
03
3AG 24163 BEAA PCZZA
531
191 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
SYNTH16
SLOTS
6, 15
(5)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
PC Connector (F interface)
Reset Command Key
Alarm Storing Pushbutton (Attended)
Lamp Test Pushbutton
Channel #1 (N.B.)
Red LED – Urgent Alarm (Critical or Major) (1)
Red LED – Not Urgent alarm (Minor)
Yellow LED – Alarm storing (Attended)
Yellow LED – Abnormal condition
Yellow LED – Indicative Alarm (Warning)
Green LED – when on, unit is active
when off, unit is standby
(2)
Bicolor LED:
Red led – local unit alarm
Green led – in service unit
(3)
U
NU
AT
AB
IN
R
(4)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
1AA 00014 0004 (9007) A4 – ALICE 04.10
N.B. The SYNTH16 board can be equipped with the SS–161 Module (refer to Figure 114. )
Figure 110. SYNTH16 Board – Front View
ED
03
3AG 24163 BEAA PCZZA
531
192 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
SLOTS
A63E1A (75 OHM)
2 to 5, 16 to 19
A63E1B (120 Ohm) 2 to 5, 16 to 19
(1)
(2)
(3)
(4)
(5)
(6)
(7)
1AA 00014 0004 (9007) A4 – ALICE 04.10
Channel # 1 –7
Channel # 8 – 14
Channel # 15 –21
Channel # 22 – 28
Channel # 29 – 35
Channel # 36 – 42
Channel # 43 – 49
Channel # 50 – 56
Channel # 57 – 63
(8)
xxxxxx
(9)
3AL XXXXX AA
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Figure 111. 63 x 2 Mbit/s Access Board – Front View
ED
03
3AG 24163 BEAA PCZZA
531
193 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
ED
LPROT
2 to 5, 16 to 19
(1)
Red led – local unit alarm
Green led – in service unit
xxxxxx
SLOTS
Bicolor LED:
531
3AL XXXXX AA
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ACRONYM
3AG 24163 BEAA PCZZA
(1)
Figure 112. Low Speed Protection Board – Front View
03
194 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
(1)
(2)
(4)
(5)
(6)
(1)
Multicolor LED
Red led – local unit alarm
Orange led – temperature major than 55 °C
Green led – in service unit
(2)
(3)
(4)
(5)
(6)
Battery A connector
Battery B connector
not used
Alarm connector
not used
(3)
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 113. FANs Subrack Cover – Front View
ED
03
3AG 24163 BEAA PCZZA
531
195 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
MODULE
ACRONYM
EQUIPPED
on CARDS
SS–161
SYNTH16
TRX STM–16 SFP MODULE
Optical cables
Figure 114. STM-16 optical SFP module
Rotary Switch
for ID
Connector SUB9D
159pin, male
Shelf ID Connector
is connected on
CONGI Board B
(Slot 20)
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 115. Shelf ID Connector for 1662SMC
ED
03
3AG 24163 BEAA PCZZA
531
196 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ED
03
3AG 24163 BEAA PCZZA
531
197 / 531
13 FUNCTIONAL DESCRIPTION
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.1 General Description
The boards equipped in 1678MCC are divided in the following types:
1.
2.
3.
Centralized Common boards
Equipment units
Traffic Ports SDH boards
13.1.1 Centralized Common Boards
The following boards are available; they are mandatory in the 1678MCC main shelf equipment about
control and connections:
•
First Level Controller and Service interfaces board (FLCSERV)
The board provides the following functionalities:
–
First Level Controller function (spare)
•
•
•
•
F interface for Local Craft Terminal (CT)
Communication with the Operation System (OS) through different interfaces (DCC,
QB3 etc.)
2 MHz Input/Output
First Level Controller and Control & General interfaces board (FLCCONGI)
The board provides the following functionalities:
–
First Level Controller function (main)
•
•
•
•
•
F interface for Local Craft Terminal (CT)
Communication with the Operation System (OS) through different interfaces (DCC,
QB3 etc.)
QB3 Interface
Housekeeping and Remote Alarm interface
Auxiliary Housekeeping interface
Note:
The two previous boards in main/spare configuration are provided (redundant EC); when the board
is in the “Active” state it manages the F interface.
•
High Capacity Matrix board
Three types of HO matrix boards exist:
1AA 00014 0004 (9007) A4 – ALICE 04.10
–
–
–
ED
MX640 with 4096 STM-1 equiv. (SDH, SONET)
MX320 with 2048 STM-1 equiv. (SDH, SONET)
MX160 with 1024 STM-1 equiv. (SDH)
03
3AG 24163 BEAA PCZZA
531
198 / 531
The board provides the following functionalities:
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
–
–
–
–
HO Matrix that performs HPC
Protection functions
HPOM / HSUT functions
Synchronization functions
Shelf Controller function
Two boards in master/slave configuration are provided (redundant SLC).
ED
03
3AG 24163 BEAA PCZZA
531
199 / 531
13.1.2 Equipment Units
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The following units are available; they are mandatory in the 1678MCC equipment about powering, cooling
and bus terminating:
•
Power Supply and Filter board (PSF)
The board provides the following functionality:
•
distribution of Power Supply (65 V) after filtering process
Two PSF boards in 1+1 configuration are provided (they are both mandatory).
•
Bus Termination board (BUSTERM)
The board provides the following functionality:
•
electrical termination to the buses routed in the backplane
Two BUSTERM boards are provided (they are both mandatory).
•
FANs unit (FAN)
The unit provides the following functionality:
•
cooling the equipment
Two FAN units are provided (they are both mandatory).
13.1.3 Traffic Ports boards
The following boards are available in the 1678MCC main shelf:
•
16xSTM–1/4 optical board (P16S1S4)
The board provides to process up to sixteen STM–1/4’s (SFP plug–in).
Any combination of optical interface (Short or Long haul) is possible on the same port. That must
be done by groups of four continuous STM–n ports.
The 16 x STM–1/4 board is a single blade board providing 16 slots. Each slot can host a
STM–1/4 SFP (small form factor plug–in) optical module, so that each board can provide up to
16 optical interfaces.
This board is 4.5 TE wide.
The 1678MCC can host up to sixteen 16 x STM–1/4 boards in one shelf. So the maximum
number of STM–1/4 interfaces per shelf is 256.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Each STM–1 SFP module is available with S–1.1, L–1.1 or L–1.2 interface and each STM–4
SFP module is available with S–4.1, L–4.1 or L–4.2 interface. So each 16 x STM–1/4 board can
host any mix of the above mentioned interfaces.
All STM–1/4 modules can be protected in SNCP or 1+1 / 1:N MSP.
ED
03
3AG 24163 BEAA PCZZA
531
200 / 531
•
16xSTM–1 board (P16S1S)
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The board provides to process up to sixteen STM–1’s (SFP plug–in).
A combination of optical interfaces (Short or Long haul) and electrical interfaces is possible on
the same port. That must be done by groups of four continuous STM–n ports.
The 16 x STM–1 board is a single blade board providing 16 slots. Each slot can host a STM–1
SFP (small form factor plug–in) optical or electrical module, so that each board can provide up
to 16 optical/electrical interfaces.
This board is 4.5 TE wide.
The 1678MCC can host up to sixteen 16 x STM–1 boards in one shelf. So the maximum number
of STM–1 interfaces per shelf is 256.
Limitation (In case of electrical interfaces): Due to mechanical restrictions, up to 32 STM–1
electrical ports can be supported within1678MCC with front cover. The boards have to be
located as follow:
–
one board on right side of the shelf
–
one board on left side of the shelf.
Each STM–1 SFP module is available with SES1, S–1.1, L–1.1 or L–1.2 interface.
•
4/8/16xSTM–16 optical board (P4S16, P8S16, P16S16)
The board provides to process up to four/eight/sixteen STM–16’s (SFP plug–in).
Any combination of optical interface (Short or Long haul) is possible on the same port.
The 4/8/16 x STM–16 board is a single blade board providing 16 slots. Each slot can host a
STM–16 SFP (small form factor plug–in) optical module, so that each board can provide up to
4/8/16 optical interfaces.
This board is 4.5 TE wide.
The 1678MCC can host up to sixteen 4/8/16 x STM–16 boards in one shelf. So the maximum
number of STM–16 interfaces per shelf is 256.
Each STM–16 SFP module is available with S–16.1, L–16.1 or L–16.2 interface, so each
4/8/16xSTM–16 board can host any mix of four/eight/sixteen STM–16 interfaces.
They may be used in the following configurations:
•
•
•
•
•
•
N x unprotected STM–16 lines
N x 1+1/1:N STM–16 terminal
N x SNC–P rings
N x 2–fiber MS–SPRing
or any combinations of the above unprotected and protected configurations
1xSTM–64 board
The board provides one STM–64 optical interface.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The 1 x STM–64 optical board (S64M) is a single slot board providing one STM–64 optical
interface (on front panel).
This board is 4.5 TE wide.
The STM–64 interface is available with FC or SC connectors.
Several interface types are available:
•
•
•
•
•
ED
S–64.2
I–64.1 (VSR2000–2R1)
L–64.2
V–64.2
U–64.2
03
3AG 24163 BEAA PCZZA
531
201 / 531
•
2xSTM–64 board
The board provides two STM–64 optical interface.
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The 2xSTM–64 optical board (P2S64M) is a single slot board providing two STM–64 optical
interface (on front panel).
This board is 4.5 TE wide. The STM–64 interface is available with FC or SC connectors.
Several interface types are available:
•
•
•
•
S–64.2
I–64.1 (VSR2000–2R1)
2xSTM-64 interfaces per board for XFP/E modules
4xSTM–64 board
The board provides four STM–64 optical interface.
The 4xSTM–64 optical board (P4S64M) is a single slot board providing four STM–64 optical
interfaces (on front panel).
This board is 4.5 TE wide. The four STM–64 interfaces are available with FC or SC connectors.
The 1678MCC can host up to sixteen 4 x STM–64 boards in one shelf. So the maximum number
of STM–64 interfaces per shelf is 64.
Several interface types are available:
•
•
I–64.1 (VSR2000–2R1)
4xSTM-64 interfaces per board for XFP/E modules
The I–64.1 board can be used for the intra–shelf connections of 1670SM OEDs. The links can
be 1+1 MSP protected.
All STM–64 boards can be used in the following configurations:
•
•
•
•
•
•
N x unprotected STM–64 lines
N x 1+1/1:N STM–64 terminal
N x SNC–P rings
N x 2–fiber MS–SPRing
or any combinations of the above unprotected and protected configurations
4/8/16xGE board
The board provides to process up to four/eight/sixteen GE optical interfaces (SFP plug–in).
Flexible mix of short range (1000SX) and long range (1000LX) optics is possible.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The 4/8/16 x GE board is a single blade board providing up to 16 slots. Each slot can host a GE
SFP (small form factor plug–in) optical module, so that each board can provide up to 4/8/16
optical interfaces.
This board is 4.5 TE wide.
The 1678MCC can host up to sixteen 4/8/16 x GE boards in one shelf. So the maximum number
of GE interfaces per shelf is 256.
Each GE SFP module is available with 1000SX or 1000LX interface, so each 4/8/16xSTM–16
board can host any mix of four/eight/sixteen GE interfaces.
They may be used in the following configurations:
•
•
ED
N x SNC–P rings
N x 2–fiber MS–SPRing
03
3AG 24163 BEAA PCZZA
531
202 / 531
•
2/4x10 GE board
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The board provides to process up to two/four GE optical interfaces (XFP plug–in).
Flexible mix of 10GE–SR, 10GE–LR and 10GE–ER is possible.
The 2/4x10GE board is a single blade board providing up to 2/4 slots. Each slot can host a XFP
optical module, so that each board can provide up to 2/4 optical interfaces.
This board is 4.5 TE wide.
•
Lower Order Matrix board
Two types of LO matrix boards exist:
–
–
LAX40 with 256 STM-1 equiv.
LAX20 with 128 STM-1 equiv.
The board provides the following functionalities:
–
–
–
–
LO Matrix
Adaptation function
Switching entities: VC–3, VC–12, VC–11 (for future VC–2)
Protection capabilities: SNCP/I, SNCP/N
Two boards in master/slave configuration are provided.
•
Lower Order Matrix Link 40G (LAC40)
This board is used to connect the 1678MCC main shelf with the LO extension shelf.
The LAC40 board is a single blade board providing 16 slots. Each slot can host a STM–16 SFP
(small form factor plug–in) optical module, so that each board can provide up to 16 optical
interfaces (in general I–16.1).
This board is 4.5 TE wide.
Max. 5 (4+1) LAC40 boards are necessary to connect a fully equipped 160G LO extension shelf.
•
ES64 board
This board has a ethernet switching function (L2 switching)
This board is 4.5 TE wide.
The ES64 board can be used in the following configuration:
1AA 00014 0004 (9007) A4 – ALICE 04.10
•
ED
always 1+1 EPS
03
3AG 24163 BEAA PCZZA
531
203 / 531
13.1.4 Lower Order Extension Shelf
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The lower order partsystem provides lower order functionality with a capacity of 160 Gbit (1 K LO matrix).
13.1.4.1 Centralized Common Boards
The following boards are available; they are mandatory in the LO extension shelf equipment about control
and connections:
•
Alarm board (ALM)
The board provides housekeeping, remote alarm and rack lamp interfaces.
•
LO Centerstage Matrix board
LX160 with 1024 STM-1 equiv.
The board provides the following functionalities:
–
–
–
–
Adaptation function
LO three stage matrix (1 : N MSP protected, N=1...7)
Protection capabilities: SNCP/I, SNCP/N
Redundant clock generator
Two boards in master/slave configuration are provided.
13.1.4.2 Equipment Units
The shelf includes also the equipment units PSF, BUSTERM and FANs as described in chapter 13.1.2 on
page 200.
13.1.4.3 Port Boards
The port board area of the shelf can be equipped with up to 16 port boards.
•
LO Adaptation 20G board (LA20)
The board provides the following functionalities:
–
1AA 00014 0004 (9007) A4 – ALICE 04.10
–
–
ED
The board is a single blade board providing 8 slots. Each slot can host a STM–16 SFP
(small form factor plug–in) optical module, so that each board can provide up to 8 optical
interfaces (in general I–16.1).
This board is 4.5 TE wide.
For the 160G LO matrix a maximum of 10 (8+2) LA20 boards per shelf are supported.
03
3AG 24163 BEAA PCZZA
531
204 / 531
13.2 Subsystems and involved Boards
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Figure 116. on page 205 illustrates, in block diagram form, some boards employed in the 1678MCC
equipment and the general operating functions.
For more details about the boards managed refer to chapter 17 on page 441.
Main shelf
optical
interface
FLCSERV
I/O board
O
T4/T5
T3/T6
First Level
Controller
Q3
DCC
Logical/
Physical
Transport
and
Adaption
Function
STM-N
2MHz/2Mb
synch G.703
OBPS
BattA / BattB
VccA / VccB
Control
FLCCONGI
OBPS
16
1
OBPS
HO MATRIX
VC-4/-nc
Matrix
BattA / BattB
SEC
T4/T5
T3/T6
First Level
Controller
Q3
DCC
BattA / BattB VccA / VccB
T0
2MHz/2Mb
synch G.703
T4/T5
VccA / VccB
Power Supply Filter A
VccA
T1
Power A
T3/T6
SLC
OBPS
DC/DC
BattA
2
Control
1
BattA / BattB
VccA / VccB
Control
Control
VccB
Power Supply Filter B
Power B
DC/DC
LO MATRIX
BattB
VC-3/VC-12/
VC11 Matrix
Control
OBPS
2
1
BattA / BattB
VccA / VccB
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 116. 1678MCC Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
205 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The functions carried out by the unit can be splitted into the following subsystems:
•
Connections subsystem
(refer to para. 13.3 on page 208)
•
Signal management subsystem
(refer to para. 13.4 on page 217)
•
Controller subsystem
(refer to para. 13.5 on page 224)
•
Synchronization subsystem
(refer to para. 13.6 on page 236)
•
Protection subsystem
(refer to para. 13.7 on page 239)
•
Performance Monitoring subsystem
(refer to para. 13.8 on page 301)
•
External Interfaces subsystem
(refer to para. 13.9 on page 303)
•
Power Supply subsystem
(refer to para. 13.10 on page 304)
•
Equipment Alarms and Test subsystem
(refer to para. 13.11 on page 312)
•
Remote Inventory subsystem
(refer to para. 13.13 on page 321)
In the following paragraphs a detailed description of each subsystem is given.
Each logical function does not correspond necessarily to a physical board but can be distributed over more
than one board. On the other side, one board can house more than one function.
1AA 00014 0004 (9007) A4 – ALICE 04.10
For each subsystem the list of the involved boards and a brief abstract of the function detailed on the
following paragraphs is reported in Table 38. on page 207.
ED
03
3AG 24163 BEAA PCZZA
531
206 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Table 38. Subsystems and involved boards
Subsystem
Board involved
Connections
MATRIX and ports
Signal management
all ports
Controller
Protection
Network
protections
Short description
On the paragraph is explained how the signal is managed between the port and the
MATRIX.
On the paragraph it is explained how the
SDH signals are elaborated on the ports.
The description in compliancy with the
G.783 ITU–T Rec.
FLCSERV and FLCCONGI, The control system is centralized.
HO MATRIX
The FLCSERV and the FLCCONGI perform
the First Level Controller (FLC) function and
the HO MATRIX performs the Second Level
Controller (SLC) function.
all ports
The following network protection are explained: linear MSP, SNCP/I and SNCP/N
(among VC–4 only), Drop & Continue + insertion SNCP, Collapsed single–node ring
interconnection, Collapsed dual–node ring
interconnection, 2F MS–SPRing. The HO
MATRIX board manages all the protections.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Equipment FLCSERV and FLCCONGI, The SLC on the HO MATRIX board controls
protections
HO MATRIX
the EPS protections.
ED
Synchronization
HO MATRIX
The MATRIX performs the synchronization
function therefore distributing the clock and
synchronism to all the equipment units.
Auxiliary and External
all ports, FLCSERV,
FLCCONGI
On the paragraph is explained how the OH
bytes (DCC) are framed and managed.
(Note: EOW and AUX channels are not supported.)
Also the External Interfaces (Housekeeping,
Craft Terminal, Remote Alarms and Rack
Alarms) are described.
Power Supply
all boards, PSF
The powering is distributed over the all
equipment boards. The PSF boards provides the 65 V and the service 3.3 V to power each board.
Equipment Alarms
and Test
all boards and modules
On the paragraph is explained the Alarms
and the Test (Loop) managed.
Remote Inventory
all boards and modules
On the paragraph is explained the Remote
Inventory architecture.
03
3AG 24163 BEAA PCZZA
531
207 / 531
13.3 Connections Subsystem
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.3.1 High Order SDH/SONET/OTN Cross Connect Subsystem
The 1678MCC cross–connect is built upon a non–blocking matrix (the HO 640/320/160Gb/s matrix) that
can interconnect AU–4s (or AU–3s) between any SDH/SONET port accessing the system.
The same board can switch ODU–x entities, implementing the G.709 optical layer.
Several types of connections can be established, such as:
•
•
•
•
unidirectional point–to–point (protected or unprotected)
bi–directional point–to–point (protected or unprotected)
unidirectional point–to–multipoint
SNCP Drop & Continue
The HO matrix capacity is max. 4096x4096 STM–1 equivalent ports at the Higher Order VC level.
The HO matrix can support, in accordance with the ITU–T G.783 Rec., the following functions:
•
MSP (Multiplex Section Protection) according to G.841, which provides protection for the
STM–N signal against line failures within a multiplex section, by using the protocol defined for
the MSP bytes: K1 and K2;
•
HPC (Higher Order Path Connection), which performs the AU–4 (AU–3) cross–connections,
assigning an incoming VC–4’s to an outgoing VC–4’s. The characteristic of the connection
depends on:
–
Type of connection (unprotected, 1+1 protected by means of SNCP/I, SNCP/N protection);
–
Input and Output connection points.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The SDH/SONET matrix is responsible for all the network protection mechanisms: SNCP and linear MSP.
The matrix is always protected in 1+1 EPS configuration.
ED
03
3AG 24163 BEAA PCZZA
531
208 / 531
13.3.2 20/40G Lower Order Subsystem
The LO Matrix is a square matrix. Two LO board types are supported:
–
–
LAX40
LAX20
Equipment
The LO Matrix is implemented in 1+1 LAX matrix boards. The LAX boards are always all equipped.
The LAX board implements the square low order matrix together with the so called adaptation function
(Higher Order path termination and adaptation function). The LAX board is always 1+1 protected.
Lower order
adaption and
monitoring
Backplane
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Principle
interface
to higher
order
subsystem
LO matrix
function
32 x 2.5 Gbit/s
Copy A and B
to/from HO Matrix
16 x 2.5 Gbit/s
16 x 2.5 Gbit/s
Figure 117. Low Order Matrix Overview
Switching entities
–
–
–
VC-3
VC-12
VC-11 (SONET).
Capacity
–
–
LAX40 has a capacity of 256 STM–1 eq. (40 Gbit/s)
LAX20 has a capacity of 128 STM–1 eq. (20 Gbit/s)
1AA 00014 0004 (9007) A4 – ALICE 04.10
This results in a maximum capacity of 256 STM-1eq. for the LO matrix, if the LAX40 board is used.
ED
03
3AG 24163 BEAA PCZZA
531
209 / 531
Protection
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
–
1+1 protected
SNCP/I and SNCP/N with:
•
Hold off timers (limited to 4 values: disabled, 10,100,1000 ms)
•
Wait to restore timers (disabled and 1 minute).
Matrix Management
Figure 118. shows the physical signal flow between HO matrix and LO matrix. Receive and transmit
direction are depicted as dedicated boards on the left and the right hand side of the HO matrix. In reality
both signal directions are unified on a board and allow the insertion of remote information into the
transmission paths.
RX direction
STM–N, VC4
structured
TX direction
1
STM–N, VC4
structured
1
STM–N, VC4
unstructured
STM–N, VC4
unstructured
...
...
2Mbit
2Mbit
STM-1e/140Mbit
STM–N, VC4
structured
HO I/O 14 *
boards 256 STM1
OED
VC4
MX640
4096 x 4096
square matrix
14 *
256 STM1
HO I/O
boards
STM-1e/140Mbit
STM–N, VC4
VC4
OED structured
STM–N, VC4
unstructured
STM–N, VC4
unstructured
Gigabit Ethernet
Gigabit Ethernet
4096
4096
256 STM1
256 STM1
LAX40
256 x 256
square matrix
1
...
256
Figure 118. Physical Matrix View with MX640 and LAX40
OEDs are connected to the main shelf via normal interfaces.
1AA 00014 0004 (9007) A4 – ALICE 04.10
In case the I/O port receives structured SDH/SONET signals (from OED or directly from an HO I/O) the
signal can be connected to an assembler located on an LAX board (refer to Figure 119. for matrix logical
view).
Low order PDH traffic (only via OED) is connected via the HO matrix to the LAX boards. The connection
is established as soon as the OED ports are put into service. The AU4 path through the HO matrix and
the assembler on the LAX board are internal. Each of the low order signals is connected with the LO matrix
to a free assembler or to another PDH port.
ED
03
3AG 24163 BEAA PCZZA
531
210 / 531
RX direction
TX direction
HO
Matrix
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
STM–N
structured
STM–N
structured
STM–N
unstructured
STM–N
unstructured
Gigabit
Ethernet
Gigabit Ethernet
STM-1e/140Mbit
I/O
I/O
board
board
Assembler
Assembler
2Mbit
LO
Matrix
STM-1e/140Mbit
2Mbit
I/O
I/O
board
board
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 119. Logical Matrix View
ED
03
3AG 24163 BEAA PCZZA
531
211 / 531
13.3.3 160G Lower Order Partsystem
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
This partsystem has a LO functionality up to the capacity of 160 Gbit. The Lower Order crossconnect
functionality is implemented in an extension shelf.
The Lower Order system of the 1678MCC contains the following functions:
–
Adaptation function (TU–Pointer Processor), 1:N protected
–
Low Order three stage matrix
•
scalable in steps of 20 GBit/s,
•
the second stage is 1+1 EPS protected,
•
the first and third stages are 1:N protected using MSP, N is 4 in case of 160G
–
Switching entities : VC–3, VC–12
–
Protection capabilities : SNCP/I, SNCP/N
–
Redundant clock generator (ETSI compliance)
The 1678MCC Main Shelf with 160G Lower Order extension shelf is shown in Figure 120.
STM –16
Intra system link
16 x STM–16 link card
(16x 1:4 MSP)
1678MCC
LO shelf
LA20
MX640GE
I/O
..
.
#1
MSP
HPC
640G
Copy A
LAC40
Link
8x2.5G
#1
..
.
Link
I/O
#11
LX160
TUPP
..
.
8x2.5G
MSP
HPC
640G
Copy B
Daffodil
Daffodil
Link
8x2.5G
..
.
LO CS
Copy A
ES
#8
Daffodil
TUPP
#P
Link
#1
TUPP
#4
8x2.5G
ES
Daffodil
TUPP
#P1
#P2
ES
ES
LO CS
Copy B
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 120. 1678MCC Main Shelf with 160G Lower Order Shelf
ED
03
3AG 24163 BEAA PCZZA
531
212 / 531
13.3.4 Transmission Management
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The following functionalities are managed:
•
•
•
•
•
•
•
J0 and J1 management
POM on AU–4 and AU–3
SUT on AU–4
MSP 1+1 @ STM–16 / STM–64
MSP 1+1 @ STM–1 / STM–4
AU–3 switching
F4 filter configuration at path layer
For more details refer to Operator’s Handbook.
13.3.4.1 Section Trace Management (J0)
The regenerator section trace identifier information is managed, according to ITU–T G.707 Rec.: when
the accepted identifier (AcTI detected in the byte J0) is different from the expected (ExTI), an alarm “Trace
Identifier Mismatch“ (TIM) is generated. The control can be disabled by setting ExTI=NULL.
13.3.4.2 Path Trace Management (J1)
The trail trace identifier information is managed, according to ITU–T G.707 Rec.: when the accepted
identifier (AcTI detected in the byte J1) is different from the expected (ExTI), an alarm “Trace Identifier
Mismatch“ (TIM) is generated. The control can be disabled by setting ExTI=NULL.
Note that the NE calculates the CRC–7 value to be inserted even if this parameter is passed to the NE
from the managing system.
13.3.4.3 Path Overhead Monitoring
Path Overhead (Non–intrusive) Monitoring function is implemented according to ITU–T G.783 Rec.
The POM function monitors the VC–4 or VC–3 for errors, and recovers the trail termination status.
It extracts and processes the payload overhead bytes from the VC.
The POM function detects the following alarms: Trace Identifier Mismatch (TIM), EXCessive error (EXC),
UNEQuipped (UNEQ), Alarm Indication Signal (AIS), Remote Defect Indication (RDI), DEGraded Signal
(DEG), Server Signal Failure (SSF).
The object modeling the POM function is created by CT/OS below the AU–4 or AU–3.
The POM can be used also for obtaining the SNCP switch criteria.
13.3.4.4 Supervisory Unequipped Termination
1AA 00014 0004 (9007) A4 – ALICE 04.10
SUT functions are implemented according to ITU–T G.783 Rec.
The object modeling the SUT function is created by CT/OS below the AU–4.
SUT on AU–3 is not supported.
ED
03
3AG 24163 BEAA PCZZA
531
213 / 531
13.3.5 Connection Management
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The following functionalities are managed:
•
•
SNCP/I on AU –4 and AU–3
SNCP/N on AU –4 and AU –3
13.3.5.1 Overview
The connection management covers:
•
•
the management of the connections at AU–4 and AU–3 level
the management of unidirectional 1+1 revertive/not revertive subnetwork connection protection
(for both AU–4 and AU–3)
The 1678MCC has the capability to manage and configure upon management request several types of
connections, namely:
•
point–to–point connection (unidirectional and bidirectional)
–
unprotected
–
protected
•
point–to–multipoint connection (unidirectional)
–
unprotected
–
protected
For the 1678MCC equipment the maximum number of cross–connections is obtained exploiting totally the
matrix capability: 4096 AU4 crossconnectable (12288 AU3 crossconnectable).
The connections are established between ports belonging to the shelves and are always performed by
the matrix: no direct connection between two ports is allowed.
The managed system allows the managing system to protect a connection. Such protected connections
can be used in network protection applications.
13.3.5.2 Unprotected Point–to–Point Connections
The following Table 39. on page 215 shows the possible unprotected point–to–point connections
(unidirectional and bidirectional).
There is not any constraint for the timeslot change for each cross–connection (i.e. the AU–4#x of a
STM–64 port can be cross–connected with the AU–4#y of a STM–16 port). Such connections are allowed
for both AU–4 and AU–3.
13.3.5.3 Protected Point–to–Point Connections
Protected point–to–point connections (unidirectional and bidirectional) are defined by Figure 121. on
page 216. Such connections are allowed for both AU–4 and AU–3.
13.3.5.4 Unprotected Point–to–Multipoint Connections
Unprotected unidirectional point–to–multipoint (broadcast) connections are defined by Figure 121. on
page 216. Such connections are allowed for both AU–4 and AU–3.
13.3.5.5 Protected Point–to–Multipoint Connections
1AA 00014 0004 (9007) A4 – ALICE 04.10
Protected point–to–multipoint connections are defined by Figure 121. on page 216.
Such connections are allowed for both AU–4 and AU–3.
ED
03
3AG 24163 BEAA PCZZA
531
214 / 531
Table 39. Point–to–point connections
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
STM–1
AU3
STM–1
AU3
X
AU4
STM–4
AU3
AU4
STM–4
AU3
X
AU3
X
X
X
AU4
X
X
X
X
AU4
–4c
X
X
X
X
X
AU4
–16c
STM–64 AU3
AU4
AU4
–4c
AU4
–16c
X
X
X
AU4 AU4 AU4
–4c –16c –64c
X
X
X
AU4
X
X
X
AU4 AU4 AU3
–4c –16c
X
X
X
AU4
STM–64
X
AU4
–4c
STM–16 AU3
AU4
–4c
X
X
AU4
AU4
STM–16
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1AA 00014 0004 (9007) A4 – ALICE 04.10
AU4
–64c
ED
X
03
3AG 24163 BEAA PCZZA
531
215 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
AU4 slot i
AU4 slot j
protected point–to–point unidirectional connection
AU4 slot x
AU4 slot i
AU4 slot j
protected point–to–point bidirectional connection
AU4 slot x
AU4 slot h
AU4 slot i
AU4 slot j
unprotected point–to–multipoint connection
AU4 slot x
Protected AU4 slot i
AU4 slot k
Protecting AU4 slot h
AU4 slot j
AU4 slot x
AU4 slot k
protected point–to–multipoint connection
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 121. Types of connections managed
ED
03
3AG 24163 BEAA PCZZA
531
216 / 531
13.4 Signal Management Subsystem
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.4.1 Introduction
This section describes the signal management architecture implemented in 1678MCC equipment.
The signal management architecture has been designed in order to obtain a flexible system in which the
switching matrix is kept as much as possible payload independent. This implies that SDH payload specific
functions are implemented in the I/O port boards.
13.4.2 SDH functional Model
SDH Payload matrices, foreseen by ITU–T standards, (i.e. MSP_RX, H PC, MSP_TX matrices) collapse
into one single device, performing fully non blocking 4096x4096 AU–4 switch, with respect to any
broadcast type.
Figure 122. on page 217 depicts the payload processing subsystem functional partitioning.
PORT BOARD
MATRIX
BOARD
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 122. SDH payload subsystem functional model: physical position of functional blocks
ED
03
3AG 24163 BEAA PCZZA
531
217 / 531
13.4.3 ITU–T/ETSI SDH Functional Block
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.4.3.1 SDH Port Board
At port board level, functions related to the payload processing are integrated, causing, in principle, a
violation of ITU–T G.783 functional model. The functional block diagram is reported in Figure 123. on
page 218, with its corresponding atomic function representation.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 123. Port board implementation and corresponding ITU–T G.783 functional model
ED
03
3AG 24163 BEAA PCZZA
531
218 / 531
The received/transmitted line signal is optical STM–N with N=1, 4, 16, 64, 256 (ITU–T G.957 Rec. and
ITU–T G.691 Rec.). The SDH frame format is compliant with ITU–T G.707 Rec.
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
a) SDH Physical Layer
–
Optical Section Layer Trail Termination: OSn_TT
OSn_TT_Sk
input LOS detection
TSF insertion on LOS detection
OSn_TT_So
signal conditioning for transmission medium
–
Optical Section Layer Adaptation to Regenerator Section Layer: OSn/RSn_A
OSn/RSn_A_Sk
descrambler
OOF count and LOF detection
SSF insertion (on LOF detection)
OSn/RSn_A_So
scrambler
b) Regenerator Section Layer
–
Regenerator Section Layer Trail Termination: RSn_TT
RS_TT_Sk
A1, A2: frame alignment detection
J0: regenerator section trace recovery and mismatch detection
B1: BIP–8 Errored Block count: even bit parity is computed and compared with B1 recovered
from the current frame
BMD: Processed for detection of a fiber failure in a single fiber transmission. BMD byte is set
in position S(2,2,1).
D1–D3: RS data communication (DCC–R) extraction
SSF detection
TSF insertion (on SSF or TIM detection)
RS_TT_So
A1, A2: frame alignment insertion
J0: regenerator section trace insertion
B1: BIP–8 calculation and insertion
BMD: BMD message insertion for detection of a fiber failure in a single fiber transmission.
D1–D3: RS data communication (DCC–R) insertion
–
Regenerator Section Layer Adaptation to Multiplex Section Layer: RSn/MSn_A
RSn/MSn_A_Sk
TSF detection
SSF insertion (on TSF detection)
RSn/MSn_A_So
no information is inserted
c) Multiplex Section Layer
1AA 00014 0004 (9007) A4 – ALICE 04.10
–
ED
Multiplex Section Layer Trail Termination: MSn_TT
MSn_TT_Sk
B2: BIP–24N Errored Block count
M1, M0: MS–REI recovery (M0 significant for STM–64/STM–256 only)
K2[6–8]: MS–RDI detection
03
3AG 24163 BEAA PCZZA
531
219 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
K2[6–8]: MS–AIS detection
D4–D12: MS data communication (DCC–M) extraction
D13–D156: Extended MS data communication (DCC–Mx) extraction (STM–256 only)
S1: SSM message extraction
TSD insertion on MS –DEG (Signal Degrade) detection
TSF insertion (on MS–AIS detection)
MSn_TT_So
B2: BIP–24N calculation and insertion
M1, M0: MS–REI insertion (M0 significant for STM–64/STM–256 only)
K2[6–8]: MS–RDI insertion
K2[6–8]: MS–AIS insertion
D4–D12: MS data communication (DCC–M) insertion
D13–D156: Extended MS data communication (DCC–Mx) insertion (STM–256 only)
S1: SSM message insertion
–
Multiplex Section Sub–layer protection function:
•
Multiplex Section Layer Adaptation to the Multiplex Section Protection Sub–layer:
MSn/MSnP_A
MSn/MSnP_A_Sk
the K1–K2 (extended to K0) information (APS protocol) is recovered
SSF insertion (on TSF detection)
SSD insertion (on TSD detection)
MSn/MSnP_A_So
generation of K1–K2 information (APS protocol – extended to K0).
–
Multiplex Section Protection Sub–layer Termination: MSnP_TT
MSnP_TT_Sk
SSF detection
TSF insertion (on SSF detection)
MSnP_TT_So
no information is inserted
–
Multiplex Section Layer Adaptation to the high Order Path Layer: MSn/Sn_A
MSn/Sn_A_Sk
AU–4 Pointer interpreter
SSF insertion (on LOP and AU–AIS detection)
PJE (Pointer Justification Event) count
MSn/Sn_A_So
AUG assembly and byte interleaving
AU–4 Pointer generator
AU–AIS generator
d) Path Layer
1AA 00014 0004 (9007) A4 – ALICE 04.10
–
ED
High Order Path Overhead Monitoring Function (POM): Snm_TT
Snm_TT_Sk
J1: Path Trace information is recovered.
G1[1–4]: The REI information is recovered.
G1[5–7]: Path Status monitoring detection ––> G1[5] is used for HP–RDI detection; G1[6 –7]
is optionally used for HP–RDI coding enhancement.
C2: Signal Label Monitoring ––> UNEQ and VC –AIS detection.
B3: VC–4 BIP–8 Errored Block Count.
TSF insertion (on SSF or UNEQ or TIM or AIS detection).
TSD insertion (on a condition of degraded signal detection).
03
3AG 24163 BEAA PCZZA
531
220 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
High Order Supervisory Unequipped Termination (HSUT) : Sns_TT
Sns_TT_Sk
J1: Path Trace information is recovered.
G1[1–4]: The REI information is recovered.
G1[5]: Path Status monitoring detection ––> G1[5] is used for HP–RDI detection; G1[6 –7] is
optionally used for HP–RDI coding enhancement.
C2: Signal Label Monitoring ––> UNEQ and VC–AIS detection.
B3: VC–4 BIP –8 Errored Block Count.
Sns_TT_So
Generation of an unequipped container and frame offset.
C2: “unequipped“ insertion.
J1: trail trace identifier is generated.
G1: insertion of RDI and/or REI information.
B3: VC–4 Bip –8 calculation and insertion.
–
VC–4 Tandem Connection Trail Termination: SnD_TT
SnD_TT_Sk
N1[1–4]: VC–4 BIP–8 extraction and EDC calculation.
N1[8][73]: RDI extraction.
N1[5]: REI extraction.
N1[7][74]: ODI extraction (Outgoing Defect Indication).
N1[6]: OEI extraction (Outgoing Error Indication).
N1[7–8]: extraction from the multiframed channel N1[7–8] of:
FAS (Frame Alignment Signal) in frames 1 to 8.
trace identifier in frames 9 to 72.
TC RDI and ODI in frames 73 to 76.
B3: BIP–8 compensation.
SnD_TT_So
N1[8][73]: RDI insertion.
N1[5]: REI insertion.
N1[7][74]: ODI insertion (Outgoing Defect Indication).
N1[6]: OEI insertion (Outgoing Error Indication).
N1[7–8]: insertion in the multiframed channel N1[7 –8] of:
FAS (Frame Alignment Signal) in frames 1 to 8.
trace identifier in frames 9 to 72.
TC RDI and ODI in frames 73 to 76.
N1[1–4]: BIP–8 calculation and insertion.
B3: BIP–8 compensation.
–
VC–4 Tandem Connection Adaptation: SnD_A
SnD_A_Sk
his function will restore the invalid Frame Start condition if that existed at the ingress of the
tandem connection.
AIS insertion.
SnD_A_So
this function will replace the incoming Frame Start signal by a local generated one if all–ONEs
VC is received.
ED
03
3AG 24163 BEAA PCZZA
531
221 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
VC–4 Tandem Connection non–intrusive monitoring: SnDm_TT
SnDm_TT_Sk
N1[1–4]: VC–4 BIP–8 extraction and EDC calculation.
N1[8][73]: RDI extraction.
N1[5]: REI extraction.
N1[7][74]: ODI extraction (Outgoing Defect Indication).
N1[6]: OEI extraction (Outgoing Error Indication).
N1[7–8]: extraction from the multiframed channel N1[7–8] of:
FAS (Frame Alignment Signal) in frames 1 to 8.
trace identifier in frames 9 to 72.
TC RDI and ODI in frames 73 to 76.
–
Path Sub–layer protection function:
Note:
The path sublayer is not only related to protection information management, but also dedicated
to the add/drop of particular POH bytes, without the need to regenerate the path layer. This is
achieved thanks to Daffodil framer, which allows POH insertion with B3 compensation.
–
Path Layer Adaptation to the Path Protection Sub–layer: Sn/SnP_A
Sn/SnP_A_Sk
the K3 information (APS protocol) is recovered
SSF insertion (on TSF detection)
SSD insertion (on TSD detection)
F2, F3: path user channel insertion
Sn/SnP_A_So
generation of K3 information (APS protocol)
F2, F3: path user channel extraction
–
Path Protection Sub–layer Termination: SnP_TT
SnP_TT_Sk
SSF detection
TSF insertion (on SSF detection)
SnP_TT_So
no information is inserted
ED
03
3AG 24163 BEAA PCZZA
531
222 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.4.4 Matrix Board
The matrix module provides switching capabilities with STS–1 minimum granularity, achieving full
SONET/SDH compatibility. Both MSPC (Multiplex Section Protection Connection) and HPC (Higher Order
Path Connection) switching functions are integrated in one single device.
The maximum switching capacity is equivalent to 12288x12288 at AU–3 level (i.e. 4096x4096 at AU–4
level), fully non blocking with respect to any broadcast type.
13.4.4.1 Matrix Physical Representation
The payload processing functionalities integrated in the matrix board are limited to AU–4 switching
operations only. The corresponding functional model of the matrix board is depicted in Figure 124. on
page 223.
The statuses of MSPC and HPC connection functions are individually calculated, as if they were two
physical entities. The switching command is then derived correlating MSPC status and HPC status.
Main Board
MSnP + Sn
Figure 124. Matrix board implementation: payload processing
MSPC connection function status is determined in order to provide protection for the STM–N signal against
channel–associated failures within a multiplex section, by using the bit–oriented protocol defined for the
MSP bytes K1, K2 and optionally K0. Under failure condition in Rx direction valid data are no longer taken
from the working line termination but from the spare one; the required switch operation for MSP protection
does not involve HPC. Similarly in Tx direction the MSPC status is such to guarantee data forking to both
working and spare lines.
HPC connection function status is generated in order to provide VC–ns connectivity among input and
output ports. The assignment of incoming VC –ns to outgoing VC–ns is defined as the “connection pattern”
which can be described by a uni–directional connection matrix and characterized by:
1AA 00014 0004 (9007) A4 – ALICE 04.10
–
–
–
ED
Type of connection (unprotected, 1+1 protected by means of SNCP/I, SNCP/N, SNCP/S protection
or 1:n SNCP by using the bit oriented protocol defined in K3 byte).
Traffic direction (unidirectional, bi –directional).
Input and output connection points.
03
3AG 24163 BEAA PCZZA
531
223 / 531
13.5 Controller Subsystem
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.5.1 Overview
The controller subsystem implements the Synchronous Equipment Management Function (SEMF)
defined by ITU–T G.783 Rec. It communicates with external management systems through a standard
QB3 CMIP interface.
The management information model is based on the ITU–T G.774 series of recommendations.
Communication with the local Craft Terminal (CT) is also based on the same interface.
The controller subsystem is responsible for applying the configuration requested by the element manager
or CT and to report the status of the equipment as well as alarm and performance information. It is also
responsible to drive automatic protection switching.
The 1678MCC has centralized control architecture, built upon a two–level model:
•
First Level Controller (FLC) mainly for DCC networking, CT/OS interface and database
management;
Second Level Controller (SLC) mainly for provisioning, alarm detection, performance
monitoring and protection switching.
•
Two microprocessors are dedicated respectively to the FLC and SLC functions.
The FLC processor is 1+1 protected (one is located on the FLCCONGI board, the other on the FLCSERV
board), like the Second Level Controller processors (located on the two HO Matrix and Lower Order Matrix
boards).
They communicate through an internal ISSB bus (ILAN – Internal LAN).
The SLC processor interfaces directly through a backplane parallel bus (ISPB – Intra Shelf Parallel Bus)
all circuits (ASICs) implementing the SDH functions in the shelf, for data collection (alarms, performance
monitoring) and configuration provisioning purposes.
A 60 GB hard disk located in the FLCCONGI board for the configuration database and SW loads provides
a mass storage board. It is protected by another 60 GB hard disk located in the FLCSERV board.
A failure on the FLCCONGI or FLCSERV board has no impact on traffic, or on automatic protection
switching functions, which are managed by the SLC processor inside the HO Matrix board.
Moreover a failure on the FLCCONGI or FLCSERV board has no impact on the node availability in the
Network Management (supervision), thanks to the FLC duplication.
DCC Channels
The number of DCC channels depends on the installed FLC type. Two types of FLCs exists:
–
–
FLC with 33 MHz PCI clock frequency
FLC with 66 MHz PCI clock frequency.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The following number of DCC channels per board and system are possible:
FLC Type
FLC 33 MHz
FLC 66 MHz
DCC per Board
16 DCC–M + 16 DCC–R
16 DCC–M + 16 DCC–R
DCC per System
61 DCC–M + 16 DCC–R
95 DCC–M + 16 DCC–R
Selection of the STM–n ports and of the DCCM or DCCR channel is via Local CT or Network Manager (NM).
ED
03
3AG 24163 BEAA PCZZA
531
224 / 531
13.5.2 FLC and SLC Functions
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
In the 1678MCC the control system is based on First Level Controller (FLC) and Second Level Controller
(SLC). Figure 125. shows the control functionality of the 1678MCC main shelf.
OS
...
GMPLS UNI
Neighbor ISP 1
GMPLS UNI
Neighbor ISP 2
Customer DCN
FLCSERV
...
FLCCONGI
internal LAN switch
DCR
internal LAN switch
EM
DCR
EM
ISSB
SLC
SLC
HO Matrix Copy A
HO Matrix Copy B
1678MCC Main shelf
Figure 125. Physical LAN Topology of Main shelf only configuration
13.5.2.1 FLC Functions
The FLC functionalities are the following:
•
provides the HW resources and SW functions required for the communication between the NE
and the managing system (OS/CT);
performs all the SW functions related to the control and management activities of the “virtual“
machine: info–model processing, event reporting and logging, equipment database
management, SW downloading and management; to support these activities the FLC function
requires a nonvolatile memory;
system memory for FLC:
–
Flash EPROM Boot bank (boot information)
–
system RAM bank (application program and data)
–
non–volatile mass–storage (database storage, SW program storage, event logging,
provisioning and maintenance data)
•
•
The board with the FLC, about the bootstrap function, can be classified as disk based: the board
bootstraps the software from the equipped Mass Storage memory on the board.
The software code resides (at least 2 copies per board) only on the Mass Storage.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The download must be done in two distinct contexts:
•
•
ED
initial: over CT on LAN
upgrade: NM via DCN
03
3AG 24163 BEAA PCZZA
531
225 / 531
In the 1678MCC NE the First Level Controller functionality is performed on FLCCONGI (main) and on
FLCSERV (spare).
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.5.2.2 SLC Functions
The SLC functionalities are the following:
•
control and management of the “real“ machine; to perform this, SLC directly interfaces the
ASICs implementing functions for data collection and configuration provisioning;
system memory for SLC:
–
Flash EPROM Boot bank (boot information)
–
system RAM bank (application program and data)
•
The duplication of SLC functionalities is based on the following Scheme:
•
•
•
one SLC is in active state and the other in stand–by state
FLC provisions both SLCs with the same data and commands
hardware (ASIC, FPGA) is controlled by the active SLC
1AA 00014 0004 (9007) A4 – ALICE 04.10
FLC bootstraps the software application through a disk based protocol, while the SLC through a Network
based protocol.
ED
03
3AG 24163 BEAA PCZZA
531
226 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.5.2.3 Control of OED Shelves and Lower Order Extension Shelf
The main shelf and the OED shelf/LO extension shelf are managed as a single NE. The control system
located in the main shelf acts as the control system of the whole NE. In case of single rack configurations
the OED shelf/LO extension shelf are connected over internal LAN switches. In case of multi rack
configurations the OED shelf/LO extension shelf are connected over external LAN switches.
Single Rack Configurations
A system configuration consisting of the 1678MCC Main shelf plus one OED shelf/LO extension shelf in
one rack has no need for an external LAN switch.
The following Figures show system configurations consisting of only one rack:
–
–
–
Main shelf plus 1670SM OED (Figure 126. )
Main shelf plus 1662SMC OED (Figure 127. )
Main shelf plus LO extension shelf (Figure 128. )
One single OED shelf/LO extension shelf can be connected directly to the internal LAN switch. This
connection is provided on the FLC boards (refer to Figure 57. on page 119 and Figure 58. on page 120).
OS
...
GMPLS UNI
Neighbor ISP 1
GMPLS UNI
Neighbor ISP 2
Customer DCN
FLCSERV
...
FLCCONGI
internal LAN switch
DCR
internal LAN switch
EM
DCR
EM
1678MCC Main shelf
CONGI A
SC A
CONGI B
SC B
OED 1670SM
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 126. Physical LAN Topology of Main shelf with single 1670SM OED configuration
ED
03
3AG 24163 BEAA PCZZA
531
227 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
OS
...
GMPLS UNI
Neighbor ISP 1
GMPLS UNI
Neighbor ISP 2
Customer DCN
FLCSERV
...
FLCCONGI
internal LAN switch
DCR
internal LAN switch
EM
DCR
EM
1678MCC Main shelf
CONGI A
SC A
SC B
OED 1662SMC
Figure 127. Physical LAN Topology of Main shelf with single 1662SMC OED configuration
OS
...
GMPLS UNI
Neighbor ISP 1
GMPLS UNI
Neighbor ISP 2
Customer DCN
FLCSERV
...
FLCCONGI
internal LAN switch
DCR
internal LAN switch
EM
DCR
EM
1678MCC Main shelf
SC A
LX160 A
SC B
LX160 B
LO Extension Shelf
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 128. Physical LAN Topology of Main shelf with single LO extension shelf
ED
03
3AG 24163 BEAA PCZZA
531
228 / 531
Multi Rack Configurations
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
For multirack configurations consisting of a 1678MCC main rack and several OED racks a pair of Ethernet
LAN switches are needed to interconnect the internal control plane.
The OED 1670SM and the LO extension shelf are connected via two LAN connections to both external
LAN switches (LSX). The 1662SMC used as a LO OED supports only one LAN interconnection. Therefore
the 1662SMC is connected non–redundant to LAN switch LSX A or LSX B (all on one).
The following Figure 129. shows the principle of multi rack system configurations with LO extension shelf,
OED 1670SM and OED 1662SMC.
OS
...
GMPLS UNI
Neighbor ISP 1
GMPLS UNI
Neighbor ISP 2
Customer DCN
FLCSERV
...
FLCCONGI
internal LAN switch
DCR
internal LAN switch
EM
DCR
EM
1678MCC Main shelf
extension LAN switch (LSX A)
SC A
LX160 A
SC B
extension LAN switch (LSX B)
CONGI A
CONGI A
CONGI B
LX160 B
EC A
SC A
LO Extension Shelf
SC B
OED 1670SM
EC B
ISSB
SC A
SC B
SYNTH16
SYNTH16
OED 1662SMC
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 129. Physical LAN Topology of Multi Rack Setup
ED
03
3AG 24163 BEAA PCZZA
531
229 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.5.3 External Communication and Routing
The purpose of the communication and routing domain is to define configuration parameters concerning
the communication protocols for the local NE, the OS and each other related NE in order to provide global
communication capabilities inside the network.
13.5.3.1 Introduction
Protocol Stack
The set of protocols used in a communications network compose a protocol stack. Thus, a protocol stack
is a prescribed hierarchy of software layers. This layered structure also allows to use different protocols
to accommodate different network architectures. A protocol stack resides in each client and server.
OSI Stack
An OSI protocol stack (short: OSI stack) is a protocol stack according to the ISO/OSI standard for
worldwide communications that defines a framework for implementing protocols in seven layers. Control
is passed from one layer to the next, starting at the application layer in one network node, proceeding to
the bottom layer, over the channel to the next node and back up the hierarchy. For routing purposes only
the first three layers of the OSI protocol stack are relevant.
1AA 00014 0004 (9007) A4 – ALICE 04.10
In an OSI network there are the following significant architectural entities (see Figure 130. ):
–
domain
A domain is any part of an OSI network that is under common administrative authority.
–
area
An area is a logical part of a domain formed by a set of adjacent routers and the data links that connect
them. Within any OSI domain, one or more areas can be defined. All routers in the same area
exchange information about all of the hosts that they can reach.
–
backbone
The areas are connected by a backbone. All routers on the backbone know how to reach all areas.
–
host
A host is a network node, router or network element (NE).
ED
03
3AG 24163 BEAA PCZZA
531
230 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Routing Domain
Area 1
L1
ES
Area 2
L2
ES
L1
IS
L1
IS
L2 IS
L2 IS
Backbone
L1
IS
L2 IS
L1
IS
L1
IS
Area 3
L1
IS
L1
IS
L1
ES
hosts/ routers/ NEs/ nodes
ES
IS
L1
L2
End System
Intermediate System
Level 1
Level 2
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 130. Example of a routing domain
ED
03
3AG 24163 BEAA PCZZA
531
231 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
OSI Stacks in the 1678MCC
The 1678MCC uses OSI stacks for communication and routing. Figure 131. shows an example of an OSI
protocol stack can be configured. Since the 1678MCC is used as a router only the first three layers of the
OSI protocol stack are shown.
The “Don’t care” in layer 1 and 2 under IP in Figure 131. means that the layer 1 and 2 protocols under IP
are not fixed, but any of the protocols of the corresponding layer shown in the left blocks can be used.
The 1678MCC provides a ready-to-use default OSI stack to which a standard local Ethernet is assigned
as physical layer. Ethernet is the most widely used local area network (LAN) access method, defined by
the IEEE as the 802.3 standard. In this handbook the terms “LAN” and “Ethernet” are used as synonyms.
OSI Protocol Stack: layer 1 - 3
3
Network
2
Data Link
1
Physical
CLNS,
ES-IS:
IS-IS:
CLNP: ISO 8880-3, 8473 / ITU Q.811
IP
ISO 9542
ISO 10589
LLC class 1: ISO 8802-2/ ITU X.802.2
CSMA/CD: ISO 8802-2/ ITU X.802.2
LAPD: ITU Q.921
Ethernet
SDH DCC-R / DCC-M
D1- D3, D4 - D12
Don’t care
Don’t care
Figure 131. OSI protocol stack (layer 1 - 3)
Multiple OSI Areas
You can create further OSI stacks to support multiple OSI Level 1 sub domains (short: OSI areas). Multiple
OSI area support means that different data communication channels (DCC) or local area network (LAN)
interfaces can be assigned to different OSI areas.
LAPD/DCC and In-Band Signalling
LAPD/DCC connections use in-band signalling, which means meta data and network control information
are transmitted in the SDH overhead bytes. Network nodes connected via LAPD/DCC build-up an in-band
data communication network (DCN).
1AA 00014 0004 (9007) A4 – ALICE 04.10
LAN and Out-Of-Band Signalling
Out-of-band signalling is the complement to in-band signalling, which means any signalling where the
meta data and network control information are not transmitted in the SDH overhead bytes. Network nodes
connected via LAN build-up an out-of-band DCN.
ED
03
3AG 24163 BEAA PCZZA
531
232 / 531
13.5.3.2 Background
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
DCC channels and external LANs can be used for the following purposes in 1678MCC:
–
Communication between local and remote NEs, and TMN managers via Q3 or QRFC1006
–
Communication between CS–Server, and Equipment Provisioning and maintenance applications via
IP
–
Communication between GMRE and ASON manager via CORBA
–
Communication between GMREs via IP
–
Fast DCC link protection is needed for the dataplane signaling and routing protocols running between
neighboring GMREs
–
IP–in–IP tunnels via the external LANs are used by GMRE as backup links for the dataplane signaling
and routing protocols
–
IP–in–CLNP tunnels are used to reach IP managed NEs through OSI network islands
–
To connect UNI clients/client networks, GMRE configures VLANs on top of the external LAN to
achieve traffic separation between DCN traffic and client signaling traffic
–
The IS–IS protocol is used for the routing of OSI management traffic
–
The OSPF protocol is used for the routing of IP management and signaling traffic
All GMRE related information are described in chapter 13.7.5 Restoration – Support of the GMPLS
Protocol.
13.5.3.3 Multi OSI Area Management
The 1678MCC provides the feature Multi OSI Area. The 1678MCC can act as a transit NE and as a
Gateway NE (GNE).
The principle of multi OSI areas
There are several OSI areas within a routing domain. Each area can include the following systems:
–
–
End System (ES)
Intermediate Systems (IS).
The Intermediate Systems can be configured as Level 1 (L1) and Level 2 (L2) systems.
Figure 130. shows an example for Multi OSI Area Routing.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Two types of routing protocols exists:
–
ES–IS
IS learns about directly connected ESs and vice versa
–
IS–IS
L1 ISs learn topology of their own area
L2 ISs learn topology of complete L2 backbone (all areas).
ED
03
3AG 24163 BEAA PCZZA
531
233 / 531
Multiple Rings on 1678MCC as Transit NE
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
In this example the 1678MCC is used as transit NE (refer also to Figure 132. ). That means:
–
–
–
–
–
–
One area per ring (or group of rings)
All NEs are Level 1 IS (L1)
(NE assuming routing functionality inside an area)
1678MCC runs one L1 osi_ll process per area
(osi_ll is equal to OSI stack)
Q–Interface Adapter (QIA) connects to one osi_ll
1678MCC is Gateway NE (GNE) for at most one area
1678MCC is transit NE for other areas.
1678MCC
QIA
osi_ll#1
L1
osi_ll#2
L1
osi_ll#3
L1
L1
L1
L1
L1
L1
A1
A2
L1
L1
L1
L1
L1
L1
L2
L1
L2
A1...A3
L1
L2
osi_ll
QIA
A3
L1
L2
OSI Area 1...3
Level 1 IS
Level 2 IS
OSI stack
Q–Interface Adapter
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 132. Multiple Rings on 1678MCC as Transit NE
ED
03
3AG 24163 BEAA PCZZA
531
234 / 531
Multiple Rings on 1678MCC as Gateway NE
–
–
–
–
–
–
One area per ring (or group of rings)
All NEs are Level 1 IS (L1)
(NE assuming routing functionality inside an area)
1678MCC runs one L1 osi_ll process per area
(osi_ll is equal to OSI stack)
Q–Interface Adapter (QIA) connects to one osi_ll
1678MCC is Gateway NE (GNE) for all areas
Each osi_ll is connected to multi–area IS–IS router via separate VLAN.
L1/L2
1678MCC
VLAN
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
In this example the 1678MCC is used as Gateway NE (refer also to Figure 133. ). That means:
QIA
osi_ll#1
L1
osi_ll#2
L1
osi_ll#3
L1
L1
L1
L1
L1
L1
A1
A2
L1
L1
L1
A3
L1
L1
L1
L1
A1...A3
L1
L2
osi_ll
QIA
VLAN
L1
OSI Area 1...3
Level 1 IS
Level 2 IS
OSI stack
Q–Interface Adapter
Virtual LAN
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 133. Multiple Rings on 1678MCC as Gateway NE
ED
03
3AG 24163 BEAA PCZZA
531
235 / 531
13.6 Synchronization Subsystem
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The synchronization subsystem is located on the matrix boards. As the SDH/SONET matrix is protected
in 1+1 configuration, also the Clock Reference function is protected.
The synchronization subsystem provides the timing reference required by all components in the network
element. The subsystem performs the functionality identified by the ITU–T recommendation G.781/G.783
as Synchronous Equipment Timing Source (SETS).
The SETS function is implemented in the SDH/SONET HO Matrix board (MX640, MX320, MX160) as
shown in Figure 134. on page 236.
Squelch
A
Selector
A
Squelch
B
from ports
T1/T2
T3/T6
Selector
C
3
2
from
FLCSERV /
FLCCONGI
Selector
B
T4/T5
to
FLCSERV /
FLCCONGI
T0
SETG
HO Matrix Board
SETS Function
OSC
Figure 134. SETS function
The SETS accepts synchronization inputs from a number of sources:
•
•
T0 is the reference signal for the internal system clock and system framing signal
STM–N traffic ports (T1)
T1 is the clock derived from an STM–N signal (from STM–N port)
2 Mbit/s traffic ports (T2)
T2 is a 2 Mbit/s signal (derived from a 2 Mbit/s framed signal – E1 port)
2 MHz (T3)
T3 is a 2 MHz signal (from FLCSERV / FLCCONGI board)
2 Mbit/s external input (T6)
1.544 Mbit/s external input (T6)
T6 is a 2 Mbit/s or 1.5 Mbit/s signal (from FLCSERV / FLCCONGI board without data)
Internal Oscillator.
•
•
•
•
•
1AA 00014 0004 (9007) A4 – ALICE 04.10
Automatic selection of one of the above sources for system timing (T0) is performed by selector B, using
quality (Synchronization Status Message (SSM) algorithm) and priority criteria. The quality criteria can be
disabled. Also manual selection is possible.
The NE clock reference is used as internal timing source and to time the outgoing STM– signals.
Automatic selection of one of the above sources (except internal oscillator) performed by selector A is
used for external devices (T4/T5). This output is duplicated (1+1) on both FLC boards to avoid single point
of failure. It can be configured for 2 MHz (T4) or 2 Mbit/s (T5). Such outputs are not available, if
1.544 Mbit/s sources are used.
ED
03
3AG 24163 BEAA PCZZA
531
236 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Up to three references (T1) may be selected among all STM–N traffic ports in the system.
Two external inputs (2 MHz or 2 Mbit/s or 1.5 Mbit/s) are available. When configured as 2 Mbit/s, the
external clock signals can carry the SSM information.
If the selected reference is 1.544 Mbit/s, then only selector B is available. In this case no quality selection
(SSM) is possible.
The Synchronous Equipment Timing Generation (SETG) function has three modes of operation: locked,
holdover and free running. In holdover mode, the SETG holds the frequency of the last valid reference with
a maximum drift of +/– 0.37–ppm per day. The accuracy of the local oscillator is 4.6 ppm, according to
ITU–T G.813.
By user command will be possible forcing the timing circuitry into holdover or free running mode.
Synchronization of NEs, within the SDH/SONET network, is necessary in order to prevent pointer
accumulation.
The timing can be provided by:
•
•
A timing signal external to the NE (T1, T2, T3, T6)
An internal timing generator (OSC)
Master–slave synchronization of SDH/SONET NE uses a hierarchy of clocks in which each level of the
hierarchy is synchronized with reference to a next higher level.
The highest level is the Primary Reference Clock (PRC).
The general structure of SETS is following described (refer to Figure 134. on page 236.):
•
The SDH Equipment Clock accepts synchronization inputs from a number of sources (T1, T2,
T3, T6)
•
Automatic selection of one of these sources is achieved by selector A or B, using quality (SSM
algorithm) and priority criteria; also manual selection is possible; T0 (after a filtering operation
by SETG block) is used like internal clock and to time the outgoing SDH STM–N signals;
(in case of T6=1.5 Mbit/s only selector B without quality criteria available)
•
STM-N/2 Mbit/s signals received at drop shelves (OEDs) can only be used for internal timing
at selector B, but not for the selector A.
•
The clock signal T4 (2 MHz) or T5 (2 Mbit/s) is a possible source for an external device.
T4 and T5 output can also be forced to T0 for testing purposes of the system clock.
In order to prevent phase jumps, always use a Secondary Support Unit (SSU) between
output T4/T5 and input of an external equipment .
1AA 00014 0004 (9007) A4 – ALICE 04.10
The SETG function filters the selected timing reference to ensure that the timing requirements at the T0
reference point are met. Additionally the SETG function filters the frequency changes caused by selecting
a different reference source to achieve clock switching without any traffic hit. It has three modes of
operation:
ED
•
Locked mode: output signal controlled by the selected external timing reference;
•
Holdover mode: SETG has lost its controlling external timing reference, and is using stored
data, acquired whilst in locked mode, to control its output; the internal oscillator signal is phase
corrected according to the stored data, and used as timing reference by SETG in the holdover
mode;
03
3AG 24163 BEAA PCZZA
531
237 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
•
Free run mode: it is not a normal operating mode. In this mode the clock has never acquired
lock with an external timing reference, or has not access to the stored data acquired during
previous lock state; the SETG output timing, in free run mode, is locked to the internal oscillator.
In 1678MCC both FLCSERV and FLCCONGI boards support one T3/T6 input signal and one T4/T5 output
signal. The T4/T5 output signal is the same for both boards.
The maximum number of STM–N / 2 Mbit/s signals, incoming from STM–N / E1 ports, that can be used
as timing reference (in the protection group) is equal to three. There is not any restriction about the number
of signals coming from each board.
ED
03
3AG 24163 BEAA PCZZA
531
238 / 531
13.7 Protection Subsystem
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The available types of protections supported in the 1678MCC equipment are:
•
Equipment Protection (EPS), refer to para. 13.7.1 on page 240, para 13.7.2 on page 241
•
Network protections, refer to para. 13.7.4 on page 247
–
MSP (Multiple Section linear trail Protection):
•
1+1 linear single–ended
•
1+1 linear dual–ended
•
N:1 (Nmax=14)
–
SNCP/I and SNCP/N
It is used on ring, linear and mesh network topology. Switching occurs on the path,
selecting (Rx side) the signal transmitted to both Tx A and Tx B (A and B are two different
directions) sides.
–
Drop & Continue (dual node or collapsed).
It is an architecture to connect sub–networks, in order to improve traffic availability with
hardware resource reduction.
–
MS–SPRing.
The 1678MCC supports the following MS–SPRing protection schemes:
•
•
2 Fiber at STM–16 interfaces
2 Fiber at STM–64 interfaces
MS–SPRing protection is supported only for sections not containing AU–3.
The main features of the 2 Fiber MS–SPRing are:
•
•
1AA 00014 0004 (9007) A4 – ALICE 04.10
D&C
Programmable WTR
The 1678MCC supports programmable WTR (Wait To Restore) time to recover from
the failure status; the following values are allowed:
–
1 – 15 min in steps of 1 min
–
20, 30, 45, 60, 90 min
–
2, 4, 8, 12, 24, 48 hours
•
Programmable Hold off Time
The Hold off Time for line switching is provisionable in the range of 0 – 10 sec with
the following steps: 0, 30ms, 50ms, 70ms, 100ms, 300ms, 500ms, 700ms, 1s, 3s,
5s, 10s.
Note:
The 1678MCC can support up to 28 2F MS–SPRing schemes at the same time
independently on they are @STM–16 and/or @STM–64.
ED
•
Centralized restoration.
The 1678MCC can automatically restore a path in a centralized meshed network, under the
1354NP manager. The path is restored at VC–4/VC–4nc level.
The centralized restoration time is < 500 ms in worst case (fiber cut scenario).
The First Level Controller function is redundant for maximizing the node availability. The same
node can manage together the meshed and ring network: the resources dedicated to the
restoration are managed by NP, while the others are managed by RM.
•
Distributed restoration.
The distributed restoration is one of the major benefits introduced with the GMPLS control
plane.
03
3AG 24163 BEAA PCZZA
531
239 / 531
13.7.1 EPS Protection Main Shelf
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The EPS protection is supported on the 1678MCC equipment for the following boards:
•
•
•
MX160/320/640GE board (redundancy of HO matrix, CRU and SLC)
LAX20/LAX40 board
FLCCONGI and FLCSERV boards (only for First Level Controller and GMRE functions)
13.7.1.1 HO Matrix EPS
The positions of main and spare matrices are fixed (at start–up and in normal conditions):
•
•
slot 10 : MX160/320/640GE main
slot 11 : MX160/320/640GE spare
1+1 MATRIX + TIMING EPS
The 1678MCC architecture merges on the same board the Matrix and Timing, as well as the SLC
driving this circuitry and the peripheral logic of each service/traffic board equipped in the shelf.
Every failure condition blocking the availability of one of these centralized functions initiates the EPS
switch algorithm, which affects simultaneously the three parts.
In case of switching due to operator commands (manual command), the Matrix + Timing + SLC
switching mechanism is traffic hitless if the NE is synchronized (in locked state), if the NE is in
free–running or in Holdover condition the switching can cause some errors on traffic.
This protection is not revertive.
External commands to control the switch position are:
•
Manual to protection: to switch from protected (Main board) to protecting board (Spare board).
This command is accepted if no failure is present on protecting board.
Manual to protected: to switch from protecting board (Spare board) to protected one (Main
board).
This command is accepted if no failure is present on protected board.
Lockout: the protection is locked, the traffic is managed by protected board independently of
its status, in failure or not in failure.
Clear: release command which is active.
•
•
•
13.7.1.2 LO Matrix EPS
The positions of main and spare LAX boards are flexible as follow. LAX A and LAX B have to be mounted
always as pair (1+1 EPS) in the port slots (slot #2 to #9 or slot #12 to #19).
The HO SLC controls the LAX20/40 like an I/O board that can be EPS protected with another LAX20/40.
1AA 00014 0004 (9007) A4 – ALICE 04.10
NOTE:
Any LAX20/40 switch leads to a transmission hit. In case of EPS, traffic will be interrupted for <50 ms!
ED
03
3AG 24163 BEAA PCZZA
531
240 / 531
13.7.1.3 FLC EPS
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The positions of main and spare First Level Controllers are fixed (at start–up and in normal conditions):
•
•
slot 20 : First Level Controller main (on FLCCONGI board)
slot 1 : First Level Controller spare (on FLCSERV board)
The EPS is characterized by the parameters shows in the following Table 40. on page 241.
Table 40. EPS Protection Scheme parameters
Parameter
Values
Architecture type
1 +1
Switching type
uni–directional (single–ended)
Operation type
not revertive
WTR time
not applicable
Switching time
= 5 min
Signal switching condition
equipment failure condition
Priority
not applicable
13.7.2 EPS Protection 1670SM Shelf
EPS protection is applicable to the service boards and to the PDH/SDH traffic boards with electrical
interfaces. In the latter case the EPS is applied to the interface traffic board only; the access module boards
are part of the line and unprotected.
General characteristics of the EPS protection mode are:
•
•
•
Switching criteria: board–missing, board–fail;
Switching time: max 50 ms;
Operation mode:1+1 EPS on matrix is always non–revertive, N+1 EPS is always revertive with
fixed WTR = 5 minutes;
External commands to control the switch position: Manual, Lockout, Clear.
•
Equipment modularity and implementation peculiarities will be case by case mentioned in the description
of the individual EPS protection.
For the EPS protection it is necessary to distinguish between:
1AA 00014 0004 (9007) A4 – ALICE 04.10
•
•
ED
High Capacity Matrix board protection (refer to para. 13.7.2.1 on page 242);
High Speed port protection: 4 x STM–1 or 16 x STM–1 (refer to para. 13.7.2.2 on page 242).
03
3AG 24163 BEAA PCZZA
531
241 / 531
EPS protection will be characterized by the following parameters:
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Parameters
Values
1 + 1 EPS
N + 1 EPS
1+1
N+1
Architecture type
Switching type
uni–directional (single–ended) uni–directional (single–ended)
Operation type
not revertive
revertive
WTR time (*)
not applicable
supported but fixed to 5 min
Equipment failure condition
Equipment failure condition
1+1
N+1
Signal switching condition
Architecture type
(*) the WTR cannot be used in case of release of operator commands.
13.7.2.1 Matrix Board Protection
The positions of main and spare matrices are fixed (at start–up and in normal conditions):
•
•
slot 22 : HCMATRIX main
slot 41 : HCMATRIX spare
1+1 MATRIX + TIMING EPS
The OMSN architecture merges on the same board the Matrix and Timing, as well as the SLC driving this
circuitry and the peripheral logic of each service/traffic board equipped in the shelf.
Every failure condition blocking the availability of one of these centralized functions initiates the EPS
switch algorithm, which affects simultaneously the three parts.
In case of switching due to operator commands ( manual command), the Matrix + Timing + SLC switching
mechanism is traffic hitless if the NE is synchronized (in locked state), if the NE is in free–running or in
Holdover condition the switching can cause some errors on traffic. This protection is not revertive.
External commands to control the switch position are:
•
Manual to protection: to switch from protected (main board) to protecting board (Spare board).
This command is accepted if no failure is present on protecting board;
Manual to protected: to switch from protecting board (Spare board) to protected one (main
board) This command is accepted if no failure is present on protected board;
Lockout: the protection is locked, the traffic is managed by protected board independently of
its status, in failure or not in failure;
Clear: release command which is active.
•
•
•
13.7.2.2 High Speed (HS) Port Protection
In 1670SM equipment are available the following two EPS:
•
•
1AA 00014 0004 (9007) A4 – ALICE 04.10
N+1
4 x STM–1 electrical
16 x STM–1 electrical
4 x STM–1 electrical EPS
The EPS is supported for the 4 x STM–1 electrical board (P4ES1N) used in conjunction with the 4 x STM–1
access module (A4ES1).
One or more N+1 EPS protection groups can be configured (up to three).
ED
03
3AG 24163 BEAA PCZZA
531
242 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The position of the spare board is flexible but in the corresponding access slot the HPROT board has to
be plugged in. The spare board has to be plugged at the left side of the main ports; the main/spare ports
have to be adjacent.
The scheme is revertive with fixed WTR= 5 min.
In 1670SM up to 15 main boards can be protected in EPS (15+1).
External commands to control the switch position are:
•
Manual to protection: to switch from protected (main board) to protecting board (Spare board);
this command is accepted if no failure is present on protecting board;
Lockout protection : the protection is locked, the no main board can be used protection;
Clear: release command, which is active.
•
•
N+1
16xSTM–1 electrical EPS
The EPS is supported for the 16STM–1 electrical/optical board (P16S1N) used in conjunction with the
16xSTM–1 electrical access module (A16ES1).
One or more N+1 EPS protection can be configured (up to three).
The position of the spare board is flexible but in the corresponding access slot the HPROT16 board has
to be plugged in. The spare board has to be plugged at the left side of the main ports; the main/spare ports
have to be adjacent.
The scheme is revertive with fixed WTR= 5 min.
In 1670SM up to 15 main boards can be protected in EPS (15+1).
External commands to control the switch position are the same of N+1 4xSTM–1 electrical EPS.
Here below are present more details referred to N+1 4xSTM–1 electrical EPS.
As High Speed ports (HS) are intended 155 Mbit/s speed ports.
Up to 16 HS ports can be housed in the basic area.
For the electrical HS ports the corresponding access boards have to be put in the access area with fixed
relations.
More than one protection group N+1 revertive can be created, depending on the equipment configuration.
For each group N+1 protected group the revertive mode is supported while the 1+1 EPS can be only
revertive.
The spare board position can be assigned in a flexible way.
The only constraints are the following:
•
•
•
•
•
the access board corresponding to the protecting board must be an HPROT access board
the HPROT board has to be plugged at the left side of the access board group (A4ES1)
the main/spare ports have to be adjacent
the protecting ports has to be plugged at the left side of the protected group of ports (P4ES1N)
the protecting/protected group of ports have to be of the same type.
Note that no protection is planned for the access board, and note also that the type of protection can’t be
changed (i.e. it is not possible to change the protection scheme from N+1 to 1+1).
1AA 00014 0004 (9007) A4 – ALICE 04.10
Manual Switch and force switch commands can be given via software by the user to activate the spare
boards.
Each access board is connected also with the previous one and with the next one; in this way N+1
protection is provided using HPROT board in last position at the left side of the access boards pertaining
to the protected port group.
Each electrical High Speed port (P4ES1N) can manage up to 4 HS streams.
ED
03
3AG 24163 BEAA PCZZA
531
243 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Input side (from the access module point of view)
The CMI encoded signal coming from the line and connected to the access board is NRZ decoded. The
clock CK is extracted from the data. By means of the back panel connections, NRZ data and CK are
forwarded to the pertaining main port and to the spare port.
Moreover NRZ data and Clock are sent to the next access board if present to perform N+1 protection.
The spare port should not be devoted to a specific main port therefore a distributed switch matrix (on every
access board) is used to allows the signal to gain the spare port.
The command criteria for the distributed switch matrix comes from the matrix board via serial interface.
Output side (from the access module point of view)
The signal, coming from Main and Spare ports via back panel connections, is coded into CMI format.
The spare port is not devoted to a specific main port, therefore the signal transmitted from the spare is
distributed to all access boards involved in the protection scheme. The connections are functionally
point–to–multipoint but physically every access board realizes a point–to–point connection towards the
previous and the next access board using a buffer to decouple and regenerate the signal.
Hardware failures types
The hardware failures causing automatic EPS protection switch can be grouped as:
•
failures causing the internal equipment link loss as powering KO, Clock loss, board missing
(referred as LOS/LOF);
failures causing traffic loss (the internal link is preserved) as for instance unlocked oscillator,
electrical interface defective and so on;
failures not causing traffic loss nor internal link loss but causing loss of management as ISBP
failure or SPI failure.
•
•
1AA 00014 0004 (9007) A4 – ALICE 04.10
Moreover some failures can cause equipment malfunctioning (as remote inventory fault, laser degrade,
loss of DC/DC synchronism).
These hardware faults are signalled to the management system and do not provokes an automatic switch.
ED
03
3AG 24163 BEAA PCZZA
531
244 / 531
13.7.3 EPS Protection 1662SMC Shelf
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The EPS protection is supported on the 1662SMC equipment for the following boards:
Equipment Boards
Protection Scheme
Number of protection schemes
Mode
1+1
1
Not revertive
N+1 (N max = 6)
1
Revertive
SYNTH16
Low Speed ports:
– 63x2Mbit/s
13.7.3.1 SYNTH16 Board Protection
The positions of main and spare SYNTH16 are fixed:
–
–
slot 6 : COMPACT ADM main
slot 15 : COMPACT ADM spare
13.7.3.2 Low Speed (LS) Port Protection
As Low Speed ports (LS) are intended the 2 Mbit/s ports.
For the relation between LS ports and access boards refer to para 12.2.4.3 on page 182.
The positions of main and spare P63E1 are optional.
The P63E1 port can manage up to 63 x 2 Mbit/s ports. Sixty–three bidirectional links are used for each
connection between P63E1 port and A63E1 access board.
The main P63E1 ports are connected in a fixed way to A63E1 access boards using point–to–point
connections. The spare P63E1 port is connected to LSPROT board also using point–to–point
connections.
Under alarm condition, the signal transmitted and received from the main port is switched towards the
LSPROT board, and then connects to the spare port.
In the following a generic description of the access board is given:
Input side
Under normal operating condition, the signal received from the line is sent to the 63 x 2 Mbit/s Pertaining
port board.
Under alarm condition, the signal received from the line is switched towards the LSPROT board. The
switching command SEL is received from the RIBUS I/F block.
A protection block is present to protect the incoming signal against spikes (G.703).
Output side
1AA 00014 0004 (9007) A4 – ALICE 04.10
Under normal operating condition, the signal received from the main port is sent to the line.
Under alarm condition, the signal received from the spare port is switched towards the LSPROT board
and then sent to the line.
The SEL command, received from the RIBUS I/F block, select the signal to sent to the line.
The LSPROT board is used to realize EPS protection for Low Speed ports. It realizes the connection
between the spare port board and LS protection bus if protection request.
The switches to select between main links and protection links are located on the access boards and
managed by the RIBUS block. The switch is activated in case of failure.
ED
03
3AG 24163 BEAA PCZZA
531
245 / 531
Hardware failures types
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The hardware failures causing automatic EPS protection switch can be grouped as:
•
failures causing the internal equipment link loss as powering KO, Clock loss, board missing
(referred as LOS/LOF);
failures causing traffic loss (the internal link is preserved) as for instance unlocked oscillator,
electrical interface defective and so on;
failures not causing traffic loss nor internal link loss but causing loss of management as ISBP
failure or SPI failure.
•
•
Moreover some failures can cause equipment malfunctioning (as remote inventory fault, laser degrade,
loss of DC/DC synchronism).
These hardware faults are signalled to the management system and do not provokes an automatic switch.
ED
03
3AG 24163 BEAA PCZZA
531
246 / 531
13.7.4 Network Protections
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.7.4.1 Multiplex Section Protection (MSP)
Special features of the 1670 OED Shelf
STM–N Linear Single–Ended 1+1 APS and STM–N Linear Dual–Ended 1+1 APS are only supported
for optical interfaces (STM–1 and STM–4 optical)!
MSP 1:N is supported for STM–1/4 optical and STM–1 electrical interfaces.
The following restrictions exist for the MSP 1:N feature for electrical interfaces in the 1670 OED shelf:
–
MSP 1:N is only supported for A16ES1/P16S1 boards.
–
No EPS allowed in case of MSP 1:N protection
That means there is no support of a mixed configuration of MSP 1:N and EPS within a shelf. Also,
if MSP is configured, no HPROT board can be provisioned.
–
HW limits a mix of port numbers only in the group of ports 1..8 and the group of ports 9..16.
–
The electrical interfaces of an OED cannot be in the same MSP group as optical interfaces.
STM–N Linear Single–Ended 1+1 APS
The whole section is duplicated from the originating node for each direction of transmission.
Tx side is permanently bridged. In Rx side the best signal is selected. As the scheme is “unidirectional
protection mode“, the switch occurs only at the near–end where the failure is detected and the K1/K2
messages are just devoted to carry info switch status to the far–end.
This protection protects against Transmission failures (LOS, LOF, MS_AIS) or section degradation
(MS_SD or MS_EXBER) or HW failure which affects the traffic.
Only Non–revertive mode is supported.
Protection takes place within 50 ms.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The implementation is compliant with the G.841 – 7.1 clause: MSP protocol compatible with the 1:N MSP
operation.
Operator command are according G.841 and the following one are supported:
•
Manual to protection: to switch from protected (Main resource) to protecting board (Spare
resource). This command is accepted if no failure is present on protecting board.
•
Manual to protected: to switch from protecting board (Spare resource) to protected one (Main
resource). This command is accepted if no failure is present on protected board.
•
Force to protection: to switch from protected (Main resource) to protecting board (Spare
resource). This command is accepted if no failure is present on protecting board.
•
Force to protected: to switch from protecting board (Spare resource) to protected one (Main
resource). This command is accepted if no failure is present on protected board.
•
Lockout: the protection is locked, the traffic is managed by protected board independently of
its status, in failure or not in failure.
•
Clear: release command which is active.
•
Exercise: not supported.
Refer to Figure 135. on page 249.
ED
03
3AG 24163 BEAA PCZZA
531
247 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
STM–N Linear Dual–Ended 1+1 APS
The whole section is duplicated from the originating node for each direction of transmission.
Tx side is permanently bridged. In Rx side the best signal is selected, in bi–directional operation mode the
selector is moved only when the two sides agreed the operation; and for this reason a side makes requests
then waiting for acknowledgements of switch action from other side by using the APS bytes.
This protection protects against Transmission failures (LOS, LOF, MS_AIS) or section degradation
(MS_SD or MS_EXBER) or HW failure which affects the traffic.
Only Non–revertive mode is supported.
Protection takes place within 50 ms.
The implementation is compliant with the G.841 – 7.1 clause: MSP protocol compatible with the 1:N MSP
operation.
Operator command are according G.841 and the following one are supported:
•
Manual to protection: to switch from protected (Main resource) to protecting board (Spare
resource). This command is accepted if no failure is present on protecting board.
•
Manual to protected: to switch from protecting board (Spare resource) to protected one (Main
resource). This command is accepted if no failure is present on protected board.
•
Force to protection: to switch from protected (Main resource) to protecting board (Spare
resource). This command is accepted if no failure is present on protecting board.
•
Force to protected: to switch from protecting board (Spare resource) to protected one (Main
resource). This command is accepted if no failure is present on protected board.
•
Lockout: the protection is locked, the traffic is managed by protected board independently of
its status, in failure or not in failure.
•
Clear: release command which is active.
•
Exercise: not supported.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Refer to Figure 135. on page 249.
ED
03
3AG 24163 BEAA PCZZA
531
248 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Single ended 1+1
1
MAIN
MAIN
2
1
SPARE
SPARE
2
a) Normal conditions
APS
1
MAIN
SWITCH
MAIN
2
MS–RDI
1
SPARE
SPARE
2
b) Unidirectional failure
Dual ended 1+1
1
MAIN
MAIN
2
1
SPARE
SPARE
2
a) Normal conditions
APS
1 SWITCH
MAIN
MAIN
2
APS
1
SPARE
SPARE
SWITCH 2
1AA 00014 0004 (9007) A4 – ALICE 04.10
b) Unidirectional failure
Figure 135. MSP Linear 1+1 single and dual ended protection
ED
03
3AG 24163 BEAA PCZZA
531
249 / 531
STM–N Linear dual–ended 1:N APS
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1:N (N=14 max.) linear protection without extra traffic is supported.
One section is used as spare resource to protect one of the N main sections when in failure.
The implementation is compliant with the G.841 – clause 7.1 MSP protocol compatible with the 1:N MSP
operation.
Only revertive mode is supported. A WTR time beween 1 and 15 minutes can be configured in steps of
1 minute. A Hold–off time between 0 and 10 seconds can be configured.
When the protection section is not in use, null signal is indicated on both sent K1 and K2 bytes.
The operation switch is bi–directional, which means that both Tx side and Rx side switch will occur (using
K1/K2 messages) in compliant with the G.841 protocol operations.
In this mechanism the priority can be assigned to the main resource so that in case of double failure the
high priority traffic is restored.
This protection protects against transmission failures (LOS, LOF, MS_AIS) or section degradation
(MS_SD or MS_EXBER) or hardware failure, which affects the traffic.
Protection takes place within 50 ms.
Operator command are according G.841 and the following one are supported:
•
Manual to protection: to switch from protected (Main resource) to protecting board (Spare
resource). This command is accepted if no failure is present on protecting board.
•
Force to protection: to switch from protected (Main resource) to protecting board (Spare
resource). This command is accepted if no failure is present on protecting board.
•
Lockout: the protection is locked, the traffic is managed by protected board independently of
its status, in failure or not in failure.
•
Clear: release command which is active.
•
Clear WTR: supported.
•
Exercise: not supported.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Refer to Figure 136. on page 251.
ED
03
3AG 24163 BEAA PCZZA
531
250 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Dual ended 1:N without extra traffic
1
2
1
MAIN
2
MAIN
1
1
#1
2
#1
2
1
2
1
MAIN
2
MAIN
1
1
#N
2
#N
SPARE
2
SPARE
a) Normal conditions
1
2
1
MAIN
2
MAIN
1
2
1
#1
#1
2
Link failure
SWITCH
1
2
SWITCH
1
MAIN
1
#N
SPARE
1AA 00014 0004 (9007) A4 – ALICE 04.10
2
MAIN
1
2
#N
b) Failure conditions
SWITCH
SWITCH
2
SPARE
Figure 136. MSP Linear 1:N Dual–Ended protection
ED
03
3AG 24163 BEAA PCZZA
531
251 / 531
13.7.4.2 SNCP (Sub–Network Connection Protection)
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Refer to Figure 137. on page 253 and Figure 138. on page 254.
Subnetwork Network Connection protection is a dedicated protection mechanism that can be used to
protect a path (e.g. that portion where two separate path segments are available) or the full end–to–end
path. It may be applied at any path layer in a layered network.
Two types of SNCP are possible:
•
SNCP/I (Inherent monitoring) that switches on SSF criteria (AU–AIS and AU–LOP);
•
SNCP/N (Non–intrusive monitoring) where POH is monitored by the POM enabled before the
matrix. The switches criteria are SSF and one or more of ExBER, TIM, UNEQ, SD; in this case
the same selection must be made on each NE of the ring.
SNCP is employed on ring networks on which several equipments have been installed.
It can be also employed in Linear or Meshed network topology.
Two operating mode can be selected for single VC SNCP:
•
revertive (the signal is switched back into the working channel, after recovery of the fault).
In the revertive operation the ”Wait time to restore” (WTR) is fixed at 5 min.
•
not revertive
As illustrated in the example shown in Figure 137. on page 253 several equipment (numbered 1 to 5) are
ring–connected on a looped path.
Each of the equipment on the node is bidirectionally connected (Side A and Side B). One of the two
directions represent the main path (clockwise). The opposite direction will utilize a second fiber line for the
spare traffic (counter clockwise).
The SNCP automatic protection intervenes upon detecting path failure (SSF).
Each transmitting signal node is permanently connected (bridge) in the main traffic direction (clockwise)
and in the protected traffic direction(counter clockwise).
The Tx signal reaches destination through two different paths thus enabling the node receiving it to select
the best one (switch).
The switching decision can be taken at the NE level (automatic switch) or at the OS level (management
switch).The forced switch and lockout command is supported.
The automatic switch is initiated upon detection of failure on the receiving end (sink side). The following
table resumes the protection scheme features for SNCP/I and SNCP/N.
Table 41. SNCP configuration
Protection type
Switching
Type
Switching
Criteria
Hold Off time
(sec)
mode
Wait to Restore time
SNCP/I
(inherent)
unidirectional/
single ended
AIS (SSF)
AU–LOP (SSF)
(not planned)
revertive/
not revertive
fixed 5 min
unidirectional/
single ended
AU–AIS (SSF)
AU–LOP (SSF)
ExBER
TIM
UNEQ
SD
selectable
(future release)
revertive/
not revertive
fixed 5 min
1AA 00014 0004 (9007) A4 – ALICE 04.10
SNCP/N
(non intrusive)
ED
03
3AG 24163 BEAA PCZZA
531
252 / 531
The example of Figure 137. on page 253 illustrates the connection between two signals (T1 between
nodes 2 and 5 and T2 between nodes 1 and 4) and relevant in/out nodes with associated pass–through.
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Figure 138. on page 254 shows two examples of failures and subsequent SNCP switching mechanism.
A failure or degrade on the main path causes to switch over to the spare one.
When the receiving end switches no information is sent to the corresponding Tx side to activate the
switching operation at the remote end (Single ended ”switching operation).
To manage switching the SNCP architecture utilizes the data inherent to the Path and not to the Line.
Switching is in fact activated by defective operations occurring at the VCn levels (AU–AIS, AU–LOP,
ExBER).
When the path is no longer available, an AIS signal is transmitted on the same path to activate protection.
In this manner SNCP can protect the paths following cable break–down or failures along the fiber and
nodes.
Cable break–down concerns all the fibers it contains hence it places traffic in both directions out–of–
service, while a failure concerns only one fiber.
The units are provided with a path switching circuit (bridge + switch).
Its enabling depends on the equipment configuration.
With SNCP each working path has a dedicated protection path.
Side B
3
Side A
T1, T2 Pass–through
2
BRIDGE
Side A
Side B
4
T2
T2 Pass–through
T1 Drop/Ins Prot.
T1
T1 Pass–through
T2 Drop/Ins Prot.
Side B
SWITCH
Side A
CLOCKWISE
1
Side A
COUNTER
CLOCKWISE
Side B
5
T1
T1 Pass–through
T2 Drop/Ins Prot.
T2
1AA 00014 0004 (9007) A4 – ALICE 04.10
Side B
T2 Pass–through
T1 Drop/Ins Prot.
Side A
NOTES: On Craft Terminal, the following terminology is used:
Pass–Through= Bidirectional Connection
Drop/Ins Prot.= Bidirectonal Protected Connection
Figure 137. Typical ring network with SNCP
ED
03
3AG 24163 BEAA PCZZA
531
253 / 531
Case of cable break between nodes 2 and 3
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Cable break
3
AU–AIS on T1,T2
2
Switch on spare path
4
SSF
T1
T2
MAIN
1
SPARE
Switch on spare path
5
SSF
T2
T1
Case of unidirectional failure between nodes 5 and 1
3
Switch on spare path
2
4
T1
T2
SSF
1
MAIN
SPARE
5
T2
T1
SSF
Switch on spare path
1AA 00014 0004 (9007) A4 – ALICE 04.10
Unidirectional failure
Figure 138. Failure examples in SNCP ring
ED
03
3AG 24163 BEAA PCZZA
531
254 / 531
13.7.4.3 Drop and Continue
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Refer to from Figure 139. on page 256 to Figure 141. on page 258.
The Drop and Continue architecture has been implemented in the network to improve traffic availability.
Drop and Continue is a way of protecting a path crossing a number of sub–networks, e.g., rings.
The sub–networks should be connected through at least two nodes (so realizing two independent
connections).
The equipment is configured as ”DROP and CONTINUE” on each interconnection node.
The subnetworks’ equipment implement the connection between two SNCP rings.
The resulting architecture affords protection against multiple failures (evenly distributed one per
subnetwork) tolerated without traffic loss (node failure or single cable cut).
The Drop and Continue feature improves traffic availability as compared with the simple ”end–to–end
SNCP”.
More subnetworks are connected the further is availability increased.
The Drop and Continue features simultaneously realizes the following on one node:
•
•
•
unidirectional pass–through
protected drop
insertion in one direction
The configurations achievable are:
•
D/C–A INS–A (called “Normal” on Craft Terminal)
•
D/C–A INS–B (called “Inverse” on Craft Terminal)
D/C stands for ”Drop and Continue”, the letter after it (A = line side” A”) indicates the ”drop ” side (e.g., “A”
means “A main side”, and consequently the spare side is the “B” one).
The end letter (INS–B or INS–A) indicates the insert side.
Note:
The letters “A” and “B” are not referred to a specific board or ports in a physical slot of the
subrack; “A” and “B” are used in the figures of this paragraph to identify a Line direction.
The ”Unidirectional pass–through” is always in the direction opposite to that of the ”insert” side (e.g., when
”INS B” the pass–through is from B side to A side).
1AA 00014 0004 (9007) A4 – ALICE 04.10
For further information refer to Figure 139. on page 256 which shows the D/C–A INS–A configuration
(called “Normal” on CT) and the D/C–A INS–B configuration (called “Inverse” on CT).
ED
03
3AG 24163 BEAA PCZZA
531
255 / 531
Drop and Continue D/C A INS A (”Normal”)
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
LINE PORT
SIDE A
LINE PORT
SIDE B
Output
Input
Output
Input
Symbol used on Craft Terminal
PORT
Input
Output
Drop and Continue D/C A INS B (”Inverse”)
LINE PORT
SIDE A
LINE PORT
SIDE B
Output
Input
Output
Input
Symbol used on Craft Terminal
PORT
Input
Output
Figure 139. Drop and Continue D/C A INS A and D/C A INS B
The ”Drop and Continue” featuring two connected SNCP rings (with dual node connection) is indicated
in Figure 140. on page 257. It shows the connection of a path signal between the two nodes 1 and 8.
The relevant path signal is:
•
•
•
connected in Drop and Continue (D/C A – INS A) in nodes 3, 4, 6 and 10
connected in pass–through in nodes 2, 5, 7, 9
connected in drop/ins protection in nodes 1, 8
Note:
The following terminology is used on Craft Terminal:
pass–through
= Bidirectional connection
drop/ins protection = Bidirectional Protected connection
1AA 00014 0004 (9007) A4 – ALICE 04.10
When in normal condition, the unidirectional way of traffic from 1 to 8 is supposed to be 1 ! 2 ! 3 ! 6
! 7 ! 8.
After a failure on the 1st ring between nodes 2 and 3 (refer to Figure 141. on page 258), the link direction
is: 1 ! 5 ! 4 ! 3 ! 6 ! 7 ! 8, with a switch on node 3.
After a second failure on the 2nd ring between nodes 6 and 7 (refer to Figure 141. on page 258) the
selected direction on the link is: 1 ! 5 ! 4 ! 10 ! 9 ! 8. The operative switch is on node 8 and the
previous pass–through between nodes 4 and 3 is no more used.
ED
03
3AG 24163 BEAA PCZZA
531
256 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1
2
5
SNCP ring
D/CA INSA
A Port 1
D/CB INS B
B
Port 2
INS
A
A
3
Port 2
Port 1
INS
B
4
Port 3
Port 3
Port 3
Port 3
6
10
INS
B
INS
A
A
B
Port 1
Port 2 B
A Port 1
D/CA INSA
Port 2
B
D/CB INSB
7
9
SNCP ring
1AA 00014 0004 (9007) A4 – ALICE 04.10
8
Figure 140. Drop and Continue
ED
03
3AG 24163 BEAA PCZZA
531
257 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1
2
5
SNCP ring
3
4
Drop & Continue
1st failure
switched
6
7
10
SNCP ring
9
8
1
2
5
SNCP ring
4
3
Drop & Continue
2nd failure
6
7
10
SNCP ring
9
8
1AA 00014 0004 (9007) A4 – ALICE 04.10
switched
Figure 141. Drop and Continue – 1st and 2nd failure
ED
03
3AG 24163 BEAA PCZZA
531
258 / 531
13.7.4.4 Multiplex Section shared Protection Rings (MS–SPRING)
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The following protection MS–SPRING is supported:
–
2 fiber MS–SPRING at STM–16
–
2 fiber MS–SPRING at STM–64
The supported MS–SPRING is compliant to the ITU–T Rec. G.841
The MS–SPRING protection is realized in the MATRIX card.
A 2 fiber MS–SPRING (Multiple Section–Shared Protection Ring) consist of a set of NEs each equipped
with a two bidirectional port, one for the clockwise and the other for the counter–clockwise. The
MS–SPRING is said ”two fiber” because each pair of adjacent NEs is linked by two fibers, one for each
direction.
The MS SPRING protection is an alternative with respect to SNCP. While MS SPRING allows the
connection at the same time on the clockwise and on the counterclockwise direction on the same AU4 that
can be inserted and extracted in each span, on the contrary the SNCP connection engages the same AU4
on both sides for the whole link.
Note:
In the following the 2F MS–SPRING at STM–16 will be explained; the same description can be
applied to 2F MS–SPRING at STM–64 taking into account that 64 AU– 4 are available and that the
bandwidth is divided into two halves of equal capacity called respectively ”working” (AU4#1 to
AU4#32) and ”protection” capacity (AU4#33 to AU4#64).
2 fiber MS–SPRING at STM–16 level
The bandwidth of a 2F MS–SPRING is divided into two halves of equal capacity called respectively
”working” (AU4#1 to AU4#8) and ”protection” capacity (AU4#9 to AU4#16). The AU4#1 is protected by
AU4#9 up to AU4#8 that is protected by the AU4#16. The ”working ” capacity is used to carry the ”high
priority traffic”, while the ”protection” capacity can be used for ”low priority” traffic that is lost in case of
failure. Refer to Figure 142. on page 260.
The MS SPRING algorithm starts as a consequence of the following section alarms:
1AA 00014 0004 (9007) A4 – ALICE 04.10
•
ED
LOS, LOF, MS AIS, EXBER (B2), SIGNAL DEGRADE (B2)
03
3AG 24163 BEAA PCZZA
531
259 / 531
PORT
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
B
B
A
A
A
1
2
3
B
B
6
5
4
A
A
B
A
B
WORKING CHANNELS (AU4#1 TO AU4#8)
PORT
PROTECTION CHANNELS (AU4#9 TO AU4#16)
Figure 142. 2F MS SPRING Connection
APS in 2–fiber MS–SPRING
In case of fibre break the APS for 2F MS–SPRING uses a synchronized sequence of ”bridge” and
”switch” operations that modify the internal connections of the two NEs adjacent to the failure and
permits the ”high priority” traffic to be restored.
Only the NEs adjacent to the failure are interested to the ”switch” and ”bridge” functions while for all other
NEs the final configuration is a ”pass through” of all ”protection” (low priority) AU4s.
Figure 143. and Figure 144. on page 261, Figure 145. and Figure 146. on page 262 highlight how the
connections are modified as a consequence of a ”bridge ” or a ”switch” operation.
The Bridge operation is performed on the Tx side while the Switch is performed on the Rx side.
•
The ”Bridge” operation on the B side has the effect of routing the outgoing ”high priority” A traffic
to the outgoing ”protection” B capacity.
The Bridge function adds a connection on the opposite side and on the relevant AU protection.
•
When a ”Switch” operation is working on the B side all the connections having an AU4
belonging to the A working capacity as a source, are replaced by connections having the
incoming B protection traffic as a source. The signals maintain the same end point connection.
The Switch function replaces the incoming flow with a protection one, coming form the opposite
side.
1AA 00014 0004 (9007) A4 – ALICE 04.10
In the same way:
ED
•
The ”Bridge” operation on the A side has the effect of routing the outgoing ”high priority” B traffic
to the outgoing ”protection” A capacity.
The Bridge function adds a connection on the opposite side and on the relevant AU protection.
•
When a ”Switch” operation is working on the A side all the connections having an AU4
belonging to the B working capacity as a source, are replaced by connections having the
incoming A protection traffic as a source. The signals maintain the same end point connection.
03
3AG 24163 BEAA PCZZA
531
260 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
A
B
A
B
A
B
A
B
protection
working
BEFORE
AFTER
Figure 143. Effect of a BRIDGE “B side” operation
A
B
A
B
A
B
A
B
protection
working
1AA 00014 0004 (9007) A4 – ALICE 04.10
BEFORE
AFTER
Figure 144. Effect of a BRIDGE “A side” operation
ED
03
3AG 24163 BEAA PCZZA
531
261 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
A
B
A
B
A
B
A
B
protection
working
BEFORE
AFTER
Figure 145. Effect of SWITCH “B side” operation
A
B
A
B
A
B
A
B
1AA 00014 0004 (9007) A4 – ALICE 04.10
BEFORE
protection
working
AFTER
Figure 146. Effect of SWITCH “A side” operation
ED
03
3AG 24163 BEAA PCZZA
531
262 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Figure 147. on page 263 depicts the final effect of Bridge and Switch synchronized steps for traffic
restoration in a network with one fault.
They are carried out via a protocol that uses the K1 and K2 bytes. The failed span is replaced by the
protection traffic of the span not affected by the failure.
The K1 and K2 are exchanged between the Node that are adjacent to the failure, instead the other Nodes
put K1 and K2 in passthrough.
SWITCH
side A
PROTECTED
SIGNAL
B
A
B
BRIDGE
side A
A
SWITCH
side B
B
BRIDGE
side B
A
1
2
3
B
6
5
4
A
(*)
(*)
A
B
A
B
WORKING CHANNELS
PROTECTED
SIGNAL
PROTECTION CHANNELS
BRIDGE
SWITCH
(*) All protection AU4 are put in Pass–through in the 5th and 6th NEs
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 147. Line break recovering operations
ED
03
3AG 24163 BEAA PCZZA
531
263 / 531
An example of 2F MS–SPRING is reported in Figure 148. on page 265.
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
In the example a ring of four nodes is protected with 2F MS–SPRING
AU4–1 carries the traffic of the span : C–B, B–A, A–D, D–C
AU4–2 carries the traffic of the span D–B (pass–through in C)
AU4–9 protects AU4–1.
AU4–10 protects AU4–2.
After a failure in the section C–B, the following actions are performed on:
–
node B : Streams access 1 and 2, previously drop–inserted on AU4–1 and AU4–2
“side A”, are switched respectively on AU4–9 and AU4– 10 “side B”.
In this way, C is reached through nodes A and D.
–
node C:
–
nodes A and D do not switch
Stream access 1, previously drop–inserted on AU4.1 “side B”, is switched on
AU4–9 “side A”.
In this way, B is reached through nodes D and A.
Rx AU4–2 “side A”, previously in pass–through on Tx AU4–2 “side B”, is looped
on Tx AU4–10 “side A”. In this way, B is reached through nodes D–A (signal
transmitted D to B).
Rx AU4–2 “side B” is no more received.
So, Rx AU4–10 “side A” is looped on the Tx AU4–2 “side A”.
In this way, the signal transmitted by node B follows the path :
A–D– C and here is looped to reaches node D again.
1AA 00014 0004 (9007) A4 – ALICE 04.10
We can obtain from the example that is possible bandwidth re–used for some traffic patterns (AU4–9
protects four connection on AU4–1) having the same protection for some several connections (shared
protection).
ED
03
3AG 24163 BEAA PCZZA
531
264 / 531
A
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
D
A
A . AU4 1
B : AU4 1
AU4.9–Prot. AU4.1
AU4.10 Prot. AU4.2
D
B
C
D
C : AU4 1
D
C
B : AU4 1
B : AU4 2
A
side B
D
B
side A
side A
side B
C
C
B
side A
AU4
1
2
9
10
side B
AU4
1
2
9
10
1AA 00014 0004 (9007) A4 – ALICE 04.10
1
2
9
10
1
2
9
10
1
side A
AU4
1
2
9
10
side B
AU4
1
2
9
10
1
2
9
10
1
2
9
10
1
2
Figure 148. 2F MS–SPRING example of operation
ED
03
3AG 24163 BEAA PCZZA
531
265 / 531
SQUELCHING FUNCTION
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The squelching function is activated when a node that carries Drop/Insert streams, remains isolated
because of a double failure.
In this case to avoid misconnections on the AU4 involved in MS SPRING protection, an AIS signal will be
inserted on Low Priority streams transmitted from the nodes adjacent to the isolated one. See Figure 149.
Before Node 2 isolation because of the double failure, the following connections were active using the
AU4#1
–
–
Stream between Port 3 and Port 1
Stream between Port 2 and Port 4
After a second failure, the Nodes adjacent to the isolated Node 2 send AIS on the Low Priority traffic
(AU4#9) by means of the Squelching function thus avoiding the misconnection between Port 3 and Port 4.
If the squelching function were not active, the MS SPRING algorithm would activate the Bridge and Switch
functions on the nodes adjacent to Node 2 thus misconnecting Port 3 and Port 4 using AU4#9 as
protection. In virtue of squelching function the nodes adjacent to isolated Node 2 send AIS on Low Priority
AU4#9 avoiding in this way the misconnection between Port 3 and Port 4 in this case.
After the failure has been removed, a similar reverse sequence of operations on the NEs adjacent to the
recovered span will be activated. The reverse procedure can start after a step programmable WTR.
PORT 1
PORT 3
PORT 2
PORT 4
AU4 #1
AU4 #1
AU4 #1
AU4 #1
B
A
B
A
SWITCH
side B
BRIDGE
side A
1
2
SWITCH
side A
BRIDGE
side B
(SF/SD)
A
(SF/SD)
3
B
AIS ON
AU4 # 9
AIS ON
AU4# 9
5
B
4
A
AIS ON
AU4 # 9
PASS–THROUGH
6
AIS ON
AU4 # 9
PASS–THROUGH
AIS ON
AU4 # 9
PASS–THROUGH
A
B
A
B
WORKING CHANNELS
1AA 00014 0004 (9007) A4 – ALICE 04.10
PROTECTION CHANNELS
Figure 149. Squelching on isolated Node connection
ED
03
3AG 24163 BEAA PCZZA
531
266 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
MS – SPRING Interworking
When a 2f MS–SPRING is interconnected with another ring (either SNCP/I or MS–SPRING), the
interconnection of the two is performed by connecting two nodes per ring with HVC connections, as shown
in Figure 150. on page 267.
Each VC4 that has to cross the ring boundary (only HVC level ring interconnections are considered here)
must be output by two nodes, one of which, the Primary Service Node (PSN) drops it and continues to the
Secondary Service Node (SSN). In the opposite direction, the SSN inserts a copy of the VC4 into the ring
and the PSN selects by means the Primary Node Service Selector function, between the VC4 coming from
the SSN and the VC4 that can be locally inserted by means an STM–1 Tributary. The selection is made
on the Path–AIS basis (AU–AIS).
The protection mechanism works on the hypothesis that the other ring selects one of the two versions of
the incoming VC4 and transmits two identical copies of the VC4 towards the PSN and the SSN (this is
guaranteed if the other ring is an MS–SPRING or an SNCP ring).
Note that the PSN and the SSN need not to be adjacent and need not to be the same for all of the VC4
that cross the ring boundary: i.e. each crossing VC4 has two associated nodes that act as PSN and SSN.
2F MS – SPRING
side A
side B
side A
side B
Secondary
Service
Node
SS
Primary
Service
Node
side A
side B
side A
side B
SNCP or MS–SPRING
1AA 00014 0004 (9007) A4 – ALICE 04.10
SS = Service Selector
Figure 150. MS SPRING Drop and Continue, Insert Continues (protected)
ED
03
3AG 24163 BEAA PCZZA
531
267 / 531
13.7.4.5 Collapsed Dual Node Ring Interconnection
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Refer to Figure 151. on page 269 and Figure 152. on page 270.
The “Collapsed dual node ring interconnection” is a way of protecting a path crossing a number of
sub–networks, e.g., rings.
The sub–networks should be connected through at least two nodes (so realizing two independent
connections).
Respect to the configuration shown in Figure 140. on page 257 (”Drop and Continue”), “Collapsed dual
node interconnection” allows a hardware reduction, since an OMSN contains several ports and a path
signal can be connected in protected mode, from a generic pot to another one, on the same equipment.
The subnetworks’ equipment implement the SNCP connection.
The resulting architecture affords protection against multiple failures (evenly distributed one per
subnetwork) tolerated without traffic loss (node failure or single cable cut).
The “Collapsed dual node ring interconnection” featuring two connected rings (with dual connection) is
indicated in Figure 151. on page 269.
SNCP protection is enabled throughout the equipment. When in normal condition, the unidirectional way
of traffic from 1 to 8 is supposed to be 1 ! 2 ! 3 ! 6 ! 8.
After a failure on the 1st ring between nodes 2 and 3 (refer to Figure 152. on page 270), the link direction
is: 1 ! 5 ! 4 ! 3 ! 6 ! 8.
Pass–through is used between nodes 4 and 3, and switch on node 3.
After a second failure on the 2nd ring between nodes 3 and 6 (refer to Figure 152. on page 270) the
selected direction on the link is: 1 ! 5 ! 4 ! 7 ! 8.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The operative switch is on node 8 and the previous pass–through between nodes 4 and 3 is no more used.
ED
03
3AG 24163 BEAA PCZZA
531
268 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1AA 00014 0004 (9007) A4 – ALICE 04.10
2
6
ED
A
C
3
03
Port 1
Port 3
1
Port 2
Port 4
8
A
C
SNCP ring
B
D
SNCP ring
Port 1
Port 3
Figure 151. Collapsed dual node interconnection
Port 2
Port 4
3AG 24163 BEAA PCZZA
531
B
D
4
5
7
269 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1
5
2
SNCP ring
switched
3
4
Collapsed dual node interconnection
1st failure
SNCP ring
6
7
8
1
2
Collapsed dual node interconnection
5
SNCP ring
3
4
2nd failure
SNCP ring
6
7
8
switched
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 152. Collapsed dual node interconnection – 1st and 2nd failure
ED
03
3AG 24163 BEAA PCZZA
531
270 / 531
13.7.4.6 Collapsed Single Node Ring Interconnection
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Refer to from Figure 153. on page 271 to Figure 155. on page 273.
The “Collapsed single node ring interconnection” is a way of protecting a path crossing a number of
sub–networks, e.g., rings.
Respect to the configuration shown in Figure 140. on page 257 (”Drop and Continue”), “Collapsed single
node ring interconnection” allows the best hardware reduction; as a matter of fact four nodes are collapsed
in one node.
The protection operating mode is similar to that described for the “Collapsed dual node ring
interconnection” (refer to para. 13.7.4.5 on page 268).
1
SNCP ring
2
Port 1
4
Port 2
3
Port 4
Port 3
5
7
SNCP ring
1AA 00014 0004 (9007) A4 – ALICE 04.10
6
Figure 153. Collapsed single node ring interconnection
ED
03
3AG 24163 BEAA PCZZA
531
271 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1AA 00014 0004 (9007) A4 – ALICE 04.10
2
5
ED
03
switched
Port 1
Port 3
6
1
SNCP ring
SNCP ring
Port 2
Port 4
Figure 154. Collapsed single node ring interconnection –1st failure
3AG 24163 BEAA PCZZA
531
3
4
7
272 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1AA 00014 0004 (9007) A4 – ALICE 04.10
2
5
ED
03
switched
Port 1
Port 3
6
1
SNCP ring
SNCP ring
Port 2
Port 4
Figure 155. Collapsed single node ring interconnection –2nd failure
3AG 24163 BEAA PCZZA
531
3
4
7
273 / 531
13.7.5 Restoration – Support of the GMPLS Protocol
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.7.5.1 Overview
The main objectives of Intelligent Optical Networks ION are:
–
–
–
–
–
–
Automatic and rapid provisioning of bandwidth.
High network flexibility and scalability.
Optimized usage of network resources.
High resilience against failures with a minimum of additional resources.
Interoperability between different vendors.
Interoperability between different technologies: IP, ATM, SDH, OTH.
These objectives can be fulfilled in networks which use the Generalized Multi Protocol Label Switching
(GMPLS) protocol.
Up to now, the Alcatel–Lucent SDH Network Elements were managed within the Alcatel–Lucent
proprietary Network Release suite which is based on a centralized concept.
The limitation of this concept is that it does not work in a multi-vendor and multi-technology environment
and that it is quite slow because all the management commands run over the Network Management
System.
1678MCC overcomes these limitations by supporting the GMPLS protocol.
GMPLS provides the following main advantages:
–
–
–
Path routing is performed at NE level (not via the Network Management System): this allows very
fast connection provisioning and distributed restoration.
It is standardized, this means that it can work in a multi-vendor environment.
It is designed to work in a multi-technology environment: IP, ATM, SDH and OTH networks.
13.7.5.2 Standardization
In order to fulfill the requirements described above, several groups have participated to the elaboration
of standards:
OIF
Optical Internetworking Forum
Industry forum to agree on interoperable standards.
Defines standard control interfaces: User to Network Interface (UNI) and Network-to-Network
Interface (NNI). Both are based on protocols defined by IETF.
IETF/RFC Internet Engineering Task Force / Request For Comments
Work inspired by Internet consideration, in charge to standardize the Internet protocols.
Defines the GMPLS protocol.
1AA 00014 0004 (9007) A4 – ALICE 04.10
ITU-T
ED
International Telecommunication Union - Telecommunication sector
Work inspired by Network Layering and legacy considerations. Scope is SDH+OTH networks
Defines the ASON recommendation.
03
3AG 24163 BEAA PCZZA
531
274 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The following standards have been defined:
UNI
User to Network Interface
NNI
Network to Network Interface
GMPLS Generalized Multi Protocol Label Switching
GMPLS is an extension of the MPLS protocol used in data networks. MPLS is a packet-based
technology which is intended to combine the advantages of packet and circuit based networks.
GMPLS is then the extension of this concept to cope additionally with SDH and OTH based
transmission networks.
Thus GMPLS includes, in addition to packet switching capable devices (IP/MPLS), also frame
(Ethernet), cell (ATM), time-slot (SONET/SDH, OTH), wavelength (optical channels) and
spatial (fiber) switching capable devices.
ASON
Automatically Switched Optical Network
ITU-T standard (G.8080) for dynamic optical networks.
G.ASTN GMPLS.Automatically Switched Transport Network
ITU-T Architecture for the implementation of ASON.
The G.ASTN is a GMPLS based network.
13.7.5.3 Network Interfaces
1AA 00014 0004 (9007) A4 – ALICE 04.10
The following network interfaces have been standardized:
UNI
User to Network Interface
The UNI is the service control interface between the transport network and a client equipment
e.g. a router.
The UNI supports the following basic functions:
–
Call control
–
Resource discovery
–
Connection control
–
Connection selection
There is no routing function associated with the UNI reference point.
Network internals are hidden to client.
NNI
Network to Network Interface
The NNI is the service control interface between nodes within the transport network.
There are two kinds of NNI: the E-NNI (External NNI), and the I-NNI (Internal NNI)
I-NNI
Internal Network to Network Interface
It is the service control interface between nodes within a network domain. The network domain
may be a vendor specific domain or a part of a network.
The I-NNI supports the following basic functions:
–
Resource discovery
–
Connection control
–
Connection selection
–
Connection routing
ED
03
3AG 24163 BEAA PCZZA
531
275 / 531
External Network to Network Interface
It is the service control interface between network domains, e.g. between different vendor
domains.
The E-NNI supports the following basic functions:
–
Call control
–
Resource discovery
–
Connection control
–
Connection selection
–
Connection routing
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
E-NNI
Carrier Domain 1
I–NNI
Client 2
E–NNI
Client 1
I–NNI
Carrier Domain 2
Transport Network
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 156. Network Interfaces UNI /NNI
ED
03
3AG 24163 BEAA PCZZA
531
276 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.7.5.4 GMPLS Protocol
The basic idea is that path routing possibilities can be negotiated directly (not via the Network
Management System) between intelligent NEs which can then setup the corresponding paths. For that
the GMPLS protocol is used.
The GMPLS protocol must support the following functions:
–
–
–
Exchange of topology and resource information between NEs.
Communication of route decisions to the involved NEs.
Setup of the corresponding paths.
The GMPLS consists of the following main protocols:
–
The routing protocols (OSPF / OSPF-TE)
Opens Shortest Path First / Opens Shortest Path First with Traffic Engineering extension.
These protocols are used to exchange topology and reachability information between NEs in order
to allow each NE to build its own topology map of the entire network or subnetwork.
A topology map basically consists of NEs and Links related information: each NE disseminates
periodically information describing the NE itself and its local links to its adjacent neighbors. The
routing information, a NE periodically receives from each of its neighbors, is used to update its local
topology map and is further advertised to all adjacent neighbors.
This mechanism ensures that each NE in the network repeatedly obtains information describing all
the NEs and links in the network.
In G.ASTNs, multiple physical links may exist between a client and the adjacent network border NE
or between adjacent NEs, respectively. For routing purposes, multiple data links may be combined
to form a single ’Traffic Engineering’ Link (TE-Link). This summarization mechanism reduces the
amount of routing information that has to be disseminated through the network.
–
The signaling protocols (RSVP / RSVP-TE)
Resource Reservation Protocol / Resource Reservation Protocol with Traffic Engineering extension)
These protocols are used to exchange information between neighbor NEs mainly for the purpose of
establishing or releasing a path across the network or subnetwork.
When a new path is being established, the signaling messages have to be processed in every NE
along that path. Signaling protocols facilitate the establishment of a link connection over a particular
transmission link between a pair of connection points (e.g. VC4-16c-CTPs). For this purpose they
convey the assigned labels between each pair of neighbor NEs. Furthermore, the signaling
messages carry client end point identification information (e.g. TNA addresses) as well as routing
information (e.g. explicit route object) which specify the route a new path has at least to follow within
a network.
From the perspective of a single NE, the upstream and downstream link connections belonging to
the same path are bound together by a crossconnection which is created between the two link
connection end points (CTPs). As a result of the individual signaling actions between the NEs along
a path and of the crossconnections which are created in each NE, an end-to-end path is established
from a source to a destination.
In the path establishment process this information is used to calculate a route from a given source
to a given destination or to determine the ’next hop’ leading to the direction of the given destination.
–
Link Management Protocol (LMP)
The Link Management Protocol (LMP) that runs between neighbor NEs is used to manage the TELinks. Furthermore it supports supervision of control channel connectivity and verification of the
physical connectivity of the transmission links.
ED
03
3AG 24163 BEAA PCZZA
531
277 / 531
13.7.5.5 GMPLS based Network: G.ASTN
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Overview
The G.ASTN (GMPLS based Automatically Switched Transport Network) implies the introduction of a
Control Plane between transport and management planes. The control plane communicates with the
underlying transport plane and with the management plane.
Even if in a G.ASTN a lot of tasks are performed autonomously by the control plane, a network
management system is required to manage the network in full context.
Management Plane
NMS
Control Plane
B
"
" SNC
SNC
Y
Y
SNC
Y
Transport Plane
B
UNI
Router
NE
NE
NNI
NMS
NE
SNC
UNI
NNI
B
B
NE
UNI
Router
NNI
Network Management System
Network Element
Subnetwork Controller
User to Network Interface
Network Node Interface
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 157. G.ASTN architecture
ED
03
3AG 24163 BEAA PCZZA
531
278 / 531
Description of the Control Plane
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The role of the Control Plane is:
–
–
–
To facilitate fast and efficient configuration of connections within the transport network.
(Switched Connections which are initiated by the client and Soft Permanent Connections SPC which
are initiated by the NMS are supported).
To reconfigure or modify connections that have previously been set up.
To perform a restoration function.
The tasks of the Control Plane are:
–
–
–
–
Network discovery: this allows a NE to find its place in the network. This means that a new NE is
automatically inserted in the network such that finally all NEs in the network are aware of the whole
topology without manual intervention.
Link discovery: this allows each pair of a link to discover the neighboring NEs. On this way a newly
installed link can automatically be inserted in the network without pre-configuration.
Service discovery: this allows two NEs to exchange information about their capabilities such that
a common set of functionalities can be agreed between them in an automatic way.
Fast and automated path provisioning.
The elements of the Control Plane are:
–
The Subnetwork Controllers SNCs
The SNC implements the GMPLS protocol and ensures the connection with the underlying NE and
with the network management system.
One SNC is associated with one NE.
–
The connections between SNCs.
The connection links transport the IP based routing / signaling / link management protocols.
They can be:
•
Dedicated Ethernet connections (Out-of-Fiber / Out-Of-Band control plane traffic).
•
SDH links using the DCC channels (In-Fiber / In-Band control plane traffic).
13.7.5.6 Benefits of the G.ASTN
1AA 00014 0004 (9007) A4 – ALICE 04.10
–
–
–
–
–
–
–
–
–
ED
Fast and automated path provisioning
Enhanced scalability
Support of multi-vendor networks
Interworking with other networks at boundary nodes
Support of multi-technology networks (IP, ATM, SDH, OTH)
Seamless integration of data and transmission networks
More efficient restoration procedure: distributed restoration against centralized restoration
Fast and efficient network reaction in failure situations
Maintenance improvement: since all necessary network information is available locally, coordination
of maintenance actions is simplified
03
3AG 24163 BEAA PCZZA
531
279 / 531
13.7.5.7 The Alcatel–Lucent Solution
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
This chapter describes how Alcatel–Lucent has implemented the GMPLS protocol in conjunction with the
1678MCC.
13.7.5.7.1 GMPLS Routing Engine: GMRE
Each 1678MCC is equipped with a controller called GMRE which runs the GMPLS protocol.
The GMRE is a SW package which is installed on top of the NE SW.
One of the major task of the GMRE is the coordination of the various actions which are necessary to
provide the dynamic establishment and release of connections in a decentralized fashion.
Reference Model
The NE together with the GMRE build the Transport NE (TNE).
Figure 158. shows the TNE reference model. It consists of:
–
–
–
–
–
–
–
1AA 00014 0004 (9007) A4 – ALICE 04.10
–
ED
A single NE + GMRE.
An internal Control Interface NMI (Q3 in the first step) between NE and GMRE SW.
At least one redundant or not redundant IP Control Channel (IPCC) between the GMRE and each
of its neighbors.
A neighbor can be a client (e.g. a router) attached to the TNE or another TNE.
The IPCC can be Out-Of-Fiber/Out-Of-Band (running on Ethernet links between GMREs) or
In-Fiber/In-Band (using the DCC on the SDH links).
At least one transmission interface between the NE and each of its neighbors associated with the
corresponding IPCCs.
GMRE management interfaces:
•
Command Line Interface CLI
•
MTNM Interface based on the CORBA protocol
The conventional NE Management Interface Q3.
03
3AG 24163 BEAA PCZZA
531
280 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Craft Terminal
Network Management System
CT
NMS
S
S S
CLI
MTNM
(CORBA based)
Q3
IPCC
S
GMRE
S
Client/Neighbor
TNE
Transmission IF
S
NMI (Q3)
NE
e.g. 1678MCC
TNE
NE
TNE
Network Element
Transport Network Element
MTNM Multi Technology Network Management
Network Management Interface
NMI
IPCC
IP Control Channel
CLI
Command Line Interface
NE Management Interface
Q3
COPS Common Open Policy Server
Figure 158. TNE reference model
The GMRE is an integral part of the TNE. It controls the resources (entirely or partially) of the underlying
NE. These resources are:
–
Connection Termination Points (CTPs).
–
Crossconnections between two CTPs.
There is a strict 1:1 relationship between GMRE and NE: there is one GMRE for one NE.
Signaling, routing and link management protocols are running over the IPCC interfaces.
Each IPCC can be operated in a redundant or non-redundant configuration and has one or multiple
associated transmission interfaces.
Each IPCC interface together with its associated transmission interface(s) is either playing the role of a
UNI or of a NNI.
The GMRE can be managed from a CT using a CLI interface or from a Network Management System
(NMS) via a CORBA based MTNM interface.
The GMRE itself controls the underlying NE via the NE conventional management interface Q3.
The Q3 interface can also be used in parallel to manage the NE in a conventional way.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The GMRE configuration data (persistency database and configuration files) can be backed up and
restored in the same way as the 1678MCC configuration data.
ED
03
3AG 24163 BEAA PCZZA
531
281 / 531
GMRE Architecture
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Figure 159. shows the top level architecture of the GMRE and its interfaces
Network Management
System
Craft Terminal
MTNM
CLI
CORBA
NMI
GMRE Management Agent
IPCC
OSPF–TE
Clients /
Neighbor
GMREs
RSVP–TE
Sig_DB
Signaling
Handler
Route
Handler
Route_
DB
LMP
Link
Management
Path Management
Path_
Link_DB
DB
NCI
NE Adaptation
GMRE
NMI
NE
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 159. GMRE: SW Top level architecture
ED
03
3AG 24163 BEAA PCZZA
531
282 / 531
Short description of the single components
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
–
–
–
–
–
–
Route management:
Coordinates all the tasks which have to be performed by the other components when connections
are set up or torn down.
Signaling handler:
Responsible to encode and decode signaling messages and to perform protocol specific tasks.
Route handler:
Maintenance of a database containing network topology and link state information.
Computation of a route from a given source to a given destination that meets a given set of
constraints.
IP Routing
Link management:
Manages the link resources from the underlying NE to all of its neighbors.
GMRE management agent:
Provides the Command Line Interface (CLI) which has to be used by the operator to configure and
control the GMRE.
CORBA NMI:
Provides an MTMN interface for management system.
NE adaptation:
Allows to map requests from other GMRE components to the specific underlying NE.
Key Mechanisms
The following key mechanisms are implemented in the GMRE:
–
Routing and Route Computation
Routing is a mechanism to get a topological map of the network, including nodes and links with their
capabilities, as well as end system reachability information. Based on this information the routing has
the means for signaling requests to calculate a route from this node to an end system (client) or to
the border of the network.
The NEs exchange their network state. Information received from one directly attached neighbor is
distributed to other directly attached neighbors. On this way, the network states are flooded within
the network and each NE obtains the entire network information.
Routing messages carry node and link information allowing the receiving nodes to learn the node
and link states.
–
Signaling
Signaling is a mechanism supporting setup, maintenance and release of routes or connections
across the network. This is achieved by exchanging signaling messages between peer nodes.
The request is passed from source to destination with intermediate node processing in a hop by hop
manner.
–
Link and Port Management
This mechanism is responsible for managing control and transport plane interfaces. It provides:
•
•
A central repository and manager for all GMRE related control and transport plane interfaces.
Informational services to other GMRE applications related to control and transport plane
interfaces.
Autodiscovery
1AA 00014 0004 (9007) A4 – ALICE 04.10
•
For each adjacent neighbor node an individual neighbor relationship is maintained, managing the control
and transport plane links.
ED
03
3AG 24163 BEAA PCZZA
531
283 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
Route Management
Route management is responsible for creating, modifying and releasing crossconnections on the NE
in response to signaling or timer events.
–
NE Adaptation
The GMRE is designed to control different types of NEs. These NEs may have different management
interfaces and different behaviors. The NE adaptation mechanism decouples the generic GMRE
applications from the specifics of the NE under control: it translates between the representation of
interfaces and labels used by the GMRE applications and the corresponding representations used
by the NE.
The NE adaptation is planned to communicate with Q3, TL1, CORBA or other interfaces. Presently,
only the Q3 adaptation is supported.
–
Management Interfaces and Agents
There is a necessity to provide access to and control of the application and data within the GMRE
in order to manage it: the GMRE must be provisioned, configured (or customized) and diagnosed
via a management system.
The management system may access the GMRE and target multiple applications such as routing,
signaling, link and route management.
–
Management CLI
The Command Line Interface CLI is a management interface via typed commands entered in an
ordinary Telnet Shell.
Management via CLI has the following objectives:
•
Translates the user input string, searches in the command tree for the corresponding command
function, executes it and print the response.
Collects trap/alarm events from the system and display them to the user.
•
The CLI provides the following features:
•
•
•
•
•
•
•
•
1AA 00014 0004 (9007) A4 – ALICE 04.10
–
ED
Easy editor mode
Command completion
Command history
Context sensitive help
Scripting: the user is able to execute a script (sequence of commands)
Security level access
Display trap/alarm events
Small effort to create a new command or to change an older one: it changes the current
command tree by adding, deleting and modifying commands.
CORBA Interface for Network Management (NMI)
The interface is based on the MTNM model of network management as standardized by TMF: thus
it can be used by the Alcatel–Lucent Network Management Systems as well as by 3rd party
applications.
03
3AG 24163 BEAA PCZZA
531
284 / 531
–
External Communication
External communication has to fulfill the following tasks:
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
•
•
•
•
•
Support redundancy of IPCCs
Support integration of the GMRE into the DCN
Support easy access to raw-IP services
Support communication with the NE under GMRE control
Handling of logical and physical interface IP addresses
The GMRE has 4 major external logical communication interfaces:
•
CLI to the GMRE manager:
Via the CLI the GMRE performs management activities and receive notifications.
The sessions are based on the telnet over TCP protocol. This allows easy access to the GMRE
via telnet from any kind of computer. No specific application is required to manage the GMRE.
IPCC interface in UNI and NNI roles to neighbor nodes
The IPCC interfaces are used to exchange signaling, routing and link management information.
The IPCCs between two nodes are optionally redundant (1:1).
Q3 for communication between GMRE and NE under GMRE control: a CMISE-like interface
is used, (full Q3 stack is planned for the future).
CORBA for communication between GMRE and network management (RM).
•
•
•
–
Persistent storage
This mechanism provides:
1AA 00014 0004 (9007) A4 – ALICE 04.10
•
•
ED
Reliable storage of application data with respect to all possible system failures.
Application with enough data for restart after any type of failure.
03
3AG 24163 BEAA PCZZA
531
285 / 531
13.7.5.8 Implementation
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
GMRE
–
–
–
–
–
–
–
The GMRE is a SW package. No additional HW is required for the implementation of the GMPLS.
The GMRE SW is distributed across the processor modules located redundantly on the FLC boards:
The protocol processing parts are deployed on the DCR modules, the DXC SW and those parts of
the GMRE SW which use persistency and which interact closely with the DXC SW are deployed on
the EM modules.
The DCR modules implement also the IP-over-DCC services used for In-Fiber / In-Band control plane
traffic.
A redundancy switch triggered by the DXC SW causes also a redundancy switch of the GMRE SW.
The operating system is LINUX for PowerPC.
The installation procedure for the GMRE SW has to be triggered by the user explicitly. De-installation
of the GMRE SW is possible.
The GMRE databases and configuration files are included into the NE configuration backup.
External Interfaces
There are two types of external interfaces:
–
–
UNI–IPCC via OF/OB DCN
NNI–IPCC
•
DCC
•
IP–in–IP tunnel via OF/OB DCN
GMRE Maintenance
For GMRE maintenance, the CT provides corresponding SMF (System Maintenance Functions):
–
–
Open CLI Telnet session to selected GMRE.
Backup/Restore for selected NE incl. GMRE.
13.7.5.8.1 Connections between GMREs
To exchange control plane traffic the GMREs can use two types of connection networks:
–
–
An external IP network.
The SDH network using the DCC channels.
External IP network (Out-Of-Fiber / Out-Of-Band control plane traffic)
The GMREs nodes are interconnected via dedicated ethernet links.
This transport mode is called Out-Of-Fiber / Out-Of-Band control plane traffic.
1678MCC supports a fully routed IP network as control plane.
GMRE-to-GMRE traffic needs to be routed Out-of-Fiber/Out-Of–Band through the customer DCN.
For this purpose the traffic can be tunneled via Generic Routing Encapsulation (GRE) or IP-in-IP.
Out-Of-Fiber/ Out-Of-Band control plane traffic allows interworking with non-Alcatel-Lucent subnetworks.
The external IP network must be completely independent from the transport plane.
1AA 00014 0004 (9007) A4 – ALICE 04.10
SDH network using the DCC channels (In-Fiber / In-Band control plane traffic)
The GMREs nodes are connected over the SDH links and make use of the DCC channels to transport the
control plane messages.
This transport mode is called ’In-Fiber / In-Band’ control plane traffic.
Using this mode, the customer needs not to invest in an additional IP network: the control plane network
can be setup and maintained on the existing SDH links.
ED
03
3AG 24163 BEAA PCZZA
531
286 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
As all GMRE protocols are IP based, an IP over DCC stack (running in parallel to the existing OSI over
DCC stack) is used to transport and route the control plane traffic between GMREs.
The IP-over-DCC interfaces can be seen as local interfaces of the GMRE protocol processor, connecting
it directly to the neighbor GMRE processors. In this case the FLCCONGI/FLCSERVICE are configured
to act as IP routers and become part of the control plane.
As the topology of the control and transport planes are not necessarily identical, the GMRE SW separates
their routing messages.
DCC Protection
In–Fibre / In–Band protection
For GMRE IF/IB signalling, static routes to the neighbor GMREs are setup on the LAPD interfaces. In case
of a failure of one LAPD, the OS chooses an alternative LAPD interface.
In case of failure of a DCC link the rerouting is realized with IP–over–LAPD–over–DCC as shown in
Figure 160.
In–Fiber / In–Band control plane traffic can only be used within Alcatel–Lucent networks.
Rerouting
Fast DCC Protection
FLC A
FLC A
GMRE Node A
IP
IP
LAPD 0
LAPD 1
DCC
DCC
failure
GMRE Node A
IP
LAPD
DCC protection
DCC
DCC
broadcast
DCC
DCC
LAPD 0
LAPD 1
IP
IP
GMRE Node B
FLC B
selection
DCC
DCC
DCC protection
LAPD
IP
GMRE Node B
FLC B
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 160. DCC Protection Mechanism In–Fibre / In–Band
ED
03
3AG 24163 BEAA PCZZA
531
287 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
In–Band / Out Of–Band protection
To provide additional robustness (regarding to the In–Fibre / In–Band protection) in case that all LAPD
interfaces are down, IP–in–IP tunnels to each GMRE neighbor and corresponding static routes on the
external LAN interface are configured. IP–in–IP tunnels are used as Out of–Band backup links for the DCC
links (refer to Figure 161. ).
Static routes over tunnels are defined in a metric. This metric is only active if all LAPDs are down.
As soon as one LAPD interface is available again, the static route is inactive and the LAPD interface is
be used again.
FLC A
tun0
GMRE Node A
IP
IP
LAPD 0
LAPD 1
DCC
DCC
failure
Customer
DCN
failure
DCC
DCC
LAPD 0
LAPD 1
IP
IP
GMRE Node B
FLC B
tun0
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 161. DCC Protection Mechanism In–Band / Out of–Band
ED
03
3AG 24163 BEAA PCZZA
531
288 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.7.5.8.2 Work Split between Control Plane and NMS
The control plane enhances the NEs with intelligent multi-vendor, end-to-end and real time capabilities
but it does not replace the NMS.
There is a request for some centralized network management functions (e.g.):
–
–
Full awareness of the current network status (configuration, routes, alarms)
Separation of network domains in order to hide network knowledge to the world.
A mixed approach is followed whereas the NMS manages the network, it:
–
–
–
ED
Provides the operator an actual view about the status of the whole network.
Allows the operator to override the control plane decisions or freeze resources such that their status
is no more under the control of the control plane.
Maintains consistency between nominal route (according to the original network planning) and
current route.
These functions are performed by the ASON Manager. The ASON Manager is a Network Protection
Architecture (NPA) as part of the Network Manager 1354RM.
03
3AG 24163 BEAA PCZZA
531
289 / 531
13.7.5.9 Main Functions supported
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.7.5.9.1 Network Management
Network construction and configuration management
–
–
–
–
–
–
Autodiscovery based on G.7714.1
Automatic provisioning of In–Fibre/In–Band control plane and IP–in–IP tunnels
Assignment and de-assignment of data bearers to TE-links
Provisioning of data bearer and TE-link related information
Retrieval of the data bearers TE-links
Network construction is driven by management system (ASON)
Connection management functions
–
–
–
–
–
–
–
–
SPC Management: 5 priority levels, support of multiple different protection/restoration schemes,
AU4CTPs as endpoints, VC–4 trails in support of GE connections
Switched Connections management
Retrieval of SPC and Switched Connections, filtering supported
Interworking of MS-SPRing and SPCs on domain boundary for SPCs (MS-SPRing on ’drop ports’)
Modification of existing SPCs: priority, protection type
Path diversity for dual homing
Support of SNCP rings (single node interconnection)
Compound link support
Communication between GMRE and ASON manager
Message loss detection mechanism which allows the ASON Manager to detect wether re-synchronization
with the GMRE is required.
CLI Integration in the USM
CLI access is managed at NE USM level:
Opening the 1678MCC USM, the 1353NM operator sees wether a GMRE instance is controlling the NE
or not.
Split NE Concept
It is possible to partition a NE and to assign these parts to different managers: e.g. a part can be managed
in a traditional way (1354RM) while another part belongs to the GMRE domain and is under GMRE control.
The partitioning is flexible.
Shared ports between different managers
1AA 00014 0004 (9007) A4 – ALICE 04.10
Drop ports are sharable between different managers (e.g. between GMRE and 1354RM).
e.g.: The GMRE closes a SNCP ring (termination of a 1+1 SNCP between 2 drop ports and an NNI port)
and the 1354RM interconnects other CTPs of these 2 ports.
ED
03
3AG 24163 BEAA PCZZA
531
290 / 531
13.7.5.9.2 Maintenance
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Maintenance functions
–
–
–
Controlled shutting down of a port
Changing of the nominal route of a SPC
Changing of the current route of a SPC/SC via soft rerouting
Alarm management
–
Alarm reporting and state change notifications
13.7.5.9.3 Distributed Restoration
With the introduction of the GMRE, Distributed Restoration is supported, which is implemented in a
distributed way. This means that the restoration actions are performed autonomously by the control plane.
In a distributed restoration network, backup route calculation and implementation is done in parallel by all
the nodes implied in the affected routes. Once a backup route has been calculated by a source node, route
reservation messages are sent to all the GMREs along the backup route. The addressed GMREs translate
the route setup messages to corresponding commands towards the underlying NE.
ED
03
3AG 24163 BEAA PCZZA
531
291 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.7.5.9.4 Protection
Protection (SNCP) is static. The protecting capacity is provisioned in advance and requires 100%
additional network resources (in case of 1+1 SNCP).
Protection performance is very fast (<50 ms), but requires 100% additional network resources (1+1
SNCP).
SNCP Ring Closure
SNCP ring closure means a domain–external SNCP that is terminated on the GMRE domain boundary.
There are many different SPC configurations possible: the external SNCP could reside in the ingress node
(head end of the connection), in the egress node (tail end of the connection), or external SNCPs could even
exist on both ends of the connection segment crossing the GMRE domain. Moreover, the connection
segment inside the GMRE domain can be unprotected, or 1+1 SNCP protected. For a subset of the
possible connection types refer to Figure 162.
Ingress
Node
Transit
Nodes
Egress
Node
SPC Setup Direction
Connection with
1+1 SNCP at
the head end
...
Connection with
1+1 SNCP at
the tail end
...
Connection with
1+1 SNCP at
both ends
...
...
SNCP protected
connection with
1+1 SNCP at
both ends
...
1AA 00014 0004 (9007) A4 – ALICE 04.10
GMRE Domain
Figure 162. SNCP Ring Closure in a GMRE Network
ED
03
3AG 24163 BEAA PCZZA
531
292 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
SNCP ring closure handles a SNCP connection at client/drop side at source and destination side. The
feature itself can be divided into:
–
Management plane handling:
Two source points and two destination points for these kind of connections are supported for set and
get operations.
–
Control plane handling:
Signaling messages are extended to carry two destination end points. The appearance of two
destination points triggers the setup of a domain external SNCP in the egress node.
13.7.5.9.5 Restoration
Restoration does not rely on an allocated protecting capacity: available resources are shared between
multiple connections within the network, leading to more optimized resource utilization.
Restoration actions require less additional network capacity, but they are typically slower.
13.7.5.9.6 Protection and Restoration
Overview
The reliability and availability performances of a network in terms of restoration times and of additional
network resources can be optimized by combining protection and restoration mechanisms.
Protection and Restoration combined provide very high reliable connections because a failed leg of the
1+1 SNCP protected connection is restored.
The Protection and Restoration process can be decomposed in 3 steps:
–
Alarm detection and correlation
After a failure has occurred, failure point and failure type are propagated to the protection processor
(K1/K2 processor which handles the APS) or to the restoration processor (GMRE).
–
Protection or restoration request
The protection resp. restoration processor correlates the actual failure situation with the actual state
of available resources, for a bidirectional route it overwrites the old cross connections with new one.
In case of protection the request is forwarded via the APS protocol, in case of restoration the request
is forwarded by means of signaling.
–
Protection switch
A protection switch is completed when both sides of a failed route have switched to the available
resource and the traffic is restored.
Main Tasks and Characteristics
In correlation with the feature ’Protection and Restoration’ the following tasks are performed:
Nominal Route Handling
1AA 00014 0004 (9007) A4 – ALICE 04.10
The nominal routes are calculated by a planning tool usually implemented in the centralized network
management system. The target is to optimize the utilization of the transport network, taking into account
the available network topology and resources, the scheduled maintenance actions and the equipment to
be installed. A nominal route is setup as a point to point connection.
ED
03
3AG 24163 BEAA PCZZA
531
293 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Route setup and release is performed by exchanging signaling messages between nodes. A setup is
requested using a route message containing a unique connection ID, desired route and service scope.
Basing on this information the setup request is passed in a hop-by-hop manner along the explicit route
to the egress node. After reaching its destination the setup request is confirmed with a RESV message.
The RESV is passed in the reverse direction and each node along the route establishes the connection
on the transport plane.
Definition of Shared Risk Groups (SRG)
The SRG is a mechanism implemented to face the failure diversity within the network.
E.g. it may happen, that a backup route cannot be established resp. activated because the nominal and
the backup routes share the same failure.
The SRG mechanism allows the modeling of single failures which affect multiple links (e.g. cable cut) and
nodes (e.g. equipment room flooded). Shared Risk Groups are defined and the TE links are assigned with
SRG identifiers. An SRG attribute may be empty, comprise a single identifier or a list of multiple identifiers.
Two entities are ’failure diverse’ if they do not share the same risk, hence if they do not belong to the same
SRG.
Source Based Restoration (SBR)
Source Based Restoration (SBR) is intended as last restoration escalation if other restoration action did
not succeed. SBR is also supported as service, however this service should be used only occasionally due
to the contention issues related to that restoration method detailed below. So SBR is applied under the
following conditions:
–
–
–
One or more legs of a PRC failed
Guarenteed Restoration was not able to find a backup and the route failed
SBR was used as a service
The SBR mechanism where the source node calculates the new route after failure, is based on the network
information before failure and the failure notification which allows to locate the failed resource in the
network. SBR is a mechanism optimized for resource utilization and not for performance.
Guaranteed Restoration (GR)
One potential backup route is calculated and registered by the source node in advance. As the network
state changes dynamically each update requires a verification wether the pre-calculated route can be kept
or might be affected and must be re-calculated.
A backup route is registered in the control plane, but is not implemented in the transport plane. After a
failure occurs, the registered backup route is activated. When the nominal route is available again, the
traffic is moved back and the backup route is deactivated.
Computation of a Backup Route
1AA 00014 0004 (9007) A4 – ALICE 04.10
The backup route computation is the process which calculates the shortest backup route for a nominal
route which fulfills a number of given diversity constraints.
The constraints can be the following:
–
Exclusion of the entities belonging to a given list of SRGs
–
Exclusion of a set of links (link diversity)
–
Inclusion of entities belonging to a given list of links that should be reused for a new route
–
Route verification if an explicit route is given by operator or NMS
The following restoration applications require the computation of a backup route:
–
PRC
ED
03
3AG 24163 BEAA PCZZA
531
294 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
–
The failed SNCP leg is restored like the post-calculated SBR. The new route must be diverse to the
redundant SNCP legs (actual and nominal) and to the failure of the actual failed leg.
Source Based Restoration
The backup route is computed after a failure has occurred on the active route. Since the point of
failure is known, the backup route must be diverse to the point of failure, using the link diversity of
the failed link.
Guaranteed Restoration
In this case the backup route is computed at setup time of the nominal route and both nominal and
backup routes must be fully (link, node and SRG) diverse.
Reversion
A restoration route is usually longer and uses more ports than the optimized nominal route. For this reason
it is very important to switch back to the nominal route as soon as it is available again.
Reversion can be done in two modes:
–
Automatically: After the nominal route becomes available, the traffic is moved back to the nominal
route as soon as the periodically end–to–end check is successful.
–
Manually: After the nominal route becomes available the connection state changes to ’ready to
revert’. The operator triggers the reversion manually.
After all nodes have selected the nominal route, the backup route can be deactivated.
Reversion does not affect the traffic and is “hitless”.
Priority and Preemption Handling
As additional network resources for protection and restoration should be minimized, it might happen in
case of several network failures that there are no more resource to restore a failed connection. In this case
a high priority route can preempt a low priority route.
A priority number is assigned to each route. Up to 5 priority levels are supported.
Priority and preemption comprise the following functionalities:
–
–
–
–
1AA 00014 0004 (9007) A4 – ALICE 04.10
–
ED
Priority based link resource handling:
The CTP label holds the priority of the link.
Priority based link resource advertisement:
The available resources are grouped according to their priorities.
Priority based route determination:
A route can be calculated for a given priority.
Priority based preemption:
The lowest priority route is preempted first.
Handling of preempted low priority traffic:
A preempted route must be torn down and the connection is removed from the HW. It is up to the
source node to verify and re-establish a nominal route once it has been preempted.
03
3AG 24163 BEAA PCZZA
531
295 / 531
13.7.5.9.7 Multicast Connections
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Multicast connections provide a unidirectional service from one source node to multiple destination points.
This is achieved by setting up a multicast tree, whereby a single resource is used per hop.
The multicast tree is characterized by unidirectional resources per link and unidirectional connections per
node. An example is shown in Figure 163.
The root of a multicast tree is the multicast source node. This is the node from which the multicast tree
is established to all destination nodes. The multicast destination nodes terminates the multicast tree
and provide traffic to the destination client nodes. A path between a multicast source node and a
destination node is called leaf.
Branch nodes are intermediate nodes that are not destination nodes, but have to provide one or more
branches to other nodes. Branch and destination nodes are a combination of both nodes: The incoming
multicast traffic must be ”dropped” towards the destination clients and ”continued” to other nodes.
Shared resource
Dedicated resource
Figure 163. Multicast connections (example)
Multicast connections are basically characterized by:
–
Unidirectional connections without reverse direction
Support of unidirectional connections (here point–to–point) that are based on bidirectional
connections (SPCs), but the reverse direction cannot be used for other connections.
1AA 00014 0004 (9007) A4 – ALICE 04.10
–
Setup of a multicast tree
•
ED
All leafs of a multicast tree have one common source node and must have the same service
type (e.g. VC4, VC4–4c, VC4–16c, VC4–64c, AU3) and the same priority.
03
3AG 24163 BEAA PCZZA
531
296 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
•
The protection types unprotected, SBR and GR are supported and can be mixed in a multicast
tree.
•
The whole multicast tree has a single source node and a common multicast group id. That
means, that all leafs have two identifiers: a common id and a leaf specific id.
•
For restoration and free routed purposes, the source node maintains the full list of links involved
in the multicast tree. This allows reuse of link resources for routing purposes. In effect the
minimum network resources are taken for adding new leafs or restoring connections to leafs.
Maintenance actions on a multicast tree
Maintenance commands for individual paths (e.g. move (nominal or current), add leaf, remove leaf,
shutting down data bearer) are supported.
–
Multicast restoration (SBR and GR)
•
Only the leafs that are affected by the fault will be restored.
•
Each leaf is restored separately, but multiple leafs are able to share resources with other leafs
of the same tree.
•
The affected leafs are processed sequentially at the source node node for routing, while setting
up the restoration path is done in parallel. Thus, a leaf can use the resources already defined
for the previous leaf without additional cost.
•
The restoration time of a single multicast tree can be considered as the sum of the leafs to be
restored. Compared to a restoration with the same amount of single connections this restoration
time can be slower, but is still in the same dimension. This effect is caused by the sequential
setup and correlation required to share common branches.
Refer to the Network Configuration Guide GMRE for network specific hints regarding multicast
connections. Refer to the CLI User Guide GMRE for the configuration of multicast connections via the
Command Line Interface.
13.7.5.10 Glossary
Backup Route
Protecting route between source and destination nodes.
Call
An association between end points that supports an instance of a service.
Also called SNC.
Client or user
Equipment that is connected to the transport network for utilizing transport services.
Example: IP routers, ATM switch, Ethernet switches.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Control Plane
Consists of IP Control Channels (IPCCs) over a Control Plane physical interface (e.g. Ethernet) plus the
GMPLS routing Engines (GMRE).
ED
03
3AG 24163 BEAA PCZZA
531
297 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Compound Link
A serial compound link interconnects two 1678MCCs, that are involved in the ASON/GMPLS control
plane, via one or multiple intermediate nodes (e.g. one or more 1670SMs). These intermediate nodes do
not participate in the control plane. This means that the two 1678MCCs are immediate neighbors from the
control plane perspective, but are not immediate neighbors in the data plane.
Refer to the Network Configuration Guide GMRE for details and restrictions. Refer to the CLI User Guide
GMRE for the configuration of compound links using the Command Line Interface.
Data Plane
Other term for Transport Plane.
Destination node
Node that terminates a connection request.
Egress node
Border node where a route exits the network.
Graceful Deletion
SDH/SONET and OTH allow contiguous route monitoring at all points (client and network). A deletion at
one point of the route would cause alarm detection in the subsequent routes and potentially consequent
actions (protection switch or re-routing). In order to suppress that undesired consequent actions at
deletion time the deletion message sequence is pre-processed by a ’deletion-in-progress’ message
turning off the monitoring along the route.
Ingress node
Border node where a route enters the network.
Also called Source node.
In-Fiber / In-Band control plane traffic
Refers to the transport of control plane traffic over a communication channel embedded in the
data-bearing physical link.
IP Control Channel (IPCC)
Logical communication link between the node and its neighbor over which control plane messages are
sent.
Management Plane
Performs management functions for the transport plane, the control plane and the system as a whole. It
also provides coordination between all the planes.
Nominal Route
Route between source and destination nodes, as calculated by the planning tool.
Out-Of-Fiber /Out-Of-Band control plane traffic
Refers to the transport of control plane traffic over a dedicated communication link, separate from the
data-bearing link, between the control plane entities.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Route
Subnetwork connection between ingress and egress nodes.
Point to Point Connection
A typical active connection with a single leg. (against 2 legs for a SNCP connection).
Policy
The set of rules applied to interfaces at the system boundary, which filters messages into an allowed set.
ED
03
3AG 24163 BEAA PCZZA
531
298 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Pre-calculated Restoration Connection (guaranteed restoration)
An optimized route restoration by which an active route can be restored by a pre-calculated
(pre-registered) but inactive backup route. As long as the nominal route is active the backup route exists
at control plane only. After failure the backup route is activated and the failed route is torn down. After
nominal route repair, an SNCP is established, the traffic is switched back to the nominal route and the
backup route is deactivated. The backup route is fully diverse. If no backup is available at the failure time
the connection is restored in SBR manner.
Protection and Restoration Combined (PRC) Connection
A combination of SNCP and SBR by which a connection is setup as an SNCP and once one leg fails the
failed leg is restored in SBR manner.
Shared Risk Group (SRG)
The route reliability depends of the diversity between working and protecting / restoration routes: the
maximum reliability is achieved when working and protection routes are completely diverse (no possible
common point of failure). The diversity level is given by defining the shared risk groups.
Soft Rerouting
Manual Switching Time
Soft Permanent Connection (SPC)
Initiated by the Management System and implemented like an end-to-end route for which a
protection/restoration scheme can be applied.
The ASON Manager has the responsibility to maintain the connection in the desired manner.
Source Based Restoration (SBR)
The source node is responsible for the restoration actions.
A typical route restoration by which a failed nominal route is restored by the source node in a flexible
manner. The restoration route is failure diverse only. The behavior and implementation is similar to the
guaranteed restoration with the difference that the restoration route is not registered before failure and
might be cranked back by any node.
Protected SBR
An MSP protected connection that is restored in SBR manner once both MSP legs failed at any
intermediate link. SBR restoration may also use unprotected MSP links.
SBR route
End-to-end connection across a restoration domain with source based restoration scheme.
Source node
Node that requests a connection.
Also called ingress node.
Switched Connection (SC)
Initiated by a client via signaling.
Maintenance is under the responsibility of the client itself.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Subnetwork Controller (SNC)
Element of the control plane which implements the GMPLS protocol. The Alcatel–Lucent SNC is the
GMRE.
Subnetwork Connection (SNC)
Dynamic relation between 2 subnetwork points at the boundary of the same subnetwork.
Also called ’Call’.
ED
03
3AG 24163 BEAA PCZZA
531
299 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Traffic Engineering Link (TE Link)
For routing purposes, multiple data links may be combined to form a single TE-Link. This summarization
mechanism reduces the amount of routing information which have to be disseminated through the
network.
Transport Network (Transport Plane, Data Plane)
Abstract representation which is defined by a set of access points (ingress and egress) and a set of
network services.
Transport Network Element (TNE)
NE within the transport network.
Virtual Private Network (VPN)
A VPN is a set of virtually dedicated transport resources, supporting a closed user group, over transport
links that are shared between multiple users.
ED
03
3AG 24163 BEAA PCZZA
531
300 / 531
13.8 Performance Monitoring Subsystem
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.8.1 Overview
The Performance Monitoring process consists of three different steps:
•
performance monitoring primitives processing: it is performed by atomic functions (termination
functions) and provides the EBC (Errored Block Count) and DS (Defect Second) defect
indications;
•
performance monitoring event processing: provides the following performance events:
–
–
–
•
ES (Errored Second): one second period in which DS is set or there is at least one errored
block;
SES (Severely Errored Second) one second period in which DS is set or the EBC is greater
or equal to Y% of the blocks in this second (Y=30 for the path);
BBE (Background Block Errors) is the count of EBC events in one second not SES;
performance monitoring Data collection & History processing: for each event, a count is
performed on a defined period (15 min or 24 h); the results of these counts are stored in
performance registers (current and historical registers).
If at least 10 consecutive seconds are SES, the period is said Unavailable Time (UAT) period.
In this time the events count is inhibited. During unavailable time, each second is counted as optional UAS
event.
The Performance Monitoring Process is performed for two different purposes:
•
Maintenance:
–
–
–
–
•
the monitoring is applied on the path or section layer
events are counted (in the available period) by 15 min and 24 h counters
trail is monitored in the two different directions independently (unidirectional counters)
it is used a degradation monitoring by threshold crossing
Quality of Service:
–
–
–
–
the monitoring is applied only on the path layer
events are counted (in the available period) only by 24 h counters
trail is monitored at the same time in the two different directions (bidirectional counters)
it is not used a degradation monitoring by threshold crossing
Types of counters are the following:
•
•
•
•
•
•
Errored Second (ES)
Severely Errored Second (SES)
Out Of Frame Second (OFS)
Background Block Error (BBE)
Unavailable Second (UAS)
Elapsed time
1AA 00014 0004 (9007) A4 – ALICE 04.10
The 1678MCC supports the suspect interval flag.
For more details about the list of PM counters supported for each 1678MCC board refer to the Operator’s
Handbook.
ED
03
3AG 24163 BEAA PCZZA
531
301 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.8.2 Monitoring Functions
Paths are often responsible of the end–to–end customer service, so they can be requested to provide
monitoring for Quality of Service purposes and, in addition, to cooperate with specific monitoring to the
network Maintenance applications.
The 1678MCC equipment has the full set of Alcatel–Lucent OMSN Performance Monitoring capabilities,
physically performed in the Matrix (HO &LO) and in the ports.
PM data collection can be individually activated on the LO–VC trail termination or on the HO–VC trail
termination of the structured VC4 afterwards groomed at LO–VC level.
PM processing is performed according to the standard G.784 recommendation: BBE, ES, SES and UAS
counters are collected.
NE–PM (near–end) monitoring on the incoming signal checks the BIP code violations using the B3 byte
(VC4, VC3) or the bits 1–2 of the V5 byte (VC12); in addition the VCn termination can provide FE–PM
(far–end) monitoring by REI&RDI information of G1 byte (VC4, VC3) or the V5 byte (VC12) processing.
On the same bi–directional VCn–TTP, the unidirectional PM collection for Maintenance application and
bi–directional collection for Quality of Service can simultaneously be activated.
In addiction the 1678MCC equipment performs the following monitoring functions:
ED
•
HTCT (Higher Order Tandem Connection Termination) which terminates the N1 byte for locally
terminated VC–4’s.
•
HTCM (Higher Order Tandem Connection Monitoring) which performs the monitoring of the N1
byte for non–terminated VC–4’s.
•
HSUT (Higher Order Supervisory Unequipped Termination) which performs the trail termination
and monitoring functions of unequipped VC–4’s by terminating and monitoring the path
overhead bytes (J1, G1, C2 and B3).
•
HPOM (Higher Order Path Overhead Monitoring) which performs the non–intrusive monitoring
of the path overhead bytes (J1, G1, C2 and B3) for non–terminated VC–4’s.
•
LPOM (Lower Order Path Overhead Monitoring) that performs the non–intrusive monitoring of
the path overhead bytes before matrix.
03
3AG 24163 BEAA PCZZA
531
302 / 531
13.9 External Interfaces Subsystem
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The following Table 42. on page 303 summarizes the External interfaces of FLCSERV, FLCCONGI,
MX160/320/640 and LAX20/40 boards.
Table 42. External Interfaces
Number
of interfaces
Logical
interfaces
Physical
connector
FLCSERV/A board
2
Q3
8 pin RJ45 (for each Q3 interface)
1
F
8 pin RJ45
1
F
USB mini–B
currently not supported!
2
2 MHz – 2 Mbit/s external output
synchronization signal
Sub–D 9 pin female
2
2 Mbit/s AUX G.703
2
64 Kbit/s AUX G.703
2
V.11 – 64 Kbit/s
2
V.24 – 9600 bit/s
1
phone jack
RJ11
currently not supported!
1
phonic extension
tripolar jack female
currently not supported!
1
debug
RJ45
25 pin SCSI + 4 coaxial
(2 input and 2 output)
currently not supported!
FLCCONGI board
2
Q3
8 pin RJ45 (for each Q3 interface)
1
F
8 pin RJ45
1
F
USB mini–B
currently not supported!
8
HouseKeeping Input
4
HouseKeeping Output
7
Remote Alarms
5
Rack Alarms
Sub–D 9 pin male
1
debug
RJ45
2 sub–D 15 pin female
MX160, MX320 (GA), MX640(GA) LAX20, LAX40, LAC40 board
1AA 00014 0004 (9007) A4 – ALICE 04.10
1
debug
RJ45
For more details about Housekeeping management refer to the CT Operator’s Handbook (chapter
“Station Alarms”).
ED
03
3AG 24163 BEAA PCZZA
531
303 / 531
13.10 Power Supply Subsystem
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The architecture of the power subsystem is distributed.
The input battery power:
–
–
–48 V (–40.5 V to –57 V) or
–60 V (–50 V to –72 V)
is delivered without level translation to all boards in the shelf.
When two inputs are used (Battery A and Battery B) the highest voltage is selected.
Each board has an on–board DC/DC converter, which generates the required voltage.
Distribution of power supplies inherently provides protection against single converter failures.
13.10.1 1678MCC Main Shelf
13.10.1.1 New Generation Top Rack Unit (NGTRU)
The 1678MCC Rack is generally equipped with the New Generation Top Rack Unit (NGTRU) where are
also located the rack lamps. The NGTRU is connected to a separate so called service power supply
“VSERV” needed for the “Rack Lamp Alarm” board and dedicated shelf alarming boards. The station
power supplies are terminated into the NGTRU. The NGTRU performs the following functions:
–
–
–
–
–
Delivers up to 6 Step-Up converter in the housed assemblies or up to 6 circuit breaker (bypass
modules)
Delivers the service battery (VSERV) to the housed assemblies
Sums up the alarms received from the shelves thus generating optical indications and transmitting
remote alarms towards an external target.
Connects the assemblies (up to 3) to the supervisory network through connectors situated into the
NGTRU
Provides up to 4 individual alarms per step up converter
There exist two types of modules using in the NGTRU:
–
The Step-Up converter
DC/DC converter with a constant output voltage of –65 V 2 V
–
The Bypass Battery module
Circuit Breaker
The NGTRU can house up to six step-up converter or bypass modules. Any mix of these parts is allowed,
but always as pair. That means branch A and branch B of the same shelf has to be fused with two step-up
converters or two bypass modules.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The circuit-breaker unit is part of the bypass module and is taken if the output voltage is equal to the input
voltage. In any case if the shelf consumption is more than 20 A (for UBattmin = –40.5 V) the Step-Up
converter will be used instead of a circuit breaker. In this case the constant output voltage of –65 V limits
the max. current (Imax).
ED
03
3AG 24163 BEAA PCZZA
531
304 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.10.1.2 Power Distribution
2–wire and 3–wire Functional Protection Earth (FPE) can be installed. Figure 165. shows the 1678MCC
power distribution with 3-wire FPE and Figure 166. shows the 1678MCC power distribution with 2-wire
FPE.
The delivery state of the step–up converters is 2–wire. A jumper is located on the rear panel of
the step–up converter (refer to Figure 164. ). In case of 3–wire systems the jumper have to be
removed!
have to be removed in
case of 3–wire systems
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 164. Step–up Converter – Location of Jumper
ED
03
3AG 24163 BEAA PCZZA
531
305 / 531
2 Batt. ret.
Top access
2 Batt. ret.
1 Batt. ret. is not
shown
Bottom access
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–a
+a
–b
+b
FPE/
GNDM
NGTRU
–a+a +b –b
NGTRU
GNDM
Rack
Rack
1 Batt. ret.
Top access
–a
+
–b
FPE/
GND M
FPE
–a+a +b –b
NGTRU
GNDM
Rack
3-wire FPE
–a
+a
–b
+b
FPE/
GNDM
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 165. 1678MCC Power Supply with 3-wire FPE
ED
03
3AG 24163 BEAA PCZZA
531
306 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Top access
–a
–b
+/FPE/
GNDM
bottom access
FPE
NGTRU
–a +a +b–b
NGTRU
GNDM
Top access
Rack
Rack
–a
+a/FPE/GNDM
–b
+b/FPE/GNDM
FPE
–a +a +b–b
NGTRU
Rack
FPE
GNDM
–a
–b
+/FPE/
GNDM
2-wire FPE
Figure 166. 1678MCC Power Supply with 2-wire FPE
The distribution of the New Generation Top Rack Unit (NGTRU) battery voltage (65V) and the distribution
of the Service Battery voltage (3.6V) inside 1678MCC equipment are illustrated at high level in
Figure 167. on page 308.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The Power Supply Filter (PSF) board get the power from the NGTRU and distributes the power to all
boards inside the main shelf.
ED
03
3AG 24163 BEAA PCZZA
531
307 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1AA 00014 0004 (9007) A4 – ALICE 04.10
ED
Distribution of Top Rack Unit power
Figure 167. Power distribution
Distribution of Service Battery voltage
03
3AG 24163 BEAA PCZZA
531
308 / 531
13.10.2 OEDs
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.10.2.1 Top Rack Unit (TRU)
The OED Rack is generally equipped with the Top Rack Unit (TRU) where are also located the rack lamps.
The TRU is connected to a separate so called service power supply “VSERV” needed for the “Rack Lamp
Alarm” board and dedicated shelf alarming boards. The TRU performs the following functions:
–
–
–
–
Delivers up to 12 circuit breakers (bypass modules)
Delivers the service battery (VSERV) to the housed assemblies
Sums up the alarms received from the shelves thus generating optical indications and transmitting
remote alarms towards an external target.
Connects the assemblies (up to 6) to the supervisory network through connectors situated into the
TRU
The TRU has been designed to distribute the Power supply voltage (A and B). All the outputs are protected
by circuit-breakers (1 to 12) having a max. of 30 A capacity. The total load amount must not exceed 60 A
for each battery. Should circuit-breakers having a capacity higher than 20 A, they have to be spaced as
most as possible inside the box to reduce over-temperature. If only one station battery is available, it is
possible to connect both Power blocks together thus utilizing a distributor with a max. of 12 outputs .The
whole current capacity must not exceed 60 A.
ED
03
3AG 24163 BEAA PCZZA
531
309 / 531
13.10.2.2 Power Distribution in the OEDs
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Two separated power branches (branch A and branch B) supply the converters. Branch A and branch B
may be connected to two different sources or to a common source.
Two circuit breaker blocks, one for each branch, are located in the power distribution unit (Top Rack Unit
– TRU) of each rack. The circuit breakers are of following types:
–
–
–
–
–
FAN unit 1670SM:
1670SM shelf:
FAN unit 1662SMC:
1662SMC shelf:
LAN switch:
4A
25 A
4A
16 A
4A
Figure 168. on page 310 show the power distribution with 3-wire FPE.
2 Batt. ret.
1 Batt. ret. is not
shown
Bottom access
2 Batt. ret.
Top access
–a
+a
–b
+b
FPE/
GND
M
TRU
FPE
Rack
Rack
TRU
–a
+a
–b
+b
FPE
1 Batt. ret.
Top access
–a
+
–b
FPE/
GND
M
FPE
Rack
TRU
–a
+a
3-wire FPE
–b
+b
FPE
–a
+a
–b
+b
FPE/
GNDM
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 168. OED Shelf Power Supply with 3-wire FPE
ED
03
3AG 24163 BEAA PCZZA
531
310 / 531
Figure 169. on page 311 shows the power distribution with 2-wire FPE.
Top access
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–a
–b
+/FPE/
GNDM
Bottom access
Rack
TRU
TRU
–a
–b
+a
+b
FPE
Rack
FPE
Top access
–a
+a
/FPE/GNDM
+b
/FPE/GNDM
–b
Rack
TRU
2-wire FPE
–a
–b
+a
+b
FPE
FPE
–a
–b
+/FPE/
GNDM
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 169. OED Shelf Power Supply with 2-wire FPE
ED
03
3AG 24163 BEAA PCZZA
531
311 / 531
13.11 Equipment Alarms and Tests Subsystem
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
In this paragraph are described the following functionalities managed in the 1678MCC equipment:
•
the Equipment Alarms (the alarms are referred to by the corresponding probable cause which
is visualized on OS);
•
the Tests (loops)
For more details about the list of all alarms and the list of all loops for each 1678MCC refer to the Operator’s
Handbook.
Refer to para. 13.10 on page 304 for details about Power Distribution.
13.11.1 Battery Failure
Battery Failure is raised only on PSF board when:
•
the corresponding Top Rack Unit (TRU) battery voltage is missing
Note: This happens, for instance, when the cable between TRU battery and PSF board is
unplugged.
13.11.2 RUM, RUTM
Each considered 1678MCC item has got a Remote Inventory.
The management of the Remote Inventory results in providing the following equipment alarms:
•
RUM (Replaceable Unit Missing): the slot is configured for an item with specific Remote
Inventory but no item is plugged in.
•
RUTM (Replaceable Unit Type Mismatch): the slot is configured for an item with specific
Remote Inventory but an item with different Remote Inventory is plugged in.
13.11.3 RUP
1AA 00014 0004 (9007) A4 – ALICE 04.10
RUP (Replaceable Unit Problem) alarm is raised on all items (except PSF board) when:
•
Battery Voltage (65V) from both PSF boards are missing.
•
At least one Service Battery voltage got by internal converter is failed.
Note: This condition takes into account double failure scenarios such as Battery Voltage (65 V)
from one PSF boards missing and the battery fuse on the item, corresponding to the other PSF
board, is broken.
•
The FLC board is present and has got a power problem.
Note: this statement applies only to FLCCONGI and FLCSERV boards
•
At least one of the three FANs in a FAN unit does not run.
On RUP occurrence, the information about its cause is provided by the alarm qualifier (i.e. “specific
problem” number).
In the RUP definition for the currently designed items of 1678MCC, the specific problem indicates the
SPIDER pin on which the problem is detected.
When more equipment problems causing the alarm on an item are contemporarily present, the specific
problem shows the first one detected by SLC.
ED
03
3AG 24163 BEAA PCZZA
531
312 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.11.4 Fuse Failure
The alarm for reporting a Battery Fuse Broken is the Fuse Failure.
For describing the fuse failure alarm usage, it is worthwhile to differentiate the PSF board from the other
boards of the NE, as follow:
•
In case of PSF board, the fuse failure alarm is raised when a battery fuse of the board is broken
and the corresponding TRU battery voltage (65V) is correctly received.
It means that fuse failure alarm cannot be raised on a PSF board, for which TRU battery voltage
is missing.
The information, about which fuse is broken inside the PSF board, is provided by the specific
problem number. The specific problem indicates the SPIDER pin on which problem is detected.
•
In case of all other boards and FAN, the fuse failure alarm is raised when a battery fuse of the
board is broken and the battery voltage of the same branch of the broken fuse is correctly
received.
It means that fuse failure alarm cannot be raised on an item, for which battery voltage of the
same branch of the broken fuse is missing.
The information about the affected battery fuse is on branch of PSF A or on branch of PSF B is provided
by the specific problem number. The specific problem indicates the SPIDER pin on which problem is
detected.
When more equipment problems causing the alarm on an item are contemporarily present, the specific
problem shows the first one detected by SLC.
Note: The Fuse Failure alarm contributes to light the red led on the board frontpanel, like RUP alarm.
13.11.5 Test Management
The functions, described in this section, are used to control and monitor the test operation and returning
the system to the normal environment (i.e. the environment before the test was performed).
The Second Level Controller (SLC) is in charge to perform the following tests on the Optical STM–N ports:
•
•
Line Loopback (external)
Internal loopback
1AA 00014 0004 (9007) A4 – ALICE 04.10
Each of these Loopbacks is performed driving ASICs on the port boards (Loop and Continue, i.e. the VC
is sent back and also continues its path).
ED
03
3AG 24163 BEAA PCZZA
531
313 / 531
13.12 Station Alarms
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.12.1 Description
The Station Alarm feature will provide the following main functions:
–
–
–
Rack lamps
Housekeeping inputs/outputs (GPIs/GPOs)
Rack reset button
The Station Alarms feature describes the concept of how the rack lamps and contacts either in the NGTRU
or TRU are driven.
Each NGTRU/TRU has 4 independent station alarms and corresponding alarm contacts which are
controlled by one shelf via the R/M–interface of the NGTRU.
There are two different TRUs in the 1678MCC. The main rack which contains the 1678MCC main shelf
(and/or the LO extension shelf) is equipped with the NGTRU (New Generation Top Rack Unit). The OED
racks are equipped with the TRU.
This chapter describes the general station alarm concept used in the 1678MCC for the main rack and OED
racks. In addition it describes the handling of the NGTRU alarms, using the housekeeping input contacts.
13.12.2 Features
The 1678 MCC has the following Station Alarm features:
–
Each rack provides one reset push button which is connected to one housekeeping input contact.
–
Each shelf has 4 outputs (Power, Lamp 1–3) to connect directly to the 4 station lamps.
–
Each 1678MCC main shelf/LO extension shelf has 3 General Purpose Input contacts (GPI) and 4
General Purpose Output contacts (GPO) for operator defined usage.
–
Each 1670SM OED shelf has 4 General Purpose Input contacts (GPI) and 2 General Purpose Output
contacts (GPO) for operator defined usage.
–
Each 1662SMC OED shelf has 4 General Purpose Input contacts (GPI) and 2 General Purpose
Output contacts (GPO) for operator defined usage.
–
It is possible to detect alarms of the equipment mounted in the NGTRU, e.g. Step up converters with
their FANs.
Only one shelf in a rack is connected to the TRU/NGTRU to control the rack lamps:
–
–
In the 1678MCC rack
•
the 1678MCC main shelf or
•
the LO extension shelf (if only the LO extension shelf is mounted in a separate rack).
In the OED rack is this generally the lower shelf (1670SM or 1662SMC).
1AA 00014 0004 (9007) A4 – ALICE 04.10
The operator has to specify for the R/M and GPI/O interfaces which shelf is responsible to drive the rack
lamps.
ED
03
3AG 24163 BEAA PCZZA
531
314 / 531
In this section, an architectural overview is given. Figure 170. is more a physical view showing all the
components or subsystems which are necessary to implement this station alarm feature. It shows the
physical interfaces which are provided by each rack:
Internal communication
Control system
Craft Terminal (CT) or Element Manager which provides a user–friendly graphical user interface
towards the operator.
P L1 L2 L3
R/M
.
TRU
HMU
Remote
alarming
Remote
alarming
Remote
alarming
P L1 L2 L3
R/M
.
TRU
Push
Button
HMU
1662SMC
1662SMC
P L1 L2 L3
R/M
Push
Button
3 x GPI
4 x GPO
HMU
P L1 L2 L3
R/M
.
NGTRU
Push
Button
3 x GPI
4 x GPO
FAN
LO
FANs
FANs
Remote
alarming
.
NGTRU
HMU
Push
Button
FAN
1678
FAN
FLC
–
–
–
ALM
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.12.3 Architectural Overview
FAN
FAN
1670SM
1662SMC
4 x GPI
2 x GPO
4 x GPI
2 x GPO
FANs
LAN
LAN
FANs
Rack #n
internal LAN
Rack #3
GPI–CTRL
OED shelf
or
LO shelf
FANs
Rack #2
GPO–CTRL
Rack #1
CT/EML
Figure 170. Station Alarm System Architecture – Physical View
13.12.4 Control of the (NG)TRU
Only the 1678MCC main shelf/LO extension shelf of the 1678 rack is connected to the NGTRU and can
drive the station lamps. In the OED rack the 1670SM or the 1662SMC shelf can be connected to the TRU.
The shelf is selected according the cabling during equipment provisioning.
Each (NG)TRU is connected with cables either to
1AA 00014 0004 (9007) A4 – ALICE 04.10
–
–
–
ED
the front panel connectors of the FLCCONGI board in case of 1678MCC main shelf,
the front panel connectors of the Alarm board in case of LO extension shelf or
the front panel connectors of the CONGI boards in case of 1670SM/1662SMC OED shelf.
03
3AG 24163 BEAA PCZZA
531
315 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.12.4.1 Control from the 1678MCC Main Shelf
On the FLCCONGI/ALM board the “Control and General Interface” (CGI) function is in charge of the
management of rack lamps and housekeeping interfaces for the 1678MCC Network Element. This
interface consists of a set of specialized parallel I/O with certain electrical properties and a DC/DC
converter to provide the local voltage (–12 V) for the housekeeping inputs.
13.12.4.2 Control from an OED Shelf
The Remote Monitoring (R/M) and housekeeping (HK) interface in OED shelves can also be accessed
via the redundant shelf controllers in the OED shelves (CONGI boards).
13.12.5 NGTRU Alarm Supervision
The NGTRU contains step up converters with FANs which need to be supervised or bypass modules. Only
in case of a failure condition of the step–up converters the equipment has to be alarmed.
Because this granularity is not needed in the 1678MCC NGTRU supervision, some of the alarms of each
step –up converter are joined in the HMU. Voutput or FAN alarm or Intern alarm of the same step–up
converter = Internal alarm.
The NGTRU offers the following alarms at the 25–pin connector interface for each of the 6 step–up
converters (24 alarm pins + ground pin):
–
–
Vinput (<38Veff)
Internal alarm
•
Voutput
•
FAN alarm
•
Intern alarm
The NGTRU Vinput alarms are mapped to fuse failures (FF), the NGTRU Internal alarms are mapped to
RUP alarms.
Only the alarms of the first step–up converter of each branch, belonging to the 1678MCC main shelf, are
wired to the housekeeping input contacts at the 1678MCC main shelf. For this a connection cable is
necessary. The challenge of this cable is the monitoring of the two step–up converter alarms for the
1678MCC main shelf via housekeeping input contacts (GPIs) by the FLCCONGI.
The first 4 GPI contacts of the main shelf are predefined. There are used to signal “Power failures” of the
4 Step–up converters which are used in the NGTRU. The alarms are VinputA, VinputB, InternalA and
InternalB. These GPI contacts can’t be assigned by the operator for other purposes.
13.12.6 Hardware Aspects
1AA 00014 0004 (9007) A4 – ALICE 04.10
The physical interfaces like rack lamp interface (RM) towards NGTRU/TRU or Housekeeping Contacts
(GPI/GPO) are provided by:
–
1678MCC Main shelf (refer to Figure 171. )
•
RM (FLCCONGI)
•
GPs (FLCCONGI)
–
1678MCC LO extension shelf (refer to Figure 172. )
•
RM (ALM)
•
GPs (ALM)
ED
03
3AG 24163 BEAA PCZZA
531
316 / 531
OED shelf 1670SM (refer to Figure 173. )
•
RM (CONGIHC_A)
•
GP (CONGIHC_A)
–
OED shelf 1662SMC (refer to Figure 174. )
•
RM (CONGI_A)
•
GP (CONGI_A)
Note:
The customer interface supporting Housekeeping contacts will be provided by the Housekeeping
Monitoring Unit (HMU).
RACK LAMPS
Upper FAN
R/M
HK & RA
1678MCC
PSF
FLCCONGI
PSF
FLCSERVICE
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
Push Button
HMU
NGTRU
Step up
Alarms
Lower FAN
3xGPI
4xGPO
Figure 171. Rack Lamp Interfaces including GP Contacts of 1678MCC Shelf
RACK LAMPS
Upper FAN
HK & RA
ALM
R/M
PSF
1678MCC
dummy plate
PSF
Push Button
HMU
NGTRU
Step up
Alarms
1AA 00014 0004 (9007) A4 – ALICE 04.10
Lower FAN
3xGPI
4xGPO
Figure 172. Rack Lamp Interfaces including GP Contacts of LO Extension Shelf
ED
03
3AG 24163 BEAA PCZZA
531
317 / 531
R/M
CONGIHC_B
HK & RA
1670SM
Push Button
HMU
AUX_HK
AUX_HK
4xGPI
2xGPO
CONGIHC_A
HK & RA
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
R/M
RACK LAMPS
FANs
Figure 173. Rack Lamp Interfaces including GP Contacts of 1670SM Shelf
1662SMC
CONGI_B
HK & RA
4xGPI
2xGPO
HK & RA
CONGI_A
R/M
R/M
RACK LAMPS
Push Button
HMU
FAN Alarms
Upper FAN
Lower FAN
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 174. Rack Lamp Interfaces including GP Contacts of 1662SMC Shelf
ED
03
3AG 24163 BEAA PCZZA
531
318 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.12.6.1 Rack Lamp (RM) Interface
The rack lamp unit provides 4 alarm lamps with colors as defined in Table 43. The (P)ower lamp indicates
“power ok” only for the shelf, that drives the rack lamps, not for the whole rack. The (P)ower lamp lit during
normal operation.
The three station alarm lamps (L1, L2, L3) can be configured by customer.
If an OED shelf drives the rack lamps, the power lamp is switched off when
both branches are OK. In case of a failed branch the power lamp is lit
(inverse behavior as normally)!
The three station alarm lamps are off in normal operation and on during dedicated alarm conditions.
Restriction if an OED shelf drives the rack lamps
There are the following restriction:
–
In case of a failed branch the alarm lamp L3 (yellow) is switched on, independent of configured alarm
filters on software side.
Table 43. Rack Lamp Colors
Lamp position
1
2
3
4
Lamp label
P
L1
L2
L3
green
red
red
yellow
Color
13.12.6.2 Reset Push Button
The reset push button will be located on the HMU. The reset push button is controlled by SW and allows
to reset all GPO contacts and the rack lamps L1 to L3.
13.12.7 Supported Customer individual Housekeeping contacts
Depending on kind of used shelf different quantity of GPIs/GPOs are supported. In case of pure OED
shelves (1670/1662) CONGI 3–wire must be used only. With this boards each rack provides up to
4 housekeeping inputs and 2 housekeeping output contacts.
In case of 1678MCC shelf/LO extension shelf up to 3 GPIs and 4 GPOs are supported at rack level.
13.12.8 Housekeeping Monitoring Unit (HMU)
The HMU is part of the 1678MCC Main and OED racks with following applications:
–
1678MCC Main Rack:
1AA 00014 0004 (9007) A4 – ALICE 04.10
•
•
•
–
Monitoring of up to six Step–Up Converter Alarms
Client Interface for Housekeeping Contacts (GPIs/GPOs)
Rack Reset Push Button
In case of OED Racks:
•
ED
Rack Reset Push Button
03
3AG 24163 BEAA PCZZA
531
319 / 531
HMU
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
HK
MS2
NGTRU
Reset Push Button
HK
NGTRU
MS1
MS2
MS3
COED
MON
MS1
COED
MS3
MON
Connector for Housekeeping
Connector for NGTRU
Connector for Main Shelf No.1/LO Extension Shelf
Connector for Main Shelf No. 2
Connector for Main Shelf No. 3
Connector for OED Shelf
Connector for FAN of 1662SMC shelf
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 175. Schematic Drawing of HMU Architecture
ED
03
3AG 24163 BEAA PCZZA
531
320 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.13 Remote Inventory Subsystem
The Remote Inventory functions permits the operator to retrieve information about any board or module
present on the equipment.
The available information is: construction date, code number, maker name, Board–type, etc. (refer to
details in the Operator’s Handbook).
The Remote Inventory function is present in all the boards and modules.
The relevant data are transported by a serial link (named RIBUS in Figure 176. on page 321) that connects
all boards or modules of the equipment.
The block ”RIBUS–I/F” of figure implements the interface of the serial link with the remote inventory device
(named RI in the figure). Further it manages the slot identifier (ID) and the board type (CType). The CType
information is contained on the RI device.
The RI can be also present on some sub–modules assembled on the board (such as optical modules,
micro–controllers and so on).
This block can also manage the visual indications of the board (LEDs) and some I/O parallel
commands/contacts/alarms that can eventually be transferred by means of the RIBUS link.
If it is not possible to read the Remote Inventory information, a “Board Fail” alarm is declared.
RI
RIBUS
I/F
SHELF
CONTROLLER
RIBUS
Generic Board (or Module)
X
Board
Indications
RIBUS
I/F
EQUIPMENT
CONTROLLER
Board
RI
ID
...
RI
RIBUS
I/F
Intracard
Module
Board I/O
Module
RI
1AA 00014 0004 (9007) A4 – ALICE 04.10
...
Figure 176. Remote Inventory Subsystem
ED
03
3AG 24163 BEAA PCZZA
531
321 / 531
13.14 OED Integration
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.14.1 General
This chapter covers the introduction of the 1670SM and 1662SMC into the 1678MCC. The reasons for
doing this are to provide external interfaces which are not offered by the 1678MCC main shelf, like 2Mbit/s,
and mainly to increment the matrix capacity which can be used for STM-1 and STM-4 interfaces.
13.14.2 System Requirements
This chapter presents the detailed requirements for the 1678 OED Integration feature. The OED
integration feature is driven by the motivation
–
–
–
–
to provide I/O types which are not supported in the 1678MCC main shelf
to reuse existing equipment as additional I/O ports
to increase the number of possible I/O ports
to allow a better usage of the HO matrix capacity in the 1678MCC main shelf by I/O types which would
be limited by the number of I/O slots in the 1678MCC main shelf.
The OED integration feature defines a complete integration of OEDs consisting of
–
–
the mechanical OED integration and
the SW OED integration.
13.14.3 Mechanical OED Integration Requirements
The following figure describes how the OEDs 1670SM and the 1662SMC are connected to the 1678MCC
main shelf and which hardware components are involved.
16 x STM_16
4 x I–64
16 x STM_16
3P
4 x I–64
LINK_P
CON_A
1P
2P
4P
CON_B
1662SMC
1678MCC Main Shelf
S16.1
SYNTH16_A
S16.1
SYNTH16_B
–
EC
1
2
3
4
VSR10G
–
LINK_W
1670SM
EC
FLCSERV
FLCCONGI
CON_A
LAN
1AA 00014 0004 (9007) A4 – ALICE 04.10
Topology
Figure 177. Schematic drawing of OED Integration
ED
03
3AG 24163 BEAA PCZZA
531
322 / 531
13.14.4 SW OED Integration Requirements
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The 1678MCC main shelf and all integrated OEDs are seen as one network element from an external point
of view. The control of the OEDs has to be done via the 1678MCC control system.
The links from the OEDs to the 1678MCC main shelf are internal links of the network element and are to
be managed internally. The SW supports the complete configuration of these internal links including the
required link protection.
The complete 1678MCC network element including all integrated OEDs runs with one selected clock
source. The SW supports the complete configuration of the synchronization mechanism in the OEDs and
main shelf.
13.14.5 Kinds of OEDs
The following OEDs are integrated into the 1678MCC:
–
–
1670SM
1662SMC
1AA 00014 0004 (9007) A4 – ALICE 04.10
The number of OEDs which can be connected to the 1678MCC main shelf is limited on one side by the
I/O ports used as link ports in the 1678MCC main shelf and on the other side by the LO matrix capacity
offered by the 1678MCC main shelf.
ED
03
3AG 24163 BEAA PCZZA
531
323 / 531
13.14.5.1 1670SM
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
General
The optical edge device 1670SM provides interfaces:
–
–
which are also supported by the 1678MCC Main shelf (several HO interfaces)
which are not supported by the 1678MCC Main shelf
Equipment
The mechanical integration is such that the 1670SM is housed in 600x300 mm racks. Back to back and
stand alone application of OED-Racks will be supported. The system is designed for 2 wire and 3 wire
application. EMC shielding is done on shelf level. The 1670SM shelves are indoor equipment and it is
recommended to be installed in a air conditioned location. The layout of the 1670SM shelf is shown in
Figure 178.
Figure 178. shows the basic equipment of a 1670SM shelf. Detailed information about basic equipment
are described in chapter 12.1 on page 147.
I/O Interfaces
The 1670SM integration offers the following interfaces:
–
–
–
–
140 Mbit/s
STM-1e
STM-1o
STM-4.
Note: For the supported I/O interfaces refer to chapter 12.1.5.1 on page 150.
1670SM
2 3 4 5 6 7 8 9 10 1112131415161718 19 20
1
21
22
23 24
2425 26 27 28 2930 31 323334 35 36 3738 3940
CONGIHC copyB
empty
empty
empty
CONGIHC copyA
Accesscards
AccessArea
41
1AA 00014 0004 (9007) A4 – ALICE 04.10
50
VSR LINK 4A
VSR LINK 4B
empty
49
HCMATRIX copyB
I/O slots assigned
to USR LINKs 4
48
VSR LINK 3B
I/O slots assigned
to USR LINKs 3
47
VSR LINK 3A
46
BTERM
I/O slots assigned
to USR LINKs 2
44 45
VSR LINK 2B
I/O slots assigned
to USR LINKs 1
43
VSR LINK 2A
VSR LINK 1A
42
VSR LINK 1B
EQUICO
HCMATRIX copyA
PortCards
PortArea
LINKArea
Figure 178. Layout of the 1670SM Shelf
ED
03
3AG 24163 BEAA PCZZA
531
324 / 531
13.14.5.2 1662SMC
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
General
The 2 Mbit/s interfaces which are not supported by the 1678MCC Main shelf are provided by the optical
edge device 1662SMC.
Equipment
The mechanical integration is such that the 1662SMC is housed in 600x300 mm racks. Back to back and
stand alone application of OED-Racks will be supported. The system is designed for 2 wire and 3 wire
application. EMC shielding is done on shelf level. The 1662SMC shelves are indoor equipment and it is
recommended to be installed in a air conditioned location. It must be noted that max 504x2 Mbit/s ports
can be equipped in one shelf. The layout of the 1662SMC shelf is shown in Figure 179.
Figure 179. shows the basic equipment of a 1662SMC shelf. Detailed information about basic
equipment are described in chapter 12.2 on page 179.
I/O Interfaces
The 1662SMC integration offers the following interfaces:
–
–
2 Mbit/s
STM-16.
Note: For the supported I/O interfaces refer to chapter 12.2.4.1 on page 181.
1662SMC
7
8
9 10 11 12 13 14
15
16 17 18 19 20
Access
Access
Access
Access
CONGI
6
B
SYNTH16 copyB
5
Port
Port
Port
Port
Port
Port
Port
Port
3 4
A
SYNTH16 copyA
2
CONGI
Access
Access
Access
Access
1
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 179. 1662SMC Shelf: Face Layout
ED
03
3AG 24163 BEAA PCZZA
531
325 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.14.6 OED Synchronization
The System-Synchronization is part of the 1678MCC Main Shelf (refer to Figure 180. ). The
synchronization with possible extension shelves (eg. 1670SM or 1662SMC) will be done without special
clock cable through standard SDH interfaces by using SSM signalling. The synchronization subsystem
provides the timing reference and represents the SDH Equipment Clock (SEC). The subsystem performs
the functionality identified by the ITU-T recommendation G.783 as SDH Equipment Timing Source
(SETS).
The OED subsystems are able to handle the Priority and Quality (SSM) synchronization algorithms
termination functionality. Source for the OED synchronization is either a customer signal or an internal
STM-n link provided by the main shelf. The synchronization information between OED and Main shelf is
done via internal standard STM-n link using SSM signalling.
1670
T1
T1
1670
1678
1662
T2
T3/T6
Figure 180. OED Synchronization for ETSI application
1AA 00014 0004 (9007) A4 – ALICE 04.10
The interfaces provided by the OEDs can distribute the system clock with or without quality indication
(SSM in S1 byte) to neighbored network elements and can also be used for clock derivation (timing
sources). Each OED operates like a normal SDH network element concerning its clock system, but only
the selector B for the system clock is used. The selectors A and C for station clock outputs are not used
in OEDs. The station clock outputs of the OEDs can be configured permanently to T4 (2MHz) with a forced
squelch (AIS). A station clock output (T4 or T5) and 2 station clock inputs (T3 resp. T6) are supported in
the main shelf of the 1678 only. The selector A in the main shelf (providing station clock output) can be
configured with STM–N timing sources located in the main shelf only.
ED
03
3AG 24163 BEAA PCZZA
531
326 / 531
13.15 1678MCC Network Requirements
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
A consistent time between the NEs of a network is a important requirement to a network. The same holds
for the distribution of the clock.
Time and Date Partsystem
All hosts within 1678MCC refer to the FLC UNIX system time. This time is synchronized to an external time
source and is distributed to the Shelf Controllers, Equipment Controllers and User Boards. The Time and
Date Partsystem covers all the functionalities to retrieve the correct time and date from time sources in
order to have this time available for functions like time stamping etc.. .
Further the Time and Date Partsystem has to ensure that:
–
–
No problems occur due to the switching of summer/winter time or to different interpretations of the
actual time base (e.g. LCT, GMT)
The operation of a network by the OS is performed without ambiguity of the time base and time
accuracy: the OS performs an interpretation of the network availability and error status on the base
of alarms correlation. This function requires that the alarm time stamps in all the NEs of the network
are created on the same time base and with a limited offset error.
1678MCC fulfills these requirements in the following way:
–
–
–
All hosts run under a common time base UTC (Universal Time Coordinated)
(On the CT the local time offset against UTC can be set by the operator for presentation purposes)
The control system supports the Network Time Protocol NTP:
The FLC and CT UNIX system time is synchronized to an external time source by application of
the NTP which is available on the external LAN.
Date and time source is a NTP time server connected to the external LAN.
NTP Server Configuration
The configuration of NTP is provided via CT/MIB/VHM/CS-Server.
One main and one spare NTP server address can be configured via CT/MIB /VHM. Initial installation shall
not require to define an NTP server address. During initial installation, the system time is set to the time
of the install server.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Note:
IP addresses which are local to the NE cannot be configured as external NTP time server addresses.
ED
03
3AG 24163 BEAA PCZZA
531
327 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
13.16 Data Application and Layer 2 Switching
In typical Metro Networks, Ethernet services are becoming more and more important. Triple Play and
Business Ethernet services are driving the traffic requirements. From the transport network perspective,
this requires Ethernet connectivity and aggregation capability, sometimes even at several points in the
network, in order to increase the network efficiency and utilization.
In order to support the Core and Metro Core data applications, 1678 MCC supports different data boards.
The functionality of these boards and the services enabled are described in the following in more detail.
13.16.1 4/8/16xGigabit Ethernet Boards
With the GE cards Ethernet Private Line services (point–to–point, EPL Type 1) can be supported.
Traffic is entering the network from customer sites using separate physical GE interfaces. The complete
GE signal will be mapped into SDH/SONET via GFP in a dedicated Virtual Concatenation Group (VCG),
either transparently or with rate adaptation. The VCs of one VCGs can run in the same or different
STM–N/OC–x links through the network. On the other end of the network the VCGs will be terminated and
the traffic is mapped back on a dedicated GE interface. It is not possible that several customer GE
interfaces share the same VCG through the network, as EPL Type 1 is a dedicated and not a shared
service.
Ethernet frames are mapped in SDH/SONET containers via a GFP code according to G.7041 with any
possible adaptation ratios:
1:N – 1 x GE –> GFP –> VC–4–Nv (with N = 1 to 7) / AU3–Nv (with N = 1 to 21)
A further aggregation of the traffic is possible at the SDH/SONET layer on a VC–4/AU3 granularity.
The Link Capacity Adjustment Scheme (LCAS) is supported, providing automatic rate adaptation from
VC–4/AU3 to VC–4–7v/AU3–21v depending on the incoming bit rate, and in case of failure of a single VC
(compliant with G.7042). If a VC fails, this failure will be signaled back to the source node to reduce the
Ethernet packet flow. The LCAS protocol ensures that the failing VC–4/AU3 will not be used anymore and
only working VC–4s/AU3s will be used for the transport of Ethernet frames. Flow control and Ethernet
performance counters are supported for quality of service purposes.
13.16.2 4x10 Gigabit Ethernet Boards
The 4x 10GE card is an Ethernet Aggregator and provides physical access of 4x 10GE interfaces. It can
be used in the same way as the GE interface described in the previous chapter (EPL Type 1).
1AA 00014 0004 (9007) A4 – ALICE 04.10
In order to achieve an optimized interfacing to other Service Providers a 10GE interface should have a
cost advantage over several times GE. In this case a multiplexed access is required, as several customer
services (VLANs) with different end–points will be carried over one physical 10 GE interface. The 4x 10GE
card addresses this requirement and provides VLAN aggregation capabilities using Ethernet Virtual
Private Line Service (EVPL Type 1, logical point–to–point).
In case several client signals are transported over the same 10 GE interface, the different VLAN tags of
the aggregation link are evaluated. The Ethernet frames will be mapped per VLAN into separate VCGs,
using GFP. So each VLAN is connected individually over the network. For each VLAN a dedicated VCG
is used. On the destination side the signal is terminated and can be handed over to the customer via
another multiplexed 10 GE interface or via a dedicated physical interface.
EVPL Type 1 functionality is supported in any kind of topology, e.g. point–to–point, hub & spoke or mesh.
ED
03
3AG 24163 BEAA PCZZA
531
328 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The 10GE board can be used amongst others for IP Backbone, Metro Ethernet interconnect and
point–to–point Ethernet private line applications. The 10GE board is the optimized board to provide EVPL
Type 1 and EVPL Type 1a.
13.16.3 ISA–ES64 Data Board
The ISA–ES64 board complements the data portfolio of the 1678 MCC. It is an advanced 20Gbit/s L2
switch and enables cost–effective Carrier Class Ethernet for Metro.
1678 MCC provides two different hardware variants of the ISA–ES64 board:
–
–
A pure L2 server board without any physical ports,
A board with an integrated 10GE physical front access (future releases).
It represents the next step of the ISA family and increases further the support of Metro Ethernet Services
for the Alcatel–Lucent transmission portfolio. The board can be used as well in IP Core applications within
the 1678MCC to provide L2 Ethernet aggregation between Core–, Service– and Edge Routers on one side
and Optical Switches on the other side. In addition to the data functionality the ISA–ES64 is optimized for
more advanced L2 switching mechanisms, beyond what is provided by the 1GE and 10GE boards.
ED
03
3AG 24163 BEAA PCZZA
531
329 / 531
14 UNITS DESCRIPTIONS MAIN SHELF
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
14.1 Introduction
The following Table 44. on page 330 up to Table 46. on page 332 sums up the units managed in the
1678MCC Main Shelf Equipment.
Table 44. Units involved in 1678MCC Main Shelf
Type / Class
Acronym
Control / Common FLCCONGI ENH.
HO Matrix
LO Matrix
SDH Port
STM–64
1AA 00014 0004 (9007) A4 – ALICE 04.10
Description
ED
FLCCONGI
FLCSERVICE ENH.
FLCSERV
FLCSERVICE ENH. ANSI
FLCSERVA
Power Supply and Filter
PSF
Bus Termination
BUSTERM
Matrix 640 Gbit/s
MX640
Matrix 640 Gbit/s ANSI
MX640GA
Matrix 320 Gbit/s
MX320
Matrix 320 Gbit/s ANSI
MX320GA
Matrix 160 Gbit/s
MX160
LO Adaptation/Matrix Board 40G
LAX40
LO Adaptation/Matrix Board 20G
LAX20
Lower Order Matrix Link 40G
LAC40
1 x STM–64
S–64.2 Optical port
S–642M
1 x STM–64
L–64.2 Optical port
L–642M
1 x STM–64
V–64.2 Optical port
V–642M
1 x STM–64
U–64.2 Optical port
U–642M
1 x STM–64
I–64.1 Optical port
I–642M
2 x STM–64
S–64.2 Optical port
P2S64M
2 x STM–64
I–64.1 Optical port
P2I64M
2 x STM–64
S–64.2 Optical XFP port
P2S64X
4 x STM–64
I–64.1 Optical port
P4I64
4 x STM–64
S–64.2
Optical port
P4S64
4 x STM–64
S–64.2
Optical XFP port
P4S64X
Width Q.ty
(TE)
4
1
2
8
2
4.5
2
5
4.5
16
03
3AG 24163 BEAA PCZZA
531
330 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Type / Class
Description
Acronym
SDH Port
STM–16
16 x STM–16 Optical port
P16S16
8 x STM–16
Optical port
P8S16
4 x STM–16
Optical port
P4S16
Width Q.ty
(TE)
4.5
16
4.5
16
4.5
16
SDH Port
STM–1/4
16 x STM–1/4 Optical port
P16S1S4
16 x STM–1
Optical/Electrical port
P16S1S
SDH Port
GE
16 x GE
Optical port
P16GE
8 x GE
Optical port
P8GE
4 x GE
Optical port
P4GE
2 x 10GE
Optical port
P2XGE
4 x 10GE
Optical port
P4XGE
4.5
*
SERVER CARD
ISA–ES64 Server Board
ES64SC
4.5
2
FAN System
FAN
FAN
––
2
* Max number of boards is limited because of the power consumption of around 140 W per board. The
maximum shelf load (of around 1.5 kW for the sum of all 16 I/O slots) mustn’t be violated (refer also to chapter 10.1.2 on page 85.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Notes:
ED
Q.ty = max number allowed in the 1678MCC Main Shelf equipment
Acronym = label shown on CT
03
3AG 24163 BEAA PCZZA
531
331 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Table 45. Electrical Modules involved in 1678MCC Main Shelf
Type
Description
Acronym
STM–1e
TRX SFP STM–1e
SES1
16
Table 46. Optical Modules involved in 1678MCC Main Shelf
Type
Description
Acronym
STM–1
S–1.1 SFP – Short Haul (wl = 1310 nm)
SS–1.1
L–1.1 SFP – Long Haul (wl = 1310 nm)
SL–1.1
L–1.2 SFP – Long Haul (wl = 1550 nm)
SL–1.2
S–4.1 SFP – Short Haul (wl = 1310 nm)
SS–4.1
L–4.1 SFP – Long Haul (wl = 1310 nm)
SL–4.1
L–4.2 SFP – Long Haul (wl = 1550 nm)
SL–4.2
I–16.1 SFP – Intra–office (wl = 1310 nm)
SI–16.1
S–16.1 SFP – Short Haul (wl = 1310 nm)
SS–16.1
L–16.1 SFP – Long Haul (wl = 1310 nm)
SL–16.1
L–16.2 SFP – Long Haul (wl = 1550 nm)
SL–16.2
Opto Transc. Module 1470nm
CWP
Opto Transc. Module 1490nm
CWP
Opto Transc. Module 1510nm
CWP
Opto Transc. Module 1530nm
CWP
Opto Transc. Module 1550nm
CWP
Opto Transc. Module 1570nm
CWP
Opto Transc. Module 1590nm
CWP
Opto Transc. Module 1610nm
CWP
Opto Tr. Module 1470nm APD
CWA
Opto Tr. Module 1490nm APD
CWA
Opto Tr. Module 1510nm APD
CWA
Opto Tr. Module 1530nm APD
CWA
Opto Tr. Module 1550nm APD
CWA
Opto Tr. Module 1570nm APD
CWA
Opto Tr. Module 1590nm APD
CWA
Opto Tr. Module 1610nm APD
CWA
Opto TRX SFP L–16.2 DWDM CH620 ... CH170
DWA
STM–4
STM–16
1AA 00014 0004 (9007) A4 – ALICE 04.10
Q.ty
ED
Q.ty
16
16
16
03
3AG 24163 BEAA PCZZA
531
332 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Type
Description
STM–64
S–64.2b
(nb1)
MS642
1, 2, 4
I–64.1
(nb2)
MI641
1, 2, 4
L–64.2
(nb3)
ML642
1
V–64.2
(nb3)
MV642
1
U–64.2
(nb3)
MU642
1
S–64.2 b
(nb4)
XS642B
2, 4
S–64.2 b Ext
(nb4)
XS642E
2, 4
L–64.2
(nb4)
XP1L12D2
2, 4
I–64.1
(nb4)
XI641
2, 4
OPTO TRX 1.25GBE SFP–SX
(nb5)
SGESX
OPTO TRX 1.25GBE SFP–LX
(nb5)
SGELX
GE
OPTO TRX 1.25GBE SFP–ZX
(nb5)
SGEZX
GE
OPTO TRX XFP 10GBASE–S
(nb6)
XGES
2, 4
OPTO TRX XFP 10GBASE–E
(nb6)
XS642B
2, 4
OPTO TRX XFP 10GBASE–L
(nb6)
XI641
2, 4
GE
1AA 00014 0004 (9007) A4 – ALICE 04.10
Notes:
ED
Acronym
Q.ty
4, 8, 16
Q.ty = max number allowed in a single system
Acronym = label shown on CT
(nb1) = hosted in S–642M, P2S64 and P4S64 boards
(nb2) = hosted in I–64.1M, P2I64M and P4I64 board
(nb3) = hosted in L–642M
(nb4) = hosted in P2S64X and P4S64X
(nb5) = hosted in P(4, 8, 16)GE boards
(nb6) = hosted in P2XGE/P4XGE boards
03
3AG 24163 BEAA PCZZA
531
333 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
14.2 First Level Controller and Control & General Interface (FLCCONGI)
The FLCCONGI board is designed as the hardware platform supporting the First Level Controller (FLC),
the Control and General Interface (CGI) and the Data Communication Channel (DCC) functions for the
1678 MCC Network Element (NE).
These functions are performed by one or two on–board microprocessors (DCR and EM), by a Multi High–
Level Data Link Controller (MHDLC) for the DCC processing and by a Complex Programmable Logic Device (CPLD) which manages the station alarms and signalling (part of the CGI function).
The FLCCONGI board is composed of the following blocks (refer to Figure 181. ):
–
–
–
First Level Controller (FLC) function
Control and General Interface (CGI) function (comprises also the synchronization reference interface)
DCC function.
Frontpanel interfaces
RL
Backpanel interfaces
FLCCONGI
RA
Qecc
17
Qecccmx
16
HK
PIO
DCC Function
SY_REF
SY_FR
LAN_A
CGI Function
DBG_DCR
ISSB_1
LCI
F
SYS_ID
USB
FLC Function
LAN switch
LAN_B
IPL
IPL_LAN
DBG_EM
DCR
SYNC
EM
HDD
ISSB_2
SPI_A
SPI_B
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 181. Block Diagram and external Interfaces of FLCCONGI enhanced
ED
03
3AG 24163 BEAA PCZZA
531
334 / 531
14.2.1 First Level Controller Function
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The first level controller function is in charge of the processing activities concerning the “Virtual Equipment
Control Element” (VECE) function for the 1678 MCC network element, consisting of:
–
–
Virtual Machine Management Function (VMMF)
Message Communication Function (MCF).
The basic element of the FLC function in the FLCCONGI/FLCSERV(A) board is the “DCR Processor Module” daughterboard. On the processor board are several basic hardware components available, as required by the FLC function:
–
–
–
–
–
Microprocessor (CPU)
System memory (Flash EPROM, RAM)
I/O parallel bus (PCI)
Serial communication channels
General Purpose Parallel I/O.
GMRE Function
The GMRE function is in charge of providing the hardware support for the GMRE software.
The basic element of the GMRE function is a Embedded Module (EM) used as a daughterboard in the
FLCCONGI/FLCSERV(A) board.
This board supplies several basic hardware components required by the function:
•
•
•
•
Microprocessor (CPU) with L2 cache
System memory (Boot Flash EPROM, RAM)
Serial communication channels
I/O parallel bus bridge interface (PCI).
Additional components related to the GMRE function are present on the motherboard: the physical
interface circuitry supporting the DBG_EM serial communication channels, which is used for debug, and
the interface toward an ATA socket, capable of hosting mass storage devices as hard disks.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The main components related to the GMRE function are:
ED
•
Parallel Bus Interface (PCI)
The FLCCONGI motherboard supports the PCI bus interface as the I/O parallel bus used by
both the OAM and the FLC processors present on the daughterboards to access local
peripheral devices.
•
Ethernet interface
The Ethernet interface of the GMRE daughterboard is used to support the QB_A, QB_B and
IPL interfaces of the FLCCONGI board. The daughterboard interface is a a IEEE 802.3 Fast
Ethernet serial communication channel, suitable for operation at both 10 Mbit/s and 100 Mbit/s.
•
Asynchronous Serial interface
The asynchronous serial interface available from the GMRE daughterboard is used to support
the DBG_EM interface of the FLCSERV(A) board.
It provides a RS–232 asynchronous communication channel for connection to a console, mainly
used for support to software debug activity.
03
3AG 24163 BEAA PCZZA
531
335 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
14.2.2 Control and General Interface Function
The Control and General Interface (CGI) function is in charge of the management of remote alarms, rack
lamps and housekeeping interfaces for the 1678 MCC network element. These interface consist of a set
of specialized parallel (I/O) with certain electrical properties, which are standardized for all NE equipment.
The equipment synchronization is here considered part of the CGI function.
All the circuitry related to the CGI functions hosted on the FLC motherboard. This includes the physical
interfaces toward the front panel connectors. The DC/DC converter provides the –12 V local voltage for
the housekeeping inputs.
14.2.3 DCC Function
The task of the DCC Partsystem is to access and route the information encoded in the DCCs.
The DCC partsystem consists of the DCCs servers (which terminate and insert the D1...D3 and D4...D12
bytes) and of their connection to the I/O boards on one side and to the external LAN on the other side.
The FLCCONGI/FLCSERV(A) is dimensioned to handle the number of DCCR and DCCM as described
in chapter 13.5 ’Controller Subsystem’ on page 224.
14.2.4 External Interfaces
The FLCCONGI supports the serial and parallel external I/O interfaces shown in Figure 181. on page 334.
These interfaces are generally used to support external or system–internal communication as required
by the FLC and CGI functions.
F Interface
The F interface is defined at the equipment level as a local interface to support the craft terminal function
for maintenance and control activities, normally provided by a PC. The physical layer (hardware) of this
interface is implemented as a point to point asynchronous serial channel (UART) with an RS–232 electrical
interface, complying with the F–LTS Alcatel–Lucent standardization requirements.
The main characteristics and operating modes of the F interface protocol, as supported by the FLCSERV
card, are:
–
–
–
–
–
Asynchronous full duplex communication protocol with NRZ data encoding;
8 bits character, 1 stop bit, odd parity;
TX and RX clocks internally generated
Supported baud–rate up to 38400 b/s (9600 b/s specified for F–LTS)
Simplified DCE configuration of the RS–232 control signals set (null modem connection).
The physical access to this interface is provided through a RJ45 on the board front panel.
DBG_DCR and DBG_EM Interfaces
These interfaces are related to the DCR and EM processors, respectively and are intended to support the
communication interface of high level run time SW debug tools.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Both consist of a RS–232 asynchronous serial channel (UART) suitable for local connection to an external
debug terminal (e.g. PC or Work Station) at a data rate of 38.4 kbit/s maximum.
Signals related to these interfaces are available with RS–232 electrical levels on a single 8–pin RJ–45
connector (i.e. the connector is shared between the two interfaces) mounted on the motherboard and
placed in the board’s front panel area.
ED
03
3AG 24163 BEAA PCZZA
531
336 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
USB Interface (currently not supported!)
This interface is planed to be connected to a local craft terminal. It consists of a serial interface compliant
with the Universal Serial Bus specification 1.1, able to support both the 12 Mbit/s (full speed) and the
1.5 Mbit/s (low speed) modes. The physical access to this interface is provided through a standard USB
mini–B receptacle on the board front panel.
LAN_A and LAN_B Interfaces
These interfaces provide a redundant high speed communication channel able to support the Ethernet
protocol IEEE 802.3. They are both used for connection to an external Operation System (OS) station and
are functionally equivalent. The layer–2 protocol functions (MAC controller) for these interface are provided by one on–board LAN switch, which is configured to support either 10BaseT or 100BaseTX connections (automatic selection); the physical layer circuitry (transceivers, line transformers, etc.) is placed on
the motherboard. The physical access to these interfaces is provided through two (one for each interface)
RJ45 on the board front panel.
SY_REF Interface
The ”1678 MCC” Network Element accepts two external timing reference signals; physical access for
these interfaces is placed on the front panel of the FLCSERV and FLCCONGI boards, to provide the redundancy required for this functionality. Timing signals can be a 2.048 MHz clock or a 2.048 Mb/s frame
(E1) in an ETSI environment, or a 1.544 MHz clock or 1.544 Mb/s frame (DS1) in a SONET architecture.
A Sub–D 9–pin female connector, as required for SONET equipments, is used as balanced physical interface for the input/output reference clocks. In ETSI environments, timing references have usually unbalanced (coaxial) connections; this makes necessary to have an external ”adapter” to support also this kind
of physical interfaces. The presence of this adapter is sensed by means of a parallel I/O of ”Spider”. The
different line impedances for both the receiver and the transmitter in the different environments are
matched by the internal circuitry of Line Interface Unit (LIU) itself, which must be configured accordingly
through its SPI interface. The possible configurations are:
–
–
–
100 Ω (T1/J1) balanced interface (on the Sub–D 9–pin female connector)
120 Ω (E1) balanced interface (on the Sub–D 9–pin female connector)
75 Ω (E1) unbalanced interface (a pair of coaxial connectors on the adapter plugged on the
Sub–D connector).
The physical access to this interface is provided through a Sub–D 9 poles female connector (DB9), accessible on the board front panel. Signal levels on this interface are compliant with ANSI T1.102 (FLCSERVA
only) and ITU–T G703 standards.
RL Interface
This interface is intended to drive a number of rack lamps showing a summary of the equipment shelves
status. It provides a standard set of galvanically insulated contacts which can be closed toward the Rack
Lamps ground, or opened, under control of the active FLC. The physical access to this interface is provided
through one Sub–D 9–poles male connector (DB9) on the board front panel.
1AA 00014 0004 (9007) A4 – ALICE 04.10
HK and RA Interfaces
The Housekeeping (HK) interface provides a number of galvanically insulated general purpose inputs and
outputs, whose meaning can be defined by the customer, while the Rack Alarms (RA) interface provides
a number of galvanically insulated output contacts, reporting the status of some equipment–related
alarms. The outputs are realized with electronic switches, which can close or open a contact toward the
independent Housekeeping Output grounds; similarly, the inputs can sense the closure of an external
switch toward the Housekeeping Input ground.
ED
03
3AG 24163 BEAA PCZZA
531
337 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The physical access to these interfaces is provided through a Sub–D 25 poles female connector (DB25),
accessible on the board front panel. The on–board ”Teroldego” CPLD device provides a set of parallel outputs dedicated to the management of the signals belonging the afore mentioned RL, HK and RA interfaces.
14.2.5 Reset Key
The FLC reset key has a multiple functionality, in that:
–
–
–
when pressed once resets the DCR processor,
when pressed twice in a short time resets the EM processor and
when keep pressed (> 3 s) it resets both processors.
The front panel is shown in Figure 58. on page 120.
ED
03
3AG 24163 BEAA PCZZA
531
338 / 531
14.3 First Level Controller and Service Interface (FLCSERV)
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
There are two types of FLCSERV:
–
–
FLCSERV enhanced (for SDH applications)
FLCSERVA enhanced ANSI (for SONET applications).
The FLCSERV(A) board is designed as the hardware platform supporting the First Level Controller (FLC),
the Control and General Interface (CGI) and the Data Communication Channel (DCC) functions for the
1678 MCC Network Element (NE).
These functions are performed by one or two on–board microprocessors (DCR and EM), by a Multi High–
Level Data Link Controller (MHDLC) for the DCC processing and by a Complex Programmable Logic Device (CPLD) which manages the station alarms and signalling (part of the CGI function).
The FLCSERV(A) board is composed of the following blocks (refer to Figure 182. ):
–
–
–
First Level Controller (FLC) function
Service and General Interface (SGI) function (comprises also the synchronization reference interface)
DCC function.
Frontpanel interfaces
SERV
Backpanel interfaces
FLCSERVICE
PH
PH_EXT
DCC Function
SY_REF
AUX
16
Qecc
17
Qecccmx
16
PIO
SY_FR
LAN_A
SGI Function
DBG_DCR
ISSB_1
LCI
F
SYS_ID
USB
FLC Function
IPL
LAN switch
LAN_B
IPL_LAN
DBG_EM
SYNC
DCR
EM
ISSB_2
HDD
SPI_A
SPI_B
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 182. Block Diagram and external Interfaces of FLCSERV(A) enhanced
ED
03
3AG 24163 BEAA PCZZA
531
339 / 531
14.3.1 Equipment Controller Function
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
This function is the same of the FLCCONGI board: refer to para. 14.2.1 on page 335.
14.3.2 Service and General Interface Function
The Service and General Interface (SGI) function is in charge of the management of the phone, phone
extension and service channels interfaces for the 1678 MCC network element. The equipment synchronization is here considered part of the SGI function.
All the circuitry related to the SGI functions hosted on the FLCSERV(A) motherboard. This includes the
physical interfaces toward the front panel connectors.
14.3.3 DCC Function
This function is the same of the FLCCONGI board: refer to para. 14.2.3 on page 336.
14.3.4 External Interfaces
The FLCSERV(A) supports the serial and parallel external I/O interfaces shown in Figure 182. on page
339. These interfaces are generally used to support external or system–internal communication as required by the FLC and CGI functions.
F Interface
The F interface is defined at the equipment level as a local interface to support the craft terminal function
for maintenance and control activities, normally provided by a PC. The physical layer (hardware) of this
interface is implemented as a point to point asynchronous serial channel (UART) with an RS–232 electrical
interface, complying with the F–LTS Alcatel–Lucent standardization requirements.
The main characteristics and operating modes of the F interface protocol, as supported by the FLCSERV
card, are:
–
–
–
–
–
Asynchronous full duplex communication protocol with NRZ data encoding;
8 bits character, 1 stop bit, odd parity;
TX and RX clocks internally generated
Supported baud–rate up to 38400 b/s (9600 b/s specified for F–LTS)
Simplified DCE configuration of the RS–232 control signals set (null modem connection).
The physical access to this interface is provided through a RJ45 on the board front panel.
DBG_DCR and DBG_EM Interfaces
These interfaces are related to the DCR and EM processors, respectively and are intended to support the
communication interface of high level run time SW debug tools.
Both consist of a RS–232 asynchronous serial channel (UART) suitable for local connection to an external
debug terminal (e.g. PC or Work Station) at a data rate of 38.4 kbit/s maximum.
Signals related to these interfaces are available with RS–232 electrical levels on a single 8–pin RJ–45
connector (i.e. the connector is shared between the two interfaces) mounted on the motherboard and
placed in the board’s front panel area.
1AA 00014 0004 (9007) A4 – ALICE 04.10
USB Interface (currently not supported!)
This interface is planed to be connected to a local craft terminal. It consists of a serial interface compliant
with the Universal Serial Bus specification 1.1, able to support both the 12 Mbit/s (full speed) and the
1.5 Mbit/s (low speed) modes. The physical access to this interface is provided through a standard USB
mini–B receptacle on the board front panel.
ED
03
3AG 24163 BEAA PCZZA
531
340 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
LAN_A and LAN_B Interfaces
These interfaces provide a redundant high speed communication channel able to support the Ethernet
protocol IEEE 802.3. They are both used for connection to an external Operation System (OS) station and
are functionally equivalent. The layer–2 protocol functions (MAC controller) for these interface are provided by one on–board LAN switch, which is configured to support either 10BaseT or 100BaseTX connections (automatic selection); the physical layer circuitry (transceivers, line transformers, etc.) is placed on
the motherboard. The physical access to these interfaces is provided through two (one for each interface)
RJ45 on the board front panel.
SY_REF Interface
The ”1678 MCC” Network Element accepts two external timing reference signals; physical access for
these interfaces is placed on the front panel of the FLCSERV and FLCCONGI boards, to provide the redundancy required for this functionality. Timing signals can be a 2.048 MHz clock or a 2.048 Mb/s frame
(E1) in an ETSI environment, or a 1.544 MHz clock or 1.544 Mb/s frame (DS1) in a SONET architecture.
A Sub–D 9–pin female connector, as required for SONET equipments, is used as balanced physical interface for the input/output reference clocks. In ETSI environments, timing references have usually unbalanced (coaxial) connections; this makes necessary to have an external ”adapter” to support also this kind
of physical interfaces. The presence of this adapter is sensed by means of a parallel I/O of ”Spider”. The
different line impedances for both the receiver and the transmitter in the different environments are
matched by the internal circuitry of Line Interface Unit (LIU) itself, which must be configured accordingly
through its SPI interface. The possible configurations are:
–
–
–
100 Ω (T1/J1) balanced interface (on the Sub–D 9–pin female connector)
120 Ω (E1) balanced interface (on the Sub–D 9–pin female connector)
75 Ω (E1) unbalanced interface (a pair of coaxial connectors on the adapter plugged on the
Sub–D connector).
The physical access to this interface is provided through a Sub–D 9 poles female connector (DB9), accessible on the board front panel. Signal levels on this interface are compliant with ANSI T1.102 (FLCSERVA
only) and ITU–T G703 standards.
PH Interface (not supported)
The PH interface allows to connect an external telephone handset, which will receive both the power supply (about 12 V, internally limited to 18 mA max.) and the analog audio, on a two–wire interface with an
impedance of 600 Ω. The receive (from the unit toward the external phone) and transmit audio (from the
phone toward the equipment) are internally separated by an on–board hybrid circuit which routes the two
audio channels to a dedicated audio processor for the analog/digital conversion. This latter is controlled
by the AUX manager FPGA ”Aton”, which selects the AUX channels bytes that will be used for the EOW.
The audio volume, both in the TX and in the RX directions, can be varied in a range of about 20 dB by
means of a digital potentiometer connected as a slave device to the on–board SPI manager ”Spider”.
Physical access to this interface is provided through a Bantam jack on the unit front panel.
1AA 00014 0004 (9007) A4 – ALICE 04.10
PH_EXT Interface (not supported)
For applications needing separate access for the transmit and receive audio of the EOW, the FLCSERV
unit supplies the PH_EXT four–wire interface. On this interface no DC power is available for the external
devices, being it galvanically insulated from the motherboard by means of transformers; both the TX and
RX audio connections have a nominal impedance of 600 Ω and, like for the PH interface, are connected
to a dedicated audio processor for the analog to digital conversion, controlled by the ”Aton” FPGA. The
audio volume, both in the TX and in the RX directions, can be varied in a range of about 20 dB by means
of a digital potentiometer connected as a slave device to the on–board SPI manager ”Spider”. The physical
access to this interface is provided through a RJ11 connector on the unit front panel.
ED
03
3AG 24163 BEAA PCZZA
531
341 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
SERV Interface
(not supported)
The AUX channels data going through the ”ATON” FPGA can be made available at the front panel SERV
interface as general digital streams, having various bit rates and reference standards. On the FLCSERV
unit there are two 64 kb/s V.11, two RS–232, two 2 Mb/s and two 64 kb/s G.703 interfaces, managed by
the ”ATON” FPGA.
The physical access to the SERV interface is provided through a front panel SCSI 26–pin female connector
and two couples of 1.0/2.3 75 coaxial connectors carrying the 2 Mb/s interfaces.
14.3.5 Reset Key
The FLC reset key has a multiple functionality, in that:
–
–
–
when pressed once resets the DCR processor,
when pressed twice in a short time resets the EM processor and
when keep pressed (> 3 s) it resets both processors.
The front panel is shown in Figure 57. on page 119.
ED
03
3AG 24163 BEAA PCZZA
531
342 / 531
14.4 Power Supply and Filter Board (PSF)
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
In the 1678MCC equipment two PSF boards are mandatory.
14.4.1 Main Characteristics
The main function of this board is to carry the Battery Voltage from the TRU (Top Rack Unit) to the
backplane thus guaranteeing the main power supply (voltage) to the boards making up the subrack.
It also supplies the Service Voltage (3.6 V) to all the boards.
The board block diagram is illustrated in Figure 183. on page 345 where are shown the following
functionalities (two sub–boards are assembled to obtain a PSF board):
•
the sub–board 1 provided with the following circuits:
–
EMI Filter: it is necessary to reduce the battery noises; the noises are rejected by the
DC/DC converters present on all the boards.
–
OC and OV protections: each battery wire is protected against overcurrents and
short–circuits by means of a fuse, while the protection against overvoltage is realized by
means of varistors.
–
Fuse Fault Detectors: it is realized with circuits situated after the fuses detecting the
battery voltage failure.
–
Battery Failure Detector: it is realized with a circuit situated before the fuses.
–
Input Power Stage: this circuit is used to power supply the DC/DC converter that
generates the service voltage for the whole subrack; it consists of a filter to reduce the
noises, a protection fuse against short–circuits with relevant fault detector and of an inrush
current limiting circuit.
•
the sub–board 2 provided with the following circuits:
–
48 V to 3.6 V DC/DC Converter
–
Service Voltage Undervoltage Detector
–
SPIDER block
–
Remote Inventory block
14.4.2 Electrical Interfaces
1AA 00014 0004 (9007) A4 – ALICE 04.10
The main electrical interfaces are:
ED
•
Battery Voltage on the front panel: it can be received through the 3–pin power male connector;
the female pole is dedicated to the mechanical ground; the battery can absorb a max of 30 A.
•
Backplane Battery Voltage: it is received through a 8–pin female connector; three battery
branches are available (10 A per branch), each branch is protected with a 30 A fuse.
•
Incoming 3.6 V Service Voltage: it is received (V3V_A_IN) from the other PSF board present
in the 1678MCC equipment; the typical absorbed current is 25 mA.
•
Alarms and signaling: the following signaling are available:
–
Lamp Test (output), through a switch on the front panel:
switch pressed=GND, switch released=high impedance.
Note: a pull–up resistor is provided at the input on the FLCCONGI.
–
Converter Synchronization (input, ALMSYNC): TTL compatible levels.
–
Slot ID (input, SLOT_ID_0): TTL compatible levels.
–
Alarm indicating 3.6 output voltage failure or voltage lower then 3.6 V (output,
V3V_A_OUT):
Alarm status: it is activated when the output voltage is lower than 3 V.
03
3AG 24163 BEAA PCZZA
531
343 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
–
–
–
Alarm Absence status: it is activated when the output voltage is higher than 3 V.
Board Missing (output): it indicates the circuit presence by means of a GND contact; one
contact indicates the presence/absence of this board to the Matrix and another contact
indicates the presence/absence of this board to the FLC.
Battery Voltage Failure alarm (output, BATT_FAIL):
Alarm status: it is activated when the Battery voltage is lower than 37 V.
Alarm Absence status: it is activated when the Battery voltage is higher than 37 V.
Note: a pull–up resistance has to be provided towards a positive voltage (3.3 V).
Broken Fuse Alarm (output, BROKEN_FUSE):
Alarm status: it is activated when at least one of the six fuses situated in series of wires
leading the battery to the backplane is broken.
Alarm Absence status: no fuse is broken.
Note: a pull–up resistance has to be provided towards a positive voltage (3.3 V).
SPI Bus: four wires are envisaged for path A and four for path B.
On board a bicolor LED is present to show:
•
•
Green: board in service
Red: internal fault (board out of service)
1AA 00014 0004 (9007) A4 – ALICE 04.10
The front panel is shown in Figure 61. on page 123.
ED
03
3AG 24163 BEAA PCZZA
531
344 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
PSF
Sub_unit 1
OC and OV
Protections
EMI Filter
GNDM
INPUT POWER
STAGE (60W)
Battery
Failure
Detector
Fuses Fault
Detectors
GNDM
Sub_unit 2
48Vcc
3,6V
SPIDER
R.I.
Slot ID
UV Detector
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 183. PSF Functional Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
345 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
14.5 Bus Termination Board (BUSTERM)
This board gives the electrical termination to buses routed on the backplane and also to provide the LCI
interface.
In the 1678MCC equipment two BUSTERM boards are mandatory.
They are allocated behind the FLCSERV(A) and FLCCONGI boards (they are inserted into the backpanel
directly; these two boards are not visible on shelf front–panel).
14.5.1 Functional Description
The board takes on board networks to adapt all the signal buses of 1678MCC backplane, that are:
•
•
•
ISPB bus
ISSB/ISSB2 bus
JTAG chain.
It also gives adaption to six 2 MHz lines (CK2M_x), two 1 Hz lines (1HzSYNC) and the power sync line
(ALMSYNC).
Furthermore, a LCI interface is present: this is the serial link between the FLC function and a serial
non–volatile memory (EEPROM) where the equipment local configuration and the MAC address data are
stored.
The bus termination board is powered by V3VA, V3VB lines coming from backpanel; these are used to
create all needed voltages within the board.
Spider and alarm control circuits are supplied by 3.3VS; data information concerning the board is stored
in a remote inventory EEPROM, while another roomier EEPROM contains the MAC address data and the
equipment local configuration.
Figure 184. on page 347 displays the block diagram of the board.
ISPB bus is the communication way between uP and the ASICs of equipment, while ISSB/ISSB2 buses
are used to connect the main FLC with the SLC hosted in the matrix board. All buses, JTAG chain included,
need double termination, one at each end: this goal is reached by inserting in the backpanel two
BUSTERM boards.
On the BUSTERM is placed a FPGA called Spider to manage SPI buses. SPI is a low speed serial
communication channel used by SC to transfer data to/from serial devices on different boards in the shelf.
Spider is connected to two SPI buses, one connected to matrix–A and one to matrix–B: it reads the
identification (ID) slot from backplane, manages remote inventory and collects power supply alarms.
On the board is mounted an EEPROM with a serial protocol called remote inventory interfaced to Spider.
This memory stores data information regarding the board as code, version, series and so on.
1AA 00014 0004 (9007) A4 – ALICE 04.10
LCI interface
It is the serial link between the FLC function and a serial EEPROM, placed on this board, where the
equipment local configuration and the MAC address data are stored.
The buffer before memory acts as MUX, since lines FLC_ACT_A and FLC_ACT_B enable control lines
toward FLCSERV(A) board or control lines toward FLCCONGI board.
ED
03
3AG 24163 BEAA PCZZA
531
346 / 531
14.5.2 Power Supply Control and Alarms
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Dedicated circuits check the presence of voltages on the board. This part generates internal alarms to FLC
(CFAIL and CMISS).
On board a bicolor LED is present to show:
•
•
green: unit in service
red: internal fault (unit out of service)
BUSTERM
6
ID
3+1
E
E
P
R
O
M
SPIDER
SPIA
SPIB
3+1
TRESHOLD
VOLTAGE
GENERATOR
(1.5V)
OSC (4 MHz)
ISPB
ISSB
ISSB2
JTAG
25
2
2
4
2 MHz CLK
1 Hz SYNC
ALMSYNC
6
2
TERMINATIONS
ADAPTION
10
LCI I/F
EEPROM
POWER LINES AND ALARMS
2
V3VA,V3VB CFAIL_BT
CMISS CMISS_BT
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 184. BUSTERM Functional Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
347 / 531
14.6 Matrix 640 Gbit/s Board
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
There are two types of Matrix 640Gbit/s:
–
Matrix 640Gbit/s enhanced (MX640)
This board is used for SDH applications.
–
Matrix 640Gbit/s advanced (MX640GA)
This board is used for SONET applications.
14.6.1 Functional description
14.6.1.1 Overview
The board MATRIX 640 Gbit/s provides SONET/SDH switching capabilities, implementing MSPC
(Multiplex Section Protection Connection) and HPC (Higher Order Path Connection) switching functions.
The 1678MCC equipment can host up to two Matrix boards; in this case, only one Matrix board at a time
is active, the other one is standing by.
The Matrix board supports the following functionalities:
•
Cross–connection with STS–1 granularity of up to 4096 STM–1 signals (12288 signals at AU3
level), non blocking
Synchronization (Clock Reference Unit)
Shelf Controller (SC)
1+1 EPS protection scheme (when two MX640 boards are present)
•
•
•
14.6.1.2 Features
The Matrix board address the following functional requirements:
•
•
•
•
•
•
•
Management of 256 bi–directional links @ 2.5/2.7 Gbit/s (for an overall capacity of 640 Gbit/s)
Forward Error Coding (FEC) protection of the 256 links through the backpanel
Payload Performance Monitoring (PM)
Traffic SubNetwork Connection Protection (SNCP)
Clock Reference Unit (CRU) of SDH quality – MX640
Clock Reference Unit (CRU) of SONET STRATUM 3 quality – MX640GA
Shelf Controller (SC)
1AA 00014 0004 (9007) A4 – ALICE 04.10
A functional block diagram with indication of main internal and external interfaces is shown in
Figure 185. on page 349.
For further details about how the MSPC and HPC functions are implemented from a logical point of view
to fulfil the ITU–T G.783 functional model.
ED
03
3AG 24163 BEAA PCZZA
531
348 / 531
Synchronization
Signals
Port Payload Links
High
Order
Matrix
Control Signals
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
MX640
Shelf
Controller
SDH/SONET
Equipment
Clock
Power
Supply
Figure 185. Matrix Board Functional Block Diagram
14.6.2 Physical Description
14.6.2.1 Overview
The board is made up of a main board and a daughter board, the PQ2/SCM (PowerQUICC2 / Shelf
Controller Module), which hosts the Shelf Controller and the ISPB bus master.
The front panel of the board provides access to the debug interface of the PQ2/SCM, to the Shelf Controller, to the PQ2/SCM processor reset button, and is provided with one multicolor LED. This LED can emit
light of three different colors, with the following meanings:
•
•
•
Red color: internal failure (board out of service)
Green color: board in–service
Orange color: board stand–by
In following paragraphs, details of different subsystems implementation will be provided.
14.6.2.2 Payload Subsystem Description
Payload Subsystem Logical and Physical High–level Description
The logical flow of traffic signals is shown in Figure 186. on page 349.
MX640(GA)
1AA 00014 0004 (9007) A4 – ALICE 04.10
MSnP + Sn
Figure 186. Payload Subsystem Logical Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
349 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The physical flow of traffic signals is shown in Figure 187. on page 350.
The board hosts four ASICs (GA #0 to GA#3). Each GA is capable to interface 66 2.5 Gbit/s links. Of these
66 links, only 64 are used in the board. Therefore, each of the four GA, as implemented on the board, is
capable to process 1024 STM–1 equivalent signals, to the required total of 4096 STM–1 equivalent
capacity.
Since the GAs (GA #0 to GA #3) work in bit slice mode, each GA process 2 out of 8 bits of the payload;
therefore, no payload interfaces between the GAs are needed.
The GA is able to protect the traffic coming from/going to the Port boards using FEC. In this case, because
of the redundancy the frequency of the signal is 10/9 of the SDH standard STM–16, that is 2.7 Gbit/s.
Each GA (GA #0 to GA #3) extracts/inserts some overhead information from/into the backpanel links. This
information is then transmitted/received by the GA #5 and GA #6 through two bi–directional 622 Gbit/s
links for each GA #0 to GA #3, as shown in Figure 187. on page 350.
The information is then processed by GA #5 regarding path criteria, alarms, PM and remote criteria and
by GA #6 concerning section and path protection.
MX640(GA)
GA #0
PQ2/SCM
GA #4
2.5 Gb/s links to /from Backpanel
(PM collection)
GA #1
GA #5
(Path criteria,
alarms, PM and
remote criteria)
GA #2
GA #6
(Section and
Path protection)
1AA 00014 0004 (9007) A4 – ALICE 04.10
GA #3
Figure 187. Payload Subsystem Physical Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
350 / 531
14.6.2.3 Power Subsystem Description
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The power subsystem is shown in Figure 188. on page 351.
The main power characteristics (actual currents and efficiencies) are reported in Table 47. on page 352.
1.2 V
To GA#0
DC/DC
On
1.2 V
To GA#1
DC/DC
On
48 V Battery A
1.2 V
To GA#2
DC/DC
Inrush
Current
Limiter
On
48 V Battery B
1.2 V
To GA#3
DC/DC
Delay
On
1.8 V
DC/DC
On
To GA#0,#1,#2,#3 and
FPGAs
1.5 V
To FPGAs
2.5 V
To FPGAs and
other logic
DC/DC
On
To Spider, LEDs
and other Service
powered logic
Service 3.6 V A
3.3 V
VREG
1.8 V
To FPGAs Hi –
Speed macros
VREG
2.5 V
To FPGAs Hi –
Speed macros
To on –board
logic
Service 3.6 V B
To GTL buffers
VREG
1.5 V
To OCXO
VTT for GTL
terminations
Note: GAs in Payload subsystem
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 188. Power Subsystem Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
351 / 531
Table 47. Power characteristics
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
DC/DC voltages, current and power
Voltage [V]
Current [A]
Power [W]
3.3
5
18
2.5
1.3
3.25
1.8
1.8
3.24
1.5
4
6
1.2
11.6
13.92
Regulators voltages, current and power
Voltage [V]
Current [A]
Power [W]
2.5
1.4
3.5
1.8
0.2
0.36
Power consumption and overall efficiency
Voltage [V]
Current [A]
Power [W]
38.4
2.8
108
48
2.2
108
72
1.53
111
14.6.2.4 Timing Subsystem Description
The Matrix board has two main synchronization sources.
One is the Clock Reference Unit (CRU), which provides the main SDH/SONET timing reference for the
whole equipment. The second is the PQ2/SCM Shelf Controller module, which provides the clocks for the
control interfaces.
In the following, each timing subsystem will be specified.
Clock Reference Unit
1AA 00014 0004 (9007) A4 – ALICE 04.10
For SDH applications (MX640) the CRU is implemented in the GA #7 with the aid of an external OCXO.
For SONET applications (MX640GA) the CRU is implemented in the GA #8 with the aid of an external
OCXO.
The GA #8 is specific for the MX640GA (SONET applications) and has the following SONET specific functions:
•
Select a reference clock (from the T1 and DS–1 inputs) as configured by SC
•
Alarm handling for DS–1 inputs
•
Hold off time handling
•
SSM extraction on DS–1 inputs.
When the equipment hosts two Matrix boards, one CRU is master and the other is slave. The slave CRU
must closely track the master CRU both in frequency and in phase. To this goal, the two CRUs must
exchange some synchronization signals.
The connections of the CRU on the board are shown in Figure 189. on page 353 for SDH and in
Figure 190. on page 354 for SONET applications.
ED
03
3AG 24163 BEAA PCZZA
531
352 / 531
BACKPANEL
To other on on–board logic
VCXO
622 MHz
622 MHz
MATRIX B
2 MHz
2 Mb/s
Clocks to
FLCCONGI
F(s)
2 MHz
2 Mb/s
DTOUT_EC
CKOUT_ES
CKOUT_EC
DTOUT_ES
OUTSD_N_10S
OUTSD_P_10S
Clocks to
FLCSERV(A)
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
MATRIX A
PHOFSIN
∆ϕ
PHOFSOUT
CK622
SY1HZ_IN
SY_1HZIN
:8
CK38CRU
CK_77S
SY_1HZOUT
SY_1HZOUT
FR2MIN
CK38A,
SYNCA
To other on on–board logic
FR2MOUT
CK38,
SYNC38
CK_H O_IN
CK_HO_IN
CK_HO_BIDIR
CK_HO_BIDIR
CK_2EXT
2 MHz
2 Mb/s
CKINEC
DIN_EC
VIOL_EC
2 MHz
2 Mb/s
CKINES
DIN_ES
VIOL_ES
FLCCONGI FLCSERV(A)
GA #7
CKINEC
DIN_EC
VIOL_EC
Clocks from Clocks from
IRQ6_SY1SEC
CK_2EXT
Six 2 MHz
CK10S
Clocks from
Ports
To GA #5 on PQ2/SCM
FR2MIN
FR2MOUT
To Backpanel
OCXO
10 MHz
To Upper
CK51CRU
And lower
FAN Units
CKOUT1
GA #3
PHOFSIN
PHOFSOUT
CKINES
DIN_ES
VIOL_ES
GA #7
Figure 189. CRU, On– and Off– Board Connections in SDH Applications
The CRU T0 and T4 PLL can lock either on the local OCXO, on any of the 2 MHz clocks coming from the
port boards, on the 2 MHz / 2 Mbit/s or 1.544 Mb/s clocks coming from the FLCSERV(A) and FLCCONGI
or on the second CRU, if present.
Then the clock system:
•
Locks a 622 MHz VCXO on the chosen primary reference. This 622 MHz clock is then
distributed on board to all SDH processing logic.
Derives from the 622 MHz clock a 38 MHz clock and 125 ms synchronism signal to be
distributed on board to all SDH processing logic and through the backpanel to every payload
processing board as the main synchronism reference.
Provides the T4 2 MHz / 2 Mbit/s (or 1.544 Mb/s) reference clocks to the FLCSERV(A) and
FLCCONGI.
Provides the 1 second synchronization signal to GA #4 on PQ2/SCM.
1AA 00014 0004 (9007) A4 – ALICE 04.10
•
•
•
ED
03
3AG 24163 BEAA PCZZA
531
353 / 531
BACKPANEL
PQ2/SCM Module
The PQ2/SCM module provides the timing references (clocks and signals) necessary to the Control subsystem.
MATRIX A
VCXO
622 MHz
1.544 MHz
1.544 Mb/s
Clocks to
FLCCONGI
622 MHz
To other on on–board logic
CK_77S
:8
∆ϕ
CKOUT_ES
DTOUT_ES
CKOUT_EC
DTOUT_EC
CK622
OUTSD_P_10S
OUTSD_N_10S
F(s)
CK38CRU
MATRIXB
1.544 MHz
1.544 Mb/s
Clocks to
FLCSERVA
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The GA #3 is included in the 622 MHz loop because the FPGA in which GA #7/GA #8 is implemented does
not provide high–frequency interfaces. Therefore, the GA #3 divides the clock by 8 before feeding it to
GA #7/GA #8.
The GA #3 then requires a complex clock system, also comprising a second PLL at a frequency of
691 MHz to support FEC.
PHOFSIN
PHOFSIN
PHOFSOUT
PHOFSOUT
SY_1HZIN
SY1HZ_IN
SY_1HZOUT
To Upper
And lower
Fan Units
CKOUT1
CK51CRU
CK38A,
SYNCA
CK_HO_IN
Clocks from
FLCCOPNGI
CKINES
DIN_ES
VIOL_ES
TO3, TO5
2x1.544MHz
TO2, TO9
I13
I12
T4 PLL
CK_2EXT
T0 PLL
FR2MIN
I11
Div
1AA 00014 0004 (9007) A4 – ALICE 04.10
SONET/SDH
MASTER/SLV
TO10
FR2MOUT
GA #8
OCXO
12.8 MHz
Ports
Sel & Div
CKINES
DIN_ES
VIOL_ES
2x77.76MHz
Clocks from
Div
CKINEC
DIN_EC
VIOL_EC
FLCSERVA
+2
CKINEC
DIN_EC
VIOL_EC
Clocks from
To Backpanel
1.544 MHz
1.544 Mb/s
Fr
CK_HO_BIDIR
1.544 MHz
1.544 Mb/s
CK38,
SYNC38
To other on on–board logic
CK_HO_IN
spare
CK_HO_BIDIR
Six 2 MHz
GA #3
SY_1HZOUT
CK_2EXT
FR2MIN
FR2MOUT
GA #8
IRQ6_SY1SEC
To FALCO on PQ2/SCM
Figure 190. CRU, On– and Off– Board Connections in SONET Applications
ED
03
3AG 24163 BEAA PCZZA
531
354 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
14.6.2.5 Control Subsystem Description
PQ2/SCM Module
The PQ2/SCM module provides the control interfaces and Figure 191. on page 356 shows their connections. They are detailed in the following paragraphs:
ED
•
Spider SPI Bus
The Spider block on the board can be controlled both via the local Spider bus driven by the
PQ2/SCM or via the remote Spider bus coming from the second Matrix board.
•
Remote Inventory: the Remote Inventory EEPROM can be accessed via SPI through
Spider in transparent mode; the EEPROM is connected to Spider Chip Select #0.
•
SPI Temperature Sensor: the SPI Temperature Sensor EEPROM can be accessed
via SPI through Spider in transparent mode; the Temperature Sensor is connected
to Spider Chip Select #1.
•
GA #9 CMISS and ID Bus
The GA #9 is used to serialize the Board Missing (CMISS) and local board Identification codes
(ID) towards the PQ2/SCM, to reduce the pin count of the PQ2/SCM connectors. The CMISS
data is used by the microprocessor to know which boards are present in the shelf. The ID data
is used by the microprocessor to know the Matrix board board version, the equipment type, the
shelf ID, etc.
•
FPGA Download Bus & Hardware Configuration Bus
This bus is used to download the local GA #5, GA #6 and GA #7/#8 on the board and to download/upgrade the remote FPGA on the other boards. This is a serial bus; the local signal levels
are CMOS, while the GTL electrical standard is used to communicate with the other boards in
the shelf.
•
ISSB Bus
This bus is multi–master backplane serial bus providing the physical connection between
boards in the same shelf. The bus uses the GTL electrical standard.
•
ISPB Bus
This bus is a parallel bus through which the microprocessor on the PQ2/SCM module can access the internal registers of ASIC or FPGA devices placed on the various boards in the shelf
which provide ISPB access.
•
I2C Bus
This is a serial bus used locally on the board to read the temperature sensors and to control the
on / off status of the outputs of the ISPB clock distribution logic.
•
IPL Bus
This bus is a 2 wire serial communication channel communication channel used by the
PQ2/SCM of a protected pair of Matrix boards to keep their configuration and status data
aligned each other.
•
ACT / OPE Active / Operative Status Management Logic
The two Matrix boards exchange some signals to decide which board is the active master.
•
Debug Interface
The PQ2/SCM provides a standard serial interface for debugging purposes. The interface is
accessible from a connector on the front panel (only for Alcatel–Lucent service persons).
03
3AG 24163 BEAA PCZZA
531
355 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
•
LAN Interface.
Two LAN interfaces of the PQ2 are transformed on the main board with transceivers to Ethernet
standard.
In case of LX160 (LO matrix of the LO extension shelf) the software image download and the
controlling from the main shelf (FLCSERVICE and FLCCONGI) will be done by using this connections. The interfaces support 10 Mbps and 100 Mbps Ethernet standard (10/100BASE–T).
•
Reset Management.
•
Interrupt Management.
From / To all
boards
From / To
other Matrix
To / From
Ports and
FLCSERV(A)
T Sensor
SPI bus
2 x LAN
I2C bus
IPL bus
Debug
ISSB bus
CFG bus
DMUX
MUX
PQ2/SCM
ID bus
CMISS bus
ACT / OPE
ISPB bus
GTL BUFFER
To / From
Ports and
other Matrix
T Sensor
SPIA
SPIDER
GTL BUFFER
To/From other
Matrix and to
FLCCONGI and
FLCSERV(A)
BUFFER
From / To
other Matrix
SPIB
From / To
other Matrix
GA #0
GA #7/#8
GA #9
GA #1
GA #5
GA #2
GA #6
GA #3
MX640 (GA)
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 191. PQ2/SCM Control Interfaces
ED
03
3AG 24163 BEAA PCZZA
531
356 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
14.6.2.6 Self Diagnosis Subsystem Description
Fuse, Battery and Undervoltage Alarms
The board has the capability to monitor the presence of both batteries A and B, the fuse status and to detect
a DC/DC or voltage regulator output undervoltage condition.
These alarms are all collected by Spider block. However, there is also a visual indication through 16 LEDs
on the back of the board, under the shield.
The undervoltage alarms are also collected.
Temperature Sensors
The board hosts three temperature sensors.
One is controlled via SPI bus and is able to give only its temperature. The other two are controlled via I2C
bus and are able to read their own temperature as well as the temperature of some remote components.
14.6.2.7 Parallel I/O description
Board LEDs
The board has a one front panel light. The light is generated by a dual LED. The color can be green, red
or a combination of the two (orange).
Spider ASIC Parallel I/Os
The Spider ASIC is used to control several board I/Os (four lines)
PQ2/SCM Parallel I/Os
The other board I/Os are controlled by PQ2/SCM general purpose I/Os.
14.6.2.8 External Interfaces Description
The external interfaces are splitted in:
•
•
•
•
High–Frequency Backpanel Signals
Low–Frequency Backpanel Signals and Power Supply Lines
Debug Front Panel Connector Signals
LAN Front Panel Connector Signals
14.6.2.9 Mechanical Design Description
The Matrix board is 8TE wide, 440 mm x 210 mm.
The front panel is shown in Figure 59. on page 121.
14.7 Matrix 320/160 Gbit/s Enhanced Board (MX320 / MX160)
The functional and physical descriptions of the MX320 and MX160 boards are similar to the MX640 board.
Only the switching capacity is different.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The following types exists:
–
Matrix 320Gbit/s enhanced (MX320)
This board is used for SDH applications.
–
Matrix 320Gbit/s advanced (MX320GA)
This board is used for SONET applications.
–
Matrix 160Gbit/s enhanced (MX160)
This board is used for SDH applications.
ED
03
3AG 24163 BEAA PCZZA
531
357 / 531
14.8 Lower Order Adaptation and Matrix 40G and 20G (LAX40 and LAX20)
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The LAX board is used in the 1678MCC Main Shelf partsystem which is introduced in 1678MCC. The main
purpose of this new partsystem is to build a 4/3/1 Crossconnect designed for the ETSI and ANSI Market.
The LAX board implements the lower order matrix together with the so called adaptation function (higher
order path termination and adaptation function), refer to Figure 192.
14.8.1 Lower Order Matrix
The lower order matrix is a square matrix. Switching is performed at VC–3 and VC–12 level in SDH application and VC–11 for SONET applications.
One LAX40 board has a capacity of 40Gb/s and is always 1+1 protected.
One LAX20 board has a capacity of 20Gb/s and is always 1+1 protected.
14.8.2 Lower Order Adaption Function
The lower order adaption function is located between the interface to HO subsystem and the matrix function (refer to Figure 192. ). In other words these chips terminate the administrative units AU4 of an STM–64
byte serial stream in receive direction into lower order VC–n and multiplexes lower order VC–n in transmit
direction into the administrative units AU4 of an STM–64 byte serial stream.
The lower order adaption function supports fault detection, alarm generation and performance monitoring
for higher and lower order.
The chip set of this function is furthermore SONET compliant. For instance the chips are capable to terminate administrative units AU3 and to process virtual tributaries VT1.5. The chips additionally support
AU3/AU4 conversion. These functionalities are used for SONET and SDH/SONET interworking.
LAX40
1AA 00014 0004 (9007) A4 – ALICE 04.10
Backplane
LO Adaptation
and Monitoring
Interface
to HO
Subsystem
Matrix
Figure 192. LAX40 Functional Overview
ED
03
3AG 24163 BEAA PCZZA
531
358 / 531
Data Connections
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The data connections between higher order matrix and the lower order matrix board are done via differential signal lines over the backplane at 2.5 Gb/s .
Synchronization and Clock Distribution
The LAX board receives two 38 MHz clock signals (Copy_A and Copy_B) and two 38MBit/s data signals
(Copy_A and Copy_B). These synchronization signals are led to VIVALDI ASIC, which performs the synchronization function. The data signal comprises frame and multiframe information (1Hz/8kHz) to synchronize the board to the 1678MCC internal framing. The data signal is read by the 38 MHz clock. The
38 MHz clock is also used to generate the 622 MHz system clock by means of a VCO.
A frame generator provides the required 1 Hz, 2 kHz and 8 kHz frame and synchronization signals for the
LAX board.
Power Subsystem
There are two independent power interface inputs, each coming from a PSF board.
On the LAX board there are four central DC/DC converters (48 V to 1.2/5 V) and four point of load (POL)
converters (5 V to 1.5/1.8/2.5/3.3 V). An inrush current limitation circuit and a filter are provided in front
of the central DC/DC converters for current limitation when the board is plugged in. A central DC/DC power
converter provides a galvanically isolated power (5 V) to the POL converters. The POL converters deliver
the various voltages:
–
–
–
–
1.5 V
1.8 V
2.5 V
3.3 V
used by the ASICs and FPGAs on the LAX board.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The front panel is shown in Figure 60. on page 122.
ED
03
3AG 24163 BEAA PCZZA
531
359 / 531
Cardpresent
SlotID
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
CLK 155
1.2 V, 2.5 V
#4 [#2 (LAX20)]
#1
TUPP
32 x 2.5 GBPS
VIVALDI
Matrix
16x2.5GBPS
STM−16
Copy A/B
Sync. A+B
AdaptationF unction
VCXO
622MHz
Clock
Clk A+B
CLK 155
1/4
Divider
ISPB
CF
from HO
Int
MOT
Sync.
Ctrl
1.2 V, 2.5 V
WSE−40
WSE−20 (LAX20)
SLC A/B
MatrixF unction
CLK 155
Sync.
16x2.5GBPS
STM−16
OHBus
MOT
Sync. MOT
Int
Ctrl
Sync.
Slot_ID
CPLD
Int.
[5..0]
SYSID
Sync.
PMIF
Spare
PQ2/SCM
ISSB_1
links
ISPBlocalbus
AMSEL1
PS interface
ISSB_2
RAM
LAN
to Partner
Debug
LAX40
(LAX20)
HW_CFG
HW_CFG
GOBLIN
FEPROM
&
SPI A
SPI B
Service
RI
&
Ctrl
GPIO
3.3 V
2.5 V
1.8 V
1.5 V
1.2 V
Power
Filter
DC/
DC
Ctrl
Power
Manager
Temp.
A, B +
A, B −
FPE
1AA 00014 0004 (9007) A4 – ALICE 04.10
3.3 V
Figure 193. LAX40 (LAX20) Board Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
360 / 531
14.9 STM–64 traffic Port Boards with not pluggable MSA Modules
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
14.9.1 Introduction
In the 1678MCC equipment several types of STM–64 interfaces are available with different
implementation on board (one, two or four optical interfaces). The optical MSA modules are not pluggable,
they are fixed on the board.
The following description covers all different items equipped. The same motherboard can support the
following modes using different equipping options:
•
•
•
•
•
•
•
•
•
4 x I64.1 optical interfaces
2 x I64.1 optical interfaces
1 x I64.1 optical interface
4 x S64.2 optical interfaces
2 x S64.2 optical interfaces
1 x S64.2 optical interface
1 x L64.2 optical interface
1 x V64.2 optical interface
1 x U64.2 optical interface
(P4I64)
(P2I64M)
(I–64.1M)
(P4S64)
(P2S64)
(S–642M)
(L–642M)
(V–642M)
(U–642M).
14.9.2 Functional Description
14.9.2.1 Overview
The STM–64 board provides optical interface for one, two or four tributaries at STM–64 rate for Short, VSR
(Intra–office), Long, Very Long and Ultra Long connections. It also contains circuitry for management,
configuration, and control of on–board devices through backplane SPI, ISPB and Hardware &
Configuration buses.
14.9.2.2 Main Features
The main features of STM–64 board are shown in the following.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The STM–64 boards are composed of a single PCB supporting various modes based on the mounting
options. Depending on the optical devices, there are different modes as mentioned.
The board has always GA #1, GA #2 and GA #3 (and GA #4 when are mounted four optical interfaces)
as common devices in the data path, for all the modes (refer to Figure 194. on page 362):
ED
•
The P4S64M board
–
4 x S–64.2 (P4S64) has four S–64.2b optical modules and its associated circuitry.
–
4 x I–64.1 (P4I64) has four I–64.1 optical modules and its associated circuitry.
•
The P2S64M board
–
2 x S–64.2 (P2S64) has two S–64.2b optical modules and its associated circuitry.
–
2 x I–64.1 (P2I64M) has two I–64.1 optical modules and its associated circuitry.
•
The S64M board
–
1 x S–64.2 (S–642M) has one S–64.2b optical module and its associated circuitry.
–
1 x L–64.2 (L–642M) has one L–64.2 optical module and its associated circuitry.
–
1 x V–64.2 (V–642M) has one V–64.2 optical module and its associated circuitry.
–
1 x U–64.2 (U–642M) has one U–64.2 optical module and its associated circuitry.
–
1 x I–64.1 (I–64.1M) has one I–64.1 optical module and its associated circuitry.
03
3AG 24163 BEAA PCZZA
531
361 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
S64.2
I64.1
GA #3
S64.2
I64.1
GA #2
GA #1
GA #2
GA #1
GA #2
GA #1
S64.2
I64.1
GA #4
S64.2
I64.1
Equipping option of P4S64M
S64.2
I64.1
GA #3
S64.2
I64.1
Equipping option of P2S64M
S64.2
L64.2
V64.2
U64.2
I64.1
GA #3
Equipping option of S64M
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 194. Equipping Options of STM–64 Boards
ED
03
3AG 24163 BEAA PCZZA
531
362 / 531
14.9.3 Physical Description
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Main components of STM–64 boards are the following (refer to Figure 195. on page 364):
•
The STM–64 board provides GA #1 device for interface with the backplane. This is a CMOS
ASIC with 2.5 Gbit/s I/O, 2 x 40 Gbit/s throughput.
•
The STM–64 board provides GA #3 (and GA #4) device as an STM–64 Framer .This is a CMOS
ASIC with 2.5 Gbit/s I/O, 2 x10 Gbit/s throughput.
•
The STM–64 board provides GA #2 device and associated SRAM for overhead management.
This is a CMOS FPGA.
•
The STM–64 board provides GA #5 device for following functions:
–
–
–
–
–
–
–
Monitor and generate various status and control signals through its ports.
Interface on–board temperatures sensors.
Interface to on–board SEEPROM for Remote Inventory information through board internal
SPI bus.
Generate signals for board status LED for board status reporting.
Provide I2C like protocol for the on–board interfacing devices.
Interface to flash EEPROM for on board FPGA code.
Provide HW&CFG bus for remote code change inside flash EEPROM.
•
The STM–64 board provides DC–DC converters to generate all the required voltages from input
48 V DC.
•
The STM–64 board provides in–rush current limiting circuitry on input 48 V DC.
•
The STM–64 board provides VCXOs and associated circuitry for external clock Generation and
PLL function.
•
The STM–64 board provides back plane interface using press–fit connectors, for following:
–
–
–
–
–
–
•
Incoming and outgoing DCC channels.
Timing information and Data flow from both switch matrices.
SPI links A and B for power up status /configuration.
ISPB bus.
Reading the slot identification.
48 V DC and 3.3 V service voltage.
The STM–64 board provides circuitry on board to:
–
–
–
–
Distribute clock / timing information coming from the back plane to different on–board
components.
Indication of programming status of GA #2.
Provide access to GA #1. GA #2 internal registers through ISPB bus and associated GTL
buffers, and their enabling circuitry.
Other miscellaneous circuitry.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The 1xSTM–64 board front panel is shown Figure 45. on page 107.
The 2xSTM–64 board front panel is shown Figure 46. on page 108.
The 4xSTM–64 board front panel is shown Figure 47. on page 109.
ED
03
3AG 24163 BEAA PCZZA
531
363 / 531
GA #2
GA #3
MSA
transponder
MSA
transponder
POWER
SUPPLY
ÍÍÍÍÍ
ÍÍÍÍÍ
ÍÍÍÍÍ
ÍÍÍÍÍ
ÍÍÍÍÍ
ÍÍÍÍÍ
ÍÍÍÍÍ
GA #4
MSA
transponder
TIMING LOGIC
backplane
from / to line
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
MSA
transponder
GA #1
Temperature
sensors
GA #5
Figure 195. STM–64 Board Functional Block Diagram
In following paragraphs, details of different subsystems implementation will be provided.
14.9.3.1 Payload Subsystem Description
The data flow on the STM–64 boards is shown in Figure 196. on page 365.
The MSA transponders connect to GA #3 which further interfaces with the backplane through GA #1. Only
GA #3 is shown in the picture as the second one (GA #4) is connected in the same way to GA #1.
MSA – GA #3 interface
The MSA transponders interface with the GA #3 (and GA #4) through 622 Mbit/s data signal lines.
1AA 00014 0004 (9007) A4 – ALICE 04.10
GA #3 – GA #1 interface
The GA #3 (and GA #4) interfaces with GA #1 through 2488 Mbit/s data signal lines. It provides a
bandwidth of 19904 Mbit/s so eight differential pair (for each direction) are used to connect GA #3 (and
GA #4) to GA #1.
ED
03
3AG 24163 BEAA PCZZA
531
364 / 531
backplane
GA #3
GA #1
16 x 2.5 Gbit/s
MSA
2
from / to Matrices A and B
4 x 2.5 Gbit/s
16 x 2.5 Gbit/s
from / to line
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
16 x 622 Mbit/s
MSA
1
16 x 622 Mbit/s
4 x 2.5 Gbit/s
Figure 196. STM–64 Board Payload Subsystem Block Diagram
14.9.3.2 Power Subsystem Description
The STM–64 board gets a supply voltage of 48 V from the back panel and uses this to generate the
voltages of 3.3 V, 5.0 V, –5.0 V, 1.2 V, 1.5 V, 1.8 V on the board.
There is an in–rush current protection circuitry provided on the board. The power scheme is summarized
in Figure 197.
+48 V
+ BATT
From
Backplane
DC/DC conv.
#1
+1.2 V
DC/DC conv.
#2
+3.3 V
–48 V
+48 V
– BATT
In rush
current
limiting
circuitry
–48 V
+48 V
–5 V
DC/DC conv.
#3
+5 V
–48 V
+48 V
1.5 V
DC/DC conv.
#4
1.8 V
–48 V
3.3 VA
From
Backplane
VS
GA #5
1AA 00014 0004 (9007) A4 – ALICE 04.10
3.3 VB
Figure 197. STM–64 Board Power Supply Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
365 / 531
14.9.3.3 Timing Subsystem Description
622MHz
VCXO
622MHz
622MHz
Phase
from / to line
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The timing and clock circuitry is shown in Figure 198. on page 366.
MSA
GA #1
77.76MHz
622MHz
GA #3
MFSYA, B
38MHz
CLK
155MHz
155MHz
77.76MHz
VCXO
GA #2
155MHz
Figure 198. STM–64 Board Timing and Clock Block Diagram
14.9.3.4 Miscellaneous Subsystems Description
Control subsystem
The GA #5 drives the GA #2 for configuration purposes.
Parallel I/O and self–diagnosis subsystems
The Parallel I/O subsystem manages Alarms, commands, LEDs present in the boards and mapping to
parallel I/O registers of the control interface, indicating meanings and activation levels.
The Self–diagnosis subsystem monitors the temperature sensor that are placed on the board.
Main alarms are related to LOS, LASER_OFF, FUSES, BATT.
On board a bicolor LED is present to show:
1AA 00014 0004 (9007) A4 – ALICE 04.10
•
•
ED
green: board in service
red: internal fault (board out of service).
03
3AG 24163 BEAA PCZZA
531
366 / 531
14.10 STM–64 traffic Port Boards with pluggable XFP MSA Modules
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Two SDH I/O boards with pluggable XFP modules are supported:
–
–
1..4x STM–64 board with XFP/XFP–E type pluggable modules
1..2x STM–64 board with XFP/XFP–E type pluggable modules
The types of introduced modules are (according to ITU–T G.691, G959):
–
–
–
I–64.1 (2 km)
S–64.2b (40 km)
L–64.2 (80 km) – XP1L12D2
From a functional point of view this board is compatible to the 4xSTM–64 MSA port board supported already in Rel. 3.0. Main difference is that the board has in service pluggable optical modules. A serializer/
deserializer (SERDES) device is needed for each XFP/XFP–E module to adapt the 10 Gbit/s serial XFI
interface to the 16bit wide SFI–4.1 interface of DAFFODIL.
14.10.1 4xSTM–64 XFP Port Board
This is a 1 to 4 interface port board supporting the following pluggable optical modules:
–
–
XFP formfactor optical modules:
•
OPT TRX S–64.2B XFP
•
OPT TRX I–64.2B XFP
•
OE – TRX XFP 80 KM STD SIZE (XP1L12D2 – L–64.2)
XFP–E formfactor optical modules:
•
OPT TRX XFP S–64.2B Ext
The board supports:
–
–
–
–
Fully equipped module configuration (4 XFP/XFP–E modules are plugged in)
Partly equipped module configuration (configuration with 1 to 4 XFP/XFP–E modules is possible)
Mixed module type configuration (any mix of different XFP/XFP–E modules is supported)
In service changeable configuration.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 199. shows a block diagram of the 4xSTM–64 board.
ED
03
3AG 24163 BEAA PCZZA
531
367 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
4xSTM–64
(XFI)
STM–64
XFP/–E
#1
SerDes
STM–64
XFP/–E
#2
SerDes
4xSTM–64
(SFI 4.1)
4xSTM–64 XFP
16xSTM–16 like
16:1
GA #3
16:1
GA #1
GA #2
STM–64
XFP/–E
#3
SerDes
16:1
GA #4
STM–64
XFP/–E
#4
SerDes
16:1
Figure 199. Functional Blocks of the 4xSTM–64 Port Board
14.10.2 2xSTM–64 XFP Port Board
This is a de–populated 4xSTM–64 XFP port board as described in 14.10.1. It is cut down to 1x Daffodil,
2x SERDES and max. 2x XFP/XFP–E modules.
The 1 to 2 interface port board supports the following pluggable optical modules:
–
–
XFP formfactor optical modules:
•
OPT TRX S–64.2B XFP
•
OPT TRX I–64.2B XFP
•
OE – TRX XFP 80 KM STD SIZE (XP1L12D2 – L–64.2)
XFP–E formfactor optical modules:
•
OPT TRX XFP S–64.2B Ext
The board supports:
–
–
–
–
Fully equipped module configuration (2 XFP/XFP–E modules are plugged in)
Partly equipped module configuration (configuration with 1 to 2 XFP/XFP–E modules is possible)
Mixed module type configuration (any mix of different XFP/XFP–E modules is supported)
In service changeable configuration.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 200. shows a block diagram of the 2xSTM–64 board.
ED
03
3AG 24163 BEAA PCZZA
531
368 / 531
2xSTM–64
(XFI)
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
STM–64
XFP/–E
#1
2xSTM–64
(SFI 4.1)
2xSTM–64 XFP
8xSTM–16 like
SerDes
16:1
GA #3
STM–64
XFP/–E
#2
SerDes
16:1
GA #1
GA #2
Figure 200. Functional Blocks of the 2xSTM–64 Port Board
14.10.3 Timing Subsystem
The timing and clock circuitry is shown in Figure 201.
622MHz
VCXO
VCXO
622MHz
622MHz
622MHz
from / to line
Phase
MFSYA, B
Phase
GA #1
XFP/–E
155MHz
SerDes 622MHz
155MHz
GA #3
77.76MHz
38MHz
CLK
155MHz
77.76MHz
VCXO
GA #2
155MHz
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 201. STM–64 XFP Board Timing and Clock Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
369 / 531
14.11 STM–16 traffic Port Board (P16S16)
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
14.11.1 Introduction
In the 1678MCC equipment several types of STM–16 interfaces are available with the same
implementation on board (up to sixteen STM–16 optical interfaces).
The following description covers all different items (S–16.1, L–16.1 and L–16.2) equipped on the P16S16
board.
The STM–16 interfaces are composed by SFP plug–in modules.
14.11.2 Functional Description
14.11.2.1 Overview
The STM–16 board provides optical interface for sixteen tributaries at STM–16 rate for Short and Long
connections. It also contains circuitry for management, configuration, and control of on–board devices
through backplane SPI, ISPB and Hardware&Configuration buses.
14.11.2.2 Main Features
The main features of STM–16 board are shown in the following.
The STM–16 boards are composed of a single PCB supporting various modes based on the mounting
options. The board has always GA #1, GA #2 and GA #3 as common devices in the data path (refer to
Figure 202. on page 371).
14.11.3 Physical Description
Main components of STM–16 boards are the following (refer to Figure 202. on page 371):
•
The STM–16 board provides GA #1 device for interface with the backplane. This is a CMOS
ASIC with 2.5 Gbit/s I/O, 2 x 40 Gbit/s throughput.
•
The STM–16 board provides GA #3 device as an STM–64 Framer .This is a CMOS ASIC with
2.5 Gbit/s I/O, 2 x10 Gbit/s throughput.
•
The STM–16 board provides GA #2 device and associated SRAM for overhead management.
This is a CMOS FPGA.
•
The STM–16 board provides GA #5 device for following functions:
–
–
–
1AA 00014 0004 (9007) A4 – ALICE 04.10
–
–
–
–
ED
Monitor and generate various status and control signals through its ports.
Interface on–board temperatures sensors.
Interface to on–board SEEPROM for Remote Inventory information through board internal
SPI bus.
Generate signals for board status LED for board status reporting.
Provide I2C like protocol for the on–board interfacing devices.
Interface to flash EEPROM for on board FPGA code.
Provide HW&CFG bus for remote code change inside flash EEPROM.
•
The STM–16 board provides DC–DC converters to generate all the required voltages from input
48 V DC.
•
The STM–16 board provides in–rush current limiting circuitry on input 48 V DC.
03
3AG 24163 BEAA PCZZA
531
370 / 531
The STM–16 board provides VCXOs and associated circuitry for external clock Generation and
PLL function.
•
The STM–16 board provides back plane interface using press–fit connectors, for following:
–
–
–
–
–
–
•
Incoming and outgoing DCC channels.
Timing information and Data flow from both switch matrices.
SPI links A and B for power up status /configuration.
ISPB bus.
Reading the slot identification.
48 V DC and 3.3 V service voltage.
The STM–16 board provides circuitry on board to:
–
–
–
–
Distribute clock / timing information coming from the back plane to different on–board
components.
Indication of programming status of GA #2.
Provide access to GA #1. GA #2 internal registers through ISPB bus and associated GTL
buffers, and their enabling circuitry.
Other miscellaneous circuitry.
SFP
module
1
GA #2
from / to line
POWER
SUPPLY
GA #3
backplane
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
•
GA #1
SFP
module
16
Temperature
sensors
TIMING LOGIC
GA #5
Figure 202. STM–16 board Functional Block Diagram
14.11.3.1 Payload Subsystem Description
1AA 00014 0004 (9007) A4 – ALICE 04.10
The data flow on the STM–16 boards is shown in Figure 203. on page 372.
The MSA transponders connect to GA #3 which further interfaces with the backplane through GA #1.
MSA – GA #3 interface
The MSA transponders interface with the GA #3 (and GA #4) through 2.5 Gbit/s data signal lines.
ED
03
3AG 24163 BEAA PCZZA
531
371 / 531
8 x 2.5 Gbit/s
GA #3
backplane
16 x 2.5 Gbit/s
GA #1
16 x 2.5 Gbit/s
SFP
16
from / to Matrices A and B
1 x 2.5 Gbit/s
SFP
1
from / to line
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
GA #3 – GA #1 interface
The GA #3 interfaces with GA #1 through 2488 Mbit/s data signal lines. It provides a bandwidth of
19904 Mbit/s so eight differential pair (for each direction) are used to connect GA #3 to GA #1.
1 x 2.5 Gbit/s
8 x 2.5 Gbit/s
Figure 203. STM–16 Board Payload Subsystem Block Diagram
14.11.3.2 Power Subsystem Description
The STM–64 board gets a supply voltage of 48V from the back panel and uses this to generate the voltages
of 3.3 V, 1.2 V, 1.5 V, 1.8 V on the board. There is an in–rush current protection circuitry provided on the
board. The power scheme is summarized in Figure 204.
+48 V
+ BATT
From
Backplane
DC/DC conv.
#1
+1.2 V
DC/DC conv.
#2
+3.3 V
–48 V
+48 V
– BATT
In rush
current
limiting
circuitry
–48 V
REG.
1.8 V
+48 V
1.5 V
DC/DC conv.
#4
1.2 V
–48 V
3.3 VA
From
Backplane
VS
GA #5
1AA 00014 0004 (9007) A4 – ALICE 04.10
3.3 VB
Figure 204. STM–16 Board Power Supply Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
372 / 531
14.11.3.3 Timing Subsystem Description
622MHz
VCXO
622MHz
622MHz
Phase
MFSYA, B
from / to line
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The timing and clock circuitry is shown in Figure 205. on page 373.
SFP
77.76MHz
622MHz
GA #1
GA #3
155MHz
38MHz
CLK
155MHz
77.76MHz
VCXO
GA #2
155MHz
Figure 205. STM–16 Board Timing and Clock Block Diagram
14.11.3.4 Miscellaneous Subsystems Description
Control subsystem
The GA #5 drives the GA #2 for configuration purposes.
Parallel I/O and self–diagnosis subsystems
The Parallel I/O subsystem manages Alarms, commands, LEDs present in the boards and mapping to
parallel I/O registers of the control interface, indicating meanings and activation levels.
The Self–diagnosis subsystem monitors the temperature sensor that are placed on the board.
Main alarms are related to LOS, LASER_OFF, FUSES, BATT.
On board a bicolor LED is present to show:
•
green: board in service
•
red: internal fault (board out of service).
The front panel is shown in Figure 44. on page 106.
14.12 STM–16 Traffic Port Board (P4S16, P8S16)
1AA 00014 0004 (9007) A4 – ALICE 04.10
The functional and physical descriptions of the P4S16 and P8S16 boards are similar to the P16S16 board.
Only the number of interfaces is different.
The front panel of P4S16 is shown in Figure 42. on page 104.
The front panel of P8S16 is shown in Figure 43. on page 105.
ED
03
3AG 24163 BEAA PCZZA
531
373 / 531
14.13 16xSTM–1/4 Traffic Port Board (P16S1–4)
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
14.13.1 Introduction
In the 1678MCC equipment several types of STM–1 and STM–4 interfaces are available with the same
implementation on board (up to sixteen STM–1 electrical interfaces, up to sixteen STM–1 optical
interfaces, up to sixteen STM–4 or a mix of STM–1 and STM–4).
For the “mixed configuration” is provided the “quartet rule”: the sixteen interfaces are managed in four
blocks (quartet) and the interfaces within the same quartet must be STM–1e/o or STM–4 (for example:
if the first interface provisioned in the same quartet is STM–1, also the other three interfaces of the quartet
have to be STM–1).
Within the quartet a mix of electrical, short haul or long haul modules is possible.
EPS for STM–1 electrical is not supported.
The following description covers all different items equipped on the P16S1–4 board:
•
•
•
for STM–1e: SES1
for STM–1o: S–1.1, L–1.1 and L–1.2
for STM–4: S–4.1, L–4.1 and L–4.2
The STM–1 and STM–4 interfaces are composed by SFP plug–in modules.
14.13.2 Functional and Physical Descriptions
The functional and physical descriptions of the P16S1–4 board are similar to P16S16 board.
1AA 00014 0004 (9007) A4 – ALICE 04.10
For the functional description refer to para. 14.11.2 on page 370.
For the physical description refer to para. 14.11.3 on page 370.
ED
03
3AG 24163 BEAA PCZZA
531
374 / 531
14.14 16xSTM–1 Traffic Port Board (P16S1S)
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
14.14.1 Introduction
In the 1678MCC equipment several types of STM–1 interfaces are available with the same implementation
on board (up to sixteen STM–1 electrical interfaces, up to sixteen STM–1 optical or a mix of both). Any
mix of the supported interfaces is allowed.
EPS for STM–1 electrical is not supported.
The following description covers all different items equipped on the P16S1S board:
•
•
for STM–1e: SES1
for STM–1o: S–1.1, L–1.1 and L–1.2
The STM–1e and STM–1o interfaces are composed by SFP plug–in modules.
14.14.2 Functional and Physical Descriptions
The functional and physical descriptions of the P16S1S board are similar to P16S16 board.
1AA 00014 0004 (9007) A4 – ALICE 04.10
For the functional description refer to para. 14.11.2 on page 370.
For the physical description refer to para. 14.11.3 on page 370.
ED
03
3AG 24163 BEAA PCZZA
531
375 / 531
14.15 4/8/16xGigabit Ethernet Port Board
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
14.15.1 Introduction
The Gigabit Ethernet (GE) board exists in three variants:
–
–
–
16xGE
8xGE
4xGE.
It can provides up to 16 SFP modules, which support the following types of interfaces:
–
–
–
Opto TRX 1.25GBE SFP–SX
Opto TRX 1.25GBE SFP–LX
Opto TRX 1.25GBE SFP–ZX.
The GE ports can be mixed in a flexible way. The optical SFP modules can be equipped in flexible way:
–
–
flexible mix of short range (1000Base–SX) and long range (1000Base–LX) optics
flexible equipment of ports from:
•
1 to 4 SFP modules (4xGE)
•
1 to 8 SFP modules (8xGE)
•
1 to 16 SFP modules (16xGE).
14.15.2 HW Functionality
The main features of the GE board are:
–
–
–
–
Ethernet point to point transport only (no L2 switch functions)
•
VC4/AU4 in SDH
•
VC3/AU3 in SONET
GE mappings
•
frame mapping according to G.7041 (GFP–F) over VC–4–Xv (X=1... 7) – SDH
•
frame mapping according to G.7041 (GFP–F) over VC–3–Xv (X=1... 21) – SONET
•
client flow control according to 802.3x, 10km client distance
15 ms differential delay compensation for virtual concatenated VC–4/VC–3 (HO VCGs only)
Support of Jumbo Frames (MTU = 9796 bytes)
The front panel of the 4xGE board is shown in Figure 42. on page 104.
The front panel of the 8xGE board is shown in Figure 43. on page 105.
The front panel of the 16xGE board is shown in Figure 44. on page 106.
The GE boards have the following capacity:
–
–
–
16xGE has max. 112 STM–1 equivalents
8xGE has max. 56 STM–1 equivalents
4xGE has max. 28 STM–1 equivalents.
1AA 00014 0004 (9007) A4 – ALICE 04.10
14.15.3 Link Capacity Adjustment Scheme (LCAS)
Defined by the G.7042 specification, LCAS is a means for the source and the sink to synchronize during
addition or deletion of members to a Virtual Concatenation Group (VCG) such that payload de–adaptation
at the sink end may be done hitless under non–defect conditions. LCAS functionality can also restore temporarily unavailable members hitless. The synchronization mechanism is necessary because of the varying delays that each member of a VCG may incur.
ED
03
3AG 24163 BEAA PCZZA
531
376 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Under the LCAS scheme, the management layer issues add/remove commands for a given member separately to the source and sink ends of a VCG. The LCAS state machine at the source end then signals to
the sink end that it is ready to add a particular member to the VCG.
The LCAS sink end state machine then checks the “to be added” member for trail failures and signals to
the source end that it is ready via an acknowledgement signal. The source end then signals the start of
the payload change and initiates the actual change. This entire “handshaking” process between the two
ends takes place via the H4 byte for higher order VC.
Again, the LCAS state machine operation is identical for both higher and lower order VC. Note that for
lower–order VC the LCAS handshaking process takes place via the K4 byte.
The importance of LCAS is pretty simple in a system architecture. By dynamically altering the bandwidth
of Sonet/SDH transport pipes, LCAS allows designers to adjust bandwidth based on Quality of Service
(QoS) or other priority considerations.
14.15.4 Functional Descriptions
Refer to schematic block diagram (Figure 206. on page 378) it is possible to see that the client signal (Gigabit Ethernet) is an optical signal that is converted from Optical to Electrical using an SFP module.
After the conversion the signal enters into VOLTA ASIC, which map the data signal (GE or FC) into SDH.
Every VOLTA can support up to 10 clients (but we use 8 interfaces) and is able to map transparently or
rate adaptive into a 10 Gbit SDH (STM64). Every VOLTA needs 8 SDRAM memories to support the Flow
Control and the Virtual Concatenation differential delay compensation up to 15 ms.
The 10 Gbit signal from VOLTA is passed to VIVALDI ASIC which double the signal and add a FEC to adapt
the STM64 to a proprietary backpanel format.
IACO FPGA is another block which mainly manages the microprocessor interface of VOLTA, receiving the
data from ISPB bus and translating the commands to VOLTA. Other use of IACO is to implement the SDH
Performance Monitoring.
The last important block is represented by GOBLIN which is an EPLD with many uses: read and write the
remote inventory, read some board alarms and activate some commands. GOBLIN communicates with
the external controller via SPI bus (protected A and B). GOBLIN is also used as an hardware configuration
manager to load external devices (FPGA) interfacing with a flash memory.
The power supply of the board are:
–
–
–
–
–
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V.
1AA 00014 0004 (9007) A4 – ALICE 04.10
All of them are obtained using four DC/DC converter which are driven by a Battery (after an OR between
BATT A and BATT B) coming from Backpanel.
ED
03
3AG 24163 BEAA PCZZA
531
377 / 531
GE
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
RAM
1
8
RAM
8
1
Cx 622 MHz
Cx 77 MHz
VOLTA
Matrix A
VIVALDI
Data
Matrix B
16
2
1
Commands
Alarms
1
ISPB
Micro
Interface
ISPB
Buffer GTLP
to/from IACO
IACO
Backpanel
Optical SFP
Module
Power Alarm
Flash
Memory
LED Control
GOBLIN
SPI Bus
RI
1.2 V
1.5 V
1.8 V
BATT A
OR
DC/DC
BATT B
3.3 V
2.5 V
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 206. GE Board Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
378 / 531
14.15.4.1 Board Functionality
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The GE board has the following functionalities:
–
Board and module management (plug–in, plug–out, Laser on/off)
–
Configuration of fixed concatenation for all interfaces (GFP–F–7v)
–
Crossconnections of VC4vTTPs, incl. SNCP support
–
Mapping and demapping of GE signal to/from VC4s, incl. ’far end’ signalling (RDI, REI) within VC4
POH
–
LOS alarm for GE interfaces
–
SSF (summary) alarm for the (16) VCAT groups in case of underlying SDH problems
–
Configuration of VC4s (TTI, alarm mask, DEG threshold)
–
Alarming of VC4s (SSF, UNEQ, RDI, DEG, TIM and LOM, LOA, SQM)
–
HO PM for VC4vTTPs
–
Modification of number of VC4s per interface
–
Configuration of ’idle’ VC4s (only used for SDH–Termination, not for mapping/demapping)
–
GE PM (Rx, Tx)
–
Link Capacity Adjustment Scheme (LCAS), refer to next chapter 14.15.4.2 for details
14.15.4.2 LCAS Management
–
Enable / disable LCAS protocol per VC–group (per port)
–
Configuration of hold–off (0..10 000 ms) and wait–to–restore (0..900 s) times.
–
Configuration of ’idle’ VC4s at individual positions, if LCAS is enabled (without LCAS, all the VC4s
with the lower IDs have to be active and only the VC4s with the upper IDs can be idle).
–
Retrieval of status information per VC–group and for each member/channel (VC4) on management
request:
1AA 00014 0004 (9007) A4 – ALICE 04.10
–
ED
•
number of working channels in receive and transmit direction per group.
•
status (fail or ok), sequence number and control packet (FIXED, ADD, NORM, EOS, IDLE,
DNU) in receive and transmit direction per channel.
All the management is done via the Q3 interface.
03
3AG 24163 BEAA PCZZA
531
379 / 531
A detailed description of the 4 main chips follows:
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ASIC VOLTA
Features are:
–
Multiprotocol mapper which optimize transport of GEthernet/Fibre Channel client Data Signals over SDH using VC
–
–
–
–
–
–
8B/10B Performance Monitoring
Transparent GFP
Frame based GFP
Supports Virtual Concatenation VC4–Xv and VC3–Xv
Provides up to 15 ms of inter tributary de–skew for VC groups using external DDR Ram
Supports LCAS functionality as for ITU–T G.7042.
ASIC VIVALDI
Features are:
–
–
–
–
–
Interfaces between Commercial Framer and Backplane
Proprietary frame building to backpanel with Slice/Deslice function
FEC and DEFEC for proprietary backpanel frame
Overhead drop/insert and interface for external device(s)
EPS protections.
FPGA IACO
Features are:
–
–
–
–
–
–
Some HPT management accessing Volta Registers
Automatic Laser Shutdown Manager
Controller of Volta Mapper
ISPB2 Interface
ISPB2/Motorola Bridge
SDH Performance Monitoring.
FPGA GOBLIN
Features are:
–
–
–
Hardware Configuration Bus Manager
Local I2C bus controller via backplane SPI bus
SPIDER–like SPI functionalities.
14.15.4.3 GE Services
1AA 00014 0004 (9007) A4 – ALICE 04.10
The GE provides the following services:
–
Bidirectional Link Pass Through (LPT)
The GE emulates a bidirectional point–to–point cable between two client devices. Failures in any direction at any point (GE line or TDM) will cause a service down notification to both ends.
–
Static Link Aggregation Group (S–LAG)
Equivalent to the bidirectional LPT service with the difference that one end is the ES64 (client) device.
ED
03
3AG 24163 BEAA PCZZA
531
380 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
Unidirectional broadcast
The GE emulates a unidirectional point–to–multipoint cable between a sender and a number of receivers. As the sender always requires a valid GE line for broadcasting, the GE laser is constantly
forced on.
–
Unidirectional Link Pass Through (LPT)
The GE emulates a unidirectional point–to–point cable between two client devices. Near end failures
(LOS, GFP errors) are propagated in the same direction, but far end failure (RDI, auto–negotiation
remote faults) are not. Therefore, the clients must notify service interruptions by other means (e.g.
bidirectional fault propagation or protocol hello).
These services can be configured via CT/NM. Refer to the Operator’s Handbook for the related configuration procedures.
ED
03
3AG 24163 BEAA PCZZA
531
381 / 531
14.16 2x/4x10 Gigabit Ethernet Port Board
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
14.16.1 Introduction
The 10GE LAN card supports point to point Ethernet Private Line (EPL) transport of 10GE LAN and Ethernet Virtual Private Line (EVPL) transport of multiple sub–rate services of 10GE via SDH/SONET network.
The 10GE EPL service is equivalent to the service provided for the 4/8/16xGE card except for the extended
range of Generic Framing Procedure (GFP)–Virtual Concatenation Group (VCG). In this case there is a
one to one relationship between the ethernet port and the GFP–VCG.
The GE services described in chapter 14.15.4.3 on page 380 are also supported for 10GE, except the
“Unidirectional Link Pass Through” service, that is supported for 1GE only.
14.16.2 HW Functionality
The main features of the board are:
–
2x/4x10GE LAN ports per board
–
XFP optical modules:
•
10GE–SR
•
10GE–LR (equivalent with I–64.1)
•
10GE–ER (equivalent with S–64.2b)
–
Board and port management via Q3
–
10GE Services
•
Ethernet Private Line (EPL), point to point transport
•
Ethernet Virtual Private Line (EVPL) according to G.8011.2 type 1
–
Ethernet port is used as a multiplexed access where traffic is separated by VLAN tags,
there is one EPL (VCG) per VLAN.
–
Up to 61 services (VCG) per 10GE Port
–
VLAN processing at line side allowing to:
•
’pop’ received VLAN tag on receive side
•
’push’ a VLAN tag with ethernet type and priority bits on transmit side
–
IA complete port (ethernet or VCG) can be used in transparent mode, e.g. for EPL services
or VLAN ignored EVPL services.
–
10GE mappings
•
frame mapping according to G.7041 (GFP–F)
(VC4 and STS1 mode cannot be mixed on a 10GE port)
–
into VC–4–nv (n= 1...64) for SDH or
–
into STS–1–nc (n= 1...192) or STS–3c–xv (x=1 to 64) for SONET
•
client flow control according to 802.3x (PAUSE frames) – only for EPL mode
–
Support of Jumbo Frames (MTU = 10240 bytes)
–
32 ms differential delay compensation for virtual concatenated VC/STS
–
PM on Ethernet
•
Interface counters
•
Aggregate counters (per VCG)
•
Service flow counters (per gMauCTP)
ED
03
3AG 24163 BEAA PCZZA
531
382 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
SDH/SONET functions: VC–4/STS–3c/STS–1 TTP incl. PM
–
CSF insertion in case of Ethernet link failures and SSF/CSF detection on VCAT sink side.
14.16.3 Ethernet Virtual Private Line (EVPL)
The EVPL service introduces a new level of hierarchy between the ethernet port and the VCG using VLAN
tags to provide multiple services at subrates of the 10GE up to the port capacity. The sub–rate services
are identified by the VLAN tag carried within the ethernet frames. Each EVPL service is mapped to a
unique VCG. The demultiplexing from one 10GE port to multiple VCGs is done on ingress side, while multiplexing of multiple EVPL services into a 10GE port must be provided on egress side.
Figure 207. shows a typical EVPL service application for the GE. The source client want to have two separate Ethernet services over the same Ethernet port to different clients. Each Ethernet frame is tagged with
an VLAN identifier to which service it belongs. The data traffic enters the SDH domain at the GE board.
For each incoming frame the VLAN identifier identifies to which VCAT group the frame belongs. If the router sends more data than the VCAT group is able to transport the traffic is dropped as no VLAN Flow Control
is defined yet. For a short traffic burst the GE is able to receive data with the full Gigabit Ethernet data rate
because the input is buffered (in the meaning of ’store and forward’).
Customer A
Port
VCG
Port
VCG
Port
VCG
Customer A
V
C
G
Customer B
Port
Port
Customer B
Figure 207. Ethernet Virtual Private Line Service
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 207. shows 4 individual EVPL services each of them marked in different color or dashed. Some
of the EVPL services enters and leaves the network in a shared manner with other services but each EVPL
is transported over a dedicated VCG.
The receiving GE is responsible to de–map the VCAT group and to multiplex the packets from different
VCAT groups to a single Gigabit interface. VCAT de–mapping includes compensation of the differential
delay between the fractions.
In order to decouple VLAN identifier assignment for each customer side the VLAN swap functions are provided at the edge of network. This allows individual assignment per customer side and avoids unique
VLAN assignment over all customer interfaces.
Required NE functions:
–
–
ED
GFP,
VCAT,
03
3AG 24163 BEAA PCZZA
531
383 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
–
–
LCAS,
L1 aggregation,
VLAN based L2 aggregation on access link
Services:
–
–
–
–
–
Ethernet leased line,
IP Backbone,
Storage Area Network (SAN),
Metro Ethernet network interconnection,
Mobile backhaul.
14.16.4 Functional Description
Figure 208. shows the basic constellation for the 2x/4x10GE. At max there are two or four 10 Gigabit
Ethernet interfaces available. The board has a maximum back–panel capacity of 128/256 VC4s
(768 STS1)s. Each port is handled by a separate NEWTON FPGA.
Optical interfaces are provided as drawers which are inserted in the main board. Four different sub–modules are available:
–
–
–
XS642B
XI641
XGESR.
Mixed interface variants are allowed on the same board. The expected 10GE card is named P2XGE/
P4XGE.
FPGA download
Goblin4G
SPI A/B
HW_CFG
Local SPI
I2C, ALS
Port #1
LED
LED control
LOS
10GE_LAN
QDR2RAM
72M
RLDRAM
288M
MAZINGA4G
FPGA
NEWTON FPGA
GAUSS
SERDES XSBI
XSBI 10GE 10GE VLAN
Core
e.g Vitesse
E/O
IF
PCS MAC MUX GFP–F, VCAT, LCAS
1x VCS8479 16x
XFP 10.3G
644M
OH IF
I2C
I2C
XFI
OH
ISPB
SFI
4.1
SFI4.1
16x
622M
IF
V
I
V
A
L
D
I
OH
Port #2
Port #3 *
To matrix
A/B
Clk38MHz
sync38Mb
Port #3 *
DC/DC
–48V A/B
1AA 00014 0004 (9007) A4 – ALICE 04.10
* in case of 4x10GE board
Figure 208. 10GE LAN Board Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
384 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The board uses the Generic Framing Procedure (GFP) with null extension header for the mapping. Optional a payload Frame Check Sequence (FCS) can be chosen.
The back–panel bandwidth can be assigned with a granularity of one VC4 (STS1) separately to the two/
four 10Gigabit interfaces (1...64 VC4 or 1..192 STS1 per port). As there is sufficient back–panel capacity
available each port can be used with full capacity (64 VC4 or 192 STS1) without any limitation. It is possible
to change the number of virtually concatenated VC4s/STS1s for any interface that is in use. The concept
is very similar to the 4/8/16xGE port whereby the back–panel capacity is group in 64 VC4/192 STS1
blocks.
ED
03
3AG 24163 BEAA PCZZA
531
385 / 531
14.16.5 Power Subsystem
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The P2XGE/P4XGE board gets its power supply of 48/60 V from the back panel and generates the following voltages by DC/DC converters (refer to Figure 209. ):
–
–
–
–
–
–
–
–5.2 V_XFP,
+5 V_XFP,
3.3 V,
3.3 V_GTL,
2.5 V,
1.8 V and
1.2 V.
There is an inrush current limitation circuit to limit the current when the board is plugged in. A 3.3 V service
voltage is used to supply GOBLIN and the power manager, which do the controlling and supervision of
the converters. All battery voltages from the back panel are fused on board, and there is a fuse supervision.
After the power converters there are various LC–filter circuits for ASICs, FPGAs, XFP modules etc.
Power failures are visualized by LED, and a power fail signal to GOBLIN is generated.
Back Panel
DC/DC OB
−5.2 V_XFP
+BATT_A
DC/DC HB
+5 V_XFP
−BATT_A
Inrush current limitation
DC/DC POL
3.3 V
3.3 V_GTL
DC/DC POL
2.5 V
1...4
+BATT_B
DC/DC POL
1.8 V
−BATT_B
1...2
DC/DC QB
1.2 V
3.6 V_A
3.3 V_Service
1A
Control
Power
Manager
GOBLIN
3.6 V_B
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 209. Power Subsystem Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
386 / 531
14.17 ES64 Server Card
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
14.17.1 Introduction
The ES64 card is part of the ISA–ES family of boards. The ISA–ES series modules provide Ethernet connectivity for LAN based clients by mapping of Ethernet flows directly onto the SDH network by means of
standard mechanism (e.g. GFP, LCAS, VCAT). In future also MPLS connectivity is provided where MPLS
flows can be transported via GFP/LAPS over SDH connections. They introduce wire speed classifying,
policing and scheduling capability using a carrier class packet switch engine for Ethernet and MPLS traffic.
14.17.2 HW Functionality
The ISA–ES cards offer specific SDH trunks (connected to SDH matrix via backplane). A simple block diagram of the ES card architecture is given in Figure 210. The ES card has a Ethernet switching function.
Ethernet frames are then mapped for example via GFP–F and LCAS into virtual concatenated Virtual Container (VC–12, VC–3 and VC–4–xv). This is implemented by the so called Multi Service Function.
Datapartunder
SNMPmanagement
Eth
Switch
TDMpartunderQ3management
Multi
Service
Function
SDH
Ports
ISA−ES64
64=cardtrunking
capacityinSTM−1eq.
TDM
Matrix
Figure 210. ISA ES64 Trunks
The ES64 has the following features:
–
–
–
1AA 00014 0004 (9007) A4 – ALICE 04.10
–
–
ED
HO virtual concatenation is supported only.
SDH (VC–4–Xv and SONET application (STS–1–xv and STS–3c–Xv) is provided.
DS3 termination is supported for STS1 termination.
No virtual concatenation is supported. DS3 Management is required for TL1 only.
20G Server Card
This card has a 20G capacity of Multi Service Function (128 VC–4 equivalents).
Interworking with remote Ethernet ports through the multi service function.
Remote Ethernet ports can be located in the same shelf (16/8/4x GE card and 4/2x 10GE LAN card)
or even in a different NE connected through the SDH network.
Support of Jumbo Frames (MTU = 9242 bytes for port 1..30 and 129..158, and MTU = 2026 bytes
(Baby Jumbo Frames) for all other ports)
03
3AG 24163 BEAA PCZZA
531
387 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
14.17.3 Functional Description
The ES64 card can interwork with remote Ethernet ports through GFP/VCAT. These ports may be located
in the same shelf (applies to 16x/8xGE card) or even can be located in a different NE connected through
the SDH network.
A block diagram of the ES64 board is shown in Figure 211.
10GMultiService
Function
Back−
plane
20G
20G
Network
Processor
Traffic
Manager
+
Switch
Driver
10GMultiService
Function
LocalDataController
Figure 211. Block Diagram of the ES64 Board
The ES64 is split into a data part (data engine) and a TDM part.
14.17.3.1 Data Engine
The so called Data Engine consist of the following main functions:
–
–
–
Network processor unit including peripherals
Traffic Manager/Switch including peripherals
Local Data Controller
The Network processor unit (NPU) has 20G throughput (bidirectional) and provides two SPI4.2 interfaces towards TDM part. Each SPI4.2 interface is able to handle 10G of traffic. Inside the NPU the data
packets are classified, headers are stripped off and internal headers are added and forwarded through
2x SPI4.2 interfaces to the Traffic Manager.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The Traffic Manager (TM) provides unicast, multicast and broadcast frame switching and various shaping
and scheduling algorithms taking into account buffer capacity, frame priority and number of queues.
The Local Data Controller (LDC) acts as a single network element providing management agents (via
SNMP and 1678MCC SC interfaces), protocol engines (R/MSTP for Ethernet, RSVP–TE, LDP, OSPF for
MPLS) and control of the data functions down to the HW.
ED
03
3AG 24163 BEAA PCZZA
531
388 / 531
14.17.3.2 TDM Part
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The TDM part of the ES64 is composed of the following functions:
–
Backplane driver
The backplane driver is compatible with the 160G/320G/640G TDM matrix of the 1678 MCC.
–
1x or 2x10 Gb/s DATA/TDM mapper functions
Mapper functions are used to map data packets coming from the data engine into GFP frames which
then are mapped into TDM signals, or to provide POS mapping (with or without PPP). Mapping options are:
•
•
•
–
GFP–F into VC–4–xv (x= 1...64) for SDH
GFP–F into STS–1–xv (x= 1...192) for SONET
GFP–F/LAPS into DS–3 into STS–1 for SONET
Up to 128 logical ports of either SDH (VC4/STS3c) or SONET (STS1/DS3) types can be used
on each Data/TDM mapper. Up to 120 DS3 termination points can be used. Separate TP pool
handling for each Data/TDM mapper is required.
Control IF
•
•
•
•
•
Remote inventory
EPS and status link via SPI
SPI bus
Control of XFP optical module
SYS_ID generation for LDC.
14.17.4 Power Subsystem
The ES64 board gets its power supply of 48/60 V from the back panel and generates the following voltages
by DC/DC converters (refer to Figure 212. ):
–
–
–
–
–
–
–
1.2 V,
1.8 V,
2.5 V,
3.3 V,
5 V,
1 V and
1.5 V.
1AA 00014 0004 (9007) A4 – ALICE 04.10
There is an inrush current limitation circuit to limit the current when the board is plugged in. All battery voltages from the back panel are fused on board, and there is a fuse supervision. After the power converters
there are various LC–filter circuits for ASICs, FPGAs, XFP modules etc.
ED
03
3AG 24163 BEAA PCZZA
531
389 / 531
Back Panel
DC/DC 60 A
1.2 V
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
+BATT_A
−BATT_A
Inrush Current
Limiter
DC/DC 25 A
Power Se9
quencing
Logic
DC/DC 25 A
1.8 V
2.5 V
DC/DC 15 A
3.3 V
DC/DC 10 A
3.6 V_A
5V
VREG 16 A
3.6 V_B
1V
3.3 V_Service
VREG 5 A
1.5 V
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 212. Power Subsystem Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
390 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
14.18 FAN Unit (FAN)
In the 1678MCC equipment two FAN units are mandatory.
The unit can be simply plugged into the backpanel as any other board of the 1678MCC, in one of the two
slots present for the purpose, at the top and at the bottom of the shelf.
FAN speeds are monitored through Spider block, that also collects alarms rising when FANs revolve below
30% of their maximum speed allowed.
The FAN unit is set up with a basic assembled PCB on which FANs are screwed on; on the same PCB
the FAN controller is also hosted.
14.18.1 Functional description
The FAN controller is the PCB dedicated to providing FANs with power, managing the speed of each of
them and monitoring speeds through Spider block, that also collects alarms rising when FANs revolve
below 30% of their maximum speed allowed.
Each FAN is powered by 48VDC voltage, supplied through a 38V–75V input acceptable range DC/DC
converter.
On the power supply of each FAN a fuse has been inserted, so that if a rotor had to be blocked for any
reason, the current absorbed from it would rise and then the fuse would break, protecting the motor from
damages.
In reality, this caution is not strictly necessary, since FANs mounted on the unit have themselves a locked
rotor protection: if the rotor is prevented from rotating and power is applied to the unit, the motor will
self–protect. When the locked rotor condition is removed the FAN will automatically restart. The motor can
sustain locked rotor conditions indefinitely throughout the full specification range of voltage and
temperature.
Figure 213. on page 393 shows the block diagram of unit.
As we can see, Spider can individually interrupt the 48V power supply of each FAN, detects temperatures
from three sensors spread across the controller board and can adjust FAN speeds by means of three
potentiometers, which provide through potential dividers variable voltages to FAN speed control pins.
The speeds of three brushless DC motors are also monitored. Is available an output signal that switches
at a frequency of 2 cycles per revolution of the FAN: when the FAN is not rotating, the output is either a
steady High or a steady Low. This signal enters a monostable that detects the presence of it and refers
to Spider. At the same time, it enters a counter triggered by a 1 Hz sync (SY1Hz) coming either from matrix
A or B (and selected by ACT lines): information about revolutions is so collected every 1 sec and read by
Spider by means of an enable command.
On board a bicolor LED is present to show:
•
•
green: unit in service
red: internal fault (unit out of service).
1AA 00014 0004 (9007) A4 – ALICE 04.10
The FAN unit front panel is shown Figure 62. on page 123.
ED
03
3AG 24163 BEAA PCZZA
531
391 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
14.18.2 Performance
Each FAN provide a flow of 167 m3/hr against a pressure of 82 Pa when running at maximum speed and
with 1.2 kg/m3 inlet air density.
In 40ºC environment at full speed condition, the grease in the bearings has an L10 life of 100,000 hours.
In 75ºC environment, the grease in the bearings has an L10 life of 40,000 hours.
14.18.3 Power Supply
The maximum current drawn by one single FAN is 0.35 A at full speed condition on 48 VDC supply,
corresponding to 16.8 W of power consumption.
With all FANs at full speed condition, the board absorbs 0.9 A when powered through battery A by a voltage
of 65 V, i.e. it has a total power consumption of 58.2 W.
14.18.4 FAN Failure
In case of a FAN failure the following instructions are very important.
No effect on transmission yet, but the FAN unit does not work properly. There is the danger of system
overheat.
If the FAN unit does not work properly, immediately replace the FAN unit.
If the operation temperature is more than 35 5C it is necessary to replace the damaged
FAN unit in max. 24 hours.
For FAN unit replacement refer to Operator’s Troubleshooting and Maintenance Handbook.
14.18.5 FAN Unit in SONET Applications
1AA 00014 0004 (9007) A4 – ALICE 04.10
The lower FAN unit is equipped with a dust filter and the upper FAN unit with a safety plate (finger guard).
ED
03
3AG 24163 BEAA PCZZA
531
392 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
SPI
A
SPI
B
ID
FAN
EEPROM
ON/OFF 1
SPIDER
ON/OFF 2
ON/OFF 3
speed ADJ 1
speed ADJ 2
speed ADJ 3
speed MON 1
speed MON 2
speed MON 3
DIG
POT
SENSOR 1
SENSOR 2
SENSOR 3
mon 1
mon 2
mon 3
counter 1
buffer 1
buffer 2
counter 2
counter 3
buffer 3
act_A
SY1Hz_B
act_B
SY1Hz_A
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 213. FAN Functional Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
393 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ED
03
3AG 24163 BEAA PCZZA
531
394 / 531
15 UNITS DESCRIPTIONS LOWER ORDER EXTENSION SHELF
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
15.1 Introduction
The following Table 48. on page 395 and Table 49. on page 395 sums up the units managed in the
1678MCC LO Extension Shelf Equipment.
Table 48. Units involved in 1678MCC LO Extension Shelf
Type / Class
Description
Acronym
Control / Common Alarm Board
LO Matrix
FAN System
Notes:
Width Q.ty
(TE)
4
ALM
1
2
Power Supply and Filter
PSF
Bus Termination
BUSTERM
LO Centerstage Matrix 160GBIT/S
LX160
8
2
Lower Order Adaptation 20G
LA20
4.5
10
FAN
FAN
––
2
Q.ty = max number allowed in the 1678MCC LO Extension Shelf equipment
Acronym = label shown on CT
Table 49. Optical Modules involved in 1678MCC LO Extension Shelf
Type
Description
Acronym
STM–16
I–16.1 SFP – Intra–office (wl = 1310 nm)
SI161
1AA 00014 0004 (9007) A4 – ALICE 04.10
Notes:
ED
Q.ty
8
Q.ty = max number allowed per LA20 board
Acronym = label shown on CT
03
3AG 24163 BEAA PCZZA
531
395 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
15.2 Lower Order Adaptation Board 20G (LA20)
The LA20 board is used in the 1678MCC LO Shelf 160G partsystem which is introduced in 1678 Metro
Core Connect. The main purpose of this new partsystem is to build a 4/3/1 cross connect designed for the
ETSI and ANSI Market.
The LA20 board implement the first and third stage of low order matrix together with the so called adaptation function (High Order path termination and adaptation function). One LA20 board has a capacity of
20Gb/s and is 1:n (1<n<7) protected.
Two LA20 groups are possible.
15.2.1 Lower Order Matrix
The lower order matrix is a three stage matrix which is distributed over 2 types of boards.
–
–
Low Order Adaptation and endstage matrix board (LA20)
Low Order CS Matrix Boards (LX160, LO functionality)
The effective switching capacity amounts to 20 Gbit/s per LA20 board.
The LA20 supports the following switching entities.
–
–
VC–3, VC–12, in SDH application
VC–11, STS–1, STS–3c, STS–12c in SONET application
Protection capabilities: SNCP/I and SNCP/N
15.2.2 Lower Order Adaption Function
The lower order adaption function is located between the interface to HO subsystem and the matrix function (refer to Figure 214. ). In other words these chips terminate the administrative units AU4 of an STM–64
byte serial stream in receive direction into lower order VC–n and multiplexes lower order VC–n in transmit
direction into the administrative units AU4 of an STM–64 byte serial stream.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The lower order adaption function supports fault detection, alarm generation and performance monitoring
for higher and lower order.
The chip set of this function is furthermore SONET compliant. For instance the chips are capable to terminate administrative units AU3 and to process virtual tributaries VT1.5. The chips additionally support
AU3/AU4 conversion. These functionalities are used for SONET and SDH/SONET interworking.
ED
03
3AG 24163 BEAA PCZZA
531
396 / 531
LA20
Backplane
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
LO Adaptation
and Monitoring
Interface
to HO
Subsystem
Matrix
Figure 214. LA20 Functional Overview
Data Connections
The data connections between higher order matrix and the lower order matrix board are done via differential signal lines over the backplane at 2.5 Gb/s .
Synchronization and Clock Distribution
The LA20 board receives two 38 MHz clock signals (Copy_A and Copy_B) and two 38MBit/s data signals
(Copy_A and Copy_B). These synchronization signals are led to VIVALDI ASIC, which performs the synchronization function. The data signal comprises frame and multiframe information (1Hz/8kHz) to synchronize the board to the 1678MCC internal framing. The data signal is read by the 38 MHz clock. The
38 MHz clock is also used to generate the 622 MHz system clock by means of a VCO.
Power Subsystem
There are two independent power interface inputs, each coming from a PSF board.
On the LA20 board there are four central DC/DC converters (48V to 1.2/5V) and four point of load (POL)
converters (5 V to 1.5/1.8/2.5/3.3 V). An inrush current limitation circuit and a filter are provided in front
of the central DC/DC converters for current limitation when the board is plugged in. A central DC/DC power
converter provides a galvanically isolated power (5 V) to the POL converters. The POL converters deliver
the various voltages:
–
–
–
–
1.5 V
1.8 V
2.5 V
3.3 V
1AA 00014 0004 (9007) A4 – ALICE 04.10
used by the ASICs and FPGAs on the LA20 board.
The front panel is shown in Figure 74. on page 141.
ED
03
3AG 24163 BEAA PCZZA
531
397 / 531
STM 16
16
2MHz ref clk bus
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
32
WSE
2.5 Gb/s
4
1
TUPP
4
IS
M
opt.
SFP
#1
2.5 Gb/s
STM 16
M
DAFFODIL
6
CLK
Rx Clocks
Center
Stage
STM 16
4
32
VIVALDI
WSE
16
4
1
2.5 Gb/s
TUPP
OS
M
2.5 Gb/s
STM 16
M OH
OH link
M
opt.
SFP
#8
OH link
HAWK
DOVE
OH link
DCC
HW cfg
SPI A
GOBLIN
−48v/60v A+B
SPI B
DC/DC
OBPS
Service
voltage
3,3v
1AA 00014 0004 (9007) A4 – ALICE 04.10
M=MotorolaBus
0v A+B
GND (FPE)
ISPB
Figure 215. LA20 Board Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
398 / 531
15.3 Lower Order Matrix 160 Gbit/s Board
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
15.3.1 Functional description
15.3.1.1 Overview
The Unit ’LO Centerstage Matrix 160GBIT/S’ provides SONET/SDH switching capabilities, implementing
MSPC (Multiplex Section Protection Connection) and HPC (Higher Order Path Connection) switching
functions.
The unit will be used in the 1678 Metro Core Connect (1678MCC). The 1678MCC equipment can host
up to two ’LO CENTERSTAGE MATRIX 160GBIT/S’ Units; in this case, only one ’LO CENTERSTAGE MATRIX 160GBIT/S’ Unit at a time is active, the other one is standing by.
The Matrix board supports the following functionalities:
•
Cross–connection with STS–1 granularity of up to 1024 STM–1 signals (3072 signals at AU3
level), non blocking
Synchronization (Clock Reference Unit)
Shelf Controller (SC)
1+1 EPS protection scheme (when two LX160 boards are present)
•
•
•
15.3.1.2 Features
The Matrix board address the following functional requirements:
•
•
•
•
•
•
Management of 256 bi–directional links @ 2.5/2.7 Gbit/s
Forward Error Coding (FEC) protection of the 256 links through the backpanel
Payload Performance Monitoring (PM)
Traffic SubNetwork Connection Protection (SNCP)
Clock Reference Unit (CRU) of SDH quality
Shelf Controller (SC)
1AA 00014 0004 (9007) A4 – ALICE 04.10
LO Centerstage Matrix 160G
High
Order
Matrix
Control Signals
Synchronization
Signals
Port Payload Links
A functional block diagram with indication of main internal and external interfaces is shown in Figure 216.
For further details about how the MSPC and HPC functions are implemented from a logical point of view
to fulfil the ITU–T G.783 functional model.
Shelf
Controller
SDH
Equipment
Clock
Power
Supply
Figure 216. LO Centerstage Matrix Board Functional Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
399 / 531
15.3.2 Physical Description
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The physical description of the LX160 board is similar to the MX640 board. Only the switching capacity
is different (refer to chapter 14.6.2 on page 349).
ED
03
3AG 24163 BEAA PCZZA
531
400 / 531
15.4 Alarm Board (ALM)
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
15.4.1 Functional description
15.4.1.1 Overview
The Alarm board is used in the 1678MCC LO Shelf 160G partsystem. One Alarm board per LO shelf is
necessary. The ALM board is mandatory because it has to provide the supervision of the step–up converters for the LO shelf. Also the service voltage have to be supervised via a backplane signal from PSF boards
like on the FLC. The ALM board functionality is a subset of the FLCCONGI board.
The ALM provides the following functionalities:
–
–
–
–
Rack alarm interface
Housekeeping inputs and outputs
Alarm lamps interface
Power supervision.
15.4.1.2 Rack Alarms Interface
The Rack Alarms (RA) interface provides a number of galvanically insulated output contacts, reporting the
status of some equipment–related alarms. The outputs are realized with electronic switches which can
close or open a contact toward the independent housekeeping output ground similarly. The physical access to the interface is provided through a Sub–D 25 poles female connector, accessible on the unit front
panel.
15.4.1.3 Housekeeping Interface
The ALM board provides a set of generic, programmable, parallel I/O contacts, physically available from
the same Sub–D 25–poles female connector used also for the rack alarms interface.
There are 8 housekeeping inputs and 4 housekeeping outputs available from the ALM board.
15.4.1.4 Rack Lamp Interface
The rack lamps interface provides a set of galvanically insulated contacts which allows to control a number
of rack lamps . these contacts are controlled by the SPIDER device parallel ports according to the main
internal alarms status of the equipment contained in a rack thus showing a summary of the shelves status.
The lamps are controlled by closing or opening the related contacts toward the separate rack lamps
ground.
The main electrical characteristics are summarized below:
–
–
–
–
–
–
Normally open contacts
Voltage polarity independent ;can accept either AC or DC signals
Maximum load current 120 mA
Open contact resistance > 50 MΩ
Closed contact < 1 Ω
X_RCH : Is not active of the ALM board
1AA 00014 0004 (9007) A4 – ALICE 04.10
Note: The rack lamp interface functionality is done under SW control.
ED
03
3AG 24163 BEAA PCZZA
531
401 / 531
15.4.1.5 Features
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The Alarm board address the following functional requirements:
–
–
–
–
–
–
–
–
–
Battery supervision , Input from the PSF board
Battery fail displayed ( Batt_A and Batt_B fail ) via X_TAND/X_GND_RA contact
3.6V service voltage for SPI devices and glue logic
Housekeeping I/O (with internal galvanic isolated power supply):
•
8 inputs
•
4 outputs
Alarm lamps
Alarm contacts
House keeping (HK) I/O and alarm contacts (RA) connector on front side
Rack lamps connector (RL) on front side
Supervision of all internal voltages
A functional block diagram with indication of main internal and external interfaces is shown in Figure 217.
15.4.1.6 Power Subsystem
1AA 00014 0004 (9007) A4 – ALICE 04.10
The Alarm board gets its power supply of 48/60 V from the back panel and generates the 3.6 V service
voltage for SPI devices.
ED
03
3AG 24163 BEAA PCZZA
531
402 / 531
Fuses
− 48/60V
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Input Power
+ 48/60V
Inrush Current Limitation & EMC
48/60V
POWER_LAMP
+12V
Rack
Lamp
CMISS
URG_LAMP
NURG_LAMP
M_LAMP
from PSF
Lamptest
Rack
Alarm
POWER
FAIL
V3V_A
V3V_B
Fuse
TS
RA
RA_GND
House
Keeping
In/Out
HK_OUT
HK _IN
HK_GND
3
RIM
2
2
STATUS_LED
Spider
MRXDA
3
3
A
SPI bus
B
SPI bus
MRXDB
URG_LED
NURG_LED
ATTD_LED
ABN_LED
IND_LED
Board_ID
Quit push button
BATFAIL_A1..3
BATFAIL_B1..3
V3VAKO
V3VBKO
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 217. ALM Board Functional Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
403 / 531
15.5 Power Supply and Filter Board (PSF)
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
This board is already described in chapter 14.4 on page 343.
15.6 Bus Termination Board (BUSTERM)
This board is already described in chapter 14.5 on page 346.
ED
03
3AG 24163 BEAA PCZZA
531
404 / 531
16 UNITS DESCRIPTIONS OED SHELF 1670SM
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
16.1 Introduction
The following Table 50. on page 405 and Table 51. on page 405 sums up the units managed in the
1670SM Shelf Equipment.
Table 50. Units involved in 1670SM
Type / Class
Description
Acronym
Width (mm)
Q.ty
CONGIHC
40
2
Equipment Controller
EQUICO
20
1
Bus Termination
BTERM
40
1
Matrix
Matrix HiCap
HCMATRIX
52
2
LINK
Optical Link Enh
HCLINKE
40
8
SDH Port
STM–4
4xSTM–4
P4S4N
20
16
SDH Port
STM–1
16xSTM–1 optical
P16OS1
20
16
16xSTM–1 electrical
P16S1N
4xSTM–1 electrical
P4ES1N
SDH Port
4x140 MBit/s
P4E4N
20
16
SDH Access
2xSTM-4
A2S4
20
16
SDH Access
STM–1
12xSTM-1 optical
A12OS1
20
16
16xSTM-1 electrical
A16ES1
4xSTM-1 electrical
A4ES1
SDH Access
2x140 MBit/s
A2S1
20
16
FAN Unit
FAN
FAN
––
2
Control / Common Control and General Interfaces
Table 51. Pluggable Modules involved in 1670SM
Type
Description
Acronym
140 MBit/s
140/155 electrical interface
ICMI
64
STM–1
S–1.1 OPTIC – Short Haul (wl = 1310 nm)
IS–1.1
256
L–1.2 OPTIC – Long Haul (wl = 1550 nm)
IL–1.2
S–4.1 OPTIC– Short Haul (wl = 1310 nm)
IS–4.1
L–4.1 OPTIC – Long Haul (wl = 1310 nm)
IL–4.1
L–4.2 OPTIC – Long Haul (wl = 1550 nm)
IL–4.2
1AA 00014 0004 (9007) A4 – ALICE 04.10
STM–4
ED
Q.ty
64
03
3AG 24163 BEAA PCZZA
531
405 / 531
16.2 STM-1 Electrical I/O Interface
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
16.2.1 4xSTM-1Electrical I/O Interface
The I/O Port board 4xSTM-1 electrical (P4ES1N) manages up to four STM-1 data signals. The physical
access points to the four STM-1 signals are available on the related Access board (A4ES1).
16.2.1.1 Port Board P4ES1N
The SDH functions required to process the STM-1 signals are implemented by an Interface ASIC (refer
to Figure 218. ). It interfaces the two HiCap Matrix boards via the backpanel. The Interface ASIC sends
and receives four STM-1 signals (data + clock) at 155 Mbit/s to/from each SPI. An external LOS is received
from each input line interface.
Complying with the ITU-T G.783 Recommendation, the Interface ASIC performs the TTF function. The
TTF block is connected to the two HiCap Matrix boards (main and spare) by means of a bidirectional link
at 622 Mbit/s (STM-4 equivalent capacity) in 1+1 configuration. It performs the sink on Rx side and source
on Tx side for the termination of the STM-1 signals. In addition, the TTF block provides the T1 timing references at 2 MHz, derived from the STM-1 input signals.
The backpanel interface supplies redundant system clocks (SYST CK, a, b) to the internal circuits of the
Interface ASIC.
The PISO blocks provide the board interface to the backpanel at a bit rate of 622 Mbit/s.
The DC/DC Converter converts the 48/60 V power supply to the following voltages:
1AA 00014 0004 (9007) A4 – ALICE 04.10
–
–
ED
+2.5 V (to supply all components on the board)
+3.3 V (to supply all components on the board).
03
3AG 24163 BEAA PCZZA
531
406 / 531
Electrical
Input/
Output
2
SPI
Electrical
Input/
Output
3
SPI
Electrical
Input/
Output
4
SPI
1AA 00014 0004 (9007) A4 – ALICE 04.10
A4ES1
from/to
HiCap Matrix
Main and spare
System–clock b
1st INTERFACE
T1
TTF
STM–1
RST
LOS
MST
MSA
P
I
S
O
(3)
DCCM
MSOH
DCCR
RSOH
(4)
P
I
S
O
DCC
(3)
(4)
T1
3 rd INTERFACE
(3)
(4)
T1
4 th INTERFACE
(3)
(4)
T1
2nd INTERFACE
Config. &
Status
622 MHz
OSC
M-bus
Driver
Management
Bus
Bus–OFF
Remote
Inventory
RIBUS
I/F
Power
Sync
Unit
Failure
to
HiCap Matrix
Main and spare
1
SPI
System–clock a
Interface ASIC
RIBUS
from/to
HiCap Matrix
Main and spare
Electrical
Input/
Output
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ID
3.3 V
DC/DC
2.5 V CONVERTERS
48/60 V
P4ES1N
from
CONGIHC
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
Figure 218. Block Diagram 4xSTM-1 Electrical I/O Interface
ED
03
3AG 24163 BEAA PCZZA
531
407 / 531
16.2.1.2 Access Board A4ES1
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The Access board 4xSTM-1 Electrical (A4ES1) is located in the Access area and provides the connection
to the line by a coaxial cable for the electrical STM-1 I/O Port board.
Figure 219. depicts the block diagram of the Access board A4ES1.
Input Side
On the input side, the CMI coded signal coming from the coaxial cable is equalized, decoded into NRZ
code and forwarded to the electrical Port board.
The command criteria SWITCH from the RIBUS I/F block selects the MUX in order to send the local
streams towards the protection Port board.
LOS alarm, if detected, is sent to the Port board. It can also be sent through a MUX towards the protection
Port board if the SWITCH command is active.
Output Side
On the output side, the signal from the Port board is coded into CMI code and then sent toward the coaxial
cable.
When EPS is active, the RIBUS I/F block sends the SWITCH command to the MUX. In this case, the signals from the protection Port board are selected and sent toward the encoder NRZ/CMI.
Control Section
RI data, such as code, series number and construction data, can be read/written via the RIBUS I/F. It also
sends the following commands:
–
–
–
FSEL for frequency selection (not used)
CLOP for loopback facility
SWITCH for EPS facility.
1AA 00014 0004 (9007) A4 – ALICE 04.10
A red/green LED is provided for board fail alarm indication on the front cover plate.
ED
03
3AG 24163 BEAA PCZZA
531
408 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
CMI
Input
PLL
CMI
LOS
NRZ
NRZ
MUX
NRZ
toprotection
Portboard
NRZ
LOS
fromprevious
Accessboard
LOS
toprotection
Portboard
NRZ
NRZ
fromP ortboard
fromprotection
Portboard
SWITCH
MUX
ACCESS1−Inputside
Mask
Adapter
CMI
Output
CMI
NRZ
toP ortboard
SWITCH
MUX
PLL
NRZtonextAccessboard
SWITCH
FSEL
CLOP
ACCESS1−Outputside
CMI
Input
CMI
Output
ACCESS2
CMI
Input
ACCESS3
CMI
Output
CMI
Input
RIBUS
I/F
SWITCH
FAIL
Remote
Inventory
CLOP
FSEL
ACCESS4
CMI
Output
to/from
HiCapMatrixboard
RIBUS
A4ES1
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 219. Block Diagram Access Board 4xSTM-1 Electrical (A4ES1)
ED
03
3AG 24163 BEAA PCZZA
531
409 / 531
16.2.2 16xSTM-1Electrical I/O Interface
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The I/O 16xSTM-1e boards increase the I/O port board density by factor 4 and the I/O shelf density by
factor 2.
Similar to the I/O 4xSTM-1e used up to now, the I/O 16xSTM-1e interface functionality is implemented in
two boards:
–
–
Port board (P16S1N)
Access board (A16ES1).
Port Board P16S1N
The Port board P16S1N performs signal processing. A block diagram of this board is shown in Figure 221.
The port boards are located in the port area. The access boards are located in the corresponding access
area. Port and access boards are connected over the backpanel.
Both boards Access and Port are one slot wide (4TE).
Access Board
1
16xSTM91electrical
16
16xSTM91
Port Board
16
(A16S1)
16xSTM91 16xSTM91equiv.
(P16ES1)
Figure 220. Relation between Port Boards/Access Boards
Two configurations are supported:
–
EPS N+1 (with N=1 to 15) protected configuration
The protection is ensured by a protection board HPROT16 located in the access area and a protection port board 16xSTM-1e located in the port area.
–
Unprotected configuration
In this case, the protection boards HPROT16 and the I/O board 16xSTM-1e (P) are not equipped.
Access Board A16ES1
The access board A16ES1 provides 16xSTM-1e interfaces.
The A16ES1 is located in the access area and provides the connection to the 16xSTM-1 electrical I/O port
board.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The description of the functionalities is similar to 4xSTM-1 electrical access board (A4ES1) described in
section 16.2.1 on page 406.
ED
03
3AG 24163 BEAA PCZZA
531
410 / 531
System–clock a
System–clock b
HPOM
HSUT
Buffer
RST
MST
.
MSA
MAIN AND SPARE
TTF
4x
STM–1
from/to Access board
P
I
S
O
DCCM
MSOH
DCCR
RSOH
(1)
MATRIX
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Interface #1
4x
STM–1
Interface #2
4x
STM–1
Interface #3
4x
STM–1
Interface #4
DCC
622 MHz
OSC
(1)
FPGA
Management
Bus
M–BUS
Driver
Bus–OFF
Remote
Inventory
2.5 V
ID
48/60 V
DC/DC
CONVERTERS
1AA 00014 0004 (9007) A4 – ALICE 04.10
P16S1N
from
CONGIHC
Unit
Failure
3.3 V
RIBUS
RIBUS
I/F
Power
Sync
from/to
MATRIX MAIN AND SPARE
Config. &
Status
Figure 221. Block Diagram 16xSTM-1 Electrical I/O Interface
ED
03
3AG 24163 BEAA PCZZA
531
411 / 531
16.3 STM-1 Optical I/O Interface
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
16.3.1 4xSTM-1Optical I/O Interface
The I/O Port board 4xSTM-1 optical (P4S1N) manages up to four STM-1 data signals. The physical access
to the four STM-1 signals is performed by optical I/F modules. Two modules are inserted in the related
Access board (A4S1), two in the Port board itself.
16.3.1.1 Port Board P4S1N
The SDH functions required to process the STM-1 signals are implemented by an Interface ASIC (refer
to Figure 222. ). It interfaces the two HiCap Matrix boards via the backpanel. The Interface ASIC sends
and receives four STM-1 signals (data + clock) at 155 Mbit/s to/from each SPI. An external LOS is received
from each input line interface.
Complying with the ITU-T G.783 Recommendation, the Interface ASIC performs the TTF function. The
TTF block is connected to the two HiCap Matrix boards (main and spare) by means of a bidirectional link
at 622 Mbit/s (STM-4 equivalent capacity) in 1+1 configuration. It performs the sink on Rx side and source
on Tx side for the termination of the STM-1 signals. In addition, the TTF block provides the T1 timing references at 2 MHz, derived from the STM-1 input signals.
The backpanel interface supplies redundant system clocks (SYST CK, a, b) to the internal circuits of the
Interface ASIC.
The PISO blocks provide the board interface to the backpanel at a bit rate of 622 Mbit/s.
Each optical transmitter reports its status to the Interface ASIC by means of the two input signals “Laser
Degrade” and “Laser Failure”.
The Automatic Laser Shutdown (ALS) algorithm is implemented by the hardware and provides the laser
shutdown command “Laser OFF” to the Interface ASIC.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The DC/DC Converter converts the 48/60 V power supply to the voltages +2.5 V and +3.3 V to supply all
components on the board. It is synchronized with a synchronization clock at 300 kHz (signal “Power Sync”,
generated by the Interface ASIC) in order to prevent EMI problems.
ED
03
3AG 24163 BEAA PCZZA
531
412 / 531
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌ
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Interface ASIC
System clock a
1st INTERFACE
SPI
Optical
module
Optical
Input/
Output
2
Optical
Input/
Output
3
Optical
Input/
Output
4
LOS
LASER D.
LASER F.
LASER OFF
RST
MST
MSA
DCCM
MSOH
DCCR
RSOH
(4)
2ndINTERFACE
INTERFACE
2nd
Optical
module
P
I
S
O
(3)
3 rd INTERFACE
Optical
module
4 th INTERFACE
Optical
module
P
I
S
O
(3)
(4)
T1
(3)
(4)
T1
(3)
(4)
T1
Config. &
Status
622 MHz
OSC
DCC
Management
Bus
M-bus
Driver
Bus–OFF
Remote
Inventory
3.3 V
2.5 V
A2S1
RIBUS
RIBUS
I/F
Power
Sync
Unit
Failure
to
HiCap Matrix
Main and spare
STM–1
from/to
HiCap Matrix
Main and spare
1
TTF
ID
48/60 V
DC/DC
CONVERTERS
from
CONGIHC
Optical
Input/
Output
T1
from/to
HiCap Matrix
Main and spare
System clock b
P4S1N
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 222. Block Diagram 4xSTM-1 Optical I/O Interface
ED
03
3AG 24163 BEAA PCZZA
531
413 / 531
16.3.1.2 Access Board A2S1
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The Access board 2xSTM-1 Optical (A2S1) is located in the Access area and provides the connection to
the line by a fiber cable for the optical STM-1 I/O Port board.
Figure 223. depicts the block diagram of the Access board A2S1.
CLOP
INPUT
LOS
LASER DEG
LINE1
LASER FAIL
OPTICAL
MODULE
SHUT DOWN
OUTPUT
DATA AND CLOCK
to/from
Port board
CLOP
INPUT
LOS
LASER DEG
LASER FAIL
OPTICAL
MODULE
SHUT DOWN
OUTPUT
FAIL
DATA AND CLOCK
REMOTE
INVENTORY
to/from
Port board
CLOP
LINE2
to/from
HiCapMatrixboard
RIBUS
I/F
RIBUS
A2S1
Figure 223. Block Diagram Access Board 2xSTM-1 Optical (A2S1)
1AA 00014 0004 (9007) A4 – ALICE 04.10
The Access board A2S1 houses up to two independent optical modules.
ED
03
3AG 24163 BEAA PCZZA
531
414 / 531
Control Section
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
RI data, such as code, series number and construction data, can be read/written via the RIBUS I/F. It also
sends the following command:
–
CLOP for loopback facility.
A red/green LED is provided for board fail alarm indication on the front cover plate.
16.3.1.3 STM-1 Optical Module
The STM-1 Optical module represents the physical access for the optical I/O Port board STM-1. Each
module provides the optical RX and TX module with level adapter, Remote Inventory and Laser Restart
button. Different Optical modules are available according to the connector type and wavelength.
EDR
Optical
Input
Rx optical module
Data in
Level
ECKR
Adapter
Clock in
LOS
EDT
ECT
Optical
Output
Tx optical module
Data out
Level
Adapter
Clock out
Laser Failure
LaserRestart
Laser Degrade
Shutdown
Optical Module
Remote
Inventory
toRIBUSI/F
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 224. Block Diagram STM-1 Optical Module
ED
03
3AG 24163 BEAA PCZZA
531
415 / 531
16.3.2 16xSTM-1 Optical I/O Interface
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The I/O 16xSTM-1o boards increase the I/O port board density by factor 4 and the I/O shelf density by
factor 2.
Similar to the I/O 4xSTM-1o used up to now, the I/O 16xSTM-1o interface functionality is implemented in
two boards:
–
–
Port board (P16OS1)
Access board (A12OS1).
Port Board P16OS1
The port board P16OS1 which provides 4 STM-1o interfaces performs signal processing of all the 16 signals.
The port boards are located in the port area. The access boards are located in the corresponding access
area. Port and access boards are connected over the backpanel.
Both boards (access and port) are one slot wide (4TE).
All optical modules are Small Form Pluggable (SFP) modules. They are different of those used in the
4xSTM-1o boards. These optical modules can be equipped in a flexible way (1 to 4 optical modules).
Only the S-1.1 interface is supported. The connectors are LC.
Otherwise the description of the functionalities is similar to 4xSTM-1o port board (P4S1N) described in
section 16.3.1 on page 412.
The relation between port board (P16OS1) and access board (A12OS1) is shown in Figure 225.
Access board
1
16xSTM–1o
interfaces
.
.
.
. 12
.
.
Port board
1 slot
12xSTM–1o
(A12SO1)
1 slot
.
.
.
.
16xSTM–1o
16xSTM–1equiv.
1
(P16OS1)
4
SFP module S–1.1
Figure 225. Relation between Port Boards/Access Boards
Access Board A12OS1
The access board A12OS1 provides 12xSTM-1o interfaces (SFP modules).
The A12OS1 is located in the access area and provides the connection to the 16xSTM-1o I/O port board.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The description of the functionalities is similar to 4xSTM-1o access board (A2S1) described in section 16.3.1 on page 412. But the A12OS1 supports up to 12 optical modules (compared to two). These
optical modules are Small Form Pluggables (SFPs) and can be equipped in a flexible way (1 to 12 optical
modules).
ED
03
3AG 24163 BEAA PCZZA
531
416 / 531
16.4 I/O Port Board STM-4
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The I/O Port board STM-4 (S4) manages one optical STM-4 data signal. The physical access is performed
by an optical module on the board.
The Port board S4 is available in variants S-4.1 (Short haul, 1300 nm), L-4.1 (Long haul, 1300 nm) and
L-4.2 (Long haul, 1500 nm), all with FC/PC or SC/PC connectors. The variants identified by JE (Joint Engineering) have better optical characteristics, typically for the dispersion values and sensitivity.
The SDH functions required to process the STM-4 signals are implemented by an Interface ASIC (refer
to Figure 226. ). It interfaces the two HiCap matrix boards via the backpanel.
Complying with the ITU-T G.783 Recommendation, the Interface ASIC performs the TTF function. The
TTF block is connected to the two HiCap matrix boards (A and B) by means of a bidirectional link at
622 Mbit/s (STM-4 equivalent capacity) in 1+1 configuration. It performs the sink on Rx side and source
on Tx side for the termination of the STM-4 signal. In addition, the TTF block provides the T1 timing references at 2 MHz, derived from the STM-4 input signal.
The backpanel interface supplies redundant system clocks (SYST CK, a, b) to the internal circuits of the
Interface ASIC.
The Interface ASIC sends and receives one STM-4 signal (data + clock) at 622 Mbit/s to/from the SPI. The
SPI is able to detect an external LOS from the input line. The optical transmitter reports its status to the
Interface ASIC by means of the two input signals “Laser Degrade” and “Laser Failure”. The ALS algorithm
is implemented by the hardware on the O/E block and provides the Laser shut down command “Laser
OFF” to the Interface ASIC. A push-button is provided for manual laser restart on the board’s front panel.
The DC/DC Converter converts the 48/60 V power supply to the following voltages:
–
–
–
+2.5 V (to supply all components on the board)
+3.3 V (to supply all components on the board)
–5.2 V (to supply the optical module).
1AA 00014 0004 (9007) A4 – ALICE 04.10
The DC/DC converter is synchronized with a synchronization clock at 300 kHz (signal ’Power Sync’, generated by the Interface ASIC) in order to prevent EMI problems.
ED
03
3AG 24163 BEAA PCZZA
531
417 / 531
System–clock a
from/to
Matrix board A and B
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
System–clock b
Interface ASIC
TTF
Optical
Input/
Output
K1,K2
Tx side
Insertion
STM–4
O/E SPI
Optical
module
LOS
LASER D.
LASER F.
RST
DCCR
RSOH
MST
K1,K2,TP
Rx side
Insertion
MSA
DCCM
MSOH
DCC
Config. & Status
Laser Restart
Management
Bus
M-bus
Driver
from/to
Matrix board A and B
622 MHz
OSC
Bus–OFF
Power
Sync
–5.2 V
3.3 V
2.5 V
DC/DC
CONVERTERS
RIBUS
RIBUS
I/F
ID
Unit
Failure
from
CONGIHC
Remote
Inventory
48/60 V
S4
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 226. Block Diagram Optical STM-4 I/O Port Board
ED
03
3AG 24163 BEAA PCZZA
531
418 / 531
16.5 I/O Port Board 4xSTM-4
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The description of the 4xSTM-4 Port board is similar to I/O STM-4 Port board, refer to section 16.4
The I/O Port board 4xSTM-4 (P4S4N) manages four optical STM-4 data signals. The physical access to
the four STM-4 signals is performed by optical IF modules. Two modules are inserted in the related Access
board (A2S4), two in the Port board itself.
The I/O Port board 4xSTM-4 (P4S4N) is available in variants S-4.1 (Short haul, 1300 nm), L-4.1 (Long
haul, 1300 nm) and L-4.2 (Long haul, 1500 nm), all with FC/PC or SC/PC connectors. The variants identified by JE (Joint Engineering) have better optical characteristics, typically for the dispersion values and
sensitivity.
16.5.1 Port Board P4S4N
The SDH functions required to process the STM-4 signals are implemented by the GAs mounted on the
board. They interfaces the two HiCap matrix boards via the backpanel.
16.5.1.1 Access Board A2S4
The Access board 2xSTM-4 optical is located in the Access area and provides two additional connections
to the line.
The Access board A2S4 houses up to two independent optical modules. Figure 227. depicts the block
diagram of the Access board A2S4.
A2S4
CLOP
LOS
INPUT
LINE1
STM94
LASER DEG
OPTICAL
MODULE
LASER FAIL
SHUT DOWN
OUTPUT
DATA AND CLOCK
to/from
Port board
CLOP
INPUT
LOS
LASER DEG
STM94
LASER FAIL
OPTICAL
MODULE
SHUT DOWN
OUTPUT
FAIL
DATA AND CLOCK
1AA 00014 0004 (9007) A4 – ALICE 04.10
REMOTE
INVENTORY
to/from
Port board
CLOP
LINE2
to/from
Matrix board
RIBUS
I/F
RIBUS
Figure 227. Block Diagram Access Board 2xSTM-4 Optical (A2S4)
ED
03
3AG 24163 BEAA PCZZA
531
419 / 531
16.5.2 STM-4 Optical Modules
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The STM-4 optical modules represent the optical physical accesses for the 4xSTM-4 Port board (P4S4N),
refer to Figure 228.
The optical module houses in the Access board A2S4 and in the Port board P4S4N.
Up to two optical modules houses in the Access board A2S4 and in the Port board P4S4N.
Each module provides the optical RX and TX module with level adapter, Remote Inventory and Laser Restart button. Different optical modules are available according to the connector type and wavelength.
OPTICAL
INPUT
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌ
EDR
RX Optical Module
Data
in
Clock in
Level
ECKR
Adapter
LOS
OPTICAL
OUTPUT
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌ
EDT
ECT
Data out
Level
Clock out
Adapter
TX Optical Module
Laser Failure
Laser Restart
Laser Degrade
Shutdown
Remote
to RIBUS IF bus
Inventory
Optical Module
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 228. Block Diagram STM-4 Optical Module
ED
03
3AG 24163 BEAA PCZZA
531
420 / 531
16.6 4x140 Mbit/s Port Board (P4E4N)
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The 4x140 Mbit/s Port board is a bidirectional unit which interfaces up to four plesiochronous 140 Mbit/s
(E4).
The choice among the two possible different interfaces is flexible and mixed configuration are allowed.
For each P4E4N Port board there are four electrical (75 Ohm) or optical module (Short and Long Haul);
two of the four module are hosted directly on the port board, the other two are hosted in the relevant access
board (A2S1).
The functions required to manage 140 Mbit/s PDH signals are implemented by the “Mapper/Demapper
140-PDH/155-STM-1” block and GA mounted on the board. The GA interfaces the two matrix on the HiCap
matrix boards via backpanel.
ED
03
3AG 24163 BEAA PCZZA
531
421 / 531
System–clock a
System–clock b
HiCap Matrix
A and B
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
G.A.
1st INTERFACE
Int.
Loop
Line
Loop
O/E
Input/
Output
1
EN 140/155
O/E LOS
Module
SPI
or
PPI
Data
MAPPER/DEMAPPER
140–PDH/155–STM1
T1
HPOM
HSUT(*)
LOS
TTF
RST
MST
(3a)
(3b)
(3c)
(3d)
Data
DCCR
RSOH
LASER D.
LASER F.
LASER OFF
MSA
DCCM
MSOH
PISO
&
SIPO
(4a)
PISO
&
SIPO
(4b)
(4c)
(4d)
DCC
O/E
Input/
Output
2
2nd INTERFACE
(3b)
(4b)
EN 140/155
3 rd INTERFACE
(3c)
(4c)
EN 140/155
SPI
( )
(3d)
(4d)
4 th INTERFACE
EN 140/155
622 MHz
OSC
Power
Sync.
T1
Config. &
Status
Remote
Inventory
T1
Management
Bus
M–BUS
Driver
CMISS
Bus–OFF
RIBUS
EN 140/155 1–4
Line Loop 1–4
Int. Loop 1–4
1.8 V
5V
A2S1
ACCESS
CARD
3.3 V
DC/DC
CONVERTERS
Hicap Matrix
A and B
SPI
( )
O/E
Input/
Output
4
T1
RIBUS
I/F
ID
F
Unit failure
+3.3 Vdc
48/60 V
2.5 V
P4E4N
FROM/TO
FROM CONGI HC HiCap Matrix A and B
O/E
Input/
Output
3
Notes:
1AA 00014 0004 (9007) A4 – ALICE 04.10
The SPI associated to the 3rd and 4th interfacees are physically on the Access board
Figure 229. P4E4N Port Board Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
422 / 531
16.6.1 2x140 Mbit/s Access Board (A2S1)
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The 2x140 Mbit/s A2S1 Access board is placed in the Access area of Main Shelf (MS).
The Access board A2S1 can house two independent modules that can be both electrical, both optical or
a mix of the two.
The Access board houses also the RIBUS I/F block function.
CLOP
LOS
INPUT
LASER DEG
LASER FAIL
ELECTRICAL
LINE1
SHUT DOWN
to/from
PORT CARD
MODULE
OUTPUT
DATA AND
CLOCK
ICMI
CLOP
INPUT
LOS
LASER DEG
ELECTRICAL
LINE2
LASER FAIL
SHUT DOWN
MODULE
OUTPUT
DATA AND
CLOCK
CLOP
FAIL
ICMI
REMOTE
INVENTORY
to/from
PORT CARD
to/from
MATRIX
RIBUS
I/F
RIBUS
A2S1 Access Board
Figure 230. A2S1 Access Board Block Diagram
16.6.2 140 Mbit/s Electrical Module (ICMI)
The electrical modules are housed in the Access board A2S1 and in the Port board P4E4N.
Up to two modules can be housed in A2S1 and P4E4N.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The module contains:
–
–
ED
a CMI interface (CMI/NRZ decoder and NRZ/CMI encoder)
a Remote Inventory block.
03
3AG 24163 BEAA PCZZA
531
423 / 531
LOS
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
RX side
Coax Input
DATA RX
CMI/NRZ
DECODER
CLOCK RX
DATA TX
TX side
Coax Output
NRZ/CMI
CLOCK TX
ENCODER
Remote
to RIBUS I/F block
Inventory
ICMI Module
Figure 231. ICMI Module Block Diagram
OMI Interface
INPUT side : the CMI electrical signal coming from the line is NRZ decoded (clock + data). The LOS alarm
is revealed.
OUTPUT side : the NRZ signal coming from the port (data + clock) is CMI coded to be sent to the line.
Remote Inventory
1AA 00014 0004 (9007) A4 – ALICE 04.10
The Remote Inventory is implemented on an E2PROM. Inventory data as code, series number, construction date are stored inside the E2PROM and can be read through the RIBUS I/F block.
ED
03
3AG 24163 BEAA PCZZA
531
424 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
16.7 High Speed Port Protection Using HPROT and HPROT16 Boards
The High speed Protection (HPROT) board is located in the Access area and provides EPS protection for
electrical high speed ports. It realizes the connection between the Access boards and protection Port
board (electrical) if protection is requested.
There are available two protection access boards:
–
–
HPROT
It is used in conjunction to A4ES1 access board + P4ES1N port board. It is needed for EPS protection
on 4xSTM-1 electrical board.
HPROT16
It is used in conjunction to A16ES1 access board + P16S1N port board. It is needed for EPS protection on 16xSTM-1 board.
These modules have to be placed in correspondence of spare port board. The general functionality of
HPROT and HPROT16 is the same. Figure 232. shows the HPROT board. The HPROT16 is similar, it
has got 16 blocks instead of 4.
The next chapters describe only the HPROT board.
The HPROT board connects up to four electrical high speed data streams from/to the neighbored last Access board related to the protected Port board group.
from/to the last
Access board related to the
protected Port board group
NRZ
CK
NRZ
CK
LOS
NRZ
CK
NRZ
CK
LOS
from/to
protection Port board
from/to the last
Access board related to the
protected Port board group
NRZ
CK
NRZ
CK
LOS
NRZ
CK
NRZ
CK
LOS
from/to
protection Port board
from/to the last
Access board related to the
protected Port board group
NRZ
CK
NRZ
CK
LOS
NRZ
CK
NRZ
CK
LOS
from/to
protection Port board
from/to the last
Access board related to the
protected Port board group
NRZ
CK
NRZ
CK
LOS
NRZ
CK
NRZ
CK
LOS
from/to
protection Port board
FAIL
to/from
HiCap Matrix board
Remote
Inventory
RIBUSI/F
RIBUS
1AA 00014 0004 (9007) A4 – ALICE 04.10
HPROT
Figure 232. Block Diagram HPROT Board
ED
03
3AG 24163 BEAA PCZZA
531
425 / 531
Control Section
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
RI data, such as code, series number and construction data, can be read/written via the RIBUS I/F. A red/
green LED is equipped for board fail alarm indication on the front cover plate.
High Speed (HS) Port Protection
The 1670SM shelf is designed to handle STM-1 electrical Ports (High Speed Ports) with N+1 (N = up to
15) Equipment Protection Switching (EPS) or no protection of the STM-1 Port boards. Up to 16 HS Port
boards can be housed in the Port area. There are 4 High Speed Ports per STM-1 Port board. It supports
up to 60 STM-1 ports (working ports per shelf) plus 4 STM-1 protection ports in case of EPS. This leads
to a maximum of 15 working boards and one protection board per 1670SM shelf (15+1 protection).
In the 1670SM shelf, the protection Port board needs to be a related High-speed Protection (HPROT)
board in the Access area (slot 4). In case of no EPS, the protection board and the HPROT board have to
be omitted.
The constraints for the main/protection Port boards are the following:
–
–
–
–
The Access board corresponding to the protecting board must be an HPROT Access board
The HPROT board has to be plugged at the left side of the Access board group (A4ES1)
The protection Port board has to be plugged in at the left side adjacent to the protected Port board
group (P4ES1N).
The protection Port board and the Port boards of the protected group have to be of the same type.
Note that no protection is planned for the Access boards, and note also that the type of protection can not
be changed (i.e. it isn’t possible to change the protection scheme from N+1 to 1+1).
Manual Switch and force switch commands can be given via software by the user to activate the protection
boards. The protections status is reported to the EC.
High Speed Connections
Each Access board is connected also with the previous one and next one in both the receive and transmit
direction; this way, N+1 protection is provided using the HPROT board in last position at the left side of
the Access boards pertaining to the protected Port board group.
The Port boards P4ES1N manage up to 4 HS signals. Protection is always enabled for all HS signals of
the switched Port board.
Input Side (from the Access Module Point of View)
The CMI encoded STM-1 signals coming from the line and connected to the Access board are NRZ decoded. The clock CK is extracted from the data. By means of the back panel connections, NRZ data and
CK are forwarded to both the pertaining main Port board and to the next Access board in the direction to
the protection Port board.
Output Side (from the Access Module Point of View)
1AA 00014 0004 (9007) A4 – ALICE 04.10
The signal, coming from main and protection ports via back panel connections, is coded into the line format
(CMI).
The protection port is not devoted to a specific main port, therefore the signal transmitted from the protection Port board is distributed to all Access boards involved in the protection scheme. The connections are
functionally point-to-multipoint but physically every Access board realizes a point-to-point connection towards the previous and the next Access board using a buffer to decouple and regenerate the signal.
ED
03
3AG 24163 BEAA PCZZA
531
426 / 531
EPS Switching Causes
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The hardware failures causing automatic EPS protection switch can be grouped as:
–
–
–
failures causing the internal equipment link loss as powering, Clock loss, board missing (referred as
LOS/LOF);
failures causing traffic loss (the internal link is preserved) as for instance unlocked oscillator, optical
module defective, electrical interface defective and so on;
failures not causing traffic loss nor internal link loss but causing loss of management as RIBUS failure
or M-bus failure.
Moreover some failures can cause equipment malfunctioning (as remote inventory fault, loss of DC/DC
synchronism).
These hardware faults are signalled to the management system and do not provokes an automatic switch.
ED
03
3AG 24163 BEAA PCZZA
531
427 / 531
16.8 Optical Link Enhanced (HCLINKE)
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Main functions and configuration
The HCLINKE board is a 10 Gbit/s interface port aimed at connecting together a 1670SM to the 1678MCC
main shelf.
The HCLINKE is hosted in a dedicated section of the 1670SM, located in the lower row, named Link Area.
Up to eight HCLINKE can be hosted in one 1670SM (four “main” and four “spare”).
The HCLINKE board can be put in the link area of the 1670SM: the roles of the main and the spare boards
and their positions are fixed (refer to chapter 12.1.2 on page 148).
Two GA (#1 to #2) are used and they provide the following capabilities:
•
•
1xSTM–64 sections (with full SDH functionalities) is generated and terminated
manage ALS
The connection between 1670SM and 1678MCC is MSP protected:
•
a Multiplex Section Protection (in according to the K1–K2 APS standard protocol) dual–ended
is implemented.
The MSP protection scheme is automatically created at the board configuration, but the following simple
rule has to be followed: the board HCLINKE spare has to be created after (and deleted before) the corresponding HCLINKE main.
Description
The main functions are: regenerator section termination, multiplex section termination and section adaptation. The GA directly interface the backplane and the optical devices. The two GA are connected to ISPB
bus via a common GTLP to TTL level converter interface.
Each HCLINKE is connected to HCMATRIX/A and HCMATRIX/B. The throughput of each interconnection
is 10 Gbit/s, obtained via 16 differential LVDS connections at 622 Mbit/s. Each HCLINKE receives from
each matrix a dedicated 622 MHz clock in LVDS format.
Each HCLINKE is connected also to the control subsystem of the 1670SM equipment, i.e.:
•
•
Intra Shelf Parallel Bus (ISPB), mastered by the active HCMATRIX
Serial Peripheral Bus (SPI) A and B, mastered by HCMATRIX/A and /B
The ISPB allows for the access to the contents of the internal registers of the ASICs hosted on the
HCLINKE board.
The SPI busses are terminated on the board via a ’Spider’ device which allows for the read and write of
some provisioning and alarms available on the board.
Each LINK slot has a ’board presence’ pin which allows the HCMATRIX boards to detect the presence of
the board.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The HCLINKE board has an optical interface which has an aggregate bandwidth of 10 Gbit/s bi–directional
for the connection to the 1678MCC main shelf.
ED
03
3AG 24163 BEAA PCZZA
531
428 / 531
Transmission resources
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The following transmission features are supported:
•
All transmission features at the VC–4 path layer are supported for the HCLINKE board (HPOM,
HSUT, HTCM/HTCT);
J0 management;
Linear MSP 1+1 bi–directional is supported between a HCLINKE–A and HCLINKE–B (fixed
scheme created with the configuration of the main/spare boards like an EPS 1+1 for HCMATRIX);
AU4–4c and AU4–16c signals can be transported.
•
•
•
The following limitations apply about transmission:
•
•
HCLINKE does not support the transport of AU4–64c signal;
no bidirectional transmission on single fiber (this is not a functional limitation).
Synchronization, auxiliary channel and loopback
No limitation applies to synchronization, so HCLINKE can be used as synchronization sources and they
can carry SSM messages.
Each HCLINKE is connected to the 6–wires synchronization bus aimed at collecting the synchronization
sources for the CRU, which is hosted on both matrices. Each of the six wires can be loaded with a 2 MHz
clock by any port of the 1670SM: this rule applies also for the HCLINKE board.
Power supply and optical characteristics
This board hosts on it the circuitry for the DC/DC converter 48V/+5V, 48/–5V and one 10 Gbit/s optical
module.
The HCLINKE board receives the battery voltage and generates through DC/DC converters following voltages:
–
–
–
–
+3.3 V
+1.8 V
+5 V
–5 V.
Also HCLINKE board receives the spider voltage +3.3 VS by backpanel.
The main optical characteristics are:
1AA 00014 0004 (9007) A4 – ALICE 04.10
wavelength:
launched average power per fiber:
sensitivity:
saturation:
ED
1290 to 1330 nm (second window)
min. –6.0 dBm
max. –1.0 dBm
–11.0 dBm
(@ BER =10 –12)
–1.0 dBm
(@ BER =10 –12)
03
3AG 24163 BEAA PCZZA
531
429 / 531
16.9 Bus Termination (BTERM)
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Refer to Figure 233. on page 430.
The main function of this board is to give the electrical termination to the buses routed on the backplane
and to supply the reference voltages of ISPB bus located on the other boards housed in the shelf.
The signal buses are:
•
•
•
•
ISPB (communication way between the microprocessor and the GA of the equipment)
ISSB (connection way between EQUICO and SC on HCMATRIX)
CK2M (reference clocks T1/T2 between port and synchronization function on HCMATRIX)
SPIDER (connection way between all boards and SC on HCMATRIX)
These buses are routed on the backplane as a ring structure; therefore it is necessary to have a double
termination, one at each end of line.
The BTERM is powered by –48 V by CONGIHC board; it generates a 3.3 V and a 1.5 V used on board
(a VTT voltage for terminations on other units).
The Bus Termination houses also the RIBUS I/F block the function of which is described on para. 13.13
on page 321 and the Remote Inventory.
On the front cover plate a green/red LED is available for board fail alarm indication.
This board is not managed by CT. It is very important to check its presence (it is mandatory) and its correct
functionality.
all
buses
all
buses
TERMINATIONS
–48V
DC – DC
Converter
3.3V
Regulator
1.5V
VTT
to other units
FAIL
from
CONGIHC
REMOTE
INVENTORY
RIBUS
I/F
RIBUS
to/from
MATRIX
BTERM
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 233. BTERM Board Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
430 / 531
16.10 Control and General Interface Board (CONGIHC)
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Each 1670SM shelf houses two Control and General Interface High-Capacity (CONGIHC) boards, referred as CONGIHC A (slot 1) and CONGIHC B (slot 21).
The CONGIHC boards are not intended as redundant (only for power and internal LAN). Each board provides a set of functions. Both boards are necessary to provide the complete set.
Table 52. lists the interfaces provided on each CONGIHC board.
CONGIHC/A
POWER A
CONGIHC/B
POWER B
Housekeeping & Remote Alarms (a subset) Housekeeping & Remote Alarms (a subset)
Rack lamps (R/M), not used
Not used
QMD (Q2), not used
Shelf ID connector
Ext. LAN 10 base 2
not used
Ext. LAN 10 base T
not used
INT LED
INT LED
Internal LAN (10 Base T) A1
Internal LAN (10 Base T) B1
Auxiliary Housekeeping (connector for FAN Auxiliary Housekeeping (connector for FAN
alarm cable)
alarm cable)
Remote Alarms
Internal LAN (10 base T) A2
Internal LAN (10 Base T) B2
Table 52. Interfaces on the Boards CONGIHC A and B
The Shelf ID connector which provides shelf identification within the Internal LAN is connected
to the front panel of the CONGIHC B board (Slot 21).
The main functions performed by the CONGIHC board are (refer to Figure 234. ) :
1AA 00014 0004 (9007) A4 – ALICE 04.10
–
–
–
–
–
–
–
–
–
–
ED
Input power stage
AND/OR and Remote Alarms (not used)
Housekeeping interface
R/M interface
QMD interface
External LAN interface
Remote Inventory
Auxiliary Housekeeping interface
Internal LAN interface (LINK 1+2)
Remote Alarms.
03
3AG 24163 BEAA PCZZA
531
431 / 531
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Input Power Stage
– Batt
+ Batt_A
MAIN
POWER
BLOCK
Station
battery – Batt_A
Service
battery
POLARITY
INVERSION
PROTECTION
PROTECTION
CICUIT
BLOCK
48V
DC/DC
3.3 V
TO
RIBUS
I/F
+3V
RACK
LAMPS
BAT FAIL
R/M
20%
URG, NURG, IND
AND/OR
HOUSEKEEPING
AND REMOTE
ALARM
6
HK–IN
not used
2 HK–OUT
AUXILIARY
HOUSEKEEPING
8+8
to/from
HiCap Matrix
Board
AUX–HK (in&out)
(connector for
FAN alarm
cable)
NON SDH
EQUIPMENT
QMD
INTERFACE
(shelf ID is connected
on CONGIHC B in
Slot 21)
not used
M
U
X
TRANSCEIVER
not used
–9V
COAX
TRANSCEIVER
INTERFACE
(CTI)
BNC
RJ45
Link#1
BNC
InternalLAN
RJ45
UNIVERSAL
ETHERNET
INTERFACE
ADAPTER
(AUI)
M
U
X
FAIL
Q3
INTERFACE
Link#2
TO ALL
BOARDS
STEP UP
CONVERTER
–9V
External LAN
TO ALL
BOARDS
+Batt
EMI
FILTER
Remote
Inventory
RJ45
LAN
DXC
INTERFACE
not used
not used
to/from
HiCap Matrix
Board
RIBUS
I/F
RIBUS
CMISS
CONGIHC
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 234. CONGIHC Board Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
432 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Input Power Stage
The input power stage decouples the power station battery. It contains the Main Power Block with EMI
input filters, a Protection Circuit Block, a Step up converter to provide –9 V and a DC/DC converter to provide the +3.3 V to the RIBUS I/F block.
QMD Interface
Interface is not used (shelf ID on CONGIHC B).
Internal LAN Interface
This interface links the 1670SM shelves via the Internal LAN to the Control partsystem. Redundant interfaces (LINK #1, #2) are provided:
–
LINK #1:
•
two BNC for 10Base2 connection type (not used)
•
RJ45 for 10BaseT connection type.
–
LINK #2:
•
RJ45 for 10Base T connection type.
ED
03
3AG 24163 BEAA PCZZA
531
433 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
16.11 Matrix Board (HCMATRIX)
The 1670SM equipment hosts up two HCMATRIX boards (referred HCMATRIX/A in the slot 22 and
HCMATRIX/B in the slot 41); only one board is active, the other one is standby.
As the HCMATRIX is in 1+1 redundant configuration, all the functions realized by the board are redundant
as well.
The HCMATRIX performs different functions:
•
•
•
•
•
•
connections between ports
equipment synchronization (Clock Reference Unit)
Shelf Controller
performance monitoring collection
power supply
remote inventory.
The HCMATRIX board has two boards: MATRIX SUPPLY (DC/DC converters) and MATRIX MOTHERBOARDS (all other functionalities).
The HCMATRIX can handle up to 512 STM–1 signals of which 256 from Port boards (and the other from
LINK boards).
MATRIX CONNECTIONS
The connections between HCMATRIX and ports are realized by means of links at 622 Mbit/s (refer to
Figure 235. on page 437).
EQUIPMENT SYNCHRONIZATION
The equipment synchronization is realized by the SETS function (Synchronous Equipment Timing
Source) that distributes to each port the pertaining synchronization signals.
A high stability oscillator at 10 MHz (VCXO – 0,37 ppm) is present to guarantee an holdover or free running
working mode compliant to the ITU–T Recs.
The clock reference (CRU) working modes can be: locked, hold over and free running.
When working in locked mode, the SETS block can select its reference signal among (the selection is accomplished by means of the software and craft terminal):
•
•
timing reference signals coming from the SDH ports (T1)
2 MHz clocks coming from the SERVICE board (T3)
The SETG block (Synchronous Equipment Timing Generation) generates:
•
a system clock T0 (at 622.08 MHz) locked to the selected reference (T1 or T3) and distributed
to the equipment;
CK38Mhz : it is derived from the system clock (T0) and is distributed to all the ports; ts frequency
is 38.88 MHz;
MFSY : it is the multiframe synchronism at 500 Hz, obtained from the ck38 MHz; it is distributed
to all the ports and boards;
a 2 MHz clock T4 used as synchronization clock towards the external, accessible from the SERVICE board;
SY1S : it is the 1 second synchronism that is sent to a GA for the managing of the Performance
Monitoring Data.
•
•
1AA 00014 0004 (9007) A4 – ALICE 04.10
•
•
ED
03
3AG 24163 BEAA PCZZA
531
434 / 531
The synchronization system is able to guarantee the hitless switching functionality in case of CRU switch
only if the two CRUs are locked. In order to work in ’locked mode’ the two CRUs exchange some signals.
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
For a detailed description of the synchronization subsystem refer to para. 13.6 on page 236.
SHELF CONTROLLER FUNCTIONS
The HCMATRIX houses the circuitry necessary to realize the Shelf Controller.
The SC provide the resources to support the SW functions related to the control and management operation of the boards. To perform its functions, the SC directly interfaces the ASICs on the board implementing
the SDH functions for data collection (faults or alarm event detections, performance monitoring data) and
configuration provisioning.
As the SC is involved in critical activities (for instance EPS), is 1+1 protected.
The internal interfaces supporting SC element for communication tasks are:
–
Management –Bus (ISPB) : it is a parallel bus connecting the SC processor to all the transport ASICs
located on the traffic boards to provide communications among the boards and the Controller, for
management of the boards (management of payload processing functions).
–
ISSB : Intra Shelf Serial Bus is a serial bus for communication among SC, EC (on the EQUICO board)
and, if present, other processor in the Shelf.
–
RIBUS (SPI): it is a serial bus connecting the SC processor to the serially interfaced devices called
RIBUS–I/F, located on each board for simple read or write operations, for communications about Remote Inventory, boards failure, bus releasing.
–
IPL : it is a channel between the two SC (active and standby).
A push–button is present to reset the SC.
The ’Board Missing’ signals of all the boards are connected with a GA.
For a detailed description of the Controller refer to para. 13.5 on page 224, where the control subsystem
is described.
PERFORMANCE MONITORING COLLECTION
The “Performance Monitoring Management” block housed on the HCMATRIX board realizes Performance
Monitoring functionalities; it collects and stores the data (Defect seconds and Errored blocks) coming from
all the flows.
The Performance Monitoring Controller is managed by a GA and can be made at:
1AA 00014 0004 (9007) A4 – ALICE 04.10
•
•
•
•
•
•
•
ED
Adaptation and Regeneration section
Multiplex section
Multiplex section adaptation
HSUT
HPOM
HPT
TCT and TCM.
03
3AG 24163 BEAA PCZZA
531
435 / 531
POWER SUPPLY
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The board receives via backpanel connectors the –48 V coming from CONGIHC boards and extracts the
main power supply via dedicated DC/DC Converters hosted on the ’MATRIX SUPPLY’ board.
The power supplies used in the HCMATRIX are the following:
•
•
•
•
+3.3 V (it is obtained by 8 DC/DC conv. –48/+3.3 V–5 A; it is the main power supply of the board)
+2.5 V (it is obtained from the +3.3 V with 7 Step Down +3.3 V/+2.5 V–5 A)
+1.7 V (it is obtained from the +3.3 V with a Step Down +3.3 V/+1.7 V–5 A)
+0.8 V (it is obtained from the +3.3 V with a Step Down +3.3 V/+0.8 V–5 A).
The Remote–Inventory and RIBUS–I/F blocks are powered by the 3.3 V power service coming from the
CONGIHC boards.
REMOTE INVENTORY
It is the memory used to maintain the board history and data.
For more details about the Remote Inventory function refer to para. 13.13 on page 321.
ED
03
3AG 24163 BEAA PCZZA
531
436 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
PERFORMANCE
MONITORING
MANAGEMENT
MATRIX
MSP
SNCP
HPC
AU4
Squelcing
HVC
622 Mb/s
Timing &
Synchronization
(SETS)
T0
10MHz
OSC
T1
SETG
Reset
FLASH
EPROM
(1 Mb)
From/to
spare MATRIX
and ports
Bus
OFF
Remote
Inventory
Unit
Failure
RIBUS
ID
From/to
spare HCMATRIX
ISSB
3.3 V
2.5 V
1.7 V
0.8 V
to ports
Management bus
M–BUS
Driver
RIBUS
I/F
RIBUS
(ck–ext)
MFSY
CK38
T0
T0
Management bus
from SDH ports
T3
T4
SC
from/to all
port cards
48/60 V
DC/DC
CONVERTERS
GROUP
from
CONGIHC
1AA 00014 0004 (9007) A4 – ALICE 04.10
HCMATRIX
Figure 235. HCMATRIX Board Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
437 / 531
16.12 FANs Unit
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Refer to Figure 236. on page 439.
In the FANs subrack can be housed two FANs units that works together in order to avoid high temperature
inside the 1670SM subrack.
Each FANS unit is composed by seven FANs and some electronic circuits necessary to:
•
•
•
FANs alarm management
Send remote alarms to the Top Rack Unit (TRU)
Power supply
In the following a description of the unit is given; more in details Figure 236. on page 439 shows how the
two FAN units work together.
FANS ALARM MANAGEMENT
Each FAN on the unit can generate an alarm signal in case of faulty (AL1A, AL1B, AL2, AL3 ... etc.): this
function actually is not used.
The “FANs alarm management” block process all this signal in order to:
•
•
generate FANs urgent alarm (URG_V)
turn on the relevant red on the unit front
One FAN faulty is enough to generate an URG_V alarm and turn on the relevant red LED on the unit.
The state of the FANs unit can be supervised by the 1670SM Craft Terminal application if the remote alarm
URG_V are connected to the Housekeeping contact on the CONGIHC board.
Note: in case of one broken FAN in one of the two FANs unit, the following indication will be display:
FANs unit with al least one broken FAN
FANs unit without broken FAN
URG_V red LED ON
URG_V red LED OFF
URG red LED ON
URG red LED ON
REMOTE ALARMS
This block process the alarms detected on the board in order to generate remote alarms towards the Top
Rack Unit:
•
URG:
•
•
NURG:
ATT:
urgent alarm generated in case of at least one broken FAN or loss of station battery.
When active the relevant red LED on the front of the unit is turned on.
not used.
attended alarm. By pressing the push–button present on the board it is possible to
store an URG alarm. This action will turn off the URG LED alarm and will light up the
yellow LED on the board; the attended command is also sent to the rack lamps.
Note: on the CT and on the OS application the URG and ATT remote alarm are named in a different way;
the relation between this two terminology is explained in Table 68. on page 494.
1AA 00014 0004 (9007) A4 – ALICE 04.10
POWER SUPPLY
The FANs unit are powered by a DC/DC converter that starting from the station battery (–48/–60 V) derive
a 12 VDC voltage. Each FAN is protected by a fuse.
Another voltage is generated (VSERVin) in order to power supply the FANS ALARMS MANAGEMENT
block if no external service battery (VSERVext) is available.
ED
03
3AG 24163 BEAA PCZZA
531
438 / 531
FANs UNIT (Board 2)
FANS
1A
2
5A
3
4
1B
5B
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
NOT USED
&
&
AND5
AL3
AL2
AND1
URG_V
BAT_B
T–URG
48/60 V
AL1A
AND1
&
FANS
1A
2
3
NOT USED
AND5
&
AL5B
AL4
AL3
AL2
AL1B
FANs UNIT (Board 1)
not used
NURG_V
not used
R A
E L
M A
O R
T M
E S
5A
URG_V
URG_V
4
URG
1B
FANS
ALARMS
MANAGEMENT
5B
48/60 V
DC/DC
Converter
URG_V
L
O
C
A
L
>
=1
A
L
A
R
M
S
ATT
URG
VSERVext
F1
F7
from/to
Top Rack Unit
RM
AL5A
AL5B
AL4
AL3
AL2
AL1B
AL1A
BAT_A
to fans
VSERVin
DC/DC
Converter
VSERVin
ALARMS
STORING
T–URG
PWAL
1AA 00014 0004 (9007) A4 – ALICE 04.10
to
CONGIHC
Housekeeping
AL5A
to
CONGIHC
Housekeeping
AL4
to
CONGIHC
Housekeeping
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
In case of station battery faulty an alarm is generated (PWAL); as consequence the URG LED and the
relevant remote alarm will be activated (T–URG).
Figure 236. FANs Unit Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
439 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ED
03
3AG 24163 BEAA PCZZA
531
440 / 531
17 UNITS DESCRIPTIONS OED SHELF 1662SMC
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
17.1 Introduction
The following Table 53. on page 441 sums up the units managed in the 1662SMC Shelf Equipment.
Table 53. Units involved in 1662SMC
Type / Class
Acronym
Width (mm)
Q.ty
Control / Common Control and General I/F
CONGI
20
2
Common / LINK
SYNTH16
40
2
Compact STM–16
Control / Common Termination Bus
BUSTERM
PDH Port
63x2 Mbit/s Port
P63E1
63x2 Mbit/s Port with retiming
P63E1N
63x2 Mbit/s Prot. (75 Ohm)
A63E1A
63x2 Mbit/s Prot. (120 Ohm)
A63E1B
63x2 Mbit/s Prot. (120 Ohm/K20)
A63E1B
Low Speed Protection
LPROT
PDH Access
1AA 00014 0004 (9007) A4 – ALICE 04.10
Description
ED
2
20
8
20
8
2
03
3AG 24163 BEAA PCZZA
531
441 / 531
17.2 63x2 Mbit/s Access Board
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Refer to Figure 237. on page 443.
The 63x2 Mbit/s access board provides the connections from back panel to the external line and vice versa
for 63 PDH signals. According to the type of line impedance (75 Ohm or 120 Ohm) and electrical characteristics different types of access board are available.
In the following a generic description of the access board is given:
INPUT side
Under normal operating condition, the signal received from the line is sent to the 63x2 Mbit/s “main” port
board.
Under alarm condition, the signal received from the line is switched towards the LSPROT board. The
switching command SEL is received from the RIBUS I/F block.
A protection block is present to protect the incoming signal against spikes ( G.703).
OUTPUT side
The two signals received from the port and LSPROT port boards 63x2 Mbit/s are sent to a selector.
The SEL command, received from the RIBUS I/F block, select the signal to sent to the line.
Remote inventory
The RIBUS I/F is present to read/write inventory data as code, series number, construction data present
on the RI (refer to para. 13.13 on page 321 for details).
Power supply
1AA 00014 0004 (9007) A4 – ALICE 04.10
The access board receive the +3.3 VDC provided by the CONGI boards.
ED
03
3AG 24163 BEAA PCZZA
531
442 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
INPUT
FROM LINE
Input–1
TO PORT CARD
SPIKE
PROTECTION
TO LSPROT CARD
SEL
OUTPUT
TO LINE
Output–1
FROM PORT CARD
SPIKE
PROTECTION
FROM LSPROT CARD
SEL
INPUT
FROM LINE
Input–63
TO PORT CARD
SPIKE
PROTECTION
TO LSPROT CARD
SEL
Output–63
OUTPUT
TO LINE
FROM PORT CARD
SPIKE
PROTECTION
FROM LSPROT CARD
SEL
REMOTE
INVENTORY
FAIL
SEL
RIBUS
IF
RIBUS
TO/FROM
SYNTH16
CMISS
+3.3 Vdc
F
FROM CONGI
63x2 MBit/s Access
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 237. 63x2 Access Board – Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
443 / 531
17.3 Low Speed Protection
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Refer to Figure 237. on page 443.
The LSPROT board is used to realize EPS protection for low speed ports. It realizes the connection between the port board and the LS protection bus if protection is requested.
The LSPROT board receives the signals coming from the port board via back panel.
Control Section
The RIBUS I/F block is present to read/write inventory data as code, series number, construction data
present on the RI (refer to para. 13.13 on page 321 for details).
Power supply
The access board receive the +3.3 VDC provided by the CONGI boards. On the front cover plate a red/
green LED is available for board failure alarm indication.
FROM LS
Protection Bus
1
TO PORT CARD
63
63
TO PORT CARD
FAIL
FROM LS
Protection Bus
1
REMOTE
INVENTORY
RIBUS
IF
RIBUS
TO/FROM
SYNTH16
CMISS
+3.3 Vdc
F
FROM CONGI
LSPROT
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 238. LSPROT Board – Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
444 / 531
17.4 63x2 Mbit/s Port Board (P63E1)
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Refer to Figure 239. on page 447.
The P63E1 is a bidirectional board which interfaces 63 plesiochronous 2048 kbit/s signals and the
STM4–BPF signal (BPF=backpanel format).
Due to the backpanel format (STM4–BPF or STM4*), the 63 plesiochronous 2 Mbit/s signals that can be
housed in an STM–1 frame, are dropped / inserted in the AU4#1 of the STM–4* frame.
The board is composed by the following blocks:
–
(G.A.)
G.A. is an ASIC (or Gate Array) that maps 63x2 Mbit/s streams into an STM–1 frame as required
by ITU–T G.783 Rec.
As the backpanel format for data exchange between 63x2 Mbit/s and Matrix board is STM–4*, the
2 Mbit/s streams are inserted/extracted on the AU4 #1 of the STM–4* frame.
INPUT side
•
PPI (E12_TT_Sk and E12/P12x_A_Sk): This block provides the electrical interface between
the physical transmission medium and the internal board format. The received 2048 kbit/s line
signal is HDB3 coded. A decoder on the physical interface decodes the signal to NRZ (non return–to–zero) format.
•
LPA (S12/P12x_A_So) :
This block adapts user data for transport in the synchronous domain. For asynchronous user data, lower order path adaptation involves bit justification. The
2.048 Mbit/s is inserted into a C–12 container (by means of asynchronous mapping), which is
synchronized (stuffing) with the correspondent TU–12.
•
V5[5–7]: Signal label insertion in the byte V5[5–7].
•
LPT (S12_TT_So) : The LPT function creates a VC–12 by generating and adding POH to a
C–12. The POH formats are defined in Recommendations G.708 and G.709.
•
J2:
trail trace identifier is generated.
•
V5[1,2]: BIP–2 is calculated and transmitted.
•
V5[3]:
the number of errors is encoded in REI.
•
V5[8]:
RDI indication is inserted.
•
LTCT So :
This block performs Tandem Connection Termination and Adaptation Source
functions, according to ITU and ETSI standards, on Low Path tributaries. It inserts into incoming
Low order VC the N2 byte, and performs BIP–2 parity compensation for that byte insertion. The
inserted N2 is composed by remote signalling, incoming error count, APId.
•
STM4–BPF I/F () :
The STM–1 equivalent signal is multiplexed into the Back–Panel STM4* equivalent signal.
The signal is sent to the ”Main” and ”Spare” MATRIX boards .
1AA 00014 0004 (9007) A4 – ALICE 04.10
OUTPUT side
ED
•
EPS :
This block select one of the two signal source provided by the MATRIX boards ”Main” and
”Spare”
•
STM4–BPF I/F () :
The STM–1 equivalent signal is demultiplexed from the Back–Panel STM4* equivalent signal.
03
3AG 24163 BEAA PCZZA
531
445 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
•
LTCT Sk :
This block performs Tandem Connection Monitoring / Termination and Adaptation Sink functions, according to ITU and ETSI standards, on Low Path tributaries (configuration
choice between Monitoring and Termination is by preset). It extracts from incoming Low order
VC the BIP–2 parity and N2 byte, and then operates alignment, detection and correlation of
alarms, error check. When Termination function is configured, it also modifies data flow by N2
byte overriding, AIS insertion, generation of remote signalling.
•
LPT (S12_TT_Sk): The LPT function terminates and processes the POH to determine the status of the defined path attributes.
•
J2:
trail trace identifier is recovered ––> TIM detection.
•
V5[1,2]: BIP–2 is recovered ––> Ex–BER, Signal Degrade alarm
•
V5[3]:
REI bit is recovered and the derived performance primitives is reported.
•
V5[8]:
RDI information is recovered and reported.
•
AIS or SSF detection ––> SSF alarm
•
LPA (S12/P12x_A_Sk): It extracts the VC12–POH and processes the TU12 pointer.
•
V5[5–7]: Signal label detection in the byte V5[5–7] ––> Signal label Mismatch
detection
•
AIS or SSF is applied if Signal label Mismatch is detected
•
PPI (E12/P12x_A_So and E12_TT_So):This block provides the interface between the internal board format and the physical transmission medium. It encodes into HDB3 code the signal
to be sent on line.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Other functions implemented are :
ED
•
Clock Reference Selection Block (on G.A): provides six 2 MHz clock links towards the MATRIX boards for synchronization purposes. The selection among the 63 flows is made via software.
•
TIMING (on G.A): receives the reference clock (38.88 MHz) and synchronism pulse (500 Hz)
from the MATRIX boards and extracts the local clocks used by the G.A.
The Tx clock is locked, by means of a PLL to the system clock or, when in free running, to a local
oscillator with a +–50 ppm drift: (51 MHz OSC) block.
•
RIBUS I/F
This block is used to read/write from/to the ”RIBUS” stream, to control the LED on the board,
to release the Management–bus in case of power failure, and to use the remote inventory. It is
powered by the + 3.3 VDC supply by CONGI boards.
•
REMOTE INVENTORY
It is the memory containing the board information, for identification purposes.
•
M–BUS Driver
It drives the input–output gates of the Management–bus. These drivers can be disabled (by
the Bus–OFF signal) in case of power failure.
•
DC/DC CONVERTER
It converts the 48/60 V power supply to the 3.3 V used to supply all the components in the board.
The DC/DC converter is synchronized with a synchronization clock at 288 MHz (signal Power–
Sync, generated by G.A.) in order to avoid EMI problems.
•
STEP DOWN
It uses the 3.3 V power supply from DC/DC Converter block to obtain the 2.5 V used to power
the Gate Array (G.A.).
03
3AG 24163 BEAA PCZZA
531
446 / 531
Input side
2Mb/s #1
PPI
sink
LPA
source
from
Access Card
ckr1
LTCT
source
ckrx
STM4
BPF
I/F
#63
2Mb/s
outputs
Access Card
#1
ckr1
2Mb/s #63
ckr63
ckr63
to
LPT
source
ckrx
cktx
6x
Output side
2Mb/s #1
PPI
source
Clock
Reference
Selection
LPA
sink
LTCT
sink
LPT
sink
ckt1
STM4
BPF
I/F
EPS
2Mb/s #63
#63
cktx
ckt63
ckt1
ckt63
Local Clocks
Power
Sync
2.5 V
CONGI A & B
DC/DC
CONV.
Config. & Status
51MHz
OSC
M–BUS
Driver
3.3 V
CMISS
Bus–OFF
F
Management
Bus
to/from
MATRIX
from
STEP
DOWN
ck–system a
ck–system b
TIMING
ckrx
cktx
G.A.
48/60 V
to
MATRIX
Main and Spare
#1
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
..
..
..
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
..
..
..
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
..
..
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
..
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
..
..
..
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
.
..
.
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
from
MATRIX
Main and Spare
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
2Mb/s
inputs
+ 3.3 Vdc
Remote
Inventory
RIBUS
I/F
RIBUS
ID
Unit
Failure
1AA 00014 0004 (9007) A4 – ALICE 04.10
63x2 MBit/s Port
Figure 239. 63x2 Mbit/s Board – Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
447 / 531
17.5 63x2 Mbit/s / G703 / ISDN–PRA Port Board (P63E1N)
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Refer to Figure 240. on page 451.
Note: The ISDN–PRA functionality is not supported by the 1678MCC up to now!
The 63x2 Mbit/s /G.703/ISDN–PRA port is similar to the basic 63x2 Mbit/s port, described in the previous
paragraph 17.4 on page 445, with the difference that the present board implements also the NT functionality on ISDN Primary Rate Access (PRA) and the “Retiming function” on the 2 Mbit/s interfaces.
The Retiming function applies the Equipment Clock to the outgoing 2 Mbit/s signal that therefore becomes
synchronized with the SDH network synchronization reference .
The additional circuit that allows this implementation consists in an elastic buffer that is able to absorb the
jitter and wander that is transferred to the PDH signal when SDH pointer justification occurs.
This feature is programmable via SW, in order to include or exclude the Retiming for each single port. The
same P63E1N board can mix ports that apply or not the retiming.
In this paragraph is reported the description of the NT ISDN–PRA function, all the other blocks functionalities are described in the previous paragraph 17.4 on page 445.
The ISDN–PRA (Integrated Services Digital Network – Primary Rate Access) is a facility to carry a number
of synchronous digital communication channels to the user over a 2048 kbit/s structured signal; the ISDN–
PRA structure is defined in recommendation ETS 300 233.
The 2048 kbit/s signals can be structured or non–structured: in this latter case, the PRA functionality must
be disabled from Craft–Terminal. The selection among structured/non–structured and basic–frame/multiframe options is achieved by means of Craft–Terminal, for individual signals.
It performs standard PRA functionality as well as some custom Leased Line functions (settings from CT.).
Figure 241. on page 452 illustrates the NT ISDN–PRA block, that performs the following functions:
1AA 00014 0004 (9007) A4 – ALICE 04.10
UPSTREAM DIRECTION
(from user to SDH network: incoming signal SY2Min, outgoing signal UP2Mout)
–
Loopback2: by means of command LB2, sent by the controller, or detected in the Sa6 message coming from the SDH network (UP2Min signal); this command sends back to the source the upstream
signal.
–
AIS Detection: the AIS alarm (AIS2M) is detected after the reception of 512 bits containing less than
3 zeroes.
–
Frame Alignment (FA): it performs basic–frame and multi–frame alignment according to ITU–T
G.706, presettable from the controller (commands BF and MF); the LOF2M alarm is declared in case
of non alignment .
–
Failure Condition: the Failure Condition FC2M alarm is the “OR” of LOS2M, LOF2M , AIS2M alarms.
–
REI alarm detection (E): the REI2M alarm is detected if E=0.
–
RAI alarm detection (A): the RAI2M alarm is detected if active for 5 consecutive frames.
–
Data Error detection (CRC–4): errors integrity check on the incoming data, according to CRC–4
procedure (Cyclic Redundancy Check), as defined in G.706. In case of errors, the alarm ERR2M is
indicated.
ED
03
3AG 24163 BEAA PCZZA
531
448 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
E bit insertion (E): the outgoing E bit is set to 0 when
•
a failure condition (FCU) is detected on signal from SDH network (UP2Min);
•
errors (ERRU) are detected on data from SDH network (UP2Min);
•
the E insertion may be inhibited from controller, in this case E=1.
•
E=1 in other cases.
–
A bit insertion (A): the outgoing A bit is set to
•
’0’ when a failure condition (FC2M) is detected on signal from user (SY2Min);
•
’1’ when Loopback2 (LB2) is activated;
•
passed transparently in other cases;
•
the A bit may be forced from controller.
•
set to ’1’ (*) when a failure condition (FCU) is detected on signal from SDH network (UP2Min);
N.B.
(*): this option is enabled only in case of Leased Line applications;
–
Sa5, Sa6 Messages:
•
the outgoing Sa6 message is inserted in 4 Sa6 bits of 4 consecutive frames, with the following
significance (listed in order of their priority/severity):
–
1000 ––> power fail
–
1111 ––> SSF or AUXPU/AISU on signal from SDH network (UP2Min);
–
1110 ––> LOFU on signal from SDH network (UP2Min);
–
1100 ––> FC2M on signal from user (SY2Min);
–
0000 ––> loopback2 (LB2) activated
–
0001 ––> alarm REI2M from user
–
0010 ––> CRC–4 errors (ERR2M) from user
–
0011 ––> simultaneous occurrence of both previous (REI2M and ERR2M)
–
0011 ––> only basic–frame alignment on SY2Min signal, when in automatic search
–
0000 ––> normal operations.
•
the outgoing Sa5 bit is set to:
–
’0’ ––> when loopback2 (LB2) is activated
–
’1’ ––> in other cases.
–
CRC–4 bits insertion: the CRC–4 on data is performed and the result is inserted on bits C1 to C4,
according to G.706.
–
Frame Word insertion (FW): the basic–frame and multi–frame alignment words are inserted on the
frame.
–
Substituted Frames insertion: the substituted frames are inserted, in case of occurrence of a failure
condition (FC2M) on incoming signal from user.
N.B.
Substituted frame is a frame with Sa4, Sa5, Sa7, Sa8 as well as all the bits in time slots
1 to 31 set to ’1’, and with A bit set to ’0’.
1AA 00014 0004 (9007) A4 – ALICE 04.10
DOWNSTREAM DIRECTION
(from SDH network to user: incoming signal UP2Min, outgoing signal SY2Mout)
–
Loopback–RX: by means of command LB–RX, sent by the controller; this command sends back to
the source the downstream signal.
–
AIS Detection: the AIS alarm (AISU) is detected after the reception of 512 bits containing less than
3 zeroes.
–
AUXP Detection: the AUXPU alarm is detected after the reception of 512 bits containing the pattern
...010101... with less than 3 deviation from the pattern itself. It can be enabled from the controller.
–
Frame Alignment (FA): it performs basic–frame and multi–frame alignment according to ITU–T
G.706, presettable from the controller (commands BF and MF); the LOFU alarm is declared in case
of non alignment.
ED
03
3AG 24163 BEAA PCZZA
531
449 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
Failure Condition: the Failure Condition FCU alarm is the “OR” of SSF, LOFU , AISU, AUXPU alarms.
N.B.
SSF =Server Signal Fail, from upstream.
–
REI alarm detection (E): the REIU alarm is detected if E=0.
–
RAI alarm detection (A): the RAIU alarm is detected if active for 5 consecutive frames.
–
Sa6: the Sa6 bit is read for every 4 consecutive frames, to check the presence of the loopback2 command, when 4XSa6=1010, for 8 consecutive times.
–
Data Error detection (CRC–4): errors integrity check on the incoming data, according to CRC–4
procedure (Cyclic Redundancy Check), as defined in G.706. In case of errors, the alarm ERRU is
indicated.
–
A* insertion: the A bit is
•
passed transparently in standard applications
•
set to ’1’ (*) when a failure condition (FC2M) is detected on signal from user (SY2Min);
•
set to ’1’ (*) when forced from the controller;
N.B.
(*): this option is enabled only in case of Leased Line applications.
–
E bit insertion (E): the outgoing E bit is set to 0 when
•
a failure condition (FC2M) is detected on signal from user (SY2Min);
•
errors (ERR2M) are detected on data from user (SY2Min);
•
the E insertion may be inhibited from controller, in this case E=1.
•
E=1 in other cases.
•
set to ’0’ (*) when Power Fail alarm (PWF) is active;
N.B.
(*): this option is enabled only in case of Leased Line applications.
–
Sa4* insertion: the bits Sa4 to Sa8 are passed transparently in standard applications,
•
Sa4 is set to ’0’ (*) when Power Fail alarm (PWF) is active, passed transparently otherwise.
N.B.
(*): this option is enabled only in case of Leased Line applications.
–
CRC–4 bits insertion: the CRC–4 on data is performed and the result is inserted on bits C1 to C4,
according to G.706.
–
Frame Word insertion (FW): the basic–frame and multi–frame alignment words are inserted on the
frame.
–
AIS insertion: a continuous bitstream of all ’ONES’ is inserted, in case of occurrence of
•
force command from the controller;
•
a failure condition (FCU) on signal from SDH network (UP2Min);
•
(*) a failure condition (FC2M) on signal from user (SY2Min).
N.B.
(*): this option is enabled only in case of Leased Line applications.
ALARMS, STATUS AND COMMANDS CONVEYED FROM/TO CONTROLLER
Every alarm, status and errors counting results are reported to the controller, for monitoring purposes:
–
LOS, REI, RAI, FC, ERR(CRC–4), SSF detected either in upstream and in downstream signal directions
N.B.
LOS = Loss of user Signal; SSF= upstream Server Signal Fail.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The controller sends the following commands, in order to enable the relevant functions:
–
ED
LB–2, LB–RX, BF, MF, ForceA, InhibitE, etc.
N.B.
BF= Basic Frame; MF = Multi Frame.
03
3AG 24163 BEAA PCZZA
531
450 / 531
from
Access Card
#1
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ..
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
..
.
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
..
.
..
..
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
.
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
..
..
.
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
..
..
ÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏ
Input side
2Mb/s #1
PPI
sink
2 Mb/s
POM
NT
ISDN
PRA
source
LPA
source
ckr1
#63
LPT
source
LTCT
source
STM4
BPF
I/F
ckrx
ckr1
2Mb/s #63
Clock
Reference
Selection
ckr63
ckr63
ckrx
6x
to
MATRIX
Main and Spare
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
2Mb/s
inputs
Output side
#1
2Mb/s #1
PPI
source
2 Mb/s
POM
NT
ISDN
PRA
sink
cktx
LPA
sink
LPT
sink
LTCT
sink
STM4
BPF
I/F
ckt1
EPS
2Mb/s #63
#63
cktx
ckt63
ckt1
ckt63
Local Clocks
Power
Sync
2.5 V
48/60 V
DC/DC
CONV.
Config. & Status
51MHz
OSC
M–BUS
Driver
3.3 V
CMISS
Bus–OFF
F
Management
Bus
to/from
MATRIX
from
CONGI A & B
STEP
DOWN
ck–system a
ck–system b
TIMING
ckrx
cktx
G.A.
from
MATRIX
Main and Spare
Access Card
to
2Mb/s
outputs
+ 3.3 Vdc
Remote
Inventory
RIBUS
I/F
RIBUS
ID
Unit
Failure
1AA 00014 0004 (9007) A4 – ALICE 04.10
63x2 MBit/s Port Board
Figure 240. 63x2 Mbit/s G.703/ISDN–PRA, Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
451 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1AA 00014 0004 (9007) A4 – ALICE 04.10
ED
To User (downstream)
03
To SDH Network (upstream)
BF MF
SY2Min
FA
AIS
CRC–4
E
LOF2M
3AG 24163 BEAA PCZZA
531
Figure 241. Functional Diagram of the NT ISDN–PRA Block
AIS 2M
LB 2
ERR2M
A
REI 2M
RAI2M
+
+
E
A
Sa5, Sa6
Messages
+
+
UP2Mout
FW
CRC–4
(*)
FCU
FCU
FC2M
SUBST
FRAMES
FC2M
ERR U
FC 2M
LOS2M
+
FC U
PWF
ERR2M
FCU (*)
FC2M
(*)
AIS
SSF
LOFu
PWF
FW
CRC–4
FC 2M
PWF
(*)
Sa4*
FC 2M
(*)
E
LB2
RAIU
AUXPu
REIU
AISu
Sa6
A*
A
AUXP
E
ERR U
AIS
LBRX
SY2Mout
+
+
+
+
+
FA
CRC–4
BF MF
FC2M
REI 2M
RAI2M ERR
2M
FC U
REI U
RAIU
ERR U
ALARMS & STATUS
CONVEYED FROM/TO CONTROLLER
FROM/TO
CONTROLLER
EQUICO
LB
BF
MF
UP2Min
452 / 531
17.6 CONGI Board
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Refer to Figure 242. on page 456.
The 1662SMC equipment can house two CONGI boards, referred as CONGI A main (slot 1) and CONGI
B (slot 20).
They are not intended as main and spare : each board provides a set of functions . Both boards are necessary to provide the complete set.
CONGI A can be used as stand alone but in this case only a subset of interfaces can be used .
Table 54. reports the interfaces present on each CONGI board.
Table 54. CONGI A and CONGI B interfaces
CONGI A (slot 1)
CONGI B (slot 20)
POWER
POWER
Housekeeping & Remote Alarms (a subset)
Housekeeping & Remote Alarms ( a subset)
Rack lamps (R/M)
Not used
QMD (Q2) – FAN Alarm
QMD (Q2) – Shelf ID
Q3 10 base 2
Not used
Q3 10 base T (LAN)
Not used
INT LED
INT LED
1AA 00014 0004 (9007) A4 – ALICE 04.10
The main functions performed by the board are:
[1]
Input power stage
[2]
AND/OR and Remote Alarms
[3]
Housekeeping interface (only on CONGI in slot 1)
[4]
R/M interface
[5]
QMD interface (only on CONGI in slot 1)
[6]
RIMMEL interface
[7]
Q3/QB3 interface (only on CONGI in slot 1)
[8]
Temperature sensor
[9]
Remote inventory.
ED
03
3AG 24163 BEAA PCZZA
531
453 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
[1] Input power stage
This circuit decouples the power station battery .
It contains the ”Main Power block” with two fuses, EMI input filters, a ”protection circuit block” , a ”step
up converter” to provide –9 V and a DC/DC converter to provide the +3.3 V to the RIBUS I/F block. In case
of fuse broken an alarm is generated (FUSE).
A solder strap is present to provide the main power (48 V) in modality “two wires” (if +Vbatt is connected
to ground or “three wire” (if + Vbatt is not connected to ground) in order to obtain a DC/I decoupling system.
[2] AND/OR and Remote Alarms
The circuit generates the remote alarms and lights up the the Rack lamps in case of station battery fault.
It is powered from the 3.3 VDC power from the service battery and uses it to control the station battery. In
case of loss of 3.3 VDC a PWANDOR alarm is generated.
The AND/OR circuit monitors the station battery and provides an alarm (BAT FAIL) in case the voltage
level decreases more than 20 % of the nominal value. If BAT FAIL alarm of the CONGI in slot 1 or the same
alarm of the CONGI in slot 20 are present , the ORALIM alarm is generated and set to the EQUICO board.
[3] Housekeeping interface
The CONGI board (3 wire) provides 4 inputs and 2 outputs contacts suitable for customer purpose.
[4] R/M interface
It is used to connect the rack lamps and incoming call signal.
Table 55. Rack lamps signals
ACRONYM
FUNCTION
T*RATTD
alarms storing
T*RURG
urgent alarm
T*RNURG
not urgent alarm
T*CH
incoming call
T*TOR
absence of one battery
N.B.
On the Craft Terminal (CT) and on the Operation System (OS). application the T*RURG, and
T* RNURG remote alarm sent toward the rack lamp are named in a different way; the relation
between this two terminology is explained in Table 68. on page 494.
[5] QMD interface
1AA 00014 0004 (9007) A4 – ALICE 04.10
It is a RS–485 interface that allows the dialogue between the NE (EC function) and a non SDH equipment.
In this case the NE acts as a mediation device.
CONGI in slot 1: FAN alarm
CONGI in slot 2: Shelf ID
ED
03
3AG 24163 BEAA PCZZA
531
454 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
[6] RIMMEL interface
This block provide a serial communication interface with the FANs Shelf in order to receive information
like presence of FANs unit, FAN alarms, FANs unit remote inventory etc. (for details about connection with
FANs Shelf refer to Installation Handbook).
“Rimmel block” is also connected with the Shelf Controller (housed on the MATRIX) and Equipment Controller (housed on the EQUICO) in order to:
–
–
–
–
manage the HOUSEKEEPING contact
provisioning remote alarm
read the 2/3 wire operating mode
detect an over–temperature inside the equipment.
[7] Q3/QB3 interface
The Q3/QB3 interface on CONGI is used for OS connection. Two connectors are available :
–
–
2 BNC for 10 Base 2 connection type
RJ45 for 10 base T connection type.
The Coaxial Transceiver Interface (CTI) circuit performs the driver/receiver interface between the Q3/QB3
coaxial cable ( BNC) and the universal ethernet adapter (AUI).
The purpose of the AUI adapter is to adapt the signal, coming from the Equipment Controller on the EQUICO, to the LAN interface. It is directly connected to the RJ45 connector or through CTI to BNC connector.
The LAN interface is only used on CONGI in slot 1.
[8] Temperature sensor
The mentioned sensor provide an alarm when the temperature inside the equipment is over 55 degree
Celsius; the alarm is than sent to the RIMMEL block.
[9] Remote inventory
1AA 00014 0004 (9007) A4 – ALICE 04.10
It is the memory used to maintain the board history and communication and routing data relevant to the
NE ; Remote Inventory activity is managed by the RIBUS I/F block.
ED
03
3AG 24163 BEAA PCZZA
531
455 / 531
2/3 wire mode
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
+ Batt_A
Station
battery – Batt_A
Fuse
Input Power Stage
MAIN
– Batt
POWER
BLOCK
Fuse
EMI
FILTER
TO ALL
BOARDS
+Batt
STEP UP
CONVERTER
–9V
PROTECTION
CICUIT
BLOCK
+3.3Vdc
TO ALL
BOARDS
DC/DC
3.3 V
to
RIBUS I/F
Fuse
BAT FAIL
48V
20%
PWANDOR
OR ALIM
OR
RACK LAMPS
BAT FAIL
R/M
AND/OR
HOUSEKEEPING
AND REMOTE
ALARM
URG, NURG, LOSQ2, INT, UP
To
SYNTH16
To other CONGI
To
SYNTH16
To SYNTH16
From
other CONGI
alarms from
SYNTH16
REMOTE ALARM
6/4 HOUSKEEPING_IN
HK–IN
2 HOUSKEEPING_OUT
HK–OUT
RIMMEL
FANS unit
to/from
SYNTH16
FANS management
Serial Link
Temperature
sensor
NON SDH
EQUIPMENT
QMD
INTERFACE
(Q2)
to/from
SYNTH16
M
U
X
TRANSCEIVER
not used
–9V
OPERATION
SYSTEM
10BASE2
COAX
TRANSCEIVER
INTERFACE
(CTI)
10BASET
FAIL
Q3
INTERFACE
UNIVERSAL
ETHERNET
INTERFACE
ADAPTER
(AUI)
Remote
Inventory
M
U
X
to/from
SYNTH16
not used
+3.3 Vdc
RIBUS
I/F
RIBUS
to/from
SYNTH16
CMISS
1AA 00014 0004 (9007) A4 – ALICE 04.10
CONGI
Figure 242. CONGI – Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
456 / 531
17.7 SYNTH16 Board
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Refer to Figure 243. on page 464.
This board use SFP optical modules,the optical module can be distinguished by letters L and S defining
their dependance on optical components used for Long distance or Short distance.
The SDH functions required to manage STM–16 signal are implemented by four G.A.(G.A. #1 to G.A..#4
in Figure 243. on page 464) mounted on the board. They interface the matrix module and a special ASIC
mounted on the SYNTH16 board.
Another G.A. (G.A.5 in Figure 243. on page 464) is present with MUX/DEMUX and loop functions. This
G.A. interface the line side with one stream at 2488 Mbit/s and the equipment side with four stream at
622 Mbit/s.
Two types of loops are possible inside this G.A.:
–
–
Line loop
Internal loop.
Referring to the ITU–T G.783 recommendation, the four G.A. performs the following functions :
–
–
–
–
TTF (only the CRISTALLO #1 )
HOA (all CRISTALLO from 1 to 4)
LPOM /LSUT (all CRISTALLO from 1 to 4)
HPOM /HSUT ( only the CRISTALLO#1).
Cross connection functions (MSP, HPC and LPC) are performed by the MATRIX H and MATRIX L modules
mounted on two SYNTH16 boards (working in 1+1 configuration).
The TTF block is connected to the MATRIX H module and G.A.#7 mounted on the SYNTH16 board
through four bidirectional links at 622 Mbit/s in 1+1 configuration (H link).
HOA block is connected both to the MATRIX modules(HPC matrices and the LPC matrices) and a special
ASIC mounted on the SYNTH16 board through two bidirectional link at 622 MBit/s each in 1+1 configuration (”X link” and “L link” respectively)
G.A.#7 are used to establish three bidirectional links at 2.5 Gbit/s between two SYNTH16 in the backpanel. This G.A. interface the matrix or G.A.#1 to #4 side with four stream at 622 Mbit/s and interface the backpanel side with one stream at 2488 Mbit/s.
The G.A.#1 send and receive four 622 Mbit/s signal (data + clock) to/from the G.A.#5.
The SPI can detect an external LOS from the input line .
The SFP optical module provides to the G.A.#1 its status by means of two input signals: Laser Degrade
and Laser Failure.
The ALS algorithm is hardware implemented and the G.A.#1 provides the Laser shut Down command (LASER OFF).
1AA 00014 0004 (9007) A4 – ALICE 04.10
TTF BLOCK (SPI, RST, MST, MSA)
This block performs the Transport Terminal Functions (sink on Input side, source on Output side) for the
STM–16 signal.
TTF block provides the T1 timing references at 2 MHz , derived from the STM–16 input signals.
ED
03
3AG 24163 BEAA PCZZA
531
457 / 531
INPUT side : from line to MSP MATRIX H Module (in SYNTH16)
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
SPI (OSn/RSn_A_Sk): it descrambles the incoming signal , counts the OOF and reveals the LOF alarm.
RST (RSn_TT_Sk): performs frame alignment detection (A1, A2) , regenerator section trace recovery (J0)
and mismatch detection, BIP–8 Errored Block count.
MST (MSn_TT_Sk): performs BIP–24 errored block count, MS–REI recovery, MS–RDI and MS–AIS
detection. TSD is applied in case of MS–DEG (signal degrade), TSF is applied if MS–AIS is detected.
MSA (MSn/Sn_A_Sk): performs AU4’s pointer interpretation, LOP and AIS detection, pointer justification.
Sixteen MSA blocks are present.
Moreover the following functions are performed on the Input side :
TP byte insertion (Rx side): since the cross connection functions are centralized , for protection purpose
TSD (Trail Signal Degrade) and TSF (Trail Signal Failure) are transmitted towards the two SYNTH16
boards.
K BYTES insertion and extraction (Rx side): this block provides the in–band transmission of K1, K2,
bytes towards the G.A.#8 mounted on SYNTH16 board. The bytes are extracted from the line when a TSF
is received and they are transmitted towards G.A.#8 mounted on SYNTH16 board.
OUTPUT side: from MATRIX H MODULE(in SYNTH16) to line
MSA (Ms/Sn_A_So): it performs AUG assembly, AU–4 pointer generation, AU–AIS generation. The sixteen AU4 structure are byte interleaved in the STM–16 structure with fixed phase relationship vs. the same
multiple signal.
MST (MSn_TT_So): it performs BIP–24 calculation and insertion, MS–REI MS–RDI and MS–AIS insertion.
RST (RSn_TT_So): it performs frame alignment insertion, regenerator section path trace insertion, BIP–8
calculation and insertion.
K BYTES insertion and extraction (Tx side): K1, K2 bytes are extracted from the frame coming from
backpanel and re–inserted on the same output line frame.
HOA BLOCK (HPT, HPA)
From HPC matrix (MATRIX H) to LPC matrix (MATRIX L)
HPT (Sn_TT_Sk): path trace information is recovered, REI information is recovered, HP–RDI and UNEQ
are detected, VC4 BIP–8 errored count block. TSF is applied if SSF or UNEQ or TIM or AIS is detected.
TSD is applied if a condition of signal degrade is detected.
Moreover:
N1 byte extraction (Rx side): for the network Tandem Connection Termination & Monitoring function
(TCT/TCM).
1AA 00014 0004 (9007) A4 – ALICE 04.10
HPA (Sn/Sm_A_Sk): VC–4 disassembly, TU pointer interpretation, LOP and TU–AIS detection,HP–SLM
and LOM detection.
ED
03
3AG 24163 BEAA PCZZA
531
458 / 531
From LPC matrix(MATRIX L) to HPC matrix(MATRIX H)
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
HPA (Sn/Sm_A_So): VC4 assembly, TU pointer generation, TU–AIS generation , signal label insertion.
HPT (Sn_TT_So): path trace identification insertion, RDI and REI indications insertion, VC–4 BIP–8 calculation and insertion.
Moreover:
N1 byte insertion (Tx side): for the network Tandem Connection Termination & Monitoring function (TCT/
TCM).
The Cristallo provides also the HSUT, HPOM (alternative) and LSUT, LPOM functions (alternative) both
in Rx and Tx side.
The main task of HSUT are:
RX side (from MSA to HPC matrix):
•
•
•
•
•
Path trace information recovery
REI recovery
HP–RDI detection (path status monitoring
UNEQ and VC–AIS detection (signal label monitoring)
VC4 BIP–8 Errored Block count.
Tx side: (from HPC matrix to MSA)
•
•
•
•
Generation of an unequipped container
”unequipped” insertion, trail trace identifier generation
RDI and /or REI information generation
VC–4 BIP–8 calculation and insertion.
The main task of HPOM are:
RX and TX side:
1AA 00014 0004 (9007) A4 – ALICE 04.10
•
•
•
•
•
•
•
ED
Signal termination
J1 path recovering
REI information recovering
HP–RDI detection (path status monitoring
UNEQ and VC–AIS detection (signal label monitoring)
VC4 BIP–8 Errored Block count
TSF is generated in case of SSF , UNEQ, TIM , AIS . TSD is generated in case of SD.
03
3AG 24163 BEAA PCZZA
531
459 / 531
The main tasks of LSUT are :
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
RX side (from HPA to LPC matrix):
•
•
•
•
Recovering of VC–m unequipped signal label
Path trace recovering
BIP–2 recovery
REI and RDI recovery.
Tx side (from LPC matrix to HPA ):
•
•
•
•
Insertion of VC–m unequipped signal label
Path trace insertion
BIP–2 insertion
REI and RDI insertion.
LSUT is used to monitor unequipped path trails.
The main tasks of LPOM are :
–
–
–
–
Trace identifier monitoring
RDI and REI recovering and deriving for performance primitives
Signal label monitoring
VC–m BIP–2 errored block count.
LPOM is used for performance monitoring purposes.
There is a module named Cesconx mounted on SYNTH16 board. The Cesconx module is the hardware
platform designed to support both the Equipment Controller (EC) and Shelf Controller (SC) functions for
the 1662SMC and equipment.
The Cesconx module through the Equipment Controller (EC) manage:
–
–
–
–
–
Local dialog with a personal computer (F interface)
Dialog with a remote Operation System for Network Management operation through interface QAUX.
Dialog with the external equipment for Network Management operations through Interface Q2
(Mediation Device Function)
Remote alarms (RE) , alarms criteria towards the rack lamps (RA), housekeeping alarms (HK) and
front cover LED
ISSB bus.
The EC performs as well all the SW functions related to the control and management activities like info–
model processing, event reporting and logging, equipment data base management, SW downloading and
management, etc.
To support its activities the EC function requires a boot memory (FEPROM) and RAM memory. The EC
and SC software is loaded from the FLC in the main shelf.
F interface:
1AA 00014 0004 (9007) A4 – ALICE 04.10
It is used for connection to a local Craft Terminal; The standard implementation of the physical layer for
the F interface consists of an RS–232 UART port accessible from the EQUICO board front panel.
Q3 interface:
It is dedicated to an OS station connection through Local Access Network (LAN); QB3 requires a 10BASE2
or a 10BaseT interface that is physical provided by CONGI board.
ED
03
3AG 24163 BEAA PCZZA
531
460 / 531
Q2 interface:
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
A mediation function interface is provided to connect the 1662SMC to non–SDH network element The
RS–485 interface and the cable connector are provided on the CONGI board.
RE, RA, HK and LEDs interface:
RE consists of parallel I/O signals used for remote alarms that can be accessed on the CONGI board
RA is dedicated to send commands toward the rack to light up the relevant lamps.; the physical interface
is available on the CONGI board.
By pressing a push button is possible to store an alarm.
HK consist of parallel I/O signals used to handle housekeeping signals (for example alarms received from
FANs Subrack, open door etc.); In this way they can be supervised by Craft Terminal. The physical interface is available on the CONGI board.
The Equipment Controller also drive the LEDs present on the front cover to display alarms or status indication concerning the equipment.
By pressing a push button present on the SYNTH16 front cover is possible to check the efficiency of the
LEDs.
ISSB bus:
It is an high performance bus supporting communication among the EC function, the SC function on the
SYNTH16.
SHELF CONTROLLER FUNCTIONS
The SYNTH16 houses the circuitry necessary to realize the Shelf Controller.
The SC provide the resources to support the SW functions related to the control and management operation of the boards. To perform its functions, the SC directly interfaces the ASICs on the board implementing
the SDH functions for data collection (faults or alarm event detections, performance monitoring data) and
configuration provisioning.
As the SC is involved in critical activities ( for instance EPS ) , is 1+1 protected.
The internal interfaces supporting SC element for communication tasks are:
1AA 00014 0004 (9007) A4 – ALICE 04.10
SPI interface
On the ”CESCONX” module the SC processor is master of the ”SPI” interface that uses this bus to
access the inventory memory devices and the parallel I/O functions that are available on board each
controlled board in the equipment for control of board’s alarm led, board status or static alarms collection. The Saby chip on board ”CESCONX” is accessible as a slave device by the SC processor
through this interface.
Signals required for this interface are available on the mother board connectors with LVTTL levels.
ED
03
3AG 24163 BEAA PCZZA
531
461 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ISPB interface
The ”ISPB” interface is supported by the SC processor and consists of a backplane parallel bus
through which the processor can access memory mapped devices (SDH ASICs) placed on board
the controlled boards (in the 1662SMC: SDH or PDH port boards, SYNTH16 boards).
The ISPB bus is effectively an out board extension of the SC processor bus, controlled through a
bridge device.
All the related signals are available on the mother board(SYNTH16) connectors with LVTTL electrical
levels; the transceivers required for the LVTTL top GTLP signal conversion must be placed on the
mother board the ”CESCONX” module is plugged on.
MATRIX module also are mounted on the SYNTH16 board,the module performs different functions:
•
•
•
connections between ports
equipment synchronization functions
performance monitoring collection.
As the MATRIX module is in 1+1 redundant configuration, all the functions realized by the board are
redundant as well.
CONNECTIONS
The connections between MATRIX and ports are realized by means of links at 622 Mbit/s (link X, link L
and link H in Figure 243. on page 464)
On the MATRIX are implemented the following SDH functions to realize the connections :
MSP (Multiplex Section Protection)
It performs the Multiplex Section Protection (linear and MS–PRING) according to the MSP algorithm result.
Refer to para 13.7 on page 239 for details on MSP.
AU4 squelching
It is used to avoid mis–connections when the MS–SPRING protection is active. For each incoming and
outgoing AU4 , should be possible to insert AIS.
SNCP (Sub–Network Connection Protection)
It performs the Sub–Network Connection Protections, in case of SNCP–ring network configuration,switching from A to B path signals (A and B are two generic transmission side).
SNCP is of types HO–SNCP (for VC–4 path signals) and LO–SNCP (for VC–3 ,VC–12, etc. path signals).
It can be SNCP/I and SNCP/N.
Refer to para 13.7 on page 239 for details on SNCP protection.
HPC (High order Path Connection)
This block acts as connection matrix, supporting cross–connection for a max of 96x96 STM1 equivalent
signals at VC–4 level.
1AA 00014 0004 (9007) A4 – ALICE 04.10
LPC (Low order Path Connection)
This block acts as connection matrix, supporting cross–connection for a max of 64x64 STM1 equivalent
signals at VC–12 level.
ED
03
3AG 24163 BEAA PCZZA
531
462 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
EQUIPMENT SYNCHRONIZATION
The equipment synchronization is realized by the SETS function (Synchronous Equipment Timing
Source) that distributes to each equipment port the pertaining synchronization signals.
A high stability oscillator at 10 MHz is present to guarantee an holdover or free running working mode compliant to the ITU–T Recs.
The clock reference working modes can be: locked, hold over and free running.
When working in locked mode, the SETS block can select its reference signal among (the selection is accomplished by means of the software and craft terminal):
–
–
–
Timing reference signals coming from the SDH ports (T1)
2 MHz signal coming from the PDH ports (T2)
2 MHz clocks (T3) or 2 Mbit/s signals (T6) coming from the SERVICE board
The T3/T6 clocks are two (i.e. T3a, T3b or T6a, T6b).
The SETG block (Synchronous Equipment Timing Generation) generates :
–
–
–
–
A system clock T0 (at 622.08 MHz) locked to the selected reference (T1, T2, T3/T6) and distributed
to the equipment.
CK38Mhz: it is derived from the system clock (T0) and is distributed to all the ports. Its frequency
is 38.88 MHz.
MFSY: it is the multiframe synchronism at 500 Hz, obtained from the ck38 MHz. It is distributed to
all the ports.
a 2 MHz clock T4 or a 2 Mbit/s signal T5 used as synchronization clock.
The T4/T5 clocks are two (T4a, T4b and T5a, T5b).
Other functions implemented are:
RIBUS. It is a serial bus connecting the SC processor to the serially interfaced devices called RIBUS–I/F,
located on each board for simple read or write operations, for communications about Remote Inventory,
boards failure, bus releasing.
RIBUS I/F is powered by the +3.3 VDC supply by CONGI boards.
A push–button is present to reset the SC.
PERFORMANCE MONITORING COLLECTION
The “Performance Monitoring Management” block housed on the SYNTH16 board realizes Performance
Monitoring functionalities; it collects and stores the data ( Defect seconds and Errored blocks) coming from
all the flows.
The Performance monitoring can be made at:
1AA 00014 0004 (9007) A4 – ALICE 04.10
–
–
–
–
–
–
ED
Adaptation and Regeneration section
Multiplex section
Multiplex section adaptation
HSUT and LSUT
HPOM and LPOM
HPT and LPT.
03
3AG 24163 BEAA PCZZA
531
463 / 531
POWER SUPPLY
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The board receives via backpanel connectors the –48 V coming from CONGI boards.
The DC/DC converter present on the board generates the following voltage:
–
–
–
–
–
–
–
+3.3 V
+2.5 V
+1.8 V
+1.7 V
+1.5 V
+1.2 V
+0.6 V.
The Remote–Inventory and RIBUS–I/F blocks are powered by the 3.3 V power service coming from the
CONGI boards.
REMOTE INVENTORY
It is the memory used to maintain the board history and data.
For more details about the Remote Inventory function refer to para 13.13 on page 321.
1AA 00014 0004 (9007) A4 – ALICE 04.10
SYNTH16
To/from CONGI
Figure 243. SYNTH16 – Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
464 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
17.7.1 FAN Unit for FAN Shelf
The FANs shelf is composed by a mechanical structure and a back–plane. The FAN Shelf is used to prevent high temperature inside the 1662SMC equipment and must be equipped with four FAN units and two
Metallic FAN grids in the rack.
Each FANs unit is composed by four FANs and some electronic circuits necessary to:
–
–
–
–
FANs and alarms management
Metallic FAN grid management
Remote inventory
Power supply.
FUNCTION SPECIFICATION:
One FAN unit controller manages the power and FAN’s alarm and controls the FAN on/off. At the same
time this controller communicate with CONGI by serial interface.
FANS ALARM MANAGEMENT
The core of the FAN unit for FAN shelf is the “FAN Controller” that perform the following functionality:
–
FAN power supply: at the start up the control of FANs is distributed in sharing mode, so the max current value is reduced at only one FAN at a time.
–
FAN control: the sensing criteria is integrated in order to have an alarm if almost one FAN is out of
order.
If an alarm is present (FAN AL1, FAN AL2, FAN AL3, FAN AL4) because a FAN is temporary out of
order, the FAN controller try every 8 sec. to restart the FAN.
–
Temperature sensor: an external sensor generate an alarm (TEMP AL) when the temperature exceed 55_ C.
–
Remote inventory: through this interface the FAN controller read the information stored in the flash
EPROM.
–
LED control: the meaning of the LED is reported in Figure 113. on page 195.
–
Serial Alarms Interface: the FAN controller reports the alarm on a serial link toward the CONGI board
in order to transfer the information to the Shelf Controller on the SYNTH16.
The FANs controller generate an alarm called ALM_URG B #n if at least one FAN is faulty or the 12 VDC
is not present.
METALLIC FAN GRID
Two metallic FAN grids are present at the bottom of the FAN shelf in order to prevent dusty problem at
cooled circuit. These FAN grid could not be removed permanently because it performs also the function
of anti–fire protection.
If the FAN grid have been removed from the shelf an electro–mechanical sensor generate the alarm signal
FILTER AL.
1AA 00014 0004 (9007) A4 – ALICE 04.10
REMOTE INVENTORY
It is a flash EPROM where are stored information about the unit like construction date, code number, maker
name, Board–type, etc.
ED
03
3AG 24163 BEAA PCZZA
531
465 / 531
The main power supply is coming from two connectors: power supply “A” and power supply “B” coming
from station battery.
The voltage value for both batteries is: 48 VDC, 3 A max; in case of failure an alarm is generated (AL BAT_A,
AL BAT_B)
A DC/DC converter on the unit provides the 12 V necessary to power the FANs. Another DC/DC converter
provides the 3.3 V power supply voltage from which through a serial regulator is derived a 2.5 V.
If one of the above secondary voltage are not present, is generated an alarm (PSU ALM #n).
ATTENTION:
When insert the FAN unit into the FAN shelf, extract the FAN unit from the FAN shelf or do any operation
on the FAN unit, be sure to wear ESD protective wrist.
BATTERY B
BATTERY A
FILTER AL1
SLOT ID
FILTER AL2
FILTER AL1
BATTERY A
BATTERY B
FILTER AL1
SLOT ID
FILTER AL2
BATTERY A
BATTERY B
FILTER AL1
FILTER AL2
FILTER AL2
SLOT ID
SENSOR
Metallic FAN Grid 2
1AA 00014 0004 (9007) A4 – ALICE 04.10
SENSOR
Metallic FAN Grid 1
ÑÑ
ÑÑ
ÑÑ
ÑÑ
ÑÑ
ÌÌ
ÑÑÌÌ
ÑÑ
ÌÌ
ÑÑÌÌ
ÑÑ
ÑÑ
ÑÑ
ÑÑ
ÑÑ
ÑÑ
ÑÑ
ÑÑ
ÑÑ
ÌÌ
ÑÑÌÌ
ÑÑ
ÌÌ
ÑÑÌÌ
ÑÑ
ÑÑ
ÑÑ
BATTERY B
BATTERY A
BATTERY B
FILTER AL1
FILTER AL2
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑ
FAN UNIT
FOR FAN SHELF 19”
#0
FAN UNIT
FOR FAN SHELF 19”
#1
FAN UNIT
FOR FAN SHELF 19”
#2
FAN UNIT
FOR FAN SHELF 19”
#3
PSU ALM #3
PSU ALM #2
PSU ALM
>
_ 1
PSU ALM #1
to
CONGI
Housekeeping
BATTERY A
SLOT ID
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
POWER SUPPLY
PSU ALM #0
ALM_URG_B #0
ALM_URG_B #1
ALM_URG_B #2
>
_ 1
ALM_URG
ALM_URG_B #3
PSU ALM #1
ALM_URG_B #1
PSU ALM #2
ALM_URG_B #2
PSU ALM #3
ALM_URG_B #3
FAN SHELF 19”
Figure 244. FANs Shelf 19” General Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
466 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
AL_12V
ALBAT_A
BATTERY A
DC/DC
Converter
BATTERY B
DC/DC
Converter
+12 V
+12 V
+3.3 V
+3.3 V
+2.5 V
+2.5 V
SERIAL
REGULATOR
P
O
W
E
R
A
L
A
R
M
PSU ALM
ALBAT_B
FANS1
FANS2
FAN AL1
FANS3
FAN AL2
+ 12 V
FANS4
FAN AL3
+ 12 V
+ 12 V
FAN AL4
+ 12 V
ALBAT_B
ALBAT_A
AL_12V
FAN AL3
FAN AL4
FAN AL2
FAN AL1
FAN
control 4
FAN
control 3
FAN
control 2
FAN
control 1
TEMP_AL
TEMPERATURE
SENSOR
REMOTE
SLOT ID
INVENTORY
FANS CONTROL
FILTER AL1
FILTER
FILTER AL2
ALARM
FAULTY FANS
SENSOR
POWER
ALARM
LED
FANS CONTROLLER
ALM_URG_A
AL_12V
AL_FAN
SERIAL
ALARM
INTERFACE
A
SERIAL
ALARM
INTERFACE
B
NOT USED
ALM_URG_B
>
_ 1
AL_FAN
NOT USED
NOT USED
FANS MANAGEMENT
to
CONGI unit
1AA 00014 0004 (9007) A4 – ALICE 04.10
FAN UNIT FOR FAN SHELF19”
Figure 245. FANs Unit for FAN Shelf 19” Block Diagram
ED
03
3AG 24163 BEAA PCZZA
531
467 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ED
03
3AG 24163 BEAA PCZZA
531
468 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
18 TECHNICAL SPECIFICATIONS
Data indicated in the handbook must be considered as standard values.
Data indicated in the contract must be considered as guaranteed values.
18.1 General Characteristics
General
Optical Line bit rate
SDH:
SONET:
155.520 Mbit/s (STM–1)
622.080 Mbit/s (STM–4)
2,488.320 Mbit/s (STM–16)
9,953.280 Mbit/s (STM–64)
155.520 Mbit/s (OC–3)
622.080 Mbit/s (OC12)
Type of optical fiber
Single mode, according to ITU–T G.652, G.653 and G.654.
Wavelength
Refer to Table 56. on page 476 up to Table 63. on page 485.
Span length
Depending on fibre type and optical power budget reported in
Table 56. on page 476 up to Table 63. on page 485.
Application types
Metro Core Connect in protected and unprotected linear links
and rings, DXC (up to 4096 STM–1 equivalent ports).
Interface types
Optical interface: STM–1, STM–4, STM–16, STM–64 and GE.
Applied standards
ITU–T G.703 for electrical interfaces
ITU–T G.707 for SDH frame and multiplexing structure
ITU–T G.957, G.958 and G.691 for optical interfaces
ITU–T G.821 and G.826 for transmission quality
ITU–T G.813 for synchronization
ITU–T G.783 for SDH equipment specification
ITU–T G.841 for network protection architectures
ITU–T G.704 and G.774 for system management functions
ITU–T G.662 and G.663 for optical amplification
ITU–T G784/G.774 for system management functions
ITU–T G.8080F for architecture of GASON
ITU–T G.828/829 for error performances
1AA 00014 0004 (9007) A4 – ALICE 04.10
ITU–T G.798 for OTN
ED
03
3AG 24163 BEAA PCZZA
531
469 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Add–Drop and Cross connect features
Cross–Connections capacity
4096 x 4096 STM–1 equivalent ports at VC–4 level (640 Gb/s)
Connectivity
Aggregate–to–tributary time slot assignment.
Aggregate–to–aggregate time slot interchange.
Tributary–to–tributary time slot assignment.
Drop&continue.
Loopbacks.
Broadcast.
Cross connect features
1678MCC has a symmetrical architecture. All traffic port
(PDH, SDH) of the same type have the same functionality and
behavior and there is no inherent split between tributaries and
aggregates. This means that it is possible the allocation of the
PDH and VCi signals into every port.
Transmission delay
For each type of cross–connection
125 µs maximum for any traffic pathway
Protections
Network protection
Linear 1+1, single and dual ended MSP.
SNC–P/I, SNC–P/N.
Collapsed single and dual node interconnection.
Centralized Restoration.
MS–SPRing: 2F @STM–16 and 2F @STM–64.
Equipment protection (EPS)
Centralized Matrix: 1+1.
Equipment Controller: 1+1.
Shelf Controller: 1+1.
Management interface
Local:
Craft Interface
(PC)
RS232 PC compatible SUB–D 9 pins at 38 Kbit/s *
Remote:
Craft Interface
(PC)
RS232 PC compatible SUB–D 9 pins at 38 Kbit/s;
it handles up to 32 NEs via DCC (D1 ÷ D3 and/or D4 ÷ D12) *
* The maximum allowable length of the serial cable for RS232 is 15 m.
This is valid if:
–
Data speed is max. 38 Kbit/s
–
Cables of category CAT–5 are used (CAT–5 is what Alcatel–Lucent is using and is requesting for
this interface)
1AA 00014 0004 (9007) A4 – ALICE 04.10
Remote:
Dual addressing
to OS
ED
Transmission
Management
Network (TMN)
interface
G.773 QB3 10 base–2 and 10 base–T connectors
Information
Model
According to ITU–T (G.774) and ETSI specifications
It allows OS redundancy
03
3AG 24163 BEAA PCZZA
531
470 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Operation processes
Configuration and provisioning
Equipment, ports, add–drop, cross–connect,synchronization,
protection, MCF, SEMF, OH connection.
Software download
It is made locally as well as remotely on non volatile memories
without traffic interruption.
Performance monitoring
According to G.784, G.826 and G.821.
Remote inventory
At board and sub–board level.
Non volatile database
Yes.
Unit and Equipment acknowledgement
Through Remote Inventory
(Company id, Unit Type, Unit Part Number, Serial Part Number, Software Part Number etc.).
For details refer to Operator’s Handbook.
Security
Password, categories (operator profile), back–up for programs
and data.
OW interface
Type
64 kbit/s G.703 co–directional or telephone front jack
Engineering OW
E1 and E2 access, DTMF in band signalling
Unit substitution characteristics (hot replacement)
For traffic boards
without interfering on other channels
For central units (redundant)
without interfering on traffic
Housekeeping
8 inputs + 4 outputs (max)
System alarms
One LED on each board, Central LEDs
(URG, NURG, ABN, IND, ATTD)
Output Housekeeping signals (CPO) and Remote Alarms
By electronic relay contacts to be connected
to external negative voltage:
Max. guaranteed current with closed condition 50 mA
Voltage drops vs ground with closed condition
–2 V ÷ 0 V
Max. allowed voltage with open condition
–72 V
Input Housekeeping signals (CPI)
1AA 00014 0004 (9007) A4 – ALICE 04.10
Max. guaranteed current with closed condition 3 mA
Voltage drops vs ground with closed condition
–2 V ÷ 0 V
Max. allowed voltage with open condition
–72 V
ED
03
3AG 24163 BEAA PCZZA
531
471 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Clock characteristics (synchronization)
Selectable input clock
2048 kHz external from 2 Mbit/s port (T2).
2048 kHz external synch clock (T3).
2.048 Mbit/s or 1.544 Mbit/s signal from FLCSERV /
FLCCONGI board without data (T6)
STM–N sync clock interface (T1).
No. of selected clock (normal mode)
6 max.
Synchronization output
2048 kHz G.703 (2 output, T4a and T4b) or 2.048
Mbit/s (2 output, T5a and T5b).
Operational modes
Locked to reference.
Free–run mode ± 4.6 ppm (PLL without reference).
Holdover mode drift 0.37 ppm max./day (PLL with
stored frequency for more than half an hour,with no
selected input frequency).
Synchronization selection
Priority and SSM algorithm.
Equipment timing source options
Free–run accuracy ±4.6 ppm.
Holdover drift 0.37 ppm per day maximum.
ED
03
3AG 24163 BEAA PCZZA
531
472 / 531
18.2 Electrical Interface Characteristics
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
18.2.1 Electrical Transmission Interfaces
2 Mbit/s
2 Mbit/s 75 W
2 Mbit/s 120 W
Bitrate
2 048 kBit/s 50 ppm
Code
HDB3
Electrical interface
Output voltage (peak to peak)
according to ITU–T G.703
2.37 V 0.237 V
Return loss
Type of line
3 V 0.3 V
w12 dB 51 – 102 kHz
w18 dB 102 – 2048 kHz
w14 dB 2048 – 3072 kHz
coaxial pair, 75 Ω
Supported signal structure
symmetrical 120 Ω
Framed and unframed
140 Mbit/s
Bitrate
139 264 kBit/s 15 ppm
Code
CMI
Electrical interface
according to ITU–T G.703
Output voltage (peak to peak)
1 V 0.1 V
Return loss
w15 dB over frequency range 7 to 210 MHz
Type of line
coaxial pair, 75 Ω
Supported signal structure
Framed and unframed
1AA 00014 0004 (9007) A4 – ALICE 04.10
STM-1e
Bitrate
155 520 kBit/s 20 ppm
Code
CMI
Electrical interface
according to ITU–T G.703
Output voltage (peak to peak)
1 V 0.1 V
Return loss
w15 dB over frequency range 8 to 240 MHz
Type of line
coaxial pair, 75 Ω
ED
03
3AG 24163 BEAA PCZZA
531
473 / 531
V.11 64Kbit/s contradirectional interface
Type
electrical, according to ITU–T Rec. V.11
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Receivers:
Input impedance
> 6 KΩ
Rx levels
”1” or ”OFF” < –0.3 V
”0” or ”ON” > +0.3 V
Drivers:
Differential output
2 V (min.)
Use: intrabuilding connections
RS–232 oversampled interface 9600 Kbit/s
Bit rate
9600 kbit/s
Mode
RS–232 Tx & Rx data only
Electrical levels
24 Vpp
Use: intrabuilding connections
18.2.2 Electrical Safety
Electrical Safety
1AA 00014 0004 (9007) A4 – ALICE 04.10
Safety status of the connections with other
equipments
ED
TNV2 (Telecommunication Network Voltage) for
Remote Alarms, Housekeeping Alarms (CPO, CPI),
Rack Lamp (RM).
SELV (Safety Extra Low Voltage) for all the other.
03
3AG 24163 BEAA PCZZA
531
474 / 531
18.3 Optical Interface Characteristics
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
18.3.1 STM–N Optical Characteristics
STM–1 optical characteristics
Types of optical interfaces
S–1.1, L–1.1, L–1.2 (alternative modules).
Characteristics are given in Table 56. on page 476.
Optical connectors
SFP plug–in
Pulse shape
refer to ITU–T G.957
STM–4 optical characteristics
Types of optical interfaces
S–4.1, L–4.1, L–4.2 (alternative modules).
Characteristics are given in Table 57. on page 477.
Optical connectors
SFP plug–in
Pulse shape
refer to ITU–T G.957
STM–16 optical characteristics
Types of optical interfaces
I–16.1, S–16.1, L–16.1, L–16.2 (alternative modules).
Characteristics are given in Table 58. on page 478.
Optical connectors
SFP plug–in
Pulse shape
refer to ITU–T G.957
STM–64 optical characteristics
Types of optical interfaces
I–64.1, S–64.2, L–64.2, V–64.2, U–64.2
Characteristics are given in Table 59. on page 479.
Optical connectors
FC/PC or SC/PC (alternative units)
1 GE optical characteristics
Types of optical interfaces
1000B–LX, 1000B–SX
Characteristics are given in Table 62. on page 484 and
Table 63. on page 485.
Optical connectors
LC–Duplex SFP (Small Formfactor Pluggable)
1AA 00014 0004 (9007) A4 – ALICE 04.10
10 GE optical characteristics
Types of optical interfaces
10GBASE–S, 10GBASE–L, 10GBASE–E, 10GBASE–Z
Characteristics are given in Table 64. on page 486 and
Table 65. on page 487.
Optical connectors
FC/PC or SC/PC (alternative units)
ED
03
3AG 24163 BEAA PCZZA
531
475 / 531
Table 56. Parameters specified for STM–1 optical interface
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
CHARACTERISTICS
DIGITAL SIGNAL
Nominal bit rate
UNIT
VALUES
Kbit/s
STM–1 according to G.707,
G.958
155,520
Application code
Operating wavelength range
nm
S–1.1
L–1.1
L–1.2
1261
÷
1360
1280
÷
1335
1480
÷
1580
MLM
MLM
SLM
TRANSMITTER at reference point S
Source type
Spectral characteristics:
– maximum RMS width
nm
7.7
4
–
– maximum –20 dB width
nm
–
–
1
– min. side mode suppression ratio
dB
–
–
30
– maximum
dBm
–8
0
0
– minimum
dBm
–15
–5
–5
dB
8.2
10
10
Mean launch power:
Minimum extinction ratio
OPTICAL PATH between S and R
Attenuation range
Maximum dispersion
Minimum optical return loss (ORL) at S
(including connectors)
Maximum discrete reflectance
between S and R
RECEIVER at reference point R
dB
0÷12
10÷28
10÷28
ps/nm
100
250
1900
dB
n.a.
n.a.
20
dB
n.a.
n.a.
–25
Type of detector
In Ga As In Ga As In Ga As
PIN
PIN
PIN
Main received power (@ BER=10–10):
– minimum (sensitivity)
dBm
–28
–34
–34
– maximum (overload)
dBm
–8
–10
–10
Maximum optical path penalty
dB
1
1
1
Maximum reflectance of receiver
measured at R
dB
–14
–14
–25
1AA 00014 0004 (9007) A4 – ALICE 04.10
n.a. = not applicable
ED
03
3AG 24163 BEAA PCZZA
531
476 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Table 57. Parameters specified for STM–4 optical interface
CHARACTERISTICS
UNIT
DIGITAL SIGNAL
Nominal bit rate
Kbit/s
Application code
Operating wavelength range
nm
VALUES
STM–4 according to G.707, G.958
622,080
L–4.1
S–4.1
L–4.2
(nb1)
1274÷1356 1280÷1335 1480÷1580
TRANSMITTER at reference point S
Source type
MLM
SLM
SLM
Spectral characteristics:
– maximum RMS width
nm
2.5
–
–
– maximum –20 dB width
nm
–
1
1
– minimum side mode suppression ratio
dB
–
30
30
Mean launch power:
– maximum
dBm
–8
+2
+2
– minimum
dBm
–15
–3
–3
dB
8.2
10
10
dB
0÷12
10÷24
10÷24
ps/nm
84
250
1900
dB
14
20
24
dB
–20
–25
–27
In Ga As
PIN
In Ga As
PIN
In Ga As
PIN
Minimum extinction ratio
OPTICAL PATH between S and R
Attenuation range
Maximum dispersion
Minimum optical return loss (ORL) at S
(including connectors)
Maximum discrete reflectance between S
and R
RECEIVER at reference point R
Type of detector
Main received power (@ BER=10–10):
– minimum (sensitivity)
dBm
–28
–28
–28
– maximum (overload)
dBm
–8
–8
–8
Maximum optical path penalty
dB
1
1
1
Maximum reflectance of receiver measured at R
dB
–20
–20
–27
1AA 00014 0004 (9007) A4 – ALICE 04.10
(nb1) : suitable for interworking with the L–4.1 of the ADM product family; in this application the power
budget is 10÷24 dB, 250 ps/nm dispersion.
ED
03
3AG 24163 BEAA PCZZA
531
477 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Table 58. Parameters specified for STM–16 optical interfaces
CHARACTERISTICS
UNIT
VALUES
DIGITAL SIGNAL
Nominal bit rate
Kbit/s
STM–16 according to G.707,
G.958
2,488,320
Application code
Operating wavelength range
I–16.1
S–16.1
L–16.1
L–16.2
1270
÷
1360
1270
÷
1360
1280
÷
1335
1500
÷
1580
MLM
SLM
SLM
SLM
nm
nm
dB
4
–
–
–
1
30
–
1
30
–
1
30
dBm
dBm
dB
–3
–10
8.2
0
–5
8.2
+2
–2
8.2
+2
–2
8.2
dB
ps/nm
dB
0÷7
12
24
0÷12
100
24
10÷24
250
24
10÷24
1600
24
dB
–27
–27
–27
–27
nm
TRANSMITTER at reference point S
Source type
Spectral characteristics:
– maximum RMS width
– maximum –20 dB width
– minimum side mode
suppression ratio
Mean launch power:
– maximum
– minimum
Minimum extinction ratio
OPTICAL PATH between S and R
Attenuation range
Maximum dispersion
Minimum ORL at S (including connectors)
Maximum discrete reflectance between S and R
RECEIVER at reference point R
Type of detector
Mean received power
(@ BER=10–10):
– minimum (sensitivity)
– maximum (overload)
Maximum optical path penalty
1AA 00014 0004 (9007) A4 – ALICE 04.10
Maximum reflectance of receiver measured at R
ED
InGaAs InGaAs InGaAs InGaAs
PIN
PIN
APD
APD
dBm
dBm
dB
–18
–3
1
–18
0
1
–27
–8
1
–28
–8
2
dB
–27
–27
–27
–27
03
3AG 24163 BEAA PCZZA
531
478 / 531
Table 59. Parameters specified for STM–64 optical interfaces
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
CHARACTERISTICS
UNIT
VALUES
DIGITAL SIGNAL
Nominal bit rate
STM–64 according to
G.707, G.958, G.691
9,953,280
Kbit/s
Application code
VALUES
I–64.1
S–64.2b
L–64.2b
1290÷1330
1530÷1565
1530÷1565
SLM
EA–ILM
EA–ILM
mW/MHz
t.b.d.
t.b.d.
t.b.d.
– maximum –20 dB width
nm
1
t.b.d.
t.b.d.
– minimum side mode suppression ratio
dB
30
30
t.b.d.
radians
t.b.d.
t.b.d.
t.b.d.
– maximum
dBm
–1
+2
12
– minimum
dBm
–6
–1
10
dB
6
8.2
8.2
dB
0÷4
3÷11
13÷22
Operating wavelength range
nm
TRANSMITTER at reference point S
Source type
Spectral characteristics:
– maximum spectral power density
– chirp parameter
Mean launch power:
Minimum extinction ratio
OPTICAL PATH between S and R
Attenuation range
Chromatic dispersion:
– maximum
ps/nm
6.6
800
1600
– minimum
ps/nm
n.a.
n.a.
t.b.d.
ps/nm
30
30
30
Minimum ORL at S (including connectors)
dB
14
24
24
Maxim. discrete reflectance between S and R
dB
–27
–27
–27
PIN
PIN
PIN
dBm
–11
–14
–14
dBm
–1
–1
–1
Maximum optical path penalty
dB
1
2
2 *)
Maxim. reflectance of receiver measured at R
dB
–14
–27
–27
Maximum DGD
RECEIVER at reference point R
Type of detector
Mean received power:
(@ BER= 10–12 and OSNR=19 dB/0.1 nm)
– minimum (sensitivity)
– maximum (overload)
1AA 00014 0004 (9007) A4 – ALICE 04.10
t.b.d.= to be defined
n.a. = not applicable
*)
= with 10dB attenuation
ED
03
3AG 24163 BEAA PCZZA
531
479 / 531
Table 60. Parameters specified for STM–64 optical interface – P1L1–2D2 long–haul application
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
CHARACTERISTICS
UNIT
VALUES
Kbit/s
STM–64 according to
G.959
9,953,280
DIGITAL SIGNAL
Nominal bit rate
Signal class
NRZ 10G long–haul
Application code
P1L1–2D2
Operating wavelength range
nm
1530÷1565
TRANSMITTER at reference point S
Source type
SLM
Spectral characteristics:
– maximum spectral power density
mW/MHz
t.b.d.
– maximum –20 dB width
nm
t.b.d.
– minimum side mode suppression ratio
dB
30
radians
t.b.d.
– maximum
dBm
+4
– minimum
dBm
0
dB
9
dB
11÷22
– maximum
ps/nm
1600
– minimum
ps/nm
t.b.d.
– chirp parameter
Mean launch power:
Minimum extinction ratio
OPTICAL PATH between S and R
Attenuation range
Chromatic dispersion:
Maximum DGD
ps/nm
30
Minimum ORL at S (including connectors)
dB
24
Maxim. discrete reflectance between S and R
dB
–27
RECEIVER at reference point R
Type of detector
Mean received power:
(@ BER= 10–12 and OSNR=19 dB/0.1 nm)
– minimum (sensitivity)
PIN
dBm
–24
dBm
–7
Maximum optical path penalty
dB
2
Maxim. reflectance of receiver measured at R
dB
–27
– maximum (overload)
1AA 00014 0004 (9007) A4 – ALICE 04.10
t.b.d.= to be defined
ED
03
3AG 24163 BEAA PCZZA
531
480 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
18.3.1.1 L–64.2 Application (Long Haul)
This is a single port board supporting the long haul application L–64.2. The optical components are not
pluggable, they are fixed on the board. A booster is integrated on the board, the booster is connected with
an optical cable on the front panel. No external booster is required.
An external 10dB attenuator has to be used between the ILM output and the input of the booster.
The L–64.2 board can be used for distances up to 80 km.
Figure 246. on page 481 shows the network block diagram for implementing L–64.2 application.
10dB
Attenuator
E/O
Tx
Framer
Booster
externalpart
O/E
Rx
Figure 246. Long Haul Application (L–64.2)
18.3.1.2 V–64.2 Application (Very Long Haul)
V–64.2 Alcatel–Lucent solution is based on usage of interfaces with Forward Error Correction (FEC), Dispersion Compensation Module (DCM) and preamplifier. The DCM is a passive component without any
control functions. Up to two DCMs are located in a Dispersion Compensation Unit (DCU). The DCU is an
external component, which is mounted as separate unit in the rack (refer to chapter 9.4 on page 77).
The V–64.2 board can be used for distances up to 120 km.
Figure 247. on page 481 shows the network block diagram for implementing V–64.2 application.
E/O
Tx
Framer
externalpart
FEC
1AA 00014 0004 (9007) A4 – ALICE 04.10
O/E
Rx
Pre−
ampl.
DCM
Figure 247. Very Long Haul Application (V–64.2)
ED
03
3AG 24163 BEAA PCZZA
531
481 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
18.3.1.3 U–64.2 Application (Ultra Long Haul)
U–64.2 Alcatel–Lucent solution is based on usage of interfaces with FEC, DCMs, booster and preamplifier. The board has the same function as the V–64.2 board with the addition of a booster and an additional
DCM.
The U–64.2 board can be used for distances up to 160 km.
Figure 248. on page 482 shows the network block diagram for implementing U–64.2 application.
pumpfailure(PF)−>HWError
inputPowerLoss(IPL)−>notreported
E/O
Tx
Framer
FEC
DCM
externalparts
LOS
O/E
Rx
Booster
pumpfailure(PF)−>HWError
inputPowerLoss(IPL)−>notreported
Pre−
ampl.
DCM
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 248. Ultra Long Haul Application (U–64.2)
ED
03
3AG 24163 BEAA PCZZA
531
482 / 531
Table 61. Parameters specified for STM–64 optical interfaces
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
CHARACTERISTICS
UNIT
VALUES
Kbit/s
STM–64 according to
Alcatel–Lucent proprietary
9,953,280
DIGITAL SIGNAL
Nominal bit rate
Application code
Operating wavelength range
V–64.2
U–64.2
nm
1550.12
1550.12
mW/MHz
t.b.d.
t.b.d.
nm
t.b.d.
t.b.d.
TRANSMITTER at reference point S
Source type
Spectral characteristics:
– maximum spectral power density
– maximum –20 dB width
– minimum side mode suppression ratio
dB
30
30
radians
00.1
00.1
– maximum
dBm
3
12
– minimum
dBm
0
10
dB
10
10
dB
20÷35
25÷44
– maximum
ps/nm
1000
1000
– minimum
ps/nm
–560
–560
ps/nm
t.b.d.
t.b.d.
– chirp parameter
Mean launch power:
Minimum extinction ratio
OPTICAL PATH between S and R
Attenuation range
Chromatic dispersion:
Maximum DGD
Minimum ORL at S (including connectors)
dB
24
24
Maxim. discrete reflectance between S and R
dB
–27
–27
PIN
PIN
dBm
–33
–34
dBm
–13.5
–13
dB
–27
–27
RECEIVER at reference point R
Type of detector
Mean received power:
(@ BER= 10–12 and OSNR=19 dB/0.1 nm)
– minimum (sensitivity)
– maximum (overload)
Maxim. reflectance of receiver measured at R
1AA 00014 0004 (9007) A4 – ALICE 04.10
t.b.d.= to be defined
ED
03
3AG 24163 BEAA PCZZA
531
483 / 531
Table 62. Parameters specified for 1000B–SX Optical Interface
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
CHARACTERISTICS
DIGITAL SIGNAL
Nominal bit rate
VALUES
Gbps
GE interface according to IEEE 802.3
1.250 Gbps
Application code
TX SIDE
1000B–SX
UNIT
CONDITIONS
MIN
MAX
Output optical power
dBm
–
–9.5
–4.0
Output optical power BOL
(25ºC, nominal power supply)
dBm
–
–8.5
–4.0
Operating wavelength range
nm
–
820
860
∆λ rms
nm
–
–
0.85
dB/Hz
–
–
–117
Relative Intensity Noise
RX SIDE
Type of detector
Sensitivity
dBm
*
–
–18.0
Sensitivity BOL
(25ºC, nominal power supply)
dBm
*
–
–19.0
Stressed Receiver Sensitivity
dBm
See IEEE 802.3
–
–12.5 (62.5µm)
–13.5 (50µm)
Maximum input optical power
dBm
–
–
0
Maximum input optical power BOL
(25ºC, nominal power supply)
dBm
–
–
+1.0
nm
–
770
860
Loss of signal – Assert Pin
dBm
–
–30
–18.0
Loss of signal – Deassert Pin
dBm
–
–30
–17.0
LOS Hysteresis
dB
–
1
4.0
Data Output Rise/Fall time
ps
–
–
250
Operating wavelength range
* With fiber:
1AA 00014 0004 (9007) A4 – ALICE 04.10
IN Ga As PIN
ED
550 m MMF 50 µm (500 MHz Km @ 850nm)
500 m MMF 50 µm (400 MHz Km @ 850nm)
275 m MMF 62.5 µm (200 MHz Km @ 850nm)
220 m MMF 62.5 µm (160 MHz Km @ 850nm)
03
3AG 24163 BEAA PCZZA
531
484 / 531
Table 63. Parameters specified for 1000B–LX Optical Interface
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
CHARACTERISTICS
DIGITAL SIGNAL
Nominal bit rate
VALUES
Gbps
GE interface according to IEEE 802.3
1.250 Gbps
Application code
TX SIDE
1000B–LX
UNIT
CONDITIONS
MIN
MAX
Output optical power (SMF)
dBm
–
–11.0
–3.0
Output optical power BOL (SMF)
(25ºC, nominal power supply)
dBm
–
–10.0
–3.0
Output optical power on MMF 50 &
62.5µm
dBm
–
–11.5
–3.0
Output optical power BOL on MMF
50 & 62.5µm (25ºC, nominal power
supply)
dBm
–
–10.5
–3.0
Operating wavelength range
nm
–
1270
1355
∆λ rms
nm
–
–
4.0
dB/Hz
–
–
–120
Relative Intensity Noise
RX SIDE
Type of detector
Sensitivity
dBm
*
–
–20.0
Sensitivity BOL
(25ºC, nominal power supply)
dBm
*
–
–21.0
Stressed Receiver Sensitivity
dBm
See IEEE 802.3
–
–14.4
Maximum input optical power
dBm
–
–
–3.0
Maximum input optical power BOL
(25ºC, nominal power supply)
dBm
–
–
–2.0
nm
–
1270
1355
Loss of signal – Assert Pin
dBm
–
–30
–21.0
Loss of signal – Deassert Pin
dBm
–
–30
–20.0
LOS Hysteresis
dB
–
1
4.0
Data Output Rise/Fall time
ps
–
–
175
Operating wavelength range
* With fiber:
1AA 00014 0004 (9007) A4 – ALICE 04.10
IN Ga As PIN
ED
550 m MMF 50 µm (400 MHz Km @ 1300nm)
550 m MMF 62.5 µm (500 MHz Km @ 1300nm)
5000 m SMF 10 µm
03
3AG 24163 BEAA PCZZA
531
485 / 531
Table 64. Parameters specified for 10GE–SR
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
PARAMETER
Digital Signal
UNIT
MIN
TYP
MAX
10GE according to IEEE 802.3ae
Nominal bit rate (Kbit/s)
10,312,5
Application code
10GBASE–SR
Optical Transmitter Data Output
Laser Safety Class
Center wavelength
Class 1 according to IEC 60825
nm
840
Optical average output power (Pout)
dBm
–7.3
Pout in shut–down (Pout_sd)
dBm
Optical modulation amplitude (OMA)
860
> –6.3
–30
dBm
Note 1
Spectral width RMS
nm
Note 1
Extinction ratio
dB
3
Eye mask
ORL at MPI–S interface
RIN12OMA (Note 2)
–1
IEEE 802.3ae–2002
dB
12
dB/Hz
–128
Link power budget
Note 4
Optical Receiver Data Input
Operating wavelength
nm
840
860
Sensitivity @ BER=1e–12 (Note 3)
dBm
< –11.9
–9.9
Receiver Sensitivity in OMA
dBm
< –13.1
–11.1
Stressed receiver sensitivity in OMA (Note 2)
dBm
Receiver reflectance
–7.5
dB
Jitter tolerance
–14
IEEE 802.3ae–2002
Note 1: Conforms to IEEE 802.3ae–2002: Triple Tradeoff Curves (TTC) figure 52–3 and table 52–8
Note 2: Test pattern and procedure according to IEEE 802.3ae–2002
Note 3: Sensitivity in average power measured in back–to–back conditions
1AA 00014 0004 (9007) A4 – ALICE 04.10
Note 4: Conforms to IEEE 802.3ae–2002, table 52–10
ED
03
3AG 24163 BEAA PCZZA
531
486 / 531
Table 65. Parameters specified for 10GE–LR,–ER,–ZR
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
CHARACTERISTICS
UNIT
VALUES
DIGITAL SIGNAL
Nominal bit rate
10GE according to
IEEE 802.3ae
10,312,5
Kbit/s
Application code
VALUES
10GBASE-LR
10GBASE-ER
10GBASE-ZR
1290÷1330
1530÷1565
1530÷1565
SLM
EA–ILM
EA–ILM
mW/MHz
t.b.d.
t.b.d.
t.b.d.
nm
1
t.b.d.
t.b.d.
dB
30
30
t.b.d.
radians
t.b.d.
t.b.d.
t.b.d.
– maximum
dBm
–1
+2
12
– minimum
dBm
–6
–1
10
dB
6
8.2
8.2
dB
0÷4
3÷11
13÷22
– maximum
ps/nm
6.6
800
1600
– minimum
ps/nm
n.a.
n.a.
t.b.d.
ps/nm
30
30
30
dB
14
24
24
dB
–27
–27
–27
PIN
PIN
PIN
Operating wavelength range
nm
TRANSMITTER at reference point S
Source type
Spectral characteristics:
– maximum spectral power density
– maximum –20 dB width
– minimum side mode suppression
ratio
– chirp parameter
Mean launch power:
Minimum extinction ratio
OPTICAL PATH between S and R
Attenuation range
Chromatic dispersion:
Maximum DGD
Minimum ORL at S (including connectors)
Maxim. discrete reflectance between S
and R
RECEIVER at reference point R
Type of detector
1AA 00014 0004 (9007) A4 – ALICE 04.10
Mean received power:
(@ BER= 10–12 and OSNR=19 dB/0.1
nm)
– minimum (sensitivity)
dBm
–11
–14
–14
– maximum (overload)
dBm
–1
–1
–1
Maximum optical path penalty
dB
1
2
2
Maxim. reflectance of receiver measured at R
dB
–14
–27
–27
ED
03
3AG 24163 BEAA PCZZA
531
487 / 531
18.3.2 Optical Safety
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
18.3.2.1 Hazard Level classification
The HAZARD LEVEL classification of the different optical interfaces is given in Table 66. on page 488.
The hazard level was assigned in accordance with the requirements of IEC 60825–1 (1998) + Am. 2
(2001) and IEC 60825–2 (2000) or IEC 60825–1 (1998) and IEC 60825–2 (2000).
Table 66. Hazard level classification of different optical interfaces
MODULE or PORT
ED
OPTICAL INTERFACE
HAZARD LEVEL
STM–1
S–1.1 (short haul)
1
STM–1
L–1.1 (long haul)
1M
STM–1
L–1.2 (long haul)
1M
STM–4
S–4.1 (short haul)
1
STM–4
L–4.1 (long haul)
1M
1M
STM–4
L–4.2 (long haul)
STM–16
I–16.1 (intra–office)
1
STM–16
S–16.1 (short haul)
1
STM–16
L–16.1 (long haul)
1M
STM–16
L–16.2 (long haul)
1M
STM–64
I–64.1 (intra–office)
1
STM–64
S–64.2 (short haul)
1M
STM–64
L–64.2 (long haul)
1M
STM–64
V–64.2 (very long haul)
1M
STM–64
U–64.2 (ultra long haul)
1M
STM–64
L–64.2CF colored port (multi channel)
1M
GE
1000B–SX
1
GE
1000B–LX
1
GE
10GBASE–S
1
03
3AG 24163 BEAA PCZZA
531
488 / 531
18.3.2.2 Incorporated Laser Sources Characteristics
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Output optical interfaces data: the wavelength and the maximum optical power at the output connector
of incorporated laser sources is given in Table 67. on page 489.
Table 67. Incorporated laser sources characteristics
MODULE or
PORT
OPTICAL
INTERFACE
WAVELENGTH
[nm]
MAX. OPT. POWER
[mW]
STM–1
S–1.1 (short haul)
1261 ÷ 1360
0.16
STM–1
L–1.1 (long haul)
1280 ÷ 1335
1
STM–1
L–1.2 (long haul)
1480 ÷ 1580
1
STM–4
S–4.1 (short haul)
1274 ÷ 1356
0.16
STM–4
L–4.1 (long haul)
1280 ÷ 1335
1.6
STM–4
L–4.2 (long haul)
1480 ÷ 1580
1.6
STM–16
I–16.1 (intra–office)
1270 ÷ 1360
1
STM–16
S–16.1 (short haul)
1270 ÷ 1360
1
STM–16
L–16.1 (long haul)
1280 ÷ 1335
1.6
STM–16
L–16.2 (long haul)
1500 ÷ 1580
1.6
STM–64
I–64.1 (intra–office)
1290 ÷ 1330
0.8
STM–64
S–64.2 (short haul)
1530 ÷ 1565
1.6
STM–64
L–64.2 (long haul)
1530 ÷ 1565
16
STM–64
V–64.2 (very long haul)
1550.12
4.5
STM–64
U–64.2 (ultra long haul)
1550.12
16
GE
1000B–SX
820 ÷ 860
0.4
GE
1000B–LX
1270 ÷ 1355
0.5
GE
10GBASE–LX
840 ÷ 860
0.4
1AA 00014 0004 (9007) A4 – ALICE 04.10
Note: the maximum optical power at the interfaces is in normal operating conditions and depends on setting and calibration carried out during the factory test or installation.
ED
03
3AG 24163 BEAA PCZZA
531
489 / 531
18.3.2.3 Location Type
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The equipment shall be installed in “restricted locations” (industrial and commercial premises) or “controlled locations” (optical cable ducts and switching centers).
18.3.2.4 Labelling
The label are affixed in factory on this cover protection fibre.
Only the labels corresponding to the worst case at 2nd and 3rd window are put on the cover.
In the following description it is specified when the label shall be affixed by the customer.
The optical interfaces which have HAZARD LEVEL 1 (refer to Table 66. on page 488) carry the following
explanatory label (a multilingual label kit is also provided):
The label is put on the fibre protection cover of the following parts:
•
•
•
•
•
•
•
STM–1 port with S–1.1 interface
STM–4 port with S–4.1 interface
STM–16 port with I–16.1 interface
STM–16 port with S–16.1 interface
STM–64 port with I–64.1 interface
GE port with 1000Base SX
GE port with 1000Base LX.
The optical interfaces which have HAZARD LEVEL 1M (refer to Table 66. on page 488) carry the hazard
symbol label:
1AA 00014 0004 (9007) A4 – ALICE 04.10
The label is affixed near the optical connectors on the front plate of the following interfaces:
•
•
•
•
•
•
•
•
•
•
•
ED
L–1.1
L–1.2
L–4.1
L–4.2
L–16.1
L–16.2
S–64.2
L–64.2
L–64.2 CF
V–64.2
U–64.2
(STM–1 port)
(STM–1 port)
(STM–4 port)
(STM–4 port)
(STM–16 port)
(STM–16 port)
(STM–64 port)
(STM–64 port)
(colored STM–64 port multi channel)
(STM–64 port)
(STM–64 port)
03
3AG 24163 BEAA PCZZA
531
490 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The optical interfaces which have HAZARD LEVEL 1M and operate at 2nd window (refer to Table 66. on
page 488), carry the following explanatory label (a multilingual label kit is also provided):
The label is affixed on the fibre protection cover of the following parts:
•
•
•
STM–1 port with L–1.1 interface
STM–4 port with L–4.1 interface
STM–16 port with L–16.1 interface.
The optical interfaces which have HAZARD LEVEL 1M and operate at 3rd window (refer to Table 66. on
page 488), carry the following explanatory label (a multilingual label kit is also provided):
The label is affixed on the fibre protection cover of the following parts:
•
•
•
•
•
•
•
STM–1 port with L–1.2 interface
STM–4 port with L–4.2 interface
STM–16 port with L–16.2 interface
STM–64 port with S–64.2 interface
STM–64 port with L–64.2 colored interface (multi channel)
STM–64 port with V–64.2 interface
STM–64 port with U–64.2 interface.
The multilingual label kit, for STM–1 ports, is placed in the same plastic bag provided together with the
module where explanatory labels (in English language), above mentioned, are put.
For all other units the multilingual label kit is inserted in the pre–package.
The multilingual label kit contains a set of label that reproduce the same (explanatory) above depicted in
the following languages:
1AA 00014 0004 (9007) A4 – ALICE 04.10
•
•
•
•
ED
Italian
French
Spanish
German.
03
3AG 24163 BEAA PCZZA
531
491 / 531
18.3.2.5 Apertures and Fibre Connectors
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The locations of apertures and fibre connectors are reported on topographical drawings of units front view
in para. 10.3 on page 103.
18.3.2.6 Engineering Design Features
In normal operating conditions, unless intentional manumission, the laser radiation is never accessible.
The laser beam is launched in optical fibre through an appropriate connector that totally shuts up the laser
radiation. Moreover a plastic cover is fitted upon optical connectors by means of screws.
In case of cable fibre break, to minimize exposure times, ALS procedure according to ITU–T G.958 Rec.
is implemented on STM–N ports.
The shutdown timing is 550 ± 50 ms; the reactivation timing is less than 850 ms.
18.3.2.7 Safety Instructions
The safety instructions for proper assembly, maintenance, and safe use including clear warning concerning precautions to avoid possible exposure to hazardous laser radiation, are reported in the handbook
“Safety Instructions”.
ED
03
3AG 24163 BEAA PCZZA
531
492 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
18.4 Power Supply Characteristics
Input Voltage (Battery):
–48/–60 VDC
in according to ETSI EN 300 132–2 V2.1.2 (2003–09)
Functional Protection Earth:
FPE–2 wire or FPE–3 wire
Max. power consumption:
1678MCC Shelf:
1670SM Shelf:
1662SMC Shelf:
ED
2000 W maximum
1000 W maximum
500 W maximum
03
3AG 24163 BEAA PCZZA
531
493 / 531
18.5 Alarm Characteristics
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
18.5.1 Units Alarms
Each port board or access board of the equipment is provided with a bicolor LED (green/red) on the front
coverplate.
This LED indicates:
•
•
when red, internal failure
when green, in service unit.
18.5.2 Centralized Equipment Alarms
All the alarms detected on the units are collected by the First Level Controller (FLC) board which will
deliver centralized optical indications (by means of LEDs on its front coverplate).
Specifically:
•
•
•
Red LED (4): detection of an URGENT alarm (MAJOR)
Red LED (5): detection of a NOT URGENT alarm (MINOR)
Yellow LED (7): detection of an ABNORMAL operative condition. Type: active loopbacks, forcing the unit into service, laser forced ON or OFF, try to restore after ALS.
Yellow LED (8): detection of an INDICATIVE alarm (WARNING)
Yellow LED (6): alarm condition ATTENDED.
•
•
Refer to para. 10.3 on page 103, where the front view of each unit and the LED locations are illustrated.
Note:
On the Craft Terminal (CT) and on the Operation System (OS) application the URGENT (URG), NOT URGENT (NURG) and INDICATIVE alarm are named in a different way; the relation between this two terminology is explained in Table 68. on page 494.
Table 68. Relation between Alarm severity terminology
Alarm severity terminology
on CT and OS
Alarm severity terminology
used for EC
CRITICAL or MAJOR
URG , T*URG, T*RURG,
MINOR
NURG, , T*NURG, T*RNURG
WARNING
INDICATIVE
INDETERMINATE (not used)
––
18.5.3 Trouble–shooting
1AA 00014 0004 (9007) A4 – ALICE 04.10
The 1678MCC equipment has been designed to dialog with a Personal Computer (PC) in order to service,
activate and trouble–shoot the equipment.
Trouble–shoot procedure for the equipment and details of the alarms for each board and relevant indications are described in the Operator’s Troubleshooting and Maintenance Handbook.
Connection with the PC is achieved through connector available on Equipment Controller board.
The board can be connected to an Operations System associated to the Transmission Management Network in order to execute operations similar to those carried out by the PC.
ED
03
3AG 24163 BEAA PCZZA
531
494 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
18.6 Mechanical Characteristics
18.6.1 1678MCC Rack
H
Equipment practice
(mechanical compatibility)
1678MCC rack according to
ETS 300 119 – 2
D
W
Rack size
(mm)
600 W x 300 D x 2200 H
Rack cabling
Vertical between rack and subrack – Front access
Back–to–back installation
Yes
18.6.2 OED Rack
Equipment practice
(mechanical compatibility)
Optinex rack according to
ETS 300 119 – 2
Rack size
600 W x 300 D x 2200 H
(mm)
Rack cabling
Vertical between rack and subrack – Front access
Back–to–back installation
Yes
1AA 00014 0004 (9007) A4 – ALICE 04.10
18.6.3 1678MCC Main Shelf
Shelf size
(mm)
(including cable channel)
533 W x 294 D x 674 H
Board size
Traffic Port board:
(mm)
217.5 D x 475 H
Cooling
Forced, heat pipe technique
Electrical Connectors
IEC 807 (Sub–D)
IEC 169–1 (coax. 1.0/2.3)
ED
03
3AG 24163 BEAA PCZZA
531
495 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
18.6.4 1678MCC Main Shelf (SONET)
Shelf size
(mm)
(including cable channel and Dust filter)
533 W x 294 D x 684 H
Board size
Traffic Port board:
(mm)
217.5 D x 475 H
Cooling
Forced, heat pipe technique
Electrical Connectors
IEC 807 (Sub–D)
IEC 169–1 (coax. 1.0/2.3)
18.6.5 1670SM Shelf
Shelf size
(mm)
Main Shelf
FANs Subrack
533 W x 280 D x 875 H
533 W x 280 D x 75 H
Board size
(mm)
Port board:
Access board:
FANs Unit:
213 D x 265 H
92 D x 265 H
495 W x 268.5 D x 28.5 H
Cooling
Forced
Electrical Connectors
IEC 807 (Sub–D)
IEC 169–1 (coax. 1.0/2.3)
1AA 00014 0004 (9007) A4 – ALICE 04.10
18.6.6 1662SMC Shelf
Shelf size
(mm)
Main Shelf
FANs Subrack
Board size
(mm)
213 D x 265 H
470 W x 250 D x 390 H
533 W x 280 D x 110 H
Cooling
Forced
Electrical Connectors
IEC 603/DIN 41612
IEC 807 (Sub–D)
IEC 169–1 (coax. 1.0/2.3)
BNC 50 Ω
RJ11
ED
03
3AG 24163 BEAA PCZZA
531
496 / 531
18.7 Environmental Conditions
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Main environmental aspects of Alcatel–Lucent products are:
–
–
–
–
–
Energy consumption during manufacturing and use,
Materials harmfulness and recyclability,
Emissions to air, water or soil related to the manufacturing and the use of the product,
Electromagnetic (EM) emissions,
Value recovery at the product end of life.
18.7.1 Waste from Electrical and Electronic Equipment (WEEE)
printed on the shelf (refer to Figure 1. on page 28 and Table 7. on page 27) denotes
The marking
compliancy with the Directive 2002/96/EC On Waste of Electrical and Electronic Equipment.
The general principle is the producer responsibility in the management of the products he puts on the market when discarded by the owner. The producer responsibility now covers the end of life of the products
sold.
The European directive is effective in a country once transposed. The starting date for the producer responsibility for the European text is August 13, 2005.
All Alcatel–Lucent products fall under in Category 3 of Annex 1A of the WEEE directive (Directive 2002/96/
EC) i.e. ”IT and Telecommunication equipment” under item ”other products transmitting sound, images
or other information by telecommunications.”
Alcatel–Lucent products fall under WEEE directive name: ”Other product or equipment of transmitting
sound, images or other information by telecommunications” in Annex 1B.
This mark will not cause any responsibility as all responsibilities will be defined by contract.
18.7.2 Acoustical noise
The acoustical noise level of the product complies with:
1AA 00014 0004 (9007) A4 – ALICE 04.10
–
ED
ETS 300 753 Environmental Class 3.1 for attended telecommunication equipment rooms (maximum
sound level 7.2 bels)
03
3AG 24163 BEAA PCZZA
531
497 / 531
18.7.3 Climatic for Operating Conditions
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The 1678MCC Equipment meets the requirements of ETSI Standards.
It uses FAN units.
The functionality of the 1678MCC Equipment, vs. Temperature, is in compliance with:
ETS 300 019–1–3 : February 1992 , class 3.1
Class 3.1 :
Temperature–controlled locations.
This class applies to a weather protected location having neither temperature nor humidity control. The
location may have openings directly to the open air, i.e. may be only partially weather protected. The
effect of direct solar radiation and heat trap conditions exist.
The climatogram is shown in Figure 249. on page 499.
This class applies to locations:
•
where installed equipment may be exposed to solar radiation and to heat radiation. It may also
be exposed to movements of the surrounding air due to draughts in buildings. They are not subjected to condensed water, precipitation, water from sources other than rain or icing;
•
without particular risks of biological attacks. This includes protective measures, e.g. special
product design, or installations at locations of such construction that mould growth and attacks
by animals, etc. are not probable;
•
with normal levels of contaminants experienced in urban areas with industrial activities scattered over the whole area and/or with heavy traffic;
•
without special precautions to minimize the presence of sand or dust, but which are not situated
in proximity to sources of sand or dust;
•
with insignificant vibration and shock.
The conditions of this class may be found in:
1AA 00014 0004 (9007) A4 – ALICE 04.10
•
•
•
•
•
•
ED
normal living or working areas, e.g. living rooms, rooms for general use (theatres, restaurants);
offices;
shops;
workshops for electronic assemblies and other electrotechnical products;
telecommunication centers;
storage rooms for valuable and sensitive products.
03
3AG 24163 BEAA PCZZA
531
498 / 531
absolute air humidity [ g/m 3 ]
air temperature [ o C ]
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ÄÄÄÄÄÄÄÄÄÄÄÄÄ
ÄÄÄÄÄÄÄÄÄÄÄÄÄ
ÄÄÄÄÄÄÄÄÄÄÄÄÄ
ÄÄÄÄÄÄÄÄÄÄÄÄÄ
ÄÄÄÄÄÄÄÄÄÄÄÄÄ
ÄÄÄÄÄÄÄÄÄÄÄÄÄ
25
Normal Conditions
Exceptional Conditions
ÄÄÄ
ÄÄÄ
relative air humidity [ % ]
Values outside this field have a probability of occurrence of less than 10 %.
Exceptional climatic limits.
Normal climatic limits: Values outside these limits have a probability of occurrence of less then 1 %.
Figure 249. Climatogram for Class 3.1
Table 69. Climate parameters for environmental class 3.1
1AA 00014 0004 (9007) A4 – ALICE 04.10
Environmental parameter
ED
Unit
3.1
(A)
Low air temperature
°C
+5
(B)
High air temperature
°C
+ 40
(C)
Low relative humidity
%
5
(D)
High relative humidity
%
85
(E)
Low absolute humidity
g/m3
1
(F)
High absolute humidity
g/m3
25
(G)
Rate of change of temperature
°C/min
0.5
(H)
Low air pressure
kPa
70
(I)
High air pressure
kPa
106
(J)
Solar radiation
W/m2
700
(K)
Heat radiation
W/m2
600
(L)
Movement of the surrounding air
m/s
5
(M)
Conditions of condensation
none
no
(N)
Conditions of winddriven rain, snow, hail, etc.
none
no
(Note 1)
(Note 2)
(Note 3)
03
3AG 24163 BEAA PCZZA
531
499 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Environmental parameter
Unit
3.1
(O)
Conditions of water from sources other than rain
none
no
(P)
Conditions of icing
none
no
Note 1 :
Averaged over a period of 5 minutes.
Note 2 :
Conditions in mines are not considered.
Note 3 :
A cooling system based on non–assisted convection may be disturbed by adverse
movement of the surrounding air.
18.7.4 Storage
The 1678MCC equipment meet the following requirements vs. storage:
ETS 300 019–1–1 : February 1992, class 1.2
Class 1.2 :
weatherproofed, not temperature controlled storage locations.
This class applies to weatherproofed storage having neither temperature nor humidity control.
The location may have openings directly to the open air, i.e., it may be only partly weatherproofed.
The climatogram is shown on Figure 250. on page 501.
This class applies to storage locations:
•
where equipment may be exposed to solar radiation and temporarily to heat radiation. They may
also be exposed to movements of the surrounding air due to draughts, e.g. through doors, windows or other openings. They may be subjected to condensed water, dripping water and to icing. They may also be subjected to limited wind–driven precipitation including snow;
where mould growth or attacks by animals, except termites, may occur;
with normal levels of contaminants experienced in urban areas with industrial activities scattered over the whole area, ad/or with heavy traffic;
in areas with sources of sand or dust, including urban areas;
with vibration of low significance and insignificant shock.
•
•
•
•
The conditions of this class may occur in:
1AA 00014 0004 (9007) A4 – ALICE 04.10
•
•
•
ED
unattended buildings
some entrances of buildings
some garages and shacks.
03
3AG 24163 BEAA PCZZA
531
500 / 531
absolute air humidity [ g/m 3 ]
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
air temperature [ o C ]
29
0.5
relative air humidity [ % ]
Figure 250. Climatogram for Class 1.2
Table 70. Climate parameters for environmental class 1.2
1AA 00014 0004 (9007) A4 – ALICE 04.10
Environmental parameter
ED
Unit
1.2
(A)
Low air temperature
(Note 1)
°C
– 25
(B)
High air temperature
(Note 1)
°C
+ 55
(C)
Low relative humidity
(Note 1)
%
10
(D)
High relative humidity
(Note 1)
%
100
(E)
Low absolute humidity
(Note 1)
g/m3
0.5
(Note 1)
g/m3
29
mm/min
no
(F)
High absolute humidity
(G)
Rain intensity
(H)
Rate of change of temperature
(Note 2)
°C/min
0.5
(I)
Low air pressure
(Note 3)
kPa
70
(J)
High air pressure
(Note 4)
kPa
106
(K)
Solar radiation
W/m2
1120
(L)
Heat radiation
W/m2
(Note 7)
(M)
Movement of the surrounding air
m/s
30
(N)
Conditions of condensation
none
yes
(O)
Conditions of precipitation (rain, snow, hail, etc.)
none
yes (Note 6)
(P)
Low rain temperature
°C
no
(Note 5)
03
3AG 24163 BEAA PCZZA
531
501 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Environmental parameter
Unit
1.2
(Q)
Conditions of water from sources other than rain
none
dripping water
(R)
Conditions of icing and frosting
none
yes
Note 1 :
For simultaneous occurrence of parameters (A) to (F) see Figure 250.
Note 2 :
Averaged over a period of 5 minutes.
Note 3 :
Note 4 :
70 kPa represent a limit value for open–air storage, normally at about 3 000 m.
Conditions in mines are not considered.
Note 5 :
This rain temperature should be considered together with high air temperature (B) and
solar radiation (K). The cooling effect of the rain has to be considered in connection with
the surface temperature of the equipment.
Note 6 :
Applies to wind–driven precipitation.
Note 7 :
Conditions of heat radiation, e.g. in the vicinity of room heating systems.
18.7.5 Transportation
The 1678MCC equipment meets the following requirements vs. transportation:
ETS 300 019–1–2 : February 1992, class 2.2
Class 2.2 :
Careful transportation (refer to Table 71. on page 503).
This class applies to transportation where special cars has been taken e.g. with respect to low temperature
and handling.
Class 2.2 covers the condition of class 2.1. In addition class 2.2 includes transportation in all types of lorries
and trailers in areas with well–developed road system.
It also includes transportation by ship and by train specially designed, shock–reducing buffers. Manual
loading and unloading of to 20 Kg is included.
Extension of extreme low temperature during transportation is permitted for the 1678MCC equipment in
its standard packing:
at –40° C for 72 hours maximum
1AA 00014 0004 (9007) A4 – ALICE 04.10
without damaging the optical interfaces.
ED
03
3AG 24163 BEAA PCZZA
531
502 / 531
Table 71. Climatic conditions for environmental classes 2.1/2.2
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Environmental parameter
2.1 and 2.2
°C
– 25
°C
+ 70
(A)
low temperature air
(B)
High temperature, air in
unventilated enclosures
(C)
High temperature, air in
ventilated enclosures or outdoor air (Note 2)
°C
+ 40
(D)
Change of temperature air/air
(Note 3)
°C
–25 / +30
(E)
Change of temperature air/water
(Note 3)
°C
+40 / +5
(F)
Relative humidity, not combined with rapid
temperature changes
%
°C
95
+40
Relative humidity, combined with rapid
temperature changes air/air, at high relative
humidity
(Note 3, 6)
%
95
(G)
°C
–25 / +30
Absolute humidity, combined with rapid
temperature changes: air/air at high water
content
(Note 4)
g/m3
60
°C
+70 / +15
(I)
Low air pressure
kPa
70
(J)
Change of air pressure
kPa/min
no
(K)
Movement of the surrounding medium, air
m/s
20
(L)
Precipitation rain
mm/min
6 (Note 7)
(M)
Radiation, solar
W/m2
1120
(N)
Radiation, heat
W/m2
600
(O)
Water from sources other than rain (Note 5)
m/s
1 (Note 7)
(P)
Wetness
none
conditions of wet surfaces
(H)
1AA 00014 0004 (9007) A4 – ALICE 04.10
Unit
(Note 1)
Note 1 :
The high temperature of the surfaces of a product may be influenced by both the
surrounding air temperature, given here, and the solar radiation through a window or
another opening.
Note 2 :
The high temperature of the surface of a product is influenced by the surrounding air
temperature, given here, and the solar radiation defined below.
Note 3 :
A direct transfer of the product between the two given temperature is presumed.
Note 4 :
The product is assumed to be subjected to a rapid decrease of temperature only (no
rapid increase). The figures of water content apply to temperatures down to the
dew–point; at lower temperatures the relative humidity is assumed to be approximately
100 %.
Note 5 :
The figure indicates the velocity of water and not the height of water accumulated.
Note 6 :
Occurrence of condensation.
Note 7 :
For short duration only.
18.7.6 EMI/EMC Condition
For the EMI/EMC condition refer to para. 2.1 on page 23 and para. 4.1 on page 25.
ED
03
3AG 24163 BEAA PCZZA
531
503 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1AA 00014 0004 (9007) A4 – ALICE 04.10
ED
03
504 / 531
DISMANTLING & RECYCLING
3AG 24163 BEAA PCZZA
531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ED
03
3AG 24163 BEAA PCZZA
531
505 / 531
19 DISMANTLING & RECYCLING
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
19.1 WEEE general Information
According to the European directive (2002/96/EC) Waste Electric and Electronic Equipment, from August
13, 2005 the ”producer” of the equipment being sold, unless otherwise specified in the contract with the
Customer, is responsible for collecting and treating Electrical and Electronic Equipment.
Equipment put on the market after August 13, 2005 have a label (refer to paragraph 4.4 on page 27) affixed
on the product. The presence of the black label indicates the product has been put on the market after
after August 13, 2005.
In next paragraphs is given a description example of how to disassemble an equipment; the same principle
can be applied to all the shelves and units composing the equipment.
The unit chosen for disassembly is one of the most complex.
–
1AA 00014 0004 (9007) A4 – ALICE 04.10
–
ED
Paragraph 19.2 describes the equipment disassembly; in detail:
•
paragraph 19.2.1 on page 507 lists the tools necessary for disassembly
•
paragraph 19.2.2 on page 508 describes the shelf disassembly
•
paragraph 19.2.3 on page 515 describes the unit disassembly
•
paragraph 19.2.4 on page 525 describes the procedure to apply in order to manage Hazardous
materials and components (example battery)
Paragraph 19.3 on page 527 reports the ECO declaration info.
03
3AG 24163 BEAA PCZZA
531
506 / 531
19.2 How to disassembly equipment
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
This equipment is designed for easy disassembly, by using screws and rivets for mechanical assembly
of shelves and modules. The variety of screw types is minimized.
Tools necessary for shelf and units disassembly are reported in paragraph 19.2.1 on page 507.
The disassembly process depends on the respective recycling methods and can be derived from the
delivered assembly instructions of the product.
19.2.1 Tools necessary for Disassembly
The following tools are necessary for unit disassembly:
–
–
–
–
–
–
ED
# T9 TORX screw driver
# T20 TORX screw driver
Crosshead screw driver
Wrench #
Scissors
Protection gloves
03
3AG 24163 BEAA PCZZA
531
507 / 531
19.2.2 Shelf Disassembly
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
In Figure 251. on page 508 is shown an example of shelf. The same rules can be applied to the specific
equipment to be dismantled.
In order to disassemble the shelf first remove the boards eventually present, included termination bus.
Shelf Front View
Shelf Rear View
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 251. Shelf Front and Rear View
ED
03
3AG 24163 BEAA PCZZA
531
508 / 531
Procedure:
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
–
–
Remove the two screws (A) in order to disassemble the handle as reported in Figure 252. on
page 509
Repeat the same procedure on the other handle.
Separate the two plastic blocks of the handle as reported in Figure 252. on page 509.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 252. Handle Removal and Disassembly
ED
03
3AG 24163 BEAA PCZZA
531
509 / 531
Unscrew all the screws present on rear cover as reported in Figure 253. (dashed lines) on page 510.
–
Remove the rear cover in order to access the shelf Back Panel.
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 253. Rear Cover Removal
ED
03
3AG 24163 BEAA PCZZA
531
510 / 531
Unscrew all the screws fastening the Back Panel to the mechanical structure of the shelf as indicated
in Figure 254. on page 511 (dashed line).
–
Remove the Back Panel from the shelf mechanical structure.
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 254. Back Panel Removal
ED
03
3AG 24163 BEAA PCZZA
531
511 / 531
Remove the upper and lower guides from the shelf access area by unscrewing the relevant screws
as indicated in Figure 255. on page 512.
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 255. Upper and Lower Guides Plane Removal
ED
03
3AG 24163 BEAA PCZZA
531
512 / 531
Remove the side wall by unscrewing the relevant screw as indicated in Figure 256. on page 513.
–
Remove the two contact springs from the side wall as indicated in Figure 257. on page 514 (refer to
chapter 19.2.4 on page 525 for info about hazardous parts dismantling).
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 256. Side Wall Removal
ED
03
3AG 24163 BEAA PCZZA
531
513 / 531
Remove the two guides of the “basic area” and the two optical fiber ducts by pulling them out as
indicated in Figure 257. on page 514.
–
Unscrew all the screws present on the other “side wall” in order to complete the shelf disassembly.
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 257. Optical Fiber Duct, Guides and Contact Spring Removal
ED
03
3AG 24163 BEAA PCZZA
531
514 / 531
19.2.3 Unit Disassembly
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
In the following figures is shown an example of unit. The same rules can be applied to the specific units
to be dismantled.
Procedure:
–
Remove the two screws (A) from the side coverplate as indicated in Figure 258. on page 515.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 258. Side Coverplate Removal
ED
03
3AG 24163 BEAA PCZZA
531
515 / 531
Remove the screws (B) that fix the two levers and subsequently pull out them from the front plate
as indicated in Figure 259. on page 516.
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 259. Levers Removal
ED
03
3AG 24163 BEAA PCZZA
531
516 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
Unscrew and extract the two optical connectors (C) as indicated Figure 260. on page 517.
–
Remove the screw (D) fixing the connectors support as indicated in Figure 260. on page 517.
–
Rotate the connectors support (E) and pull it sideways to be removed as indicated Figure 260. on
page 517.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 260. Optical Connectors Support Removal
ED
03
3AG 24163 BEAA PCZZA
531
517 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
Remove the two screws (F) from the side coverplate as indicated in Figure 261. on page 518.
–
Extract from the top the contact spring (G) as indicated in Figure 261. on page 518 (refer to
chapter 19.2.4 on page 525 for info about hazardous parts dismantling).
–
Extract the fibers from the cavity (H) as indicated in Figure 261. on page 518.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 261. Side Coverplate and Contact Spring Removal
ED
03
3AG 24163 BEAA PCZZA
531
518 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
Disconnect the two flat cables (M) as indicated in Figure 262. on page 519.
–
Unscrew (L) connectors with the aid of a wrench as indicated Figure 262. on page 519.
–
Remove the fibers (N) from supports pulling them out Figure 262. on page 519.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 262. Internal Connectors Removal
ED
03
3AG 24163 BEAA PCZZA
531
519 / 531
Remove the two screws (O) on the other side of the board that fixes the dissipator to the Printed
Circuit Board (PCB) as indicated in Figure 263. on page 520.
–
The dissipator can now be removed (refer to Figure 264. on page 521).
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
Figure 263. Dissipator Removal
–
Remove the screws (P) from dissipator as indicated in Figure 264. on page 521.
–
Now the two modules on the other side of the dissipator are free to be removed (refer to
Figure 266. on page 522);
Pay attention during modules removal because of white conductive paste (refer to chapter
19.2.4 on page 525 for info about hazardous parts dismantling).
1AA 00014 0004 (9007) A4 – ALICE 04.10
–
ED
Remove the plastic part (X) in Figure 265. on page 521 by unscrewing the screw present on the rear
side of the dissipator.
03
3AG 24163 BEAA PCZZA
531
520 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Figure 264. Modules Removal from Dissipator
1AA 00014 0004 (9007) A4 – ALICE 04.10
–
Remove the screws (Q) and (R) that fix the daughter board and pull it out from the mother board (refer
to Figure 265. on page 521).
Figure 265. Daughter Board Removal
ED
03
3AG 24163 BEAA PCZZA
531
521 / 531
Cutaway gold plated connector (S) from daughter board (refer to Figure 266. on page 522).
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
–
Figure 266. Gold Connector Removal
1AA 00014 0004 (9007) A4 – ALICE 04.10
–
ED
Remove all internal cables as indicated in Figure 267. on page 523. To remove cables it is enough
to pull them out from their support.
03
3AG 24163 BEAA PCZZA
531
522 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1AA 00014 0004 (9007) A4 – ALICE 04.10
Figure 267. Internal Cables Removal
–
Remove screws (T) that fix the metal support to the mother board as indicated in Figure 268. on
page 524.
–
Remove the metal support.
–
Cutaway the gold plated connector (U) from mother board.
ED
03
3AG 24163 BEAA PCZZA
531
523 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
1AA 00014 0004 (9007) A4 – ALICE 04.10
ED
03
Figure 268. Connector metal Support Removal
3AG 24163 BEAA PCZZA
531
524 / 531
19.2.4 Hazardous Materials and Components
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Table 72. on page 525 lists the presence or not of hazardous substance/components.
Note: The system cabling is designed for reduced halogen content. All the traffic cabling is fully PVC free.
Table 72. List of hazardous materials and components present in the equipment
Materials/Substances
Presence
in the
Equipment
Batteries External
(Mercury/NiCad/Lithium/Other)
NO
Batteries Internal
(Mercury/NiCad/Lithium/Other)
NO
Mercury
NO
Cadmium
NO
Capacitors with PCBs
NO
Capacitors with substance of concern +
height > 25 mm, diameter > 25 mm or
proportionately similar volume
NO
Gas discharge lamps
NO
Mercury containing Backlighting lamps
NO
Plastic containing brominated flame retardants other than in Printed Circuit Assemblies
NO
Liquid Crystal Displays with a surface
greater than 100 cm2
NO
Asbestos
NO
Refractory ceramic fibres
NO
Thermal conductive paste
YES
Radio–active substances
NO
Beryllium Oxide
NO
Other forms of Beryllium
ED
YES
Where
In all units where dissipators are present a
withe thermal conductive paste is used in
between mechanical parts.
In Figure 265. on page 521 an example is
shown.
Note: Protective plastic gloves must be
used in order to avoid contact between
hands and thermal conductive paste. Pay
attention to avoid contact of thermal conductive paste with eyes.
Refer to Figure 257. on page 514 and
Figure 261. on page 518 point G.
Note: Copper–beryllium contact spring
must be separated from other material
and must be fused in a specific regulated
environment.
03
3AG 24163 BEAA PCZZA
531
525 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Materials/Substances
Presence
in the
Equipment
Pressure volume
NO
Liquids volume
NO
Gasses volume
NO
“Hidden” mechanical springs or other
equivalent parts
NO
Ozone depleting substances, according to
those categories that are already banned
in the Montreal protocol.
NO
Chloroparaffins with chain length 10–13 C
atoms, chlorination greater than 50% contained in mechanical plastic parts heavier
than 25g,
NO
Lead contained in mechanical parts heavier than 25 g.
NO
Polychlorinated biphenyls (PCB) or polychlorinated terphenyls (PCT).
NO
Polybrominated biphenyls and their ethers
(CAS no. 32534–81–9, CAS no.
32536–52–0, CAS no. 1163–19–5, CAS
no.13554–09–6) contained in mechanical
parts heavier than 25 g, in concentrations
exceeding the natural background levels.
NO
ED
Where
03
3AG 24163 BEAA PCZZA
531
526 / 531
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
19.3 ECO Declaration
The 1678 MCC is the next generation Broadband and Wideband Cross Connect. Addressing transmission
Metro & Core networks, it combines unmatched density and high capacity together with data–aware
capabilities.
Thanks to its density, it allows for a modernization of Central Offices and concentrate in one single node
multi–ring features (evolution of 1670SM), cross–connect functionalities like restoration and GMPLS
(evolution of 1674 Lambda Gate), as well as data functionality (along the lines of OMSN ISA features).
All Central Office required transport functions are integrated in one node. This provides operators with full
network flexibility at a minimum cost.
Weight and Dimensional Characteristics
Equipment Type
No
Rack
inclusive TRU
1
OED 1662SMC
fully equipped
1
OED 1670SM
fully equipped
1
Main 1678MCC/LO
fully equipped
1
Rack (Optinex)
inclusive NGTRU
1
Dimensions
depth x width x height
[in mm]
Weight
300 D x 600 W x 2200 H
49 kg
250 D x 470 W x 390 H
27 kg
280 D x 533 W x 850 H
65 kg
294 D x 533 W x 575 H
60 kg
300 D x 600 W x 2200 H
49 kg
EXTENSION OF SYSTEM LIFETIME
The product is designed to ensure an outstanding quality of service through very high traffic transmission,
connection and protection performances and minimum service interruption.
The life utility is at least 5 years. This means that maintenance will be assured for at least 5 years.
The system architecture facilitates future extendibility and upgradeability:
–
On–site configuration changes as e.g. extension of the node traffic capacity without re–cabling of
interconnections.
–
Implementation of new features and functionalities by remote Software download.
1AA 00014 0004 (9007) A4 – ALICE 04.10
The terms and conditions of warranty, service availability and spare parts availability are individually
agreed between Alcatel–Lucent and the customer and are part of the relevant contractual commitments.
ED
03
3AG 24163 BEAA PCZZA
531
527 / 531
POWER CONSUMPTION
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The product is designed for low power consumption. Developing new components with very high
integration density and low voltage supply leads to a significant reduction of power consumption.
Depending on the number and type of I/O ports the power consumption may vary in a wide range. The
power consumption of the several boards is shown in the following table.
Table 73. Power Consumption
Configuration of PBAs
Power conMain
sumption
1678MCC
[W] (per item)
LO ext.
Shelf
1678MCC Shelf
0
x
Matrix 640 Gbit/s
130
x
Matrix 320 Gbit/s
130
x
Matrix 160 Gbit/s
130
x
LAX40
70
x
LAX20
52
x
FLCCONGI
30
x
FLCCONGI enhanced
37
x
FLCSERVICE
30
x
FLCSERVICE enhanced
37
x
Power Supply Filter
18
x
x
Termination Bus
3
x
x
16xSTM–1
72
x
16xSTM–1/4
72
x
4xSTM–16
60
x
8xSTM–16
60
x
16xSTM–16
76
x
LAC40
76
x
Opto TRX SFP I/S/L–16
1.5
x
1xL–64.2
46
x
1xV–64.2
48
x
1xU–64.2
53
x
4xSTM–64 XFP
95
x
2xSTM–64 XFP
70
x
Opto TRX I64.2 XFP
3.5
x
Opto TRX S64.2 XFP
3.5
x
Opto TRX S64.2 XFP Ext.
6.5
x
4xGE
58
x
8xGE
58
x
16xGE
70
x
2x10GE
107
x
4x10GE
157
x
Step–up Converter in NGTRU
21
Bypass module in NGTRU
1
ED
OED
1670SM
OED
1662SMC
x
03
3AG 24163 BEAA PCZZA
531
528 / 531
Power consumption
[W] (per item)
Main
1678MCC
LO ext.
Shelf
1678MCC FAN
80
x
x
LAN switch (separate shelf)
35
LA20
116
x
LX160
106
x
ALM
3
x
1670SM Shelf
0
x
CONGIHC
12
x
Matrix Hi–Cap
100
x
Termination Bus 1670
2
x
HCLINKE
24
x
2x140/STM–1 opt./elect. Adapter
0.5
x
4x140/STM–1 opt./elect. Adapter
12
x
16xSTM–1 opt./elect. Adapter
25
x
16xSTM–1 electrical Access
24
x
2xSTM–4 Access
9
x
4xSTM–4 Port
24
x
HPROT16
0.5
x
12xSTM–1 opt. Access compact
22
x
16xSTM–1 opt. Port compact
12
x
1670 FAN Unit
30
x
1662SMC Shelf
0
x
CONGI
6
x
T_Bus
2
x
Access 63x2Mbit/s
2
x
63x2Mbit/s PORT
12
x
LPROT
1
x
SYNTH16
51
x
FAN Shelf
0
x
FAN Unit
20
x
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
Configuration of PBAs
OED
1670SM
OED
1662SMC
RADIO FREQUENCY EMISSION
Regarding conformance with radio frequency emission requirements, the product complies with:
–
–
European directive 89/336/EEC (EMC–directive)
ETS 300 386 V1.3.2 (Ed05/2003)
ACOUSTICAL NOISE
1AA 00014 0004 (9007) A4 – ALICE 04.10
The acoustical noise level of the product measured according to ISO 7779 and ISO 3745 was 7.93 bels.
ED
03
3AG 24163 BEAA PCZZA
531
529 / 531
MATERIALS
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
The product does not contain:
–
–
–
–
–
–
–
–
Asbestos,
Cadmium,
Mercury,
Ozone depleting substances, according to those categories that are already banned in the Montreal
protocol,
Chloroparaffins with chain length 10–13 C atoms, chlorination greater than 50% contained in
mechanical plastic parts heavier than 25g,
Lead contained in mechanical parts heavier than 25g,
Polychlorinated biphenyls (PCB) or polychlorinated terphenyls (PCT),
Polybrominated biphenyls and their ethers (CAS no. 32534–81–9, CAS no. 32536–52–0, CAS no
1163–19–5, CAS no. 13654–09–6) contained in mechanical parts heavier than 25g,
in concentrations exceeding the natural background levels.
The system cabling is designed for reduced halogen content.
DISASSEMBLY
The product is designed for easy disassembly, by using screws and rivets for mechanical assembly of
racks and modules. The variety of types of screws is minimized. No particular tools are needed for the
disassembly of the racks and shelves/subracks. The disassembly process depends on the respective
recycling methods and can be derived from the delivered assembly instructions of the product.
BATTERIES
The product requires no backup batteries.
PACKAGING
The packaging of the product complies with the directive 94/62/EEC concerning packaging and packaging
waste. Depending on the means of transportation the racks are packed in a cardboard or wooden box,
which can easily be recycled after use. Environmentally harmful materials are not used for packaging. The
packaging materials are marked according to ISO 11 469. If required by the customer and agreed by both
parties, Alcatel–Lucent can take care of the proper disposal of all packaging materials.
TAKE BACK INFORMATION
On request of customers, Alcatel–Lucent can take care of the take back of depreciated equipment and
of the ecological safe and appropriate disposal under conditions to be agreed.
For that purpose Alcatel–Lucent co–operates with qualified companies.
DOCUMENTATION
1AA 00014 0004 (9007) A4 – ALICE 04.10
In order to reduce paper consumption for Customer Documentation, Alcatel–Lucent delivers the Generic
Customer Documentation as a CD–ROM. The CD–ROM contains interactive HW Descriptions, SW
Descriptions, Functional Descriptions, Maintenance Manuals and User Guides. This allows the operator
to put the documentation on a server accessible by all relevant people in the organization without any
additional paper copies.
Additionally more specific documentations as e.g. information about products and solutions, services and
support, training events etc. will be provided by means of Alcatel–Lucent website accessible by all
customers. This will allow distribution of up–to–date information very quickly and without wasting natural
resources.
ED
03
3AG 24163 BEAA PCZZA
531
530 / 531
1AA 00014 0004 (9007) A4 – ALICE 04.10
All rights reserved. Passing on and copying of this
document, use and communication of its contents
not permitted without written authorization.
ED
03
END OF DOCUMENT
3AG 24163 BEAA PCZZA
531
531 / 531