EE539: Analog Integrated Circuit Design
Opamp-summary
Nagendra Krishnapura
Department of Electrical Engineering
Indian Institute of Technology, Madras
Chennai, 600036, India
26 March 2008
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Differential pair opamp
Vdd
M3
M4
Iref
out
inp
M1
M2
inn
I0
M0
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Differential pair opamp
Gm
Gout
Ao
Acm
Ci
ωu
pk , zk
Svi
2
σVos
Vcm
Vout
SR
Isupply
gm1
gds1 + gds3
gm1 /(gds1 + gds3 )
gds0 /gm3
Cgs1 /2
gm1 /CL
p2 = −gm3 /(Cdb1 + Cdb3 + 2Cgs3 ); z1 = 2p2
16kT /3gm1 (1 + gm3 /gm1 )
2
2 2
σVT
1 + (gm3 /gm1 ) σVT 3
≥ VT 1 + VDSAT 1 + VDSAT 0
≤ Vdd − VDSAT 3 − VT 3 + VT 1
≥ Vcm − VT 1
≤ Vdd − VDSAT 3
±I0 /CL
I0 + Iref
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Cascode output resistance
Rout = gmc/gdscgm1 + 1/gdsc + 1/gm1
(negligible)
Rout = gmc/gdscGs + 1/Gs + 1/gdsc
Rout = gmc/gdscgds1 + 1/gdsc + 1/gds1
Vbiasc
Vbiasc
Rout = 1/gdsc(1+gmc/gm1)
Vdd
(negligible)
Mc
Gs
Vbias1
Mc
Gs=gds1
M1
Vbiasc
Mc
M1
Vbias1
Gs=gm1
differential pair: Mc degenerated
by M1’s source impedance (gm1)
Output resistance looking into one side of the differential
pair is 2/gds1 (gm 1 = gm c in the figure)
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Opamp: dc small signal analysis
Bias values in black
Incremental values in red
Impedances in blue
Total quantity = Bias + increment
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Differential pair: Quiescent condition
M3
Vdd
M3
M4
M4
I0/2
I0/2
Vcm
M1
I0/2
M2
Vdd
Vdd-VGS3 (by symmetry)
I0/2
Vcm
Vcm
Vbias0
M1
zero current
I0/2
M2
Vcm
+
−
Vdd-VGS3
Vbias0
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Differential pair: Transconductance
M3
M4
Vdd
gmvd/2
I0/2
Vcm
+vd/2
gmvd
I0/2
gmvd/2
M1
gmvd/2
I0/2
M2
Vcm
-vd/2
+
−
Vdd-VGS3
vx ~ 0
Vbias0
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Differential pair: Output conductance
M3
M4
I0/2
vTgds1/2
Vcm
I0/2
M1
vTgds1/2
I0/2
M2
Vdd
vTgds1/2 + vTgds3
vTgds1/2
Vcm
+
−
vT(gds1 + gds3)
Vdd-VGS3
+vT
Vbias0
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Telescopic cascode: Quiescent condition
M3
M4
Vdd
I0/2
Vbiasp2
M7
M8
zero current
M5
+
−
M6
Vdd-VGS3
Vbiasn2
I0/2
Vcm
M1
I0/2
M2
Vcm
Vbias0
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Telescopic cascode: Transconductance
M3
M4
Vdd
gmvd/2
Vbiasp2
M7
M8
I0/2
gmvd/2
gmvd
gmvd/2
gmvd/2
M5
M6
Vdd-VGS3
Vbiasn2
I0/2
Vcm
+vd/2
M1
+
−
gmvd/2
I0/2
M2
Vcm
-vd/2
vx ~ 0
Vbias0
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Telescopic cascode: Output conductance
M3
M4
vTgds5gds1/2gm5
Vdd
I0/2
Vbiasp2
M7
M8
M5
M6
vTgds5gds1/2gm5 + vTgds7gds3/gm7
vTgds5gds1/2gm5+
−
gds5gds1/2gm5
Vbiasn2
vTgds5gds1/2gm5
Vcm
I0/2
M1
I0/2
M2
gds1/2
vT(gds5gds1/gm5 + gds7gds3/gm7)
Vdd-VGS3
+vT
Vcm
vTgds5gds1/2gm5
Vbias0
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Folded cascode: Quiescent condition
M9
M10
I0/2+I1
Vdd
I0/2+I1
M5
Vbiasp1
M6
I1
Vbiasp2
I1
zero current
I0/2
Vcm
M1
Vbias0
I0/2
M2
Vcm
M7
M8
Vbiasn2
I1
+
−
VGS3
I1
M3
M4
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Folded cascode: Transconductance
M9
M10
I0/2+I1
M5
gmvd/2
gmvd/2
I0/2
Vcm
+vd/2
M1
M6
I1
gmvd/2
Vdd
I0/2+I1
Vbiasp1
gmvd/2
I1
Vbiasp2
gmvd
I0/2
M2
Vcm
M7
M8
gmvd/2
Vbiasn2
-vd/2
+
−
VGS3
vx ~ 0
Vbias0
gmvd/2
I1
I1
M3
gmvd/2
M4
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Folded cascode: Output conductance
M9
M10
vTgds5gds1/2gm5
vTgds5gds1/2gm5
I0/2+I1
I0/2
Vcm
M1
M5
M2
Vbiasp1
M6
I1
I0/2
Vdd
I0/2+I1
Vbiasp2
I1
gds1/2
vTgds5(gds1/2+gds9)/gm5
zero current
M7
Vcm
M8
Vbiasn2
+
−
vT(gds5(gds1+gds9)/gm5 + gds7gds3/gm7)
VGS3
+vT
Vbias0
vTgds5gds1/2gm5
I1
I1
M3
vTgds5gds1/2gm5 + vTgds7gds3/gm7
M4
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Differential pair: Noise
in0/2+in1/2-in2/2+in3
in0/2+in1/2-in2/2+in3
in3
in4
in0/2+in1/2-in2/2
in1
in2
Vcm
in0/2+in1/2-in2/2
in1-in2+in3-in4
in0/2-in1/2+in2/2
+
−
Vdd-VGS3
Vcm
in0
in0/2-in1/2+in2/2
in0
Carry out small signal linear analysis with one noise
source at a time
Add up the results at the output (current in this case)
Add up corresponding spectral densities
Divide by gain squared to get input referred noise
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Telescopic cascode opamp
M3
M4
Vdd
Vbiasp2
M7
M8
out
M5
M6
M1
M2
Vbiasn2
inp
inn
Vbias0
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Telescopic cascode opamp
Gm
Gout
Ao
Acm
Ci
ωu
pk , zk
p2,4
Svi
2
σVos
Vout
SR
Isupply
gm1
gds1 gds5 /gm5 + gds3 gds7 /gm7
gm1 /(gds1 gds5 /gm5 + gds3 gds7 /gm7 )
gds0 /gm3
Cgs1 /2
gm1 /CL
p2 = −gm3 /(Cdb1 + Cdb3 + 2Cgs3 )
p3 = −gm5 /Cp5
p4 = −gm7 /Cp7
appear for one half and cause mirrror zeros
16kT /3gm1 (1 + gm3 /gm1 )
2
2 2
σVT
1 + (gm3 /gm1 ) σVT 3
≥ Vbiasn1 − VT 5
≤ Vbiasp1 + VT 7
±I0 /CL
I0 + Iref
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Folded cascode opamp
M9
M10
Vdd
Vbiasp1
M5
M6
Vbiasp2
out
inp
inn
M1
M2
M7
M8
Vbiasn2
Vbias0
M3
Nagendra Krishnapura
M4
EE539: Analog Integrated Circuit Design
Folded cascode opamp
Gm
Gout
Ao
Acm
Ci
ωu
pk , zk
Svi
2
σVos
Vout
SR
Isupply
gm1
(gds1 + gds9 )gds5 /gm5 + gds3 gds7 /gm7
gm1 /((gds1 + gds9 )gds5 /gm5 + gds3 gds7 /gm7 )
gds0 /gm3
Cgs1 /2
gm1 /CL
p2 = −gm3 /(Cdb1 + Cdb3 + 2Cgs3 )
p3 = −gm5 /Cp5
p4 = −gm7 /Cp7
p2,4 appear for one half and cause mirrror zeros
16kT /3gm1 (1 + gm3 /gm1 + gm9 /gm1 )
2
2 2
2 2
σVT
1 + (gm3 /gm1 ) σVT 3 + (gm9 /gm1 ) σVT 9
≥ Vbiasn1 − VT 5
≤ Vbiasp1 + VT 7
± min{I0 , I1 }/CL
I0 + I1 + Iref
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Body effect
All nMOS bulk terminals to ground
All pMOS bulk terminals to Vdd
Acm has an additional factor gm1 /(gm1 + gmb1 )
gm5 + gmb5 instead of gm5 in cascode opamp results
gm7 + gmb7 instead of gm7 in cascode opamp results
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Two stage opamp
bias
stage 1
stage 2
Vdd
M3
M4
Iref
M11
RL
Rc
inn
M1
M2
Voutbias
inp
Cc
CL
I0
M0
Nagendra Krishnapura
M12
EE539: Analog Integrated Circuit Design
Two stage opamp
Vdd
gm1
inp
−
inn
+
M11
single stage
opamp
out
Rc
Cc
I1
First stage can be Differential pair, Telescopic cascode, or
Folded cascode; Ideal gm1 assumed in the analysis
Second stage: Common source amplifier
Frequency response is the product of frequency responses
of the first stage gm and a common source amplifier driven
from a current source
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Common source amplifier: Frequency response
Vo (s)
Vd (s)
=
a3 =
a2 =
a1 =
gm 1 gm 11 sCc (Rc − 1/gm 11 ) + 1
G1 GL
a3 s 3 + a 2 s 2 + a 1 s + 1
Rc C1 CL Cc
G1 GL
C1 Cc + Cc CL + CL C1 + Rc Cc (G1 CL + C1 GL )
G1 GL
Cc (gm 11 + G1 + GL + G1 GL Rc ) + C1 GL + G1 CL
G1 GL
G1 : Total conductive load at the input
GL : Total conductive load at the output
C1 : Total capacitive load at the input
CL : Total capacitive load at the output
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Common source amplifier: Poles and zeros
p1 ≈ −
p2 ≈
p3
z1
G1
gm 11
1
+ G1 Rc ) + C1 (1 + G
GL + 1 +
GL )
+CL
c
c
gm 11 C1C+C
+ GL + G1 CC1c+C
+ G1GL Rc C1C+C
c
c
C
−
Rc Cc (G1 CL +GL C1 )
C1 Cc
+
C
+
L
C1 +Cc
Cc +CL
Cc (
G1
GL
1
1
1
+
+
≈ −
CL Cc
C1
1
=
(1/gm 11 − Rc )Cc
1
Rc
G1 GL
+
+
C1
CL
Unity gain frequency
ωu ≈
Cc 1 +
GL
gm 11
+
G1
gm 11
Nagendra Krishnapura
+
gm 1
G1 GL Rc
gm 11
+ C1 gGmL + gGm1
11
11
EE539: Analog Integrated Circuit Design
Common source amplifier: Frequency response
Pole splitting using compensation capacitor Cc
p1 moves to a lower frequency
p2 moves to a higher frequency (For large Cc ,
p2 = gm 11 /CL )
Zero cancelling resistor Rc moves z1 towards the left half s
plane and results in a third pole p3
z1 can be moved to ∞ with Rc = 1/gm 11
z1 can be moved to cancel p2 with Rc > 1/gm 11 (needs to
be verified against process variations)
Third pole p3 at a high frequency
Poles and zeros from the first stage will appear in the
frequency response—Ym1 (s) instead of gm 1 in Vo /Vi
above
Mirror pole and zero
Poles due to cascode amplifiers
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Two stage opamp
Ao
Acm
Ci
ωu
pk , zk
Svi
2
σVos
Vcm
Vout
SR+
SRIsupply
gm1 gm11 /(gds1 + gds3 )(gds11 + gds12 )
gds0 gm11 /gm3 (gds11 + gds12 )
Cgs1 /2
gm1 /Cc
See previous pages
≈ 16kT /3gm1 (1 + gm3 /gm1 )
2
2 2
≈ σVT
1 + (gm3 /gm1 ) σVT 3
≥ VT 1 + VDSAT 1 + VDSAT 0
≤ Vdd − VDSAT 3 − VT 3 + VT 1
≥ VDSAT 12
≤ Vdd − VDSAT 11
I0 /Cc
min{I0 /Cc , I1 /(CL + Cc )}
I0 + I1 + Iref
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Fully differential circuits: Noise
in3
M3
M4
CMFB
-
Vcm
M1
in3
in4
vn,half
+
vn,full
in1
M3
in2
M2
Vcm
M1
in1
half circuit(small signal)
M0
Sn,full = 2Sn,half
Calculate noise spectral density of the half circuit
Multiply by 2×
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Fully differential circuits: Offset
voff,full
M1
M4
M3
∆VT3
voff,half
+
∆VT2
M2
Vcm
∆VT1
+
−
-
∆VT1
+
−
∆VT4
+
−
∆VT3
+
−
Vcm
+
−
M3
+
−
Vdd
M1
half circuit(small signal)
M0
v2off,full = 2v2off,half
Calculate mean squared offset of the half circuit
Multiply by 2× if mismatch (e.g. ∆VT ) wrt ideal device is
used
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Fully differential circuits: Offset
Vdd
M3
+
−
M4
+
−
M3
∆VT34
voff,full
M1
+
M2
Vcm
∆VT12
+
−
+
−
Vcm
-
∆VT12
∆VT34
voff,half
M1
half circuit(small signal)
M0
v2off,full = v2off,half
Calculate mean squared offset of the half circuit
Multiply by 1× if mismatch between two real devices is
used
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Opamp comparison
Gain
Noise
Offset
Swing
Speed
Differential
pair
−
=
=
−
++
Telescopic
cascode
++
=
=
−
+
Nagendra Krishnapura
Folded
cascode
+
high
high
+
−
Two
stage
++
=
=
++
+
EE539: Analog Integrated Circuit Design
Differential pair
Vdd
M3
M4
Iref
out
inp
M1
M2
inn
I0
M0
Low accuracy (low gain) applications
Voltage follower (capacitive load)
Voltage follower with source follower (resistive load)
In bias stabilization loops (effectively two stages in
feedback)
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Telescopic cascode
M3
M4
Vdd
Vbiasp2
M7
M8
out
M5
M6
M1
M2
Vbiasn2
inp
inn
Vbias0
Low swing circuits
Switched capacitor circuits
Capacitive load
Different input and output common mode voltages
First stage of a two stage opamp
Only way to get high gain in fine line processes
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Folded cascode
M9
M10
Vdd
Vbiasp1
M5
M6
Vbiasp2
out
inp
inn
M1
M2
M7
M8
Vbiasn2
Vbias0
M3
M4
Higher swing circuits
Higher noise and offset
Lower speed than telescopic cascode
Low frequency pole at the drain of the input pair
Switched capacitor circuits (Capacitive load)
First stage of a two stage class AB opamp
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Two stage opamp
bias
stage 1
stage 2
Vdd
M3
M4
Iref
M11
RL
Rc
inn
M1
M2
Voutbias
inp
Cc
CL
I0
M0
M12
Highest possible swing
Resistive loads
Capacitive loads at high speed
“Standard” opamp: Miller compensated two stage opamp
Class AB opamp: Always two (or more) stages
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design
Opamps: pMOS versus nMOS input stage
nMOS input stage
Higher gm for the same current
Suitable for large bandwidths
Higher flicker noise (usually)
pMOS input stage
Lower gm for the same current
Lower flicker noise (usually)
Suitable for low noise low frequency applications
Nagendra Krishnapura
EE539: Analog Integrated Circuit Design