RNS INSTITUTE OF TECHNOLOGY, BENGALURU - 98
DEPARTMENT OF INFORMATION SCIENCE AND ENGINEERING
21CS43: Microcontroller and Embedded System
IV SEMESTER ‘A’, ‘B’,’C’ SECTION
ASSIGNMENT – 1
Submission Date: 15/07/2023
Common Questions
BATCH
Q No.
1
CO's
CO1
L1
CO1
With neat diagram explain ARM core.
L1
CO1
4
What is pipeline? Explain ARM7 three stage pipeline.
L1
CO1
5
What are Exceptions, Interrupts, and the Vector Table
L1
CO1
6
7
Explain the operation of SMLAL, BLX instruction
L1
CO2
What is the output of the following instruction?
SUB r0, r1, r1, ASR #1, when
r0 = 0x00000000
r1 = 0x00000005
Explain the operation of STMIA instruction
L4
CO2
L1
CO2
What is the output of the following instruction?
SWP r0, r1, [r2], when
mem32[0x8000] = 0x56782345
r0 = 0x00000000
r1 = 0x55556789
r2 = 0x00008000
What is the output of the following instruction?
UMULL r0, r1, r2, r3, when
r0 = 0x00000000
r1 = 0x00000000
r2 = 0xf0000002
r3 = 0x00000002
Group Wise Assignment
Give the comparison between microprocessor and
microcontroller.
With a neat diagram explain the functional block diagram of a
microcontroller.
L4
CO2
L4
CO2
L2
CO1
L1
CO1
Explain briefly the data processing instructions for ARM processor.
L1
L1
CO2
CO2
L1
CO1
L2
CO1
3
Questions
8
9
10
1
2
B1
Levels
L1
Explain embedded system software.
2
Common
Question
Explain embedded system hardware with diagram briefly.
3
4
5
Explain briefly program status register instructions with syntax and
example
Discuss the core extensions for ARM processor.
1
List the features of RISC processors.
VS, SN &Dr. NSB Dept. of ISE,
RNSIT
L1: Knowledge L2: Understand
Page 1
2022-2023
L3: Apply
L4: Analyze
L5: Evaluate
L6: Create
RNS INSTITUTE OF TECHNOLOGY, BENGALURU - 98
DEPARTMENT OF INFORMATION SCIENCE AND ENGINEERING
21CS43: Microcontroller and Embedded System
IV SEMESTER ‘A’, ‘B’,’C’ SECTION
ASSIGNMENT – 1
Submission Date: 15/07/2023
2
B2
L2
List the features that are adopted and rejected by ARM from the
RISC design philosophy.
With a neat diagram explain the functional block diagram of a L1
microprocessor.
Explain barrel shift operations in ARM processor.
L1
3
4
B3
B4
5
1
2
3
4
5
1
Write ARM ALP for data transfer, arithmetic and logical operation
Explain briefly the loading constants.
CO1
L1
L2
L3
L2
L3
L2
L1
CO2
CO1
CO1
CO1
CO2
CO2
CO1
L1
L1
CO1
CO2
2
3
4
Explain the ARM swap instruction with an example code.
L1
CO2
5
Explain the ARM Single-Register and Multiple-Register load-store
addressingmodes with example.
Explain the ARM programmer’s model with complete register sets
available with a neat diagram.
Explain the different processor modes of the ARM processor.
L1
CO2
L1
CO1
L1
CO1
3
4
Explain Load and Store instructions
Explain briefly the active registers available in user mode.
L1
L1
CO2
CO1
5
With a neat diagram explain Barrel Shifter.
L1
CO1
1
2
List the different states of the ARM and explain.
L2
What is pipelining? Explain the concept of pipeline used in ARM7 L1
processor.
Explain briefly the software interrupt instruction with syntax and
L1
example
If R5=5, R7=8 and using the following instruction, write values of
L4
R5, R7 after execution MOV R7,R5, LSL#2
L5
Explain the following instructions of ARM processor
with suitable example: 1) MVN 2) RSB 3) ORR 4)
MLA 5) SMULL 6) LDR 7) SWP 8) SWPB
CO1
CO1
2
B6
Differentiate between SRAM and DRAM.
Justify the need for memory hierarchy design.
Differentiate between RISC and CISC
CO1
With a neat diagram explain the software abstraction levels used in
embedded systems.
Explain the ARM core dataflow model with a neat diagram
Explain Branch instructions.
1
B5
Explain briefly coprocessor instructions with syntax and example.
CO1
3
4
5
Staff-In-Charges
VS, SN &Dr. NSB Dept. of ISE,
RNSIT
L1: Knowledge L2: Understand
Chief Course Coordinator
CO2
CO2
HoD,ISE
Page 2
2022-2023
L3: Apply
CO2
L4: Analyze
L5: Evaluate
L6: Create