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ENGR 2214 Digital Design Oklahoma City Community College Lab 1 Lab 1 -- Basic Logic Gate Functions Name:______________________________ Date:________________________________ Verification of AND Gate Function: 1. Using the SN74HC08 datasheet, complete the schematic in Figure 1 by filling in the pin numbers for š¯‘‰ , GND, and one of the AND gates. 2. Assemble the circuit shown in Figure 1 on the Digital Trainer and complete the truth table shown in Table 1. 3. Have the instructor verify your work and initial your results. Figure 1. AND Gate Schematic Diagram A B 0 0 0 1 1 0 1 1 Y Table 1. AND Gate Truth Table ENGR 2214 Digital Design Oklahoma City Community College Lab 1 Verification of OR Gate Function: 1. Using the SN74HC32 datasheet, complete the schematic in Figure 2 by filling in the pin numbers for š¯‘‰ , GND, and one of the OR gates. 2. Assemble the circuit shown in Figure 2 on the Digital Trainer and complete the truth table shown in Table 2. 3. Have the instructor verify your work and initial your results. Figure 2. OR Gate Schematic Diagram A B 0 0 0 1 1 0 1 1 Y Table 2. OR Gate Truth Table ENGR 2214 Digital Design Oklahoma City Community College Lab 1 Verification of XOR Gate Function: 1. Using the SN74HC86 datasheet, complete the schematic in Figure 3 by filling in the pin numbers for š¯‘‰ , GND, and one of the XOR gates. 2. Assemble the circuit shown in Figure 3 on the Digital Trainer and complete the truth table shown in Table 3. 3. Have the instructor verify your work and initial your results. Figure 3. XOR Gate Schematic Diagram A B 0 0 0 1 1 0 1 1 Y Table 3. XOR Gate Truth Table ENGR 2214 Digital Design Oklahoma City Community College Lab 1 Verification of NOT Gate Function: 1. Using the SN74HC04 datasheet, complete the schematic in Figure 4 by filling in the pin numbers for š¯‘‰ , GND, and one of the NOT gates. 2. Assemble the circuit shown in Figure 4 on the Digital Trainer and complete the truth table shown in Table 4. 3. Have the instructor verify your work and initial your results. Figure 4. NOT Gate Schematic Diagram A Y 0 1 Table 4. NOT Gate Truth Table