EE719 (ZELE)
Mixed-Signal VLSI Design
Course Project [Points : 50]
• The project is based on Cadence simulations.
• Use nmos1v lvt and pmos1v lvt transistors from the GPDK 45nm technology library and resistors, capacitors from
analoglib library.
• The final submission must be named as Rollnumber Yourname Project PartX.pdf.
• Submissions after deadline will not be accepted under any circumstances.
• The submission must contain appropriate plots labelled clearly.
• MOSFETs in schematics must be annotated with all required parameters. Eg. Width, Length, Fingers, Multipliers.
• Include the testbench schematics for all the simulations.
• Cadence simulation related tutorials will be provided.
• Report all values with appropriate units in tabular format wherever it is necessary.
• If we find evidence of copying in any question, all involved students would be awarded ZERO marks for the project.
• A Viva Voce Examination will be conducted after the submission of the project report.
PROBLEM STATEMENT
Design a Flash ADC. This involves designing a sample-and-hold circuit and then a comparator. The specifications for
the sample-and-hold circuit are listed in Table 1.
Parameter
Number of bits (N)
Supply Voltage (VDD )
Input Voltage Swing (VFS )
Temperature (T)
ENOB (Nyquist Bandwidth)
THD (Nyquist Bandwidth)
Sampling Frequency (Fs )
Clock Rise, Fall times (Tr , Tf )
Value
10
1.2 V
0.6 - 1.0 V
27C
>8 bits
>55 dB
1 GHz
10 ps
Table 1: Bootstrap Switch Specifications
Load capcitance to be used in testbench:
CL = 250 fF
The following design modules will be provided:
1. Testbenches
(a) bootstrap switch tb
References
1. The Bootstrapped Switch : B. Razavi, “The Bootstrapped Switch [A Circuit for All Seasons]”, 2015
2. The Design of a Bootstrapped Sampling Circuit : B. Razavi, “The Design of a Bootstrapped Sampling Circuit [The
Analog Mind]”, 2021
1
PART 1 [20 Marks]
Boot-strapped Sample-and-Hold Circuit
Submission Deadline : 01 March 2023 11:55PM
References 1 and 2 should help guide you in the design for this part. Note that for your convenience you can create
separate schematic files for each of the sub-parts. Each sub-part in your report must contain:1. Annotated schematics
2. Annotated graphs (Transient Waveform & 1024 point FFT Plot)
3. Table of results (Include Screenshot of Spectrum Tool Output)
4. Observations and Comments
1 (a). Simulate the schematic given in figure 1 in Cadence. Provide hand-calculations and reason out your choices
for parameters chosen. Give a sine input (near Fs /5) using vsin from analoglib to your design and verify the output.
[2]
X
Vin
+
VB
-
Vout
M1
C1
Figure 1: Basic Boot-strap
Tabulate the parameters:
Parameter
Width
Length
M1
C1
<value >
Table 2: Parameter values
1 (b). With the ideal-case as our base design, let’s progress onto building an implementable design. In a new
schematic file, simulate figure 2b. Reason out your choices for parameters chosen. Give a sine input (near Fs /5) to your
design and verify the output.
[3]
P
+
VB
-
φ
S2
Vin
φ
X
P
S4
+
VB
Vout
M1
Vin
C1
M2
X
φ
M4
φ
Vout
M1
C1
(a) With Ideal switch
(b) Replacing Switches with MOSFETs
Figure 2: Introducing Sampling
Tabulate the parameters:
Parameter
Width
Length
M2
M4
Table 3: Parameter values
2
1 (c). Our next step is to ensure that we can disable bootstrapping. In a new schematic file, simulate figure 3b.
Reason out your choices for parameters chosen. Give a sine input (near Fs /5) to your design and verify the output. [3]
φ
P
X
S2
+
VB
-
P
φ
S4
S6
Vin
φ
M6
S3
Vout
M1
φ
X
M4
+
VB
-
φ
φ
φ
M2
M3
Vin
Vout
M1
C1
C1
(a) With Ideal switch
(b) Replacing Switches with MOSFETs
Figure 3: Disabling Bootstrapping
Parameter
Width
Length
M6
M3
Table 4: Parameter values
1 (d). Let’s complete the design! Let’s introduce the boot-strap capacitor and put in a mechanism to charge it after
each cycle. In a new schematic file, simulate figure 4b. Reason out your choices for parameters chosen. Give a sine input
(near Fs /5) to your design and verify that the output. Plot the region of operation for each of the transistors. Does this
match your expectations? Reason out.
[5]
VDD
φ
P
S5 +
VDD
φ
S6
Vin
VDD
φ
φ
X
S2
φ
M2
P
X
S4
M5 +
VDD
-
CB
CB
M4
φ
φ
φ
M6
S3
Vout
M1
Vin
M3
Vout
M1
C1
C1
(a) With Ideal switch
(b) Replacing switches with MOSFETs
Figure 4: Introducing the Bootstrap Capacitor
Parameter
Width
Length
M5
CB
<value >
Table 5: Parameter values
1 (e). For each of the parts from 1 (b) - 1 (d), give an input sine wave of frequencies near Fs /5 and Fs /2. Use the
spectrum tool to analyse the output frequency spectrum and determine the ENOB and THD in each case. (Note: Ensure
that the values of m, N are such that there is coherent sampling. Please include these values used in your report as well.)
Provide annotated screenshots with the input signal peak marked. Tabulate the ENOB and THD in each case and provide
a reason for the trend observed.
[7]
Sub-part
1 (b)
1 (c)
1 (d)
ENOB - Fs /5
THD - Fs /5
ENOB - Fs /2
Table 6: Parameter values
3
THD - Fs /2
1 (f ). Provide a table for the final parameters:
Parameter
Width
Length
M1
M2
M3
M4
M5
M6
Table 7: Final Parameters
4
C1
<value >
CB
<value >