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Accelerating Genetic Algorithm Based Security constrained Economic Load Dispatch

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By: Solomon M.
AAIT, Addis Abeba
Photo: Power System Control Center (EMS)
Course Project
1. Motivations
2. Objectives
3. Methods
4. Results Obtained Baseline System
5. Parallelism and Results Obtained
6. Conclusions
2021
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
Security constrained economic generation dispatch
(SCED) represents one of the most important
problems in power systems engineering.
▪ It is a technique commonly used by operators in every
day system operation.

SCED reduces system cost by allocating the real
power among the online generating units.
▪ While taking other system constraints into
consideration.
▪ Economic generation is vital for power generators.
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
One of the main impediments in wide application of
economic dispatch is the slowness of algorithm
execution time .
▪ Particularly in large power systems.

The available software tools are traditionally
designed for serial codes and optimized using
single-processor computers.
▪ Inadequate in terms of execution time (for large and
complex power grid).

2021
Genetic Algorithms is appealing due to its efficiency
and parallel-ability.
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
Development of an efficient Genetic Algorithm
based security constrained economic dispatch using
multiple processor parallel computations.
▪ Make solution converged in shorter time,
by Reducing execution time (for large and complex power
grid).
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As a good starting point for designing an efficient
parallel program is developing a good serial
program.
▪ Development of GA based baseline security constraint
economic dispatch (SCED) code.
▪ in visual studio, C++.

Code profiling on baseline implementation
▪ Using Intel’s VTune Profiler.
▪ To identify performance bottlenecks
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

Implementation of efficient parallel GA based SCED.
Analysis of output equivalency.
▪ By comparing serial and parallel programs performance
analysis outputs.
Standard Institute of Electrical and Electronic
Engineers (IEEE) 118 bus system is used as a case
study ( 54 generators –> Individuals)
 Baseline GA based SCED is implemented for:

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
There are a lot of loops in Genetic Algorithm
implementation.
▪ But not all are parallelable or may result in an increased
execution time instead of reducing it.

After detailed investigation two candidate loops are
identified.
▪ Loop that creates chromosomes.
▪ Loop that evaluates fitness of individuals.
▪ ( as indicated by the hotspot analysis it is slowing down the program)

OpenMP “Open Multi-Processing” is used to
implement the parallelism.
▪ It is a multi-vendor standard to perform shared-memory
multiprocessing. (OpenMP Consortium)
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Advise, KU Leuven
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Advise, KU Leuven
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




The availability of parallel processing hardware and software
presents an opportunity to apply this new computation
technology to solve power system problems.
Parallel processing will aid to increase cost and speed efficiency.
In this work, the comparison between the parallel solution
execution time and baseline system execution time is presented
for a GA based SCED problem for Institute of Electrical and
Electronic Engineers (IEEE) IEEE 118 bus system.
Parallel implementation of GA based SCED has advantage of
efficiently using processing resources and reducing execution
time, from 125.26s to 74.9s for this case study.
It is still possible to further improve execution time of the
presented case study.
▪ Ex: The use of Profiler Guided Optimization technique (PGO).
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1.
Genetic Algorithm Optimization in C/C++.
https://link.springer.com/content/pdf/10.1007%2F978-3-540-73190-0_9.pdf
2.
3.
Analyze Common Performance Bottlenecks with Intel® VTune Profiler
https://software.intel.com/content/dam/develop/external/us/en/documents/v
tune-tutorial-common-bottlenecks-windows.pdf
A Genetic Algorithm Function Optimizer in C++.
https://www.technical-recipes.com/2012/a-genetic-algorithm-function-optimizer-in-c/
4.
An Introduction to Genetic Algorithms
https://www.whitman.edu/Documents/Academics/Mathematics/2014/carrjk.pdf
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Thank you
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