Digital Systems Design : BECE102L
Lab-1
Mode Sim Demo
Dr. Vikas Vijayvargiya
Associate Professor
Department of Micro and Nano-Electronics
School of Electronics Engineering
Dr Vikas Vijayvargiya
Model Sim Demo
Model Sim Demo :
Example Using AND Gate using Gate Level Modeling
Dr Vikas Vijayvargiya
Gate Level Modeling
Dr Vikas Vijayvargiya
Introduction to Verilog
Dr Vikas Vijayvargiya
Gate Level Modeling
Logic Circuit of the AND gate
Dr Vikas Vijayvargiya
Gate Level Modeling
Logic Circuit of the AND gate
Gate-level modeling
module AND_2(output Y, input A, B);
and(Y, A, B);
endmodule
Dr Vikas Vijayvargiya
Gate Level Modeling
Gate-level modeling
Logic Circuit of the AND gate
module AND_2(output Y, input A, B);
and(Y, A, B);
endmodule
OR
module AND_2( Y, A, B);
Input A,B;
output Y;
and(Y, A, B);
endmodule
Dr Vikas Vijayvargiya
Gate Level Modeling
Dr Vikas Vijayvargiya
Gate Level Modeling
Dr Vikas Vijayvargiya
Gate Level Modeling
Dr Vikas Vijayvargiya
Gate Level Modeling
Create Folder on Desktop: Test
Inside Folder: Simulation folder
Dr Vikas Vijayvargiya
Gate Level Modeling
Browse and locate “Test” Folder
Dr Vikas Vijayvargiya
Gate Level Modeling
Browse and locate “Simulation” Folder
Browse and locate “Test” Folder
Dr Vikas Vijayvargiya
Gate Level Modeling
Dr Vikas Vijayvargiya
Gate Level Modeling
Dr Vikas Vijayvargiya
Gate Level Modeling
Write file name
Dr Vikas Vijayvargiya
Gate Level Modeling
file name: And_gate_Modeling
Dr Vikas Vijayvargiya
Gate Level Modeling
Dr Vikas Vijayvargiya
Gate Level Modeling
Dr Vikas Vijayvargiya
Gate Level Modeling
Save it
Dr Vikas Vijayvargiya
Gate Level Modeling
Compile Selected
Dr Vikas Vijayvargiya
Gate Level Modeling
Dr Vikas Vijayvargiya
Gate Level Modeling
Start Simulation
Dr Vikas Vijayvargiya
Gate Level Modeling
Start Simulation
Dr Vikas Vijayvargiya
Gate Level Modeling
Dr Vikas Vijayvargiya
Gate Level Modeling
Dr Vikas Vijayvargiya
Gate Level Modeling
Dr Vikas Vijayvargiya
Gate Level Modeling
Dr Vikas Vijayvargiya
Gate Level Modeling
Dr Vikas Vijayvargiya
Gate Level Modeling
Dr Vikas Vijayvargiya
Gate Level Modeling
Dr Vikas Vijayvargiya
Gate Level Modeling
Dr Vikas Vijayvargiya
Gate Level Modeling
Dr Vikas Vijayvargiya
Gate Level Modeling
Dr Vikas Vijayvargiya
Gate Level Modeling
Dr Vikas Vijayvargiya
Gate Level Modeling
Verify output and Input
With respect to
Curser Position
Dr Vikas Vijayvargiya
Gate level Modeling
Problem statement : 1
Write Verilog code in one file for all gates using gate level modeling
and then after verify its operation.
Dr Vikas Vijayvargiya