EE194-EE290C 28 nm SoC for IoT CMOS VLSI Design by Neil H. Weste and David Money Harris Synopsys’ IC Compiler™ ImplementaJon User Guide Synopsys’ Timing Constraints and OpJmizaJon User Guide Tips • This is by no means comprehensive. • Key is to get to the “good enough” ASAP. • Must develop intuiJve understanding what the tool is trying to accomplish. DC Converts a design descripJon wriWen in a HDL, into an opJmized gate-level netlist mapped to a specific logic library. When the synthesized design meets funcJonality, Jming, power, and other design goals, you can pass the design to IC Compiler for physical implementaJon. Liberty Timing File(LIB) The .lib file is an ASCII representaJon of the Jming and power parameters associated with any cell in a parJcular semiconductor technology. The Jming and power parameters are obtained by simulaJng the cells under a variety of condiJons and the data is represented in the .lib format. The .lib file contains Jming models and data to calculate: • I/O delay paths • Timing check values • Interconnect delays I/O path delays and Jming check values are computed on a per-instance basis. Path delays in a circuit depend upon the electrical behavior of interconnects between cells. This parasiJc informaJon can be based on the layout of the design, but must be esJmated when no layout informaJon is available. Also it is not possible to predict the process, voltage and temperature variaJons and deraJng factors can be included to compensate for these variaJons. Liberty Timing File(LIB) Cell-based delay calculaJon is modeled by characterizing cell delay and output transiJon Jme (output slew) as a funcJon of input transiJon Jme (input slew) and the capaciJve load on the output of the cell. Each cell has a specific number of input-to-output paths A B Z C • Path delays can be described for each input signal transiJon that affects an output signal • The path delay can also depend on signals at other inputs (state dependencies) Liberty Timing File(LIB) Delay,Power, Timing Checks Input Slew Output Capacitance Lookup-table (non-linear delay) model. Liberty Timing File(LIB) Delay,Power, Timing Checks Input Slew Output Capacitance Lookup-table (non-linear delay) model. FF pMOS SF TT FS SS slow q Transistors have uncertainty in parameters Process: Leff, Vt, tox of nMOS and pMOS Vary around typical (T) values q Fast (F) Leff: short Vt: low tox: thin q Slow (S): opposite q Not all parameters are independent for nMOS and pMOS fast Parameter VariaJon slow nMOS fast Environmental VariaJon q VDD and T also vary in time and space q Fast: VDD: high T: low Corner Voltage Temperature F 1.98 0C T 1.8 70 C S 1.62 125 C Process Corners q Process corners describe worst case variations - If a design works in all corners, it will probably work for any variation. q Describe corner with four letters (T, F, S) - nMOS speed - pMOS speed - Voltage - Temperature Important Corners q Some critical simulation corners include Purpose nMOS pMOS VDD Temp Cycle time S S S S Power F F F F Subthreshold leakage F F F S Design Objects Top Level ParJJoning Design Environment Before a design can be opJmized, you must define the environment in which the design is expected to operate. You define the environment by specifying operaJng condiJons, system interface characterisJcs, and wire load models. OperaJng condiJons include temperature, voltage, and process variaJons. System interface characterisJcs include input drivers, input and output loads, and fanout loads. The environment model directly affects design synthesis results. Drive CharacterisJcs To determine the delay and transiJon Jme characterisJcs of incoming signals, Design Compiler needs informaJon about the external drive strength and the loading at each input port. Drive strength is the reciprocal of the output drive resistance, and the transiJon delay at an input port is the product of the drive resistance and the capacitance load of the input port. Design Compiler uses drive strength informaJon to buffer nets appropriately in the case of a weak driver. By default, Design Compiler assumes zero drive resistance on input ports, meaning infinite drive strength. Drive CharacterisJcs By default, Design Compiler assumes zero capaciJve load on input and output ports. Wire Load Models Wire load models esJmate the effect of wire length and fanout on the resistance, capacitance, and area of nets. Design Compiler uses these physical values to calculate wire delays and circuit speeds. Semiconductor vendors develop wire load models, based on staJsJcal informaJon specific to the vendors’ process. The models include coefficients for area, capacitance, and resistance per unit length, and a fanout-to-length table for esJmaJng net lengths (the number of fanouts determines a nominal length). Design Rule Constraints Design Rule Constraints MIPS Layout ICC The IC Compiler tool is a single, convergent netlist-to-GDSII design tool for chip designers developing very deep submicron designs. It takes as input a gate-level netlist, a detailed floorplan, Jming constraints, physical and Jming libraries, and foundry-process data, and it generates as output a GDSIIformat file of the layout. ICC Design Flow • Create floorplan and a power plan. • Legalized placement of leaf cells and resolves Jming closure. • Improves clock skew and clock inserJon delay. • Performs global rouJng. • Filler cells, Antenna diodes, density fills etc. Centered around three core commands. Design PreparaJon The IC Compiler tool uses a Milkyway design library to store your design and its associated library informaJon. The IC Compiler tool requires both logic libraries and physical libraries. Logic Libraries The IC Compiler tool uses logic libraries to provide Jming and funcJonality informaJon for all standard cells. In addiJon, logic libraries can provide Jming informaJon for hard macros, such as RAMs. The tool supports logic libraries that use nonlinear delay models (NLDMs) and Composite Current Source (CCS) models and automaJcally selects the Jming models to use, based on the contents of the logic libraries. NLDMs do not contain enough informaJon to characterize the delay of a gate driving a complex RC interconnect network with the accuracy desired by some users. They also lack the accuracy to fully characterize noise events. Physical Libraries The IC Compiler tool uses Milkyway reference libraries and technology files to obtain physical library informaJon. The Milkyway reference libraries contain physical informaJon about the standard cells and macro cells in your logic library. The Milkyway database can contain different representaJons of the same cell, called “views” of that cell. These are the main types of views used in the IC Compiler tool: •CEL view: The full layout view of a physical structure such as a via, standard cell, macro, or whole chip; contains placement, rouJng, pin, and netlist informaJon for the cell. •FRAM view: An abstract representaJon of a cell used for placement and rouJng; contains only the metal blockages, allowed via areas, and pins of the cell. •FILL view: A view of metal fill, which is used for chip finishing and has no logic funcJon, created by the signoff_metal_fill command in the IC Compiler tool. •CONN view: A representaJon of the power and ground networks of a cell, created by the PrimeRail or IC Compiler tool and used by PrimeRail for IR drop and electromigraJon analysis. •ERR view: A graphical view of physical design rule violaJons found by verificaJon commands in the IC Compiler tool such as verify_zrt_route or signoff_drc. Verify Libraries To achieve good results, you must have high-quality libraries. Before you process your design, you should use the check_library command to ensure that the logic libraries and physical libraries are correct and consistent. check_library verifies the consistency of cell names, pin names, area values, bus naming convenJons, operaJng condiJon scaling, antenna rules, and so on. It generates a detailed report on any errors or inconsistencies that are found. Design PreparaJon Reading the design AnnotaJng the Floorplan informaJon CreaJng Logical Power and Ground connecJon • Aler you read in the design, you must ensure that there are logical connecJons between the power and ground nets and the power, ground, and Je-off pins on the cells in your design. Linking Design • When the IC Compiler tool performs Jming analysis, each cell instance in the design must be linked to a cell in the link libraries, which provides its Jming informaJon. Placement & OpJmizaJon There are many configuraJon senngs that affect the behavior of placement and opJmizaJon. Placement Keepout Margin: A keepout margin is a region around the boundary of fixed macros in your design in which no other cells are placed. Placement & OpJmizaJon Global Keepout Margin Placement & OpJmizaJon Area based placement blockages The IC Compiler tool supports the following types of area-based placement blockages: • Hard A hard blockage prevents the placement of standard cells and hard macros within the specified area during coarse placement, opJmizaJon, and legalizaJon. • Hard macro A hard macro blockage prevents the placement of hard macros within the specified area during coarse placement, opJmizaJon, and legalizaJon. • Sol A sol blockage prevents the placement of standard cells and hard macros within the specified area during coarse placement, but allows opJmizaJon and legalizaJon to place cells within the specified area. • ParJal A parJal blockage limits the cell density in the specified area during coarse placement, but has no effect during opJmizaJon and legalizaJon. • Pin A pin blockage prevents the global router from rouJng in the specified area, and the pin placer from assigning pins to the area. Placement & OpJmizaJon High fanout net synthesis During placement and opJmizaJon, the IC Compiler tool does not buffer clock nets as defined by the create_clock command, but it does, by default, buffer other high-fanout nets, such as resets or scan enables, using a built-in high-fanout synthesis engine. Placement Area UJlizaJon U>liza>on Placement area uJlizaJon, or simply “uJlizaJon,” means the percentage of area available for placement that is already occupied by placed cells. For example, a uJlizaJon of 80 percent means that 80 percent of the available area is occupied by cells and 20 percent is empty and can sJll be used for addiJonal cell placement, for movement of cells for legalizaJon and opJmizaJon, or as an allowance to prevent excessive rouJng congesJon.
