High Current V-I Circuits + + IN OUT Volts- Amps The Four Musketeers of HPL Recognize John Brown Analyze Art Kay Synthesize Tim Green Tina-ize Tina-TI 1 V-I Circuit “Recognize” Objectives ➢ Potential Applications, End Equipment, Markets ➢ Circuit Topologies ➢ Circuit Stability Issues ➢ Power Dissipation Issues ➢ Transient Protection Issues ➢ PCB Issues ➢ Semiconductor Overstress Issues 2 V-I Circuit “Analyze, Synthesize, Tina-ize ” Objectives ➢ Provide Synthesis Techniques for Common Topologies ➢ Provide Tools to Simplify Stability Analysis ➢ Provide Analysis Techniques for Power Dissipation ➢ Provide Solutions for Common Transient Problems ➢ Provide Tips for PCB Layouts ➢ Provide Tricks for Tina-TI Analysis 3 Power Amplifiers Strategy for Markets 1. High Volume Growth Communications Optical Networking ONET (TECs, Laser Diode Pumps, Avalanche Photodiode Bias HV) DLP Digital Light Projectors (high voltage OPA) Industrial Electromechanical (OPA, PWM) Automotive Electromechanical (OPA, PWM) 2. Gen Std Catalog Products Steady Growth Industrial, Medical, Lab, ATE, Some Audio, Consumer High Speed Buffers, High Voltage, High Current OPAs 4 Power Amplifiers Applications in Markets 1. Test, Particularly Automated ATE Analog Pin Driver, Power V & I Excitation 2. COMPETITION 1. Mostly Discrete 2. National Semiconductor, ST, Maxim, Power Line Communication Allegro, ON-SEMI, International High Pulse Current Drive Through Transformer Rectifier, Infineon, Toshiba or Capacitor Coupled ac Power Line (Residential & Commercial) 3. Displays High Current Driver for Dithering Projected Light Beam, High Voltage for Ink Jet Printers 4. Industrial, Medical, Scientific, Analytical, and Laboratory TEC Drivers, Electromechanical Linear Valve/Positioner Drivers, Motors, Power Supplies 5. Optical Networking / Gen Laser Systems TEC Drivers (Thermo-electric Coolers), Laser Pumps 6. Some Audio Headphone and Speaker Drivers 7. Some Automotive Power Steering Pumps, Window Motors 5 Review - Essential Principles ➢ Poles, Zeros, Bode Plots ➢ ➢ ➢ ➢ ➢ ➢ Op Amp Loop Gain Model Loop Gain Test β and 1/β Rate-of-Closure Stability Criteria Loop Gain Rules-of-Thumb for Stability RO and ROUT 6 Commercial Break (Shameless Self-Promotion) See 15 Part Series: “Operational Amplifier Stability” http://www.analogzone.com/acqt0704.htm 7 Poles and Bode Plots G A = VOUT/VIN fP 100 Actual Function VOUT X100,000 Straight-Line Approximation 80 A (dB) R 0.707G = -3dB VIN -20dB/Decade -6dB/Octave C 60 40 Single Pole Circuit Equivalent 20 ➢ Pole Location = fP ➢ Magnitude = -20dB/Decade Slope 0 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) ▪ Slope begins at fP and continues down as frequency increases ▪ Actual Function = -3dB down @ fP +90 (degrees) +45 ➢ Phase = -45°/Decade Slope through fP 0o Frequency (Hz) 0 10 +-45 100 1k 10k 100k 1M -45o/Decade 10M ▪ Decade Above fP Phase = -90° ▪ Decade Below fP Phase = 0° ➢ A(dB) = 20Log10(VOUT/VIN) -45o @ fP -90 8 -90o Zeros and Bode Plots A = VOUT/VIN 100 C X100,000 A (dB) 80 R +20dB/Decade +6dB/Octave 60 VOUT 40 Straight-Line Approximation 1.414G = +3dB (1/0.707)G = +3dB 20 Actual Function Single Zero Circuit Equivalent G ➢ Zero Location = fZ 0 1 10 100 fZ 1k 10k 100k 1M +90o ➢ Magnitude = +20dB/Decade Slope 10M Frequency (Hz) +90 ▪ Slope begins at fZ and continues up as frequency increases ▪ Actual Function = +3dB up @ fZ +45o/Decade (degrees) +45 +45o @ fZ 0o Frequency (Hz) 0 10 +-45 -90 100 1k 10k 100k 1M 10M ➢ Phase = +45°/Decade Slope through fZ ▪ Decade Above fZ Phase = +90° ▪ Decade Below fZ Phase = 0° ➢ A(dB) = 20Log10(VOUT/VIN) 9 Op Amp: Intuitive Model VO RO K(f) IN+ VOUT x1 RIN + - VDIFF IN- 10 Op Amp Loop Gain Model network RF network RI =VFB/VOUT VOUT VFB VOUT RF + + VFB VIN RI - VOUT/VIN = Acl = Aol/(1+Aolβ) If Aol >> 1 then Acl ≈ 1/β Aol: Open Loop Gain VIN + Aol VOUT β: Feedback Factor Acl: Closed Loop Gain 11 Stability Criteria VOUT/VIN = Aol / (1+ Aolβ) If: Aolβ = -1 Then: VOUT/VIN = Aol / 0 → ∞ If VOUT/VIN = ∞ → Unbounded Gain Any small changes in VIN will result in large changes in VOUT which will feed back to VIN and result in even larger changes in VOUT → OSCILLATIONS → INSTABILITY !! Aolβ: Loop Gain Aolβ = -1 → Phase shift of +180°, Magnitude of 1 (0dB) fcl: frequency where Aolβ = 1 (0dB) Stability Criteria: At fcl, where Aolβ = 1 (0dB), Phase Shift < +180° Desired Phase Margin (distance from +180° Phase Shift) > 45° 12 Traditional Loop Gain Test RI Op Amp Loop Gain Model RF network Op Amp is “Closed Loop” VFB VOUT + + VIN - SPICE Loop Gain Test: RI Break the Closed Loop at VOUT RF network Ground VIN VFB VY 1GH - VOUT + 1GF Inject AC Source, VX, into VOUT Aolβ = VY/VX + VIN + - VX Open for AC Short for DC - Short for AC Open for DC 13 β and 1/β network RF network RI =VFB/VOUT VOUT VFB VOUT RF + + VIN - VFB RI β is easy to calculate as feedback network around the Op Amp 1/β is reciprocal of β Easy Rules-Of-Thumb and Tricks to Plot 1/β on Op Amp Aol Curve 14 Loop Gain Using Aol & 1/β Plot (in dB) 1/β on Op Amp Aol (in dB) Open Loop Response Aol Aolβ = Aol(dB) – 1/β(dB) Note how Aolβ changes with frequency 100 Proof (using log functions): 80 20Log10[Aolβ] = 20Log10(Aol) - 20Log10(1/β) Aol (Loop Gain) Aol (dB) 60 = 20Log10[Aol/(1/β)] = 20Log10[Aolβ] 40 fcl Closed Loop Response Acl 20 0 1 10 100 1k 10k Frequency (Hz) 100k 1M 10M 15 Stability Criteria using 1/β & Aol At fcl: Loop Gain (Aol) = 1 Aol 100 Rate-of-Closure @ fcl = (Aol slope – 1/β slope) fcl1 80 ** fcl2 Aol (dB) 60 * *20dB/decade Rate-of-Closure @ fcl = STABLE **40dB/decade Rate-of-Closure@ fcl = UNSTABLE fcl3 40 ** * 20 fcl4 0 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) 16 Loop Gain Bandwidth Rule: 45 degrees for f < fcl Aolβ (Loop Gain) Phase Plot 180 fcl fp1 -135o “Phase Shift” (degrees) 135 Frequency (Hz) 90 10 45 100 1k fp2 10k fz1 100k 1M 10M 45o “Phase Margin” 0 -45 Loop Stability Criteria: <-180 degree phase shift at fcl Design for: <-135 degree phase shift at all frequencies <fcl Why?: Because Aol is not always “Typical” Power-up, Power-down, Power-transient → Undefined “Typical” Aol Allows for phase shift due to real world Layout & Component Parasitics 17 Poles & Zeros Transfer: (1/β, Aol) to Aolβ fp1 100 Aol 100 Aol & 1/β Plot 80 Aol 60 fcl A (dB) A (dB) Loop Gain Plot (Aolβ) fp1 80 60 fz1 40 40 20 20 fz1 fp2 fcl 0 0 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) To Plot Aolβ from Aol & 1/β Plot: Poles in Aol curve are poles in Aolβ (Loop Gain)Plot Zeros in Aol curve are zeros in Aolβ (Loop Gain) Plot Poles in 1/β curve are zeros in Aolβ (Loop Gain) Plot Zeros in 1/β curve are poles in Aolβ (Loop Gain) Plot [Remember: β is the reciprocal of 1/β] fp2 18 Frequency Decade Rules for Loop Gain Loop Gain View: fp1 Poles: fp1, fp2, fz1; Zero: fp3 Rules of Thumb for Good Loop Stability: 100 ➢ Place fp3 within a decade of fz1 fp1 and fz1 = -135° phase shift at fz1 fp3 < decade will keep phase from dipping further Aol A (dB) 80 ➢ Place fp3 at least a decade below fcl Allows Aol curve to shift to the left by one decade 60 fcl Rn Cn RF 40 fp3 1/Beta 20 fp2 - fz1 + VIN 0 VOUT RI + CL - 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) VOUT/VIN 19 Op Amp Model for Derivation of ROUT ROUT = RO / (1+Aolβ) RF RI RO -IN RDIFF VFB VE xAol + VO IOUT - 1A + +IN VOUT Op Amp Model From: Frederiksen, Thomas M. Intuitive Operational Amplifiers. McGraw-Hill Book Company. New York. Revised Edition. 1988. ROUT = VOUT/IOUT 20 Op Amp Model for Loop Stability Analysis ➢ RO is constant over the Op Amp’s bandwidth ➢ RO is defined as the Op Amp’s Open Loop Output Resistance ➢ RO is measured at IOUT = 0 Amps, f = 1MHz (use the unloaded RO for Loop Stability calculations since it will be the largest value → worst case for Loop Stability analysis) ➢ RO is included when calculating for Loop Stability analysis 21 RO & Op Amp Output Operation ➢ Bipolar Power Op Amps ➢ CMOS Power Op Amps ➢ Light Load vs Heavy Load 22 RO Measure w/DC Operating Point: IOUT = 0mA V+ VOUT Bipolar All NPN Output V23 RO Measure w/DC Operating Point: IOUT = 0mA RO = VOA / AM1 RO = 9.61mVrms / 698.17μArms RO = 13.765Ω 24 RO Measure w/DC Operating Point IOUT = 4.45mA Sink 25 RO Measure w/DC Operating Point IOUT = 4.45mA Sink RO = VOA / AM1 RO = 3.45Vrms / 706.25µArms RO = 4.885Ω 26 RO Measure w/DC Operating Point IOUT = 5.61mA Source 27 RO Measure w/DC Operating Point IOUT = 5.61mA Source RO = VOA / AM1 RO = 3.29mVrms / 700.98μArms RO = 4.693Ω 28 RO Measure w/DC Operating Point IOUT = 2.74A Source 29 RO Measure w/DC Operating Point IOUT = 2.74A Source RO = VOA / AM1 RO = 314.31uVrms / 550.1μArms RO = 0.571Ω 30 RO Measure w/DC Operating Point IOUT = 2.2A Sink 31 RO Measure w/DC Operating Point IOUT = 2.2A Sink RO = VOA / AM1 RO = 169.92uVrms / 635.16μArms RO = 0.267Ω 32 RO Measure w/DC Operating Point IOUT = 0A V+ VOUT MOSFET Complementary Output 33 RO Measure w/DC Operating Point IOUT = 0A RO = VOA / AM1 RO = 4.42mVrms / 702.69μArms RO = 6.29Ω 34 RO Measure w/DC Operating Point IOUT = 1A Sink 35 RO Measure w/DC Operating Point IOUT = 1A Sink RO = VOA / AM1 RO = 166.76μVrms / 540.19μArms RO = 0.309Ω 36 RO Measure w/DC Operating Point IOUT = 1A Source 37 RO Measure w/DC Operating Point IOUT = 1A Source RO = VOA / AM1 RO = 166.61μVrms / 540.34μArms RO = 0.308Ω 38 Non-Inverting Floating Load V-I ➢ Basic Topology ➢ Stability Analysis (w/effects of Ro) ✓ 1/ & Aol Test ✓ Loop Gain Test ✓ Transient Test ➢ Small Signal BW for Current Control 39 Non-Inverting V-I Floating Load RF 1k V- 15 VP R1A 20k VIN Ili m - VOA R1B 20k + VP + +5V U2 OPA548 R2 10k + E/S V+ 15 -5V -1V LL 15m IOUT -3.03A VP +1V 3.03A VRS RL 1.5 VP RS 330m Op Amp Point of Feedback is VRS Op Amp Loop Gain forces +IN (VP) = -IN = VRS IOUT = VP / RS IOUT = {(R2*VIN) / (R1A + R1B + R2)} / RS 40 Non-Inverting V-I Floating Load RO Reflected Outside of Op Amp RF 1k F B#1 V- 15 VFB VO Ili m - U2 OPA548 R1A 20k + + VIN + VCV1 RO 13.77 + + VOA E/S R1B 20k - R2 10k V1 0 x1 - LL 15m V+ 15 RL 1.5 VP VRS RO = 13.765 @ No Load RO = 0.267 @ Full Load RS 330m 41 Non-Inverting V-I Floating Load FB#1 DC 1/ Derivation FB#1 DC 1/Beta LL is a SHORT DC Beta FB#1 = VFB/VO DC 1/Beta FB#1 = VO/VFB VFB = VO*RS RO+RL+RS RF 1k VFB Set VO = 1 VFB = RS VO (RO+RL+RS) VO Ili m - U2 OPA548 + + x1 VCV1 RO 13.77 + + VOA E/S - LL 15m - VO = (RO+RL+RS) VFB RS VO = (13.77+1.5+0.33) VFB 0.33 VO = 47.27 →33.49dB VFB RL 1.5 20Log10 (47.27) = 33.49dB VRS RS 330m 42 Non-Inverting V-I Floating Load FB#1 1/ Derivation Beta FB#1 = VFB/VO RF 1k 1/Beta FB#1 = VO/VFB VFB VFB = VO*RS RO+XLL+RL+RS VO Ili m - U2 OPA548 + + x1 VCV1 RO 13.77 + + XLL = jLL VOA E/S - Set VO = 1 LL 15m - RL 1.5 VRS VFB = RS VO (RO+RL+RS) + jLL VO = (RO+RL+RS) + jLL VFB RS VFB = RS / LL VO (RO+RL+RS) + j LL VO = (RO+RL+RS) + j VFBLL RS / LL Pole in Beta FB#1: fp = Ro+RL+RS 2LL Zero in 1/Beta FB#1: fz = Ro+RL+RS 2LL RS 330m fz = 13.77+1.5+0.33 215mH fz = 165Hz 43 Non-Inverting V-I Floating Load FB#1 1/Data for RO No Load & Full Load IOUT RO fz DC 1/ No Load 0A 13.765W 165Hz 33.49dB Full Load 1A 0.267W 22.25Hz 16.06dB 44 OPA548 Data Sheet Aol 45 Non-Inverting V-I Floating Load FB#1 1/ Plot for RO No Load & Full Load 120 OPA548 Aol Gain (dB) 100 80 60 STABLE 40 fz 1/ FB#1 w/RO=13.765W 20 0 fz 1/ FB#1 w/RO=0.267W 1 10 100 1K 10K Frequency (Hz) 100K 1M 10M 46 Non-Inverting V-I Floating Load FB#1 1/ Tina SPICE RF 1k V- 15 VT VOA Ili m - VCV1 + + U2 OPA548 R1A 20k + + RO 13.77 VOA2 VG1 E/S R1B 20k - R2 10k LT 1G CT 1G + VFB LL 15m - V+ 15 VP 1/Beta FB#1 = VT/VFB Aol = VOA/VF B Loop Gain = VOA/VT RO = 13.765 @ No Load RO = 0.267 @ Full Load RL 1.5 VRS RS 330m 47 Non-Inverting V-I Floating Load FB#1 1/ Tina SPICE Results T 120.00 100.00 OPA548 Aol 80.00 Gain (dB) STABLE 1/Beta FB#1 RO = 13.77 ohms 60.00 40.00 20.00 0.00 -20.00 10 100 1k 10k Frequency (Hz) 100k 1M 10M 48 Non-Inverting V-I Floating Load FB#1 1/ Tina SPICE Results T 120.00 100.00 OPA548 Aol Gain (dB) 80.00 STABLE 60.00 40.00 20.00 1/Beta FB#1 RO = 0.267 ohms 0.00 -20.00 10 100 1k 10k Frequency (Hz) 100k 1M 10M 49 Non-Inverting V-I Floating Load FB#1 Loop Gain Tina SPICE Results STABLE 50 Non-Inverting V-I Floating Load FB#1 Transient Analysis Tina SPICE Circuit RF 1k RO = 13.765 @ No Load RO = 0.267 @ Full Load V- 15 VOA Ili m - VCV1 + + U2 OPA548 R1A 20k + + RO 267m VOA2 E/S R1B 20k - - LL 15m V1 0 R2 10k + V+ 15 VG1 100Hz 330mVpk tr=tf =10ns VP RL 1.5 VRS RS 330m + A AM1 51 Non-Inverting V-I Floating Load FB#1 Transient Analysis Tina SPICE Results T 282.89m AM1 -252.74m 330.00m VG1 -330.00m 13.25 VOA STABLE -14.74 13.30 VOA2 -14.79 68.12m VP -66.20m 93.35m VRS -83.40m 0.00 5.00m 10.00m Time (s) 15.00m 20.00m 52 Non-Inverting V-I Floating Load Add FB#2 and Predict 1/ 120 Note: Load Current Control begins to roll-off in frequency where FB#2 dominates OPA548 Aol 100 Gain (dB) FB#1 80 60 fz1 40Hz 40 FB#2 fz 1/ FB#1 w/RO=13.765W 20 36dB 1/ fz 1/ FB#1 w/RO=0.267W 0 1 10 100 1K 10K Frequency (Hz) 100K 1M 10M 53 How will the two feedbacks combine? Answer: The largest β (smallest 1/β) will dominate! Large β Small β - 54 Non-Inverting V-I Floating Load FB#2 Circuit RF 1k CF 68n Rd 61.9k FB#2 V- 15 VT VFB VOA VCV1 + + + + - R2 10k V+ 15 VP RO = 13.765 @ No Load 1/Beta = VT/VFB RO = 0.267 @ Full Load Aol = VOA/VF B Loop Gain = VOA/VT VOA2 CT 1G E/S R1B 20k RO 267m - + U2 OPA548 R1A 20k LT 1G O An pe a n Se lyze FB pa F #1 ra B# te 2 Ili m - LL 15m FB#1 VRS RL 1.5 VT RS 330m 55 Non-Inverting V-I Floating Load FB#2 High Frequency 1/ FB#2 High Frequency 1/Beta CF is a SHORT Hi-f 1/Beta FB#2 = VOA/VFB Hi-F Beta FB#2 = VFB/VO Hi-f 1/Beta FB#2 = 36dB RO 13.77 36dB → 10(36/20) = 63 VOA IFB Hi-F Beta FB#2 = 1/63 = 0.15848931 Rd 61.9k Set VO = 1 Beta=VFB CF 68n IFB = VFB/(RF+RS) IFB = 0.15848931/(1k+0.33)=15.85uA VFB RF 1k VOA-VFB = Rd IFB 1 - 0.15848931 = 62.09k→ use 61.9k 15.85uA RS 330m 56 Non-Inverting V-I Floating Load FB#2 fz1 FB#2 1/Beta - fz1 RO 13.77 fz1 = 1 2CF*(RO+Rd+RF+RS) VOA Rd 61.9k VFB CF 68n RF 1k But if: Rd > 10*RF Rd > 10*RS Rd > 10*Ro Then: fz1 1 2CF*Rd CF 1 2fz1*Rd CF = 1 240Hz*61.9k = 64.2nF Use: CF = 68nF RS 330m 57 Non-Inverting V-I Floating Load Tina SPICE Loop Test RF 1k CF 68n Rd 61.9k V- 15 VT VFB VOA Ili m VCV1 + + U2 OPA548 R1A 20k + + - R2 10k V+ 15 RO 267m VOA2 CT 1G E/S R1B 20k LT 1G - + - VT VP RO = 13.765 @ No Load 1/Beta = VT/VFB RO = 0.267 @ Full Load Aol = VOA/VF B Loop Gain = VOA/VT LL 15m RL 1.5 VRS RS 330m 58 Non-Inverting V-I Floating Load Aol and 1/ Tina SPICE Results 59 Non-Inverting V-I Floating Load Loop Gain Tina SPICE Results 60 Non-Inverting V-I Floating Load IOUT/VIN AC Response Circuit RF 1k CF 68n Rd 61.9k V- 15 VFB VOA Il im - + + VCV1 + + U2 OPA548 R1A 20k + RO 267m VOA2 E/S R1B 20k - + - A VIN R2 10k IOUT V+ 15 VP RO = 13.765 @ No Load 1/Beta = VT/VF B RO = 0.267 @ Full Load Aol = VOA/VFB Loop Gain = VOA/VT LL 15m RL 1.5 VRS RS 330m 61 Non-Inverting V-I Floating Load IOUT/VIN AC Tina SPICE Results 62 Non-Inverting V-I Floating Load IOUT/VIN Transient Circuit RF 1k Rd 61.9k CF 68n V- 15 VFB VIN Il im - VCV1 + + U2 OPA548 R1A 20k + + 330mVp 100Hz tr=tf =10ns VOA + VOA2 E/S R1B 20k - R2 10k RO 267m - + A V+ 15 VP IOUT LL 15m RO = 13.765 @ No Load RO = 0.267 @ Full Load RL 1.5 VRS RS 330m 63 Non-Inverting V-I Floating Load IOUT/VIN Transient Tina SPICE Results T 231.12m IOUT -197.99m 330.00m VIN -330.00m 4.06 VOA -7.59 76.27m VRS -65.33m 0.00 2.50m 5.00m Time (s) 7.50m 10.00m 64 Inverting V-I Floating Load RF 2k V- 15 Ili m - + +5V U2 OPA548 RI 10k VIN + -5V VOA + E/S LL 15m -3.03A V+ 15 IOUT +3.03A Op Amp Point of Feedback is VRS Op Amp Loop Gain forces VRS = -VIN (RF/RI) IOUT = {-VIN*(RF/RI)} / RS IOUT = -VIN*{RF/ (RI*RS)} RL 1.5 VRS -1V +1V RS 330m Stability Analysis & Compensation Techniques similar to Non-Inverting V-I Floating Load 65 Grounded Load V-I Improved Howland Current Pump ➢ Basic Topology ➢ Stability Analysis (w/effects of Ro) ✓ 1/ & Aol Test ✓ Loop Gain Test ✓ Transient Test ➢ Small Signal BW for Current Control 66 Improved Howland Current Pump IL Accuracy Circuit RT allows for trim to optimum ZOUT and improved DC Accuracy RT 0 RF 5k RI 1k VM 100m X1G - - + + VCV1 RS 5 VL RZ 1k VO + A IL RX 5k RX RF RS RF RX VP + 1 + − VM + RZ RI RZ RI RZ IL = RS 1 + RX + RS + RX − RF RL RL RZ RZ RI RL 10 VP 200m 1 67 Improved Howland Current Pump V-I DC Accuracy Calculations RT 2.858407 0 2.858407 2.858407 2.858407 2.858407 2.858407 2.858407 RF RX 5000 5000 5000 5000 5050 5000 5000 5050 5000 5000 5000 5000 5000 5000 5000 5000 0 2.858407 5050 5050 4950 4950 RI RZ RS RL 1000 1000 5 10 1000 1000 5 10 1000 1000 5 10 1000 1000 5 10 1010 1000 5 10 1000 1010 5 10 1000 1000 5.05 10 1000 1000 5 10.1 990 990 1010 1010 4.95 4.95 IL 0.100000052 0.099866893 0.102371216 0.098700599 0.097727653 0.101353602 0.099009365 0.099999329 10 0.108995522 10 0.109152449 VL 1.000000100 0.998668931 1.023712000 0.987005991 0.977276527 1.013536000 0.990094651 1.009993000 VO 1.500667000 1.498669000 1.536255000 1.481159000 1.466563000 1.520981000 1.490756000 1.510665000 1.089955000 1.630222000 1.091524000 1.632570000 AM1 Sensitivity (%) 0.000000000 0.133158931 -2.371162767 1.299452324 2.272397818 -1.353549296 0.990686485 0.000723 Comments Rt adjusted for Ideal IL Rt=0, Nominal Values 1% Resistor Changes 1% Resistor Changes 1% Resistor Changes 1% Resistor Changes 1% Resistor Changes 1% Resistor Changes -8.995465322 1% Worst Case w/RT=0) -9.152392241 1% Worst Case w/RT=Nom) 1% Resistors (w/RT=0) could yield only 9% Accuracy at T=25°C Still useful for V-I control in Motors/Valves → V-Torque Control Outer position feedback adjusts V for final position 68 Improved Howland Current Pump General Equation RF Set RX=RF and RZ=RI RF 5k RI 1k - VM 100m RI 1k Iset Imon VO Iflag RS 5 U1 OPA569 VL + + En VP 200m Tflag R3 500k − R5 500k RS + 1 VM RI RF RI RI RL RS 1 + + RF RF + R4 500k IL = RF Rset 5.76k VP 1 + LL 30m RL 3 Vs+ 5 + RF 5k A IL 69 Improved Howland Current Pump Simplified Equation RF 5k RI RS RI 1k - RI 1k Imon VO Iflag RS 5 U1 OPA569 VL + + En VP 200m Tflag R3 500k VM 100m Iset R5 500k IL = RF R4 500k ( VP − VM ) Rset 5.76k Assume: RF = RX RI = RZ RF>>RS RF>>RL LL 30m RL 3 Vs+ 5 + RF 5k A IL 70 Improved Howland AC Analysis RI 1k - RZ1k Imon VO Iflag RS5 U1OPA569 VL + + En RI VP 200m Tflag R3 500k VM 100m Iset R5 500k - R4 500k Rset 5.76k RF5k LL 30m RL3 Vs+ 5 + RF RX5k + A IL Op Amp sees differential [(-IN) – (+IN)] feedback = - - + (Must be positive number else oscillation!) 71 Improved Howland AC Analysis − Aol 1/ = 1 (-) - (+) VOUT + 72 Improved Howland AC Analysis Include Effects of RO RF 5k + - Vbeta RZ 1k Iset Imon LT 1G Iflag En VP 200m RS 5 VCV1 + + U1 OPA569 + + VOA VT VO VL RO 309m Tflag - CT 1G - LL 30m + VM 100m V RO = 6.29 No Load RO = 0.308 Full Load R3 500k RI R5 500k RI 1k R4 500k Rset 5.76k Aol = VO/Vbeta 1/Beta = VT/Vbeta Loop Gain = VO/VT VM VG1 RL 3 Vs+ 5 + A IL RX 5k VP RF 73 Improved Howland - Calculation - Calculation VO - = VM/VO Set VO = 1→ - = VM RO6.29 RF5k VM = VO * RI RO + RF + RI VM = 1 * 1k = 0.166492127 6.29 + 5k + 1k - = 0.166492127 VM RI 1k - is constant over frequency since just resistors are in feedback path. 74 Improved Howland + Calculation + DC Calculation + = VP/VO Set VO = 1→ + = VP 1/+ Poles and Zeros: Since RF & RI >> RS & RL then: RS 5 VL 1*3 = 0.2099937018 6.29 + 5 + 3 RF 5k VP = RL 3 VL * RI RF+ RI VP VP = + = VP/VO Set VO = 1→ + = VP RO 6.29 Since RF & RI >> RS & RL: VL = VO * RL RO + RS + RL VL = 0.2099937018 * 1k = 0.03499895 5k +1k + DC = 0.03499895 + AC Calculation + Calculation VO LL 30m RI 1k LL Inductor: Short for + DC Open for + Hi-f fz = RO + RS +RL 2*LL fz = 6.29 + 5 +3 = 75.8Hz 2*30m fp = RF + RI 2*LL fp = 5k + 1k = 31.83kHz 2*30m + Hi-f: VP = RI RF + RI + RO + RS VP = 1k = 0.166353644 5k + 1k + 6.29 + 5 + Hi-f = 0.166353644 75 Improved Howland 1/ Calculation Calculation DC = -) - + DC) DC = 0.166492127 - 0.03499895 = 0.131493777 1/ DC = 7.6 → 17.62dB Hi-f = (-) - (+ Hi-f) Hi-f = 0.166492127 - 0.166353644 = 0.000138483 1/ Hi-f = 7221.1→ 77.17dB 1/Poles and Zeros directly from 1/+ fz = 75.8Hz fp = 31.83kHz 76 Improved Howland - Calculation RO = Full Load - Calculation RO = Full Load VO - = VM/VO Set VO = 1→ - = VM RO 308m RF 5k VM = VO * RI RO + RF + RI VM = 1 * 1k = 0.166658111 308m + 5k + 1k - = 0.166658111 VM RI 1k - is constant over frequency since just resistors are in feedback path. 77 Improved Howland + Calculation RO = Full Load + DC Calculation + AC Calculation + Calculation RO = Full Load VO + = VP/VO Set VO = 1→ + = VP + = VP/VO Set VO = 1→ + = VP RO 308m Since RF & RI >> RS & RL: VL = VO * RL RO + RS + RL VL = 1/+ Poles and Zeros: Since RF & RI >> RS & RL then: RS 5 1*3 = 0.361054278 309m + 5 + 3 RF 5k VP = VL * RI RF+ RI VP VP = 0.361054278 * 1k = 0.060175713 5k +1k + DC = 0.060175713 fz = RO + RS +RL 2*LL fz = 308m + 5 +3 = 44.08Hz 2*30m fp = RF + RI 2*LL fp = 5k + 1k = 31.83kHz 2*30m VL RL 3 LL 30m RI 1k LL Inductor: Short for + DC Open for + Hi-f + Hi-f: VP = RI RF + RI + RO + RS VP = 1k = 0.166519352 5k + 1k + 308m + 5 + Hi-f = 0.166519352 78 Improved Howland 1/ Calculation RO = Full Load Calculation RO = Full Load DC = -) - + DC) DC = 0.166658111 - 0.060175713 = 0.106482398 1/ DC = 9.39 → 19.45dB Hi-f = (-) - (+ Hi-f) Hi-f = 0.166658111 - 0.166519352 = 0.000138759 1/ Hi-f = 7206.7→ 77.15dB 1/Poles and Zeros directly from 1/+ fz = 44.08Hz fp = 31.83kHz 79 Improved Howland 1/ Calculation No Load & Full Load IL RO No Load 0A 6.29W fz 75.8Hz fp DC 1/ Hi-f 1/ 31.83kHz 17.62dB 77.17dB Full Load 1A 0.308W 44.08Hz 31.83kHz 19.45dB 77.15dB Change in RO from No Load to Full Load has no significant impact on the 1/ Plot 80 OPA569 Data Sheet Aol 81 Improved Howland 1/ Plot - Full Load 120 OPA569 Aol 100 Gain (dB) fp 31.83kHz 80 1/ RO=Full Load 60 STABLE 40 fz 44.08Hz 20 0 1 10 100 1K 10K Frequency (Hz) 100K 1M 10M 82 Improved Howland 1/ Tina SPICE Plot - Full Load STABLE 83 Improved Howland Loop Gain Tina SPICE Plot - Full Load STABLE 84 Improved Howland Tina Transient Analysis Circuit +/-10mV 100Hz - RI Iset Imon R5 500k VO Iflag RS 5 VL U1 OPA569 RZ 1k + + En VP 500m Tflag R3 500k VG2 + RI 1k R4 500k Rset 5.76k RF 5k LL 30m RL 3 Vs+ 5 + RX 5k A IL RF 85 Improved Howland Tina Transient Analysis Results T 514.33m IL 476.55m 10.00m VG2 -10.00m 2.57 STABLE VL -2.94 4.97 VO -414.75m 0.00 5.00m 10.00m Time (s) 15.00m 20.00m 86 Improved Howland Modified 1/ for Stability 120 OPA569 Aol 100 Gain (dB) fp 31.83kHz 80 + FB#2 to Modify 1/ 1/ RO=Full Load 60 fz1 40 fz 44.08Hz Modified 1/ 20 0 1 10 100 1K 10K Frequency (Hz) 100K 1M 10M 87 + FB#2 Calculation to Modify 1/ for Stability + FB#2 Calculation (1) VO + FB#2 RO 308m (0.15658111) VL RF 5k RL 3 VP Id Rd 13k LL 30m RI 1k Ii + FB#2 fz1 Calculation Desired 1/ = 40dB → x100 Desired = 0.01 - = 0.166658111 fz1 = 1 2RdCf Cf = 1 fz1*2*Rd Cf = 1 = 0.2782429F 44Hz*2*13k + = (-) - + = 0.166658111 - 0.01 + = 0.15658111 = VP RS 5 If + FB#2 Calculation: Hi-f Analysis Ind ucto r is o pen fo r Hi-f Analysis If = VO - VP [set VO = 1, RF >> RO, RS] RF If = 1 - 0.15658111 = 168.68377A 5k Cf = 0.27F (standard value) Ii = VP RI Cf 270n Capacitor is short for Hi-f Analysis Ii = 0.15658111 = 156.58111A 1k Id = If - Ii Id = 168.68377A - 156.58111A Id = 12.10266A Rd = VP Id Rd = 0.15658111 = 12.937743k 12.10266A Rd = 13k (standard value) 88 Improved Howland AC Analysis Final Design for Stability + VP 200m RZ 1k Imon LT 1G Iflag En RS 5 VCV1 + + U1 OPA569 + + Cf 270n Rd 13k VM 100m Vbeta Iset VOA VT VO VL RO 309m Tflag - CT 1G - LL 30m + RI - RO = 6.29 No Load RO = 0.308 Full Load R3 500k V R5 500k Rset 5.76k RI 1k R4 500k RF 5k VM Aol = VO/Vbeta 1/Beta = VT/Vbeta Loop Gain = VO/VT VG1 RL 3 Vs+ 5 + A IL RX 5k VP RF 89 Improved Howland AC Analysis 1/ - Final Design for Stability fcl 90 Improved Howland AC Analysis Loop Gain - Final Design for Stability fcl 91 Improved Howland AC Transfer Analysis IL/VIN - Final Design for Stability RI En Cd 270n Rd 13k + + VP 500m Imon Iflag RS 5 VL U1 OPA569 RZ 1k VIN Iset VO Tflag R3 500k + - R5 500k RI 1k R4 500k Rset 5.76k RF 5k LL 30m RL 3 Vs+ 5 + RX 5k A IL RF 92 Improved Howland AC Transfer Analysis IL/VIN - Final Design for Stability 93 Improved Howland Transient Analysis IL/VIN - Final Design for Stability - VP 500m Imon VO Iflag RS 5 VL U1 OPA569 RZ 1k + + En Tflag R3 500k +/-10mV 100Hz RI Cf 270n Rd 13k + VIN Iset R5 500k RI 1k R4 500k Rset 5.76k RF 5k LL 30m RL 3 Vs+ 5 + RX 5k A IL RF 94 Improved Howland Transient Analysis IL/VIN - Final Design for Stability T 510.68m IL 489.03m 10.00m VIN -10.00m 2.50 VL 12.44m 4.96 VO 2.55 0.00 5.00m 10.00m Time (s) 15.00m 20.00m 95 High Current V-I General Checklist ➢Large Signal & Transient SOA Considerations (V=L*di/dt) ➢Bipolar Output Stages & Oscillations ➢High Current Grounding ➢High Current PCB Traces ➢High Current Supply Issues ➢Power Supply Bypass (Low f & High f) ➢Transient Protection (Supply, VIN, VOUT) ➢Power Dissipation Considerations (see “V-I Circuits Using External Transistors” section) ❖Consider: ✓Short Circuit to Ground Power Dissipation ✓Heatsink Selection ✓Current Sense Resistor (RS) Power Dissipation 96 V-I Large Signal Limits: V=Ldi/dt Laws of Physics dictate: V=Ldi/dt dt = Ldi/V V- 15 VOA (12V) U2 OPA548 Il im - + + Rule of Thumb: VLL = VOA - VRL - VRS VLL = VOA - IL*RL - IL*RS E/S LL 15m RL 1.5 IL dt = LL*dIL/VLL IL dt = 15m*1/10.17 = 1.47ms Fastest IL/VIN Slew Rate = 1A/1.47ms Limit VIN Slew Rate x V-I Gain to match IL/VIN Slew Rate RS 330m OPA548 Slew Rate = 10V/us VOA dt = VOA/(Slew Rate) VOA dt = 12V/(10V/us) = 1.2us V+ 15 + A VLL = 12 - 1*1.5 - 1*0.330 = 10.17V IL (1A) Rule of Thumb: VOA dt < (IL dt)/10 1.2us < 1470us/10 1.2us < 147us Op Amp Slew Rate < (IL/VIN Slew Rate)/10 97 Violate the Laws of Physics and Pay the Price! Instant Current Change Steady State Current Flow 13.17V 30V +15V +15V +15V + - RL 1.5W -15V LL 30mH + 0.99V - RS 0.33W 1.5W 15V 4.5V RL IL 3A LL 30mH -15V + IL 3A -15V RS 0.33W 98 Instant V-I Reversal → SOA Violations 99 Output Stages ✓ fosc > UGBW ✓ oscillates unloaded? -- no ✓ oscillates with VIN=0? -- no RF 100kW L O A D RI 100kW + VIN VOUT + RSN 10W to 100W - CSN F to 1F -VS PROBLEM Some Op Amps use composite output stages, usually on the negative output, that contain local feedback paths. Under reactive loads these output stages can oscillate. SOLUTION The Output R-C Snubber Network lowers the high frequency gain of the output stage preventing unwanted oscillations under reactive loads. 100 ✓ fosc < UGBW ✓ oscillates unloaded? -- no ✓ oscillates with VIN=0? -- yes Ground Loops RI RF VIN + - PROBLEM RGv - +VS VOUT VIN + -VS - RGw RL IL RGx + RGy “Ground” Ground loops are created from load current flowing through parasitic resistances. If part of VOUT is fed back to Op Amp +input, positive feedback and oscillations can occur. SOLUTION RI “Star” Ground Point RF - +VS VOUT + -VS RL RG Parasitic resistances can be made to look like a common mode input by using a “Single-Point” or “Star” ground connection. 101 ✓ fosc < UGBW ✓ oscillates unloaded? -- may or may not ✓ oscillates with VIN=0? -- may or may not PCB Traces RI RF + + VIN - Rs VOUT GND DO NOT route high current, low impedance output traces near high impedance input traces. DO route high current output traces adjacent to each other (on top of each other in a multi-layer PCB) to form a twisted pair for EMI cancellation. 102 ✓ fosc < UGBW ✓ oscillates unloaded? -- no ✓ oscillates with VIN=0? -- may or may not Supply Lines Ls PROBLEM Gain Stage PROBLEM Power Stage +vs RL IL - Rs + CL -vs Load current, IL, flows through power supply resistance, Rs, due to PCB trace or wiring. Modulated supply voltages appear at Op Amp Power pins. Modulated signal couples into amplifier which relies on supply pins as AC Ground. Power supply lead inductance, Ls, interacts with a capacitive load, CL, to form an oscillatory LC, high Q, tank circuit. 103 Proper Supply Line Decouple CLF SOLUTION CLF: Low Frequency Bypass < 4 in <10 cm RHF 10μF / Amp Out (peak) Aluminum Electrolytic or Tantalum CHF +VS < 4 in (10cm) from Op Amp - CHF: High Frequency Bypass + 0.1μF Ceramic -VS < 4 in <10 cm Directly at Op Amp Power Supply Pins CHF RHF RHF: Provisional Series CHF Resistance 1Ω < RHF < 10Ω CLF Highly Inductive Supply Lines 104 Transient Protection High frequency bypass, ceramic (0.1F) Low frequency bypass, Tantalum or Aluminum Electrolytic, (10F per peak amp of output current) POWER SUPPLY Bypass D8 1N4148 D7 1N4148 INPUT Protection D3 1N4148 C1 100n V+ 15 VIN+ + + C2 22u Stack diodes to allow for differential overdrive to achieve fastest slew rate Fast reverse-recovery flyback diodes rate at least 2x Vsupply Z1 1N5246 D1 MUR140 E/S OUTPUT Protection + U2 OPA548 - D5 1N4148 Ili m D2 MUR140 V- 15 D6 1N4148 VIN- + C4 22u D4 1N4148 C3 100n LL 30m Z2 1N5246 POWER SUPPLY Protection RL 3 Anode For lower leakage & lower capacitance use diode connected JFET CF 100n T1 2N3369 Cathode Zeners or Semiconductor Transient Suppressors prevent Power Supply overvoltage, reverse polarity protection, low impedance for transient energy from ouptut flyback diodes. Semiconductor Transient Suppressors have larger junction areas than zeners and can diddpate larger amounts of power for short periods of time. 105 V-I Circuits Using External Transistors ➢ Choosing the Transistor ➢ Power Dissipation Considerations ➢ Traditional Floating Load Circuit ➢ Novel V-I Using Opposite Polarity Transistor 106 Example: OPA335 and Bipolar Transistor Supply: 5V Utility Gain Buffer V1 5 Output Swing: 0V to 5V Load: 20ohm (250mA max) - T1 !NPN + + + U1 OPA335 Vin V1 5 How do we choose the BJT? R1 100 Vout 107 Bipolar Junction Transistor (BJT) T2 TIP29C Collector ib + rb’ vin Base NPN iout = hfe x ib - T18 !PNP Emitter Collector Base PNP Emitter 108 Design Process for Selecting Transistor Do simple rule of thumb calculations Select device using parametric search (Digikey example) Do detailed analysis Repeat if design goals are not achieved. 109 Simple Rule of Thumb Calculations 1. 2. 3. 4. 5. Power / Package Collector Current Base Current Vceo (Collector to Emitter Break Down Voltage) Vbe (Base to Emitter Voltage) 110 DC Power Dissipation When is there maximum power in the output transistor? DC Signal ) RL Vcc − Vout ) 2 P(transistor) vs. V(load) for a DC Signal 40.35 R L 0.3 Vout Power_Maximum P 2 Vcc 2 4 RL 0.25 P(Transistor) P Vout Vout V cc 0.2 0.15 V cc 0.1 2 0.05 0 0 P 1 2 3 4 5 V(load) for a DC Signal 111 AC Power Dissipation When is there maximum power in the output transistor? AC Sinusoidal Signal ) Vcc Vout V + 2 2 RL out RL −1 2 2 Vcc Power_Maximum P 2 Vcc 2 2 Pc(Push-Pull) vs Vload for an AC Sinusoidal Signal 2 2 RL P(Push Pull Output Transistors) P Vout 2 V cc 0.3 R L 0.25 0.2 2 Vcc 0.15 0.1 0.05 0 0 P 1 2 3 4 5 V(load) peak AC Sinusoidal Voltage 112 Maximum Power in the External Transistor Use the DC Maximum Power Dissipation for Worst Case Power_Maximum V cc 2 4 R L ( 5V) 2 4 20W ) 112.5mW Double the power for margin over temperature PowerRat ing Power_Maximum2 ( 112.5mW) ( 2) 225mW 113 Characteristics of Different Package Types Package MaxPower TA = 25C No heat sink MaxPower TA = 85C No heat sink MaxPower TC = 25C RθJA RθJA 1in2 pad RθJC SOT-23 0.3 0.15 1 400 250 --na-- SOT-223 0.75 0.4 3 175 80 --na-- DPAC IPAC 1.5 0.65 20 100 50 6.25 TO-220 2 1 50 62.5 --na-- 2.78 TO-3 4.2 2.2 100 30 --na-- 1.25 For our example 114 Different Package Types TO-3 IPAK DPAK SOT-223 SOT-23 TO-220 115 Simple Rule of Thumb Calculations 1. 2. 3. 4. 5. Power / Package Collector Current Base Current Vceo (Collector to Emitter Break Down Voltage) Vbe (Base to Emitter Voltage) We’ve looked at Power. Now let’s investigate current. 116 Max Collector Current in the External Transistor The OPA335 is a “rail-to-rail” out Vout_max = Vopa_max – Vbe = 5V – 0.6V = 4.4V Max Output Current = (Vout_max)/RL =4.4V / (20Ω) = 220mA Add 20% margin Ic_max rating > (220mA)(1.5) = 330mA 117 Maximum Base Current in the External Transistor Standard BJT Power Transistor: Typical hfe_min = 20. Base Current = Ic_max / hfe_min = 220mA / (20) = 11mA (too high) Use a Darlington. Typical minimum hfe_typ = 1000. U1(good) BCX38B Base Current = Ic_max / hfe_min = 220mA / (1000) = 220uA Darlington Use less than 2mA for good swing to the rail. 118 Simple Rule of Thumb Calculations 1. 2. 3. 4. 5. Power / Package Collector Current Base Current Vceo (Collector to Emitter Break Down Voltage) Vbe (Base to Emitter Voltage) Now let’s investigate voltage ratings. 119 BJT Breakdown Voltages V1 5 • Max voltage across any junction is 5V • Most transistor breakdown > 50V U1 OPA335 - T1 !NPN + • Provide Capacitive Isolation V1 5 Vout R1 100 Vin • Add a protection resistor in the base • Limit base current + + R2 1k 120 Design Process Here is the are the results of the rule of thumb calculations Do simple rule of thumb calculations Power Rating > 225mW Package Type: SOT23 Ic_max rating > 330mA Type: Darlington NPN Using Digikey parametric search Select device using parametric search (Digikey example) Do detailed analysis Narrow from 4638 → 8 transistors. Repeat if design goals are not achieved. 121 Parametric Search Results The result of the Digikey parametric search. We choose the least expensive one MMBT6427 @ $0.104. 122 Design Process Now we verify if our choice will really work! Do simple rule of thumb calculations Select device using parametric search (Digikey example) Do detailed analysis Repeat if design goals are not achieved. 123 MMBT6427 Data Sheet Look at the “Maximum Ratings” No problem -- were working with 5V. Ic_max= 220mA (lots of margin) 124 Maximum Power / Junction Temperature • Maximum power dissipation dictates device (junction) temperature • Device temperature is also effected by -- Ambient temperature -- Package Type (Data specifications) -- Heat sink -- Air flow 125 Maximum Power / Junction Temperature MMBT6427 Transistor Power_Maximum = 112.5mW Rule of thumb: double Power_Maximum. Power_Rating > 225mW (edge of Spec) Are we ok? 126 Look at Thermal Model Thermal model with no heat sink TJ PD Analogous to an electrical circuit TJ= PD( RθJA) + TA RθJA T – is analogous to voltage R – is analogous to resistance TA P – is analogous to current TA 127 Use the Thermal Model Assuming TA = 25oC TJ = PD( RθJA) + TA = (112.5mW)(556oC/W) + 25oC = 87.5oC What is the maximum ambient operating temperature? Tmax_ambient = 150oC – 62.5oC = 87.5oC (Enough margin?) 128 Thermal Model for the Heat Sink TJ RθJC PD TC TJ = PD( RθJC + RθCS + RθSA) + TA PD – The power dissipation of the transistor TJ – The junction temperature TC – The case temperature RθCS TS RθSA TS – The heat sink temperature TA – The ambient temperature TA 129 Here is the Mechanical Description Case RθJC Junction Heat Sink RθCS RθSA Ambient 130 Junction to Case – RθJC T= PD( RθJC + RθCS + RθSA) + TA Typical Transistor in a TO220 Package 131 Case to Sink – RθCS T= PD( RθJC + RθCS + RθSA) + TA 132 Sink to Ambient – RθJC T= PD( RθJC + RθCS + RθSA) + TA Example Heat Sink 133 Sink to Ambient – RθJC T= PD( RθJC + RθCS + RθSA) + TA Natural Convection is 100 Feet /min 134 Detailed Analysis So Far 1. Breakdown Voltages 2. Ic_max 3. Power / Junction Temperature 4. VBE / Output Swing 5. IB / Op-Amp Drive 135 Output Swing (Consider Vbe) Vout_buffer_max = 5V – 1.4V = 3.6V Disadvantage of the Darlington MMBT6427 Transistor U1 BCX38B 1.4V Darlington 250mA 136 Output Swing (Consider Vbe over Temperature) Typical ΔVbe = -2mV/oC At -25oC ΔVbe = (-2mV/oC)(T – Troom) ΔVbe = (-2mV/oC)(-25oC – 25oC) = 0.1V Vbe = 1.4V + 0.1V = 1.5V At 85C Vbe = 1.4V - 0.12V = 1.28V 137 What’s the Real Output Swing? What’s the Real Max Current Out? Iout_max Estimate: MMBT6427 Transistor Iout_max = Vout/RL = 5/20 = 250mA 1.4V From the Graph: Vbe = 1.4V 1.37V Refine Iout_max: Iout_max = (Vout – Vbe)/RL = (5 -1.4)/20 = 180mA Refine Vbe: Vbe = 1.37V 250mA 180mA 138 Is the Base Current Okay? MMBT6427 Transistor Worst Case hfe = 2.7k Ib_max = Ic_max / hfe_min Ib_max = 250mA / 2700 = 92.5uA (no problem) 139 Summary of Buffer Design Using Bipolar Transistor Spec. Design Worst Case Transistor Data Sheet Rating Comment Max Current 250mA 500mA Max Vbe 1.5V Limits the buffer output swing to 3.5V Max Ambient Temperature 87.5C Determined using power dissipation and the thermal model. Ib – Max Base Current 92.5uA Vce 5V 40V Vcb 5 40V 140 Bipolar Junction Transistor (BJT) T2 TIP29C Collector ib + rb’ vin Base NPN iout = hfe x ib - T18 !PNP Emitter Collector Base PNP Emitter 141 What T7 IRFD110 about design using Power MOSFETS? Drain Gate vin rin iout = gm x vin N-Channel T16 2N6804 Source Drain Gate P-Channel Source 142 Power MOSFET vs Power BJT Power MOSFET Power BJT • Voltage to Current device • Current to Current I device – no gate current – base current significant • Vgs depends on transistor and Id • Vbe = 0.7V for standard • Vgs typically ranges 2V to 10V • Vbe = 1.4V for Darlington Design process for MOSFET similar to BJT 143 Current Sources Design Example Two Different Topologies Traditional Floating Load Inverted Transistor Floating Load 1. Easy To Stabilize 1. More Difficult to Stabilize 2. Headroom Limited by VBE (VGS) 2. More headroom than “Traditional” 3. Bandwidth Limited By Load 3. Wider Bandwidth than “Traditional” 144 Standard Floating Load Current Source with BJT Current Boost Rf 100 Vin = VG1*1k/(1k+9k) Vin = 0.1VG1 V2 25 V1 5 U1 OPA277 R5 9k + R3 50 U2 BD679 + VG1 R6 1k + R1 1k V2 25 RL 15 LOAD Vrsen = Vin Aol = Vout/Vf b 1/Beta = Vtest/Vf b AolBeta = Vout/Vtest I_load = Vrsen/Rsen + Vrsen - Rsen 330m LL 150m Sense Resistor 145 Traditional Floating Load Current Source DC Analysis Rf 100 Series Resistor Limits Base Current and Isolates Op-Amp From Capacitance. Asymmetrical supplies Increased output swing → faster di/dt V2 25 V1 5 U1 OPA277 R5 9k + R3 50 U2 BD679 + V2 25 RL 15 LOAD LL 150m Aol = Vout/Vf b 1/Beta = Vtest/Vf b AolBeta = Vout/Vtest + Vrsen - Rsen 330m VG1 R6 1k + R1 1k Sense Resistor 146 DC Analysis of Transistor BD675 Spec Design Worst Case Transistor Data sheet Ib max 1.5A/750 = 2mA hfe_min = 750 Op-Amp Swing 25 – 1.0 = 24V 25 – 1.5 = 23.5V Output Swing BJT 24 – 2.4 = 21.6V @125C 23.5 – 2.6 = 20.9V @-25C Iout Max 21.6V/15 = 1.39A 20.9V/15 = 1.39A Pmax (25)2/(4*15)=10.12W Ta max 76.5C (Ta max> 60C) Tj @ Ta=60C =Pd(Rjc + Rjs + Rsa) + Ta Tjmax=150C =10.12W(3.13 + 0.44 + 3.7) + 60 (Using heat sink) =133C 147 @125C @-25C @125C @-25C Icmax=4A --see Tj -- AC Stability Analysis Rf 100 Add in the test circuitry Vfb V2 25 U1 OPA277 + L2 1G U2 BD679 R1 1k V2 25 Vtest RL 15 LL 150m Aol = Vout/Vf b 1/Beta = Vtest/Vf b AolBeta = Vout/Vtest Rsen 330m R6 1 + R3 50 + R5 9 Vtest Vout V1 5 C2 1G Short out the signal source 148 Before Tina SPICE →Do a Hand Analysis R7 100 This section is a simple buffer V2 25 Vtest Vfb R3 50 C2 1G U2 BD679 + Find 1/β by looking at the feedback path. R1 1k Vtest R4 15 1/ β = Vtest/Vfb Aol = Vout/Vf b 1/Beta = Vtest/Vf b AolBeta = Vout/Vtest R2 330m L1 150m 149 Before Tina SPICE → Do a Hand Analysis Rf 100 Vfb Rsen Vt est Rsen + RL + j XL XL 2f LL Replace the buffer with a wire, and analyze as a series circuit. Solving for Beta Vfb Rsen + RL Vfb j 2f LL) +1 Rsen + RL + Vt est C2 1G Vtest Rsen Vtest This has a pole f or or a zero for 1/ Rsen + RL f LL 150m 1 RL + Rsen 15 + 0.33 2 LL 2 ( 0.15) Aol = Vout/Vf b 1/Beta = Vtest/Vf b AolBeta = Vout/Vtest Rsen 330m 2f LL) RL 15 16.27Hz 150 fb t est R sen + RL + j XL Hand Analysis of β (1/β) High and Low Frequency XL 2f LL Extremes At high frequencys Solving for Beta Vfb Vt est β Transfer Function =0 Rsen So 1/ = at high frequency s At low f requencys So 1/ = RL + Rsen Rsen Vfb Vt est = Rsen + RL Vfb j 2f LL) +1 Rsen + RL Vt est Rsen RL + Rsen This has a pole f or or a zero for 1/ 2f LL) RL + Rsen 1 20 log 20 Log 33.34 Rsen Rsen + RL f 1 RL + Rsen 15 + 0.33 2 LL 2 ( 0.15) 151 16.27 Hz Using Information from the Transfer Function 1/β Curve STABLE 33dB 16Hz 20dB/d ec Problem 40dB/dec rate-ofclosure 152 Using Information from the Transfer Function R7 100 Cf 334n Vfb Rd 31.6k V2 25 U1 OPA277 + L2 1G U2 BD679 R1 1k + R6 1 + R3 50 C2 1G R5 9 This circuit’s 1/β plot. Vtest Vout V1 5 - Vtest V2 25 R4 15 L1 150m How will the two feedbacks combine? Aol = Vout/Vf b 1/Beta = Vtest/Vf b AolBeta = Vout/Vtest R2 330m V3 2 Add another feedback path to stabilize the circuit. 153 How will the two feedbacks combine? Large β Answer: The largest β (smallest 1/β) will dominate! Small β - 154 General Example: How would the red and blue curves add? Remember curves shown are 1/β curves, not β curves! 155 General Example: How would the red and blue curves add? Remember that the curves shown are 1/β curves, not β Curves! The combined feedback will follow the smallest 1/β curve (the larges β). 156 How to Select FB#2 to Stabilize the Circuit Set the cut frequency so that there is one decade margin before the intersection of FB#1 and FB#2. 1decade FB#2 1decade Move the FB#2 curve up or down until there is 1 decade margin between the AOL curve and the intersection with the FB#1 curve. 157 How to Select FB#2 to Stabilize the Circuit FB#2 Stable The combination of FB#1 and FB#2 has a 20dB/decade rate-ofclosure. 158 How to Separate the Two Paths Rf 100 Cf 17.8n Rd 178k Break the FB#1 path here! + C2 1G Vtest Vfb Vtest RL 15 Aol = Vout/Vf b 1/Beta = Vtest/Vf b AolBeta = Vout/Vtest Rsen 330m LL 150m 159 Solve for β Rf 100 Cf 17.8n Rd 178k Feedback #2: Just using a simple voltage devider rule Vfb Rf + Rsen ) V Rf + Rsen ) + Rd + j Xcf ) t est 1 2 f Cf j 2 f Cf Vfb Vt est + Rf + Rsen + Rd Vtest ) Rf + Rsen ) j 2 f Cf) 1 + Rf + Rsen + Rd ) j 2 f Cf) RL 15 β LL 150m Aol = Vout/Vf b 1/Beta = Vtest/Vf b AolBeta = Vout/Vtest Rsen 330m 1 + Rf + Rsen ) Vfb Vt est C2 1G Xcf Vtest Vfb 160 Plot for 1/β Vfb Vt est Rf + Rsen ) j 2 f Cf) 1 + Rf + Rsen + Rd ) j 2 f Cf) cut f req at f Rf + Rsen + Rd) 2 f Cf) 1 2 Cf Rf + Rsen + Rd at low f requency at high f req Vfb Vt est ) 1 Vfb Vt est = 1 =0 Rf + Rsen ) Rf + Rsen + Rd) -> at low f req. Rf + Rsen + Rd -> 20 log Rf + Rsen 1 at high f req. 161 Values Required for this Example f = 15Hz, High Freq 1/β = 50dB 1decade FB#2 f = 15Hz High freq 1decade 1/β = 50dB 162 Using f = 15Hz, High Freq 1/β = 50dB Solve for Rd and Cf Selecting Components for Stability Ndb Rf + Rsen + Rd 20 log Rf + Rsen Rd Ndb 20 Rf + Rsen ) 10 − Rf − Rsen Rd 50 20 ( 100 + 0.33) 10 − 100 − 0.33 31.6kW Cf = 1 2 f Rf + Rsen + Rd ) −9 Cf = 308.403 10 163 Verify Stability Using Tina-SPICE Plenty of phase margin Worst Case 45o 164 Look at Transient Response Using Tina-SPICE R7 100 Cf 334n Rd 31.6k V1 5 U1 OPA277 R5 9 + V2 25 Vopa R3 50 + V + U2 BD679 V2 25 R4 15 L1 150m + A Ic R2 330m R6 1 + R1 1k Vtest Vce 165 Look at Transient Response Using Tina-SPICE T 636.39m Ic 575.79m 21.16 Vce 10.26 16.40 Vopa 5.51 2.10 Vtest 1.90 0.00 50.00m 100.00m Time (s) 150.00m 200.00m 166 The AC Transfer Function Using Tina-SPICE -3dB Mag(Iout/Vin) Phase(Iout/Vin) -45o 167 Current Sources Design Example Two Different Topologies Traditional Floating Load Inverted Transistor Floating Load 1. Easy To Stabilize 1. More Difficult to Stabilize 2. Headroom Limited by VBE (VGS) 2. More headroom then “Traditional” 3. Bandwidth Limited By Load 3. Wider Bandwidth then “Traditional” Done with the traditional floating load Lets look at the inverted topology. 168 Inverted Transistor Floating Load DC Analysis V2 25 Z1 1N2808 Gate U1 OPA277 V1 5 Source R5 9k V3 2 + R1 5k + + T1 IRF9130 V Vds Vopa Vsource R6 1k + - Drain V2 25 L1 150m R4 15 R2 330m Vsense Common source configuration. + A Vgs does not effect headroom. Iout R7 1k 169 Inverted Transistor Floating Load DC Analysis Z1 1N2808 V2 25 U1 OPA277 V1 5 R5 9k + + T1 IRF9130 V Vds V2 25 R4 15 L1 150m Resistor Isolates Op-Amp from Gate Capacitance Zener protects gate from over voltage. Vsense R2 330m V3 2 + R1 5k Vopa Vsource R6 1k + - + A Iout R7 1k 170 Vtest U1 OPA277 Z1 1N2808 Inverted Transistor Floating Load AC Analysis V1 5 R5 9k - R1 5k T1 IRF9130 + C1 1G Vout V3 3 + R6 1k + L2 1G V2 25 R4 15 VG1 Add test circuit VFB1 L1 150m V2 25 + A AM1 R7 1k Loop Gain = Vout/Vtes t Aol = Vout/Vf b F B#1 = Vtest/VF B1 F B#2 = Vtest/VF B2 1/Beta = Vtest/Vf b R2 330m DC Bias Required for proper functionality 171 Stability Analysis of Inverted Transistor Floating Load Circuit with No Compensation T 120.00 loop_gain 100.00 80.00 one_over_beta Gain (dB) 60.00 aol 40.00 20.00 0.00 Note the Complex Conjugate zero (180o phase shift). -20.00 -40.00 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) 60dB Rate of Closure 180.00 loop_gain Phase [deg] 90.00 0.00 -90.00 -180.00 1 10 100 1k 10k Frequency (Hz) 100k 1M 10M 172 Loop Gain = Vout/Vtes t Aol = Vout/Vf b F B#1 = Vtest/VF B1 F B#2 = Vtest/VF B2 1/Beta = Vtest/Vf b Vtest U1 OPA277 Z1 1N2808 Add a Zero into Feedback Path V1 5 R5 9k + Vfb R1 5k T1 IRF9130 C1 1G + V L2 1G C1 330n + Vout V3 3 R6 1k + V2 25 VFB1 R1 5k R4 15 VG1 L1 150m V2 25 + A C2 330n AM1 Cin R2 330m R7 1k C1 1u MOSFET 173 Add a Zero into Feedback Path 80.00 U1 OPA277 V1 5 one_over_beta R5 9k V3 3 + + V L2 1G + Vfb Vout 20.00 - T1 IRF9130 C1 330n + 0.00 V2 25 R1 5k C1 1G aol 40.00 R6 1k Gain (dB) 60.00 loop_gain Z1 1N2808 100.00 Vtest Loop Gain = Vout/Vtes t Aol = Vout/Vf b F B#1 = Vtest/VF B1 F B#2 = Vtest/VF B2 1/Beta = Vtest/Vf b T 120.00 V2 25 -20.00 R4 15 VG1 1 10 100 1k 10k 100k 1M Frequency (Hz) VFB1 180.00 L1 150m -40.00 10M + loop_gain A Select f=100Hz so that the zero occurs before the complex conjugate. AM1 R7 1k R2 330m Phase [deg] 90.00 0.00 C -90.00 1 2 f R 1 330nF 2 ( 100Hz) 500kW ) -180.00 1 10 100 1k 10k Frequency (Hz) 100k 1M 10M 174 AC Stability Result Zero In Feedback T 120.00 100.00 aol 80.00 Gain (dB) 60.00 loop_gain 40.00 one_over_beta 20.00 0.00 -20.00 -40.00 Note: The complex conjugate zero is gone. 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) 180.00 Loop Gain=0 loop_gain Phase [deg] Phase margin < 0 0.00 -180.00 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) 175 Use another Feedback Path FB#2 will dominate at high frequencies T 120.00 100.00 aol 80.00 Gain (dB) 60.00 loop_gain 40.00 one_over_beta 20.00 FB#2 0.00 -20.00 -40.00 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) 176 180.00 loop_gain Use another Feedback Path Cf 180n Vtest U1 OPA277 Z1 1N2808 VFB2 Loop Gain = Vout/Vtes t Aol = Vout/Vf b F B#1 = Vtest/VF B1 F B#2 = Vtest/VF B2 1/Beta = Vtest/Vf b V1 5 R5 9k + Vfb R1 5k T1 IRF9130 C1 1G + V L2 1G C2 330n + Vout V3 3 R6 1k + V2 25 V2 25 VG1 L1 150m R4 15 VFB1 20dB/dec 0dB R2 330m R7 1k 177 Hand Calculations for New Feedback Path Cf 180n VFB2 R6 1k R5 9k V3 3 Req R5 || R6 Vfb Req Vt est Req + XC Vtest Loop Gain = Vout/Vtes t Aol = Vout/Vf b F B#1 = Vtest/VF B1 F B#2 = Vtest/VF B2 1/Beta = Vtest/Vf b Vfb Vt est β Req Req + 1 j 2 f C Vfb j 2 f C Req Vt est j 2 f C Req + 1 178 Hand Calculations for New Feedback Path Vfb j 2 f C Req Vt est j 2 f C Req + 1 fc = 1kHz 1 Vt est Vfb 1 Vt est Vfb f -> at low freq -> 1 at high f req (0dB) 1 2 Req C 20dB/dec In this example 0dB the cut f requency 179 Hand Calculations for New Feedback Path Req C 1kW )|| 10kW ) 1 0.9kW We want to set the cut frequency at about 1kHz 1 2 Req f 176nF 2 0.9kW ) ( 1kHz) T 120.00 100.00 aol 80.00 Gain (dB) 60.00 loop_gain 40.00 one_over_beta 20.00 FB#2 0.00 -20.00 -40.00 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) 180 180.00 loop_gain Final Compensation: Look at AC Stability Cf 180n U1 OPA277 Z1 1N2808 VFB2 Vtest V1 5 R5 9k + Vfb R1 5k T1 IRF9130 C1 1G + V L2 1G C2 330n + Vout V2 25 VG1 R4 15 L1 150m V3 3 R6 1k + V2 25 VFB1 R7 1k R2 330m Loop Gain = Vout/Vtes t Aol = Vout/Vf b F B#1 = Vtest/VF B1 F B#2 = Vtest/VF B2 1/Beta = Vtest/Vf b 181 Final Compensation: Look at AC Stability T 120.00 Gain (dB) aol one_over_beta_fb2 one_over_beta_fb1 40.00 The composite 1/β is relatively flat for all significant loop gain. one_over_beta -40.00 1 10 100 1k 10k 100k 1M 10M 10k 100k 1M 10M Frequency (Hz) 180.00 135.00 Phase [deg] loop_gain Plenty of phase margin (65deg) 90.00 45.00 0.00 1 10 100 1k Frequency (Hz) 182 Final Compensation: Look at Transient C3 180n U1 OPA277 V1 5 C1 330n Z1 1N2808 V2 25 R5 9k - V Vds Vout V2 25 R4 15 + Vload L1 150m V + A AM1 R7 1k R2 330m V3 2 T1 IRF9130 Vopa Vsource + + R6 1k + + R1 5k Vsense 183 Final Compensation: Look at Transient T 638.26m AM1 574.59m 34.00 Vds 431.20m 24.37 Vload -9.20 20.80 Vopa 20.78 24.57 Vout -9.00 210.63m Vsense 189.62m 100.00m Vsource -100.00m 0.00 50.00m 100.00m Time (s) 150.00m 200.00m 184 The AC Transfer Function Using Tina-SPICE Gain I out V in 185 Current Sources Design Example Summary Traditional Floating Load Inverted Transistor Floating Load 1. Easy To Stabilize 1. More Difficult to Stabilize 2. Headroom Limited by VBE (VGS) 2. More headroom then “Traditional” 3. Bandwidth Limited By Load 3. Wider Bandwidth then “Traditional” For the example: For the example: Vout Swing Max = 20.9V Vout Swing Max = 24.65V Bandwidth = 100Hz Bandwidth = 800Hz (Bandwidth is maximized) (This could be compensated for wider bandwidth) 186 High Power V-I Circuit Applications ➢ Power Packages ➢ ➢ ➢ ➢ ➢ Parallel Outputs for Higher Current V-I Using External Shunt V-I Using Internal Shunt (Burr-Brown Exclusive) Bridge Tied Load Constant Current PWM Driver 187 OPA548 OPA548 OPA569 TO-220-7 DDPAK-7 HSOP-20 DRV104 SO-14 OPA549 ZIP-11 DRV103 SO-8 3584 TO-3 (History) OPA561 HTSSOP-20 Power Operational Amplifier Packages OPA567 QFN-12 5x5mm OPA564 HSOP-20 Top Pwr Pad 188 Power Operational Amplifier Packages OPA569 SSOP 20-pin QFN-28-pin Chip Cap SON-8-pin OPA567 QFN 12-pin 189 Power Amplifier OPA567, 569, 561 & DRV103, 104 Adapter Boards Available From Tucson OPA567 OPA569 190 Power Op Amps Paralleling Outputs for More Drive Current 191 OPA548 Power Op Amp Application Paralleling for More Output Current +8V to 60V Total Supply NOTES: (1) Works well for G < 10. Input offset causes output current to flow between amplifiers with G > 10. Gains (resistor ratios) of the two amplifiers should be carefully matched to ensure equal current sharing. (2) As configured (ILIM connected to V–) output current limit is set to 10A (peak). Each amplifier is limited to 5A (peak). Other current limit values may be obtained, see Figure 3, “Adjustable Current Limit”. 3A cont 6A continuous 3A cont Output Swing to Rail Spec with 3A Load (V+) – 4.1V (V–) + 3.7V 192 OPA569 Power Op Amp Application Paralleling for More Output Current +2.7V to 5.5V Total Supply 2A cont Vos is Averaged and BW, SR are That of One Amplifier 2A cont 4A continuous Output Swing to Rail with 2A Load (V+) – 0.3V (V–) + 0.3V 193 Power Op Amps Bridge Tied Load for Floating Output 194 OPA549 Power Op Amp Application Bridge => 2x Voltage & 4x Power Out High Power TEC, up to 8A Neil Albaugh Circuit Simulation +24V 5V +24V VTEC = 14V 5V Physical Contact With a Circuit Output Swing to Rail with 8A Load Won’t Swing Very Close to Supply Rail but Drives 8A Out (V+) – 4.8V (V–) + 4.6V 195 OPA569 Power Op Amp Application Bridge => 2x Voltage & 4x Power Out High Power TEC, up to 2A Can be 3V 300mV Physical Contact With a Circuit Can be 3V Usually +2.5V Output Needs to Swing Close to Supply Rail Only IC in Industry That Does This!!! 196 Designing Power Current Sources Feedback using External Shunt Resistor 197 OPA541 Power Op Amp Application Howland Power Current Source Rtrim 1Ω RS 1Ω Transfer Function 500mA out per 10V in I VRL = 50mA per Volt 198 OPA541 Power Op Amp Application Howland Power Current Source Transfer Function 600mA out per 10V in = 60mA per Volt 199 OPA541 Power Op Amp Application Howland Power Current Source 200 OPA569 Power Op Amp Application -5V Single Supply with +Vin Constant Current Using Ext ISHUNT Feedback Grounded Anode 201 OPA569 Power Op Amp Application -5V Single Supply with +Vin Grounded Anode LED Driver Scope Photo Plus Voltage +1V 0V 0V Minus Voltage LED Off LED On -1.25V 0V -2. 25V 202 OPA569 Power Op Amp Application -5V Single Supply with +Vin Grounded Anode LED Driver Scope Photo Plus Voltage +1V 0V 0V LED Off Minus Voltage 50sec Fall -1.25V 0V LED On 40sec Fall -2. 25V 203 OPA569 Power Op Amp Application -5V Single Supply with +Vin Grounded Anode LED Driver Scope Photo Plus Voltage +1V 0V 0V LED On 100sec Rise Minus Voltage LED Off -1.25V 15msec Rise Slow -2. 25V 0V 204 OPA569 Power Op Amp Application -5V Single Supply with +Vin Grounded Anode LED Driver Scope Photo Plus Voltage +1V 0V 0V 12sec Fall Minus Voltage LED Off -1.25V 12sec Fall -2. 25V 0V LED On 205 OPA569 Power Op Amp Application -5V Single Supply with +Vin Grounded Anode LED Driver Scope Photo Plus Voltage +1V 0V 0V 12sec Rise Minus Voltage LED Off LED On 1.5msec Rise Slow -1.25V 0V -2. 25V 206 OPA569 Power Op Amp Application -5V Single Supply with +Vin Grounded Anode LED Driver Scope Photo Plus Voltage +1V 0V 0V Minus Voltage -1.25V 0V LED Off -2.25V LED On 207 Designing Power Current Sources Feedback using Internal Current Monitor (Instead of External Shunt Resistor) 208 OPA569 Power Op Amp Application 2.5V Bipolar Supplies with -Vin Constant Current Using IMONITOR Feedback Vin+2.5V -2.5V Feedback Through IMONTIOR 4.2kW R1 Io is Independent of changes in Rload (LED aging). +2.5V 12 13 Iin = 2.5V / 4.2kW = 0.6mA 9 - 14 15 OPA569 Io = Iin x 475 6 Io = (Vin / Rin) x 475 = 285mA 5 IMONTIOR = (1/475 x Io) 3 + 17 18 -2.5V Io Constant Current Vo pin RSET 33kW 350mA Grounded Cathode +2.5V -2.5V Luxeon Star-0 High Power LED on Heat Sink 209 OPA569 Power Op Amp Application 2.5V Bipolar Supplies with -Vin Grounded Cathode LED Driver Scope Photo +2.5V -2.5V +2.5V -2.5V +2.5V LED Off LED On -2.5V 210 OPA569 Power Op Amp Application 2.5V Bipolar Supplies with -Vin Grounded Cathode LED Driver Scope Photo +2.5V -2.5V +2.5V -2.5V LED On LED Off +2.5V -2.5V 211 OPA569 Power Op Amp Application +5V Single Supply with +Vin Constant Current Using IMONITOR Feedback Vin+5V 0V 4.2kW Feedback Through IMONTIOR 1,500pF R1 +5V 5 +2.5V = 285mA 10kW 14 15 OPA569 10kW 6 9 - 3 + +5V VLED +2.5V 0V 12 13 Io = Iin x 475 Io = (Vin / Rin) x 475 IMONTIOR = (1/475 x Io) +5V Iin = +2.5V / 4.2kW = +0.6mA Io is Independent of changes in Rload (LED aging) and +5V. 17 18 Use REF3025 to make independent of +5V. Io Constant Current Vo pin RSET 33kW 350mA Vout +2.5V 0V Luxeon Star-0 High Power LED on Heat Sink +5V to Anode 212 OPA569 Power Op Amp Application +5V Single Supply with +Vin +5V to Anode LED Driver Scope Photo +5V 0V +5V +2.5V LED Off 0V +5V +2.5V LED On 0V 213 OPA569 Power Op Amp Application +5V Single Supply with +Vin +5V to Anode LED Driver Scope Photo +5V 0V +5V +2.5V LED Off 0V +5V +2.5V LED On 0V 214 OPA569 Power Op Amp Application +5V Single Supply with +Vin +5V to Anode LED Driver Scope Photo +5V 25sec Fall 0V +5V +2.5V LED Off 15sec Fall 0V +5V +2.5V 35sec LED On Delay Charging Internal Gate Cap 0V 215 OPA569 Power Op Amp Application +5V Single Supply with +Vin +5V to Anode LED Driver Scope Photo +5V 4sec Rise 0V +5V +2.5V LED Off 5sec Rise 0V +5V +2.5V LED On 0V 216 OPA569 Power Op Amp Application +5V Single Supply with +Vin +5V to Anode LED Driver Scope Photo +5V 0V +5V +2.5V 0V +5V LED Off +3.6V +2.5V LED On 0V 217 OPA569 Power Op Amp Application +5V Single Supply with +Vin +5V to Anode LED Driver Scope Photo +5V 0V +5V +2.5V 0V +5V LED Off +3.6V +2.5V LED On 0V 218 OPA569 Power Op Amp Application +5V Single Supply with +Vin +5V to Anode LED Driver Scope Photo +5V +2.5V 0V +5V +2.5V 0V LED Off LED On +3.6V +2.5V 0V 219 OPA569 Power Op Amp Application +5V Single Supply with +Vin Constant Current Using IMONITOR Feedback Feedback Through IMONTIOR 1,500pF 4.2kW +0.25V R1 IMONTIOR = (1/475 x Io) +5V 12 13 Iin = +2.5V / 4.2kW = +0.6mA 5 Io = Iin x 475 9 - 14 15 OPA569 Io = (Vin / Rin) x 475 = 285mA Io is Independent of changes in Rload (LED aging) and +5V. Vin+ +2.75V +0.25V 6 Vo pin 3 + 17 18 Io Constant Current RSET 33kW 350mA +0.25V offset is used to maintain min voltage on IMONITOR Current Source Grounded Cathode Vout +2.5V 0V Luxeon Star-0 High Power LED on Heat Sink 220 OPA569 Power Op Amp Application +5V Single Supply with +Vin Grounded Cathode LED Driver Scope Photo +5V +2.5V 0V +2.8V 0V LED On LED Off +2.5V 0V 221 OPA569 Power Op Amp Application +5V Single Supply with +Vin Grounded Cathode LED Driver Scope Photo +5V +2.5V 0V +2.8V 0V LED On +2.5V LED Off 0V 222 OPA569 Power Op Amp Application +5V Single Supply with +Vin Scope Capture Grounded Cathode LED Driver LED On Oscillation (333kHz, 0.64Vp-p), Cf = 0 pF 0.64Vp-p Loop Instability LED Off 3us per cycle => 333kHz 0V +2.5V Clean (small overshoot), Cf = 1,500pF Very Clean, Cf = 33,000pF +2.5V Stable 0V V: 0.2V / small div T: 0.5us / small div Stable +2.5V 0V 223 OPA569 Power Op Amp Application +5V Single Supply with +Vin Grounded Cathode LED Driver Scope Photo +5V +2.5V 0V +2.8V 5sec Fall 0V LED On 5sec Fall +2.5V LED Off 0V 224 OPA569 Power Op Amp Application +5V Single Supply with +Vin Grounded Cathode LED Driver Scope Photo +5V +2.5V 0V +2.8V 12sec Rise 0V 12sec Delay Charging Internal Gate Cap LED Off LED On 12sec Rise +2.5V 0V 225 OPA569 Power Op Amp Application +5V Single Supply with +Vin Grounded Cathode LED Driver Scope Photo +5V +2.5V 0V +2.8V 0V LED On +2.5V LED Off 0V 226 OPA569 Power Op Amp Application +5V Single Supply with +Vin Grounded Cathode LED Driver Scope Photo +5V +2.5V 0V +2.8V 0V LED On +2.5V LED Off 0V 227 Designing Power Current Sources Feedback using Internal Current Monitor (Instead of External Shunt Resistor) 228 OPA569 Power Op Amp Application +5V Single Supply, Current Source Tina Simulation Power Current Source, Single Output (Voltage Controlled Current Source) Vpedistal Voffsetting 2.5 V+ John Brown 9/3/2005 Rset = 9800 (1.18 / Ilimit) = 33k ohms for 0.35A Limit Imonitor = 1/475 x Iout V+ 5 NS NS1 NS Cf1 0 Iin = +2.5V peak / 4.2k ohms = +0.6mA peak Ilimit = 350mA Iout = Iin x 475 = 285mA NS1 Vout NS or Node Sets (NS1 & NS2) at +0.25V Are Needed To Make Simulator Converge to an Operating Point. R4 33k Transfer function = 110mA out / 1V in Rin 4.2k Iset - Imon Iflag Iout Am Iout = 0A to 0.35A Rseries 0 Vload Voffsetting 250m + + Tflag En RL 1G +2.75V +0.25V + +0.25V offset is used to maintain min voltage on Imonitor Current Source CL 0 LED1 CQX35A U1 OPA569 Rled around 7 ohms Vin Rseries Is Not Needed With Current Source Drive. V+ Rlim 46.2k 23.2k 11.5k 7.68k 5.76k 5.26k Iout 0.25A 0.5A 1.0A 1.5A 2.0A 2.2A That is: Unless Independent Protection is Needed In Case of Amplifier Failure (e.g. +5V out), Although Ilimit Set Will Protect the Load From Excess Current Drive Anyway. 229 OPA569 Power Op Amp Application +5V Single Supply, Current Source Tina Simulation 230 OPA569 Power Op Amp Application +5V Single Supply, Current Source Tina Simulation 231 OPA569 Power Op Amp Application +5V Single Supply, Current Source Tina Simulation 232 Designing Power Voltage Sources Tina Simulations Voltage Source Drive 233 OPA569 Power Op Amp Application +5V Single Supply, Voltage Source Tina Simulation Power Voltage Source, Single Output (Voltage Controlled Voltage Source) Vpedistal V+ Imonitor = 1/475 x Iout Cf 0 Rset = 9800 (1.18 / Ilimit) = 33k ohms for 0.35A Limit V+ 5 Rf 10k NS NS1 NS Voffsetting 2.5 John Brown 9/3/2005 NS1 NS or Node Sets (NS1 & NS2) at +0.25V Are Needed To Make Simulator Converge to an Operating Point. Vout Ilimit = 350mA R1 4.75k R4 33k Vmonitor Rin 10k Iset - Imon Iflag Transfer function = 110mA out / 1V in Iout Am Iout = 0A to 0.35A max limit Rseries 10 Vload Rmon = Vmon / Imon Imon = Iout / 475 + + Tflag En RL 1G CL 0 LED1 CQX35A + U1 OPA569 Choose Vmon = 2V, Then Rmon = 2V / (200mA / 475) = 4.75k ohms Rled around 7 ohms Vin +2.5V +0V V+ Rlim 46.2k 23.2k 11.5k 7.68k 5.76k 5.26k Rseries Is Needed With Voltage Source Drive Iout To Limit Voltage Across LED Load. 0.25A 0.5A 1.0A 1.5A 2.0A 2.2A Ilimit Set Will Protect the Load From Excess Current Drive Anyway. 234 OPA569 Power Op Amp Application +5V Single Supply, Voltage Source Tina Simulation 235 OPA569 Power Op Amp Application +5V Single Supply, Voltage Source Tina Simulation 236 Power Op Amps Bridge Tied Load for Floating Output With Constant Current Source 237 OPA551 Power Op Amp Application 24V Single Supply, Current Source 238 OPA551 Power Op Amp Application 24V Single Supply, Current Source 239 OPA551 Power Op Amp Application 24V Single Supply, Current Source 240 OPA551 Power Op Amp Application 24V Single Supply, Current Source 241 OPA725 + Power Transistors Power Op Amp Application 5V Single Supply, Current Source Voltage- Controlled Current Source TEC Driver Neil P. Albaugh TI- Tucson 1 August 2005 V+ VNS1 V+ 5 NS V- 5 NS2 C1 1n V+ NS V+ U4 TIP120 V- R8 50k NS2 NS C2 1n V- U6 TIP120 NS1 R4 200k R7 50k NS - R1 10 R6 200k + AM1 + R2 20m + U1 OPA725 VG1 V+ + U2 OPA725 U5 TIP125 V- + R10 10 Thermoelectric Cooler U3 TIP125 R3 10k - R9 10 RL 1 V+ VNote: R5 10k By pass capacitors not s hown. 242 OPA725 + Power Transistors Power Op Amp Application 5V Single Supply, Current Source 243 OPA725 + Power Transistors Power Op Amp Application 5V Single Supply, Current Source 244 OPA569 Power Op Amp Application +5V Single Supply, Bridge Current Source Resistive Load Tina Simulation R lim Iout Power Current Source, Differential Output 46.2k 0.25A (Voltage Controlled Dual Current Source) 23.2k 0.5A John Brown 8/31/2005 11.5k 7.68k 5.76k 5.26k Imonitor = 1/475 x Iout Vpedistal V+ Transfer function = 2V / A R2 10k Cf1 0 Voffsetting 2.5 Cf2 0 V+ 5 2A Lim Vout1 R4 5.76k 1.0A 1.5A 2.0A 2.2A R1 10k Vout2 2.2A Lim R6 4.6k Rin 475 Iset Imon Iflag Iout Iflag Imon Iset - RL 2.2 + - U1 OPA569 Vpedistal Vpedistal 2.5 V+ Cdiff 0 Tflag Tflag C2 0 En C1 0 + + Vin En + + Vpedistal U2 OPA569 V+ Rset = 9800 (1.18 / Ilimit) 245 OPA569 Power Op Amp Application +5V Single Supply, Bridge Current Source Resistive Load Tina Simulation 246 OPA569 Power Op Amp Application +5V Single Supply, Bridge Current Source Resistive Load Tina Simulation 247 OPA569 Power Op Amp Application +5V Single Supply, Bridge Current Source Resistive Load Tina Simulation 248 OPA569 Power Op Amp Application +5V Single Supply, Bridge Current Source Resistive Load Tina Simulation 249 OPA569 Power Op Amp Application +5V Single Supply, Bridge Current Source Resistive Load Tina Simulation Swings 0.3V to Each Rail Vout1 = +5V - 0.3V = +4.7V max swing Vout2 = +5V - 0.3V = +4.7V max swing (Vout1 - Vout2) = 4.4V max swing Rload min = 4.4V / 2A = 2.2 ohms Output Current and Voltage Iin = Vin / Rin Iout = Iin x 475 = (Vin / Rin) x 475 Vout = [Iout] x (RL) = [(Vin / 475 ohms) x 475] x (RL) Transfer Function: Iout / Vin = [(Vin / Rin) x 475] / Vin = (1 / Rin) x 475 = 1A out / 1V in Example of max Output Current and Voltage Iout = Iin x 475 = (2V / 475 ohms) x 475 A/A = 2A max Vout1 = (Vpedistad + delta V) = (2.5V) + {Iout x RL/2 = [(2V / 475 ohms) x 475 A/A] x (1.1 ohms)} = 2.5V + 2.35V = 4.7V out Vout2 = (Vpedistad - delta V) = (2.5V) -Iout x RL/2 = [(2V / 475 ohms) x 475 A/A] x (1.1 ohms) = 0.3V out Vout1 - Vout2 = 4.7V - 0.3V = 4.4V 250 OPA569 Power Op Amp Application +5V Single Supply, Bridge Current Source Inductive Load Tina Simulation R lim Iout Power Current Source, Differential Output 46.2k 0.25A (Voltage Controlled Dual Current Source) 23.2k 0.5A John Brown 8/31/2005 11.5k 7.68k 5.76k 5.26k Imonitor = 1/475 x Iout Vpedistal V+ Transfer function = 2V / A R2 10k Cf1 1n Voffsetting 2.5 Cf2 1n V+ 5 2A Lim Vout1 R4 5.76k 1.0A 1.5A 2.0A 2.2A R1 10k Vout2 2.2A Lim R6 4.6k Rin 475 Iset Imon Iflag Iout Iflag RL 2.2 Imon Iset - L1 100u + - U1 OPA569 Vpedistal Vpedistal 2.5 V+ Cdiff 0 Tflag Tflag C2 0 En C1 0 + + Vin En + + Vpedistal U2 OPA569 V+ 251 OPA569 Power Op Amp Application +5V Single Supply, Bridge Current Source Inductive Load Tina Simulation 252 OPA569 Power Op Amp Application +5V Single Supply, Bridge Current Source Inductive Load Tina Simulation Swings 0.3V to Each Rail Vout1 = +5V - 0.3V = +4.7V max swing Vout2 = +5V - 0.3V = +4.7V max swing (Vout1 - Vout2) = 4.4V max swing Rload min = 4.4V / 2A = 2.2 ohms Output Current and Voltage Iin = Vin / Rin Iout = Iin x 475 = (Vin / Rin) x 475 Vout = [Iout] x (RL) = [(Vin / 475 ohms) x 475] x (RL) Transfer Function: Iout / Vin = [(Vin / Rin) x 475] / Vin = (1 / Rin) x 475 = 1A out / 1V in Example of max Output Current and Voltage Iout = Iin x 475 = (2V / 475 ohms) x 475 A/A = 2A max Vout1 = (Vpedistad + delta V) = (2.5V) + {Iout x RL/2 = [(2V / 475 ohms) x 475 A/A] x (1.1 ohms)} = 2.5V + 2.35V = 4.7V out Vout2 = (Vpedistad - delta V) = (2.5V) -Iout x RL/2 = [(2V / 475 ohms) x 475 A/A] x (1.1 ohms) = 0.3V out Vout1 - Vout2 = 4.7V - 0.3V = 4.4V 253 DRV103 / DRV104 Low or Hi PWM Drivers PWM Constant Output Current Application 254 DRV103 Constant Current PWM Driver Up to 3A Out SO-8 PowerPad DMOS Power Transistor 8V-40V 0.1Ω Vref Osc Input Low-side Switch 5 INA139 Load 5.2Ω 9mH - DRV103 + 6 5V PWM 8 10K Delay 2.2nF 100K 2 NC 191K 3 1 4 OPA340 5V + V 2.2nF 100K Iset 1A/V 255 DRV103 Constant Current PWM Driver Iset = 0.8V DRV103 0.835 I-load(A) 0.83 0.825 Iavg 0.82 0.815 0.81 8 12 16 20 24 28 32 36 Vsup(V) 256 DRV104 Constant Current PWM Driver Up to 1.5A peak SO-8 PowerPad DMOS Power Transistor 8V-32V 10 8,9 INA139 Vref Input - HighOsc side Switch 5V 5 470pF PWM 10K Delay 2.2nF 6,7 2 NC 191K 3 1 + DRV104 14 0.2Ω 11 Load 5.2Ω 9mH 100K 5V + V 2.2nF 100K Iset 0.5A/V OPA340 257 DRV104 Constant Current PWM Driver I_Load(A) Iset = 1.6V DRV104 0.815 0.814 0.813 0.812 0.811 0.81 0.809 0.808 0.807 Iavg 8 12 16 20 24 28 32 Vsup(V) 258 The End… Or Just the Beginning of High Current V-I Circuits? John Brown Tim Green Art Kay Tina SPICE 520-746-7348 520-746-7780 520-746-6072 www.designsoftware.com brown_john@ti.com green_tim@ti.com kay_art@ti.com 259