THE UNIVERSITY OF MELBOURNE
Semester 1 Assessment, 2021
Department of Electrical and Electronic Engineering
ELEN30014 Analog and Digital Electronics Concepts
Writing time: 180 minutes
Reading time: 15 minutes
Scanning and submission time: 30 minutes
TOTAL time: 225 minutes
This paper has 9 pages
Authorised materials:
This is an open book, hand-written exam and the following materials are permitted:
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Any material loaded onto Canvas as part of the subject content.
Notes (printed, hand-written and digital/electronic).
Online books and materials .
Language dictionaries.
Calculators (any model), computers, electronic tablets, pens, rulers, etc.
Instructions to students:
• Attempt ALL questions.
• The questions carry weight in proportion to the marks in brackets after the question numbers.
These marks total 100 marks.
• All answers on this exam must be handwritten (whether using pen and paper or a tablet).
• All working must be scanned and submitted to Gradescope before the end of the exam time.
Ensure your student number is written on each answer page that you upload.
• Submission time is reserved for scanning and uploading. It is your responsibility to submit
within the allocated submission time and late submissions will attract a penalty. If you have
difficulties in submitting your answers, inform your Subject Coordinator immediately.
• Any updates to the exam will be made via Canvas announcements during the examination
time.
• Collusion is not allowed under any circumstances. Collusion includes, but is not limited
to, talking to, phoning, emailing, texting or using the internet to communicate with other
students. Similarly, you cannot communicate with any other person via any means about the
content of this exam during the examination time. If another student contacts you during the
examination period, please inform the subject coordinator immediately.
• Plagiarism, through the use of sources without proper acknowledgement or referencing, is not
permitted and can attract serious penalties. Plagiarism includes copying and pasting from the
Internet without clear acknowledgement and paraphrasing or presenting someone else’s work as
your own. Note that this definition also applies to work completed during the semester as part
of a group. All responses to this exam paper must be entirely your own work, unless otherwise
acknowledged.
ELEN30014 Analog and Digital Electronics Concepts, Semester 1 Assessment, 2021
Question 1 (10 marks)
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5⌦
t=0
5⌦
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+
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5⌦
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20 V
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+
=
i(t)
0.04 F
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vc (t)
1H
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=
+
<latexit sha1_base64="1pAhOsp+iR+0ugLYK9j3lvNeboM=">AAAB6XicbVBNS8NAEJ3Ur1q/qh69LBahp5JUUY8FLx6r2FpoQ9lsN+3SzSbsToQS+g+8eFDEq//Im//GbZuDtj4YeLw3w8y8IJHCoOt+O4W19Y3NreJ2aWd3b/+gfHjUNnGqGW+xWMa6E1DDpVC8hQIl7ySa0yiQ/DEY38z8xyeujYjVA04S7kd0qEQoGEUr3V+2++WKW3PnIKvEy0kFcjT75a/eIGZpxBUySY3pem6CfkY1Cib5tNRLDU8oG9Mh71qqaMSNn80vnZIzqwxIGGtbCslc/T2R0ciYSRTYzojiyCx7M/E/r5tieO1nQiUpcsUWi8JUEozJ7G0yEJozlBNLKNPC3krYiGrK0IZTsiF4yy+vkna95p3X6ncXlUY1j6MIJ3AKVfDgChpwC01oAYMQnuEV3pyx8+K8Ox+L1oKTzxzDHzifPyMujQQ=</latexit>
6V
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Consider the circuit shown above. The switch in the circuit shown has been closed for a long time
and is opened instantaneously at t = 0 as indicated in the diagram.
(a) [1 mark] Find the voltage across in the capacitor vC (0− ) and the inductor current i(0− ) before
the switch opens.
(b) [2 marks] For t > 0, what type of damping will the circuit exhibit and why?
(c) [7 marks] Find i(t) for t > 0 using ONLY time-domain methods.
Page 2 of 9
ELEN30014 Analog and Digital Electronics Concepts, Semester 1 Assessment, 2021
Question 2 (24 marks)
(a) [6 marks] Consider the circuit shown below, where vc (0− ) = 2V and i(0− ) = 1A.
+ vc (t)
i(t)
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+
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<latexit
1F
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e t u(t) A
1⌦
1⌦
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<latexit sha1_base64="uGqgJhZVojM8FelQXIEKC0i+uzo=">AAAB8XicbVBNSwMxEJ2tX7V+VT16CRahBym7VdBjwYs3K9gP7C4lm2bb0CS7JFmhLP0XXjwo4tV/481/Y9ruQVsfDDzem2FmXphwpo3rfjuFtfWNza3idmlnd2//oHx41NZxqghtkZjHqhtiTTmTtGWY4bSbKIpFyGknHN/M/M4TVZrF8sFMEhoIPJQsYgQbKz16yD/37wQd4n654tbcOdAq8XJSgRzNfvnLH8QkFVQawrHWPc9NTJBhZRjhdFryU00TTMZ4SHuWSiyoDrL5xVN0ZpUBimJlSxo0V39PZFhoPRGh7RTYjPSyNxP/83qpia6DjMkkNVSSxaIo5cjEaPY+GjBFieETSzBRzN6KyAgrTIwNqWRD8JZfXiXtes27qNXvLyuNah5HEU7gFKrgwRU04Baa0AICEp7hFd4c7bw4787HorXg5DPH8AfO5w87uI/m</latexit>
1H
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<latexit sha1_base64="9shEmRavyCHYoXlGMw+54VsUWa4=">AAAB7XicbVDLSgNBEOyNrxhfUY9eFoMQL2E3CnoMePEYwTwgWcLsZDYZMzuzzPQGQsg/ePGgiFf/x5t/4yTZgyYWNBRV3XR3hYngBj3v28ltbG5t7+R3C3v7B4dHxeOTplGppqxBlVC6HRLDBJesgRwFayeakTgUrBWO7uZ+a8y04Uo+4iRhQUwGkkecErRSc9xTZbzsFUtexVvAXSd+RkqQod4rfnX7iqYxk0gFMabjewkGU6KRU8FmhW5qWELoiAxYx1JJYmaC6eLamXthlb4bKW1LortQf09MSWzMJA5tZ0xwaFa9ufif10kxug2mXCYpMkmXi6JUuKjc+etun2tGUUwsIVRze6tLh0QTijaggg3BX315nTSrFf+qUn24LtXKWRx5OINzKIMPN1CDe6hDAyg8wTO8wpujnBfn3flYtuacbOYU/sD5/AH+CY6p</latexit>
vo (t)
<latexit sha1_base64="k9UJx89nUNUoAlR96Xes4Ip7M68=">AAAB+XicbVDJSgNBEK2JW4zbqEcvjUGIoGEmCnqMePEYwSyQjKGn05M06VnorgmEIX/ixYMiXv0Tb/6NneWg0QcFj/eqqKrnJ1JodJwvK7eyura+kd8sbG3v7O7Z+wcNHaeK8TqLZaxaPtVciojXUaDkrURxGvqSN/3h7dRvjrjSIo4ecJxwL6T9SASCUTRS17b5Y3aOE5KW8JR0zshN1y46ZWcG8pe4C1KEBWpd+7PTi1ka8giZpFq3XSdBL6MKBZN8UuikmieUDWmftw2NaMi1l80un5ATo/RIECtTEZKZ+nMio6HW49A3nSHFgV72puJ/XjvF4NrLRJSkyCM2XxSkkmBMpjGQnlCcoRwbQpkS5lbCBlRRhiasggnBXX75L2lUyu5FuXJ/WayWFnHk4QiOoQQuXEEV7qAGdWAwgid4gVcrs56tN+t93pqzFjOH8AvWxzcmopH0</latexit>
<latexit sha1_base64="epvcpLQKggQcO8NxJPcwQsrGXII=">AAAB53icbVBNS8NAEJ3Ur1q/qh69LBahF0signorePHYgrGFNpTNdtKu3WzC7kYopb/AiwcVr/4lb/4bt20O2vpg4PHeDDPzwlRwbVz32ymsrW9sbhW3Szu7e/sH5cOjB51kiqHPEpGodkg1Ci7RN9wIbKcKaRwKbIWj25nfekKleSLvzTjFIKYDySPOqLFS87xXrrg1dw6ySrycVCBHo1f+6vYTlsUoDRNU647npiaYUGU4EzgtdTONKWUjOsCOpZLGqIPJ/NApObNKn0SJsiUNmau/JyY01noch7Yzpmaol72Z+J/XyUx0HUy4TDODki0WRZkgJiGzr0mfK2RGjC2hTHF7K2FDqigzNpuSDcFbfnmV+Be1m5rXvKzUq3kaRTiBU6iCB1dQhztogA8MEJ7hFd6cR+fFeXc+Fq0FJ585hj9wPn8A212Maw==</latexit>
Find vo (t) for t ≥ 0, using frequency domain techniques.
(b) [8 marks] You are given a Linear Time Invariant system with the following transfer function
H(s) =
s2
2s + 10
+ 7s + 12
An input source vi (t) is applied to the system at time t = 0, and the following output vo (t) is
observed:
vo (t) = (10e−3t − 20e−4t + 10e−5t )u(t)
Assume that the system has no energy stored at time t = 0− . Determine vi (t). Show all of your
work.
Page 3 of 9
ELEN30014 Analog and Digital Electronics Concepts, Semester 1 Assessment, 2021
Question 2 (continued)
(c) [10 marks] Consider the circuit shown below
i(t)
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<latexit sha1_base64="ettAHaHiAmloHPZXp2vzUfcOHX0=">AAAB73icbVBNSwMxEJ2tX7V+VT16CRahB1l2q6LHgiAeK9haaJeSTbNtaDZZk6xQlv4JLx4U8erf8ea/MW33oK0PBh7vzTAzL0w408bzvp3Cyura+kZxs7S1vbO7V94/aGmZKkKbRHKp2iHWlDNBm4YZTtuJojgOOX0IR9dT/+GJKs2kuDfjhAYxHggWMYKNldqee4G6p+imV654rjcDWiZ+TiqQo9Erf3X7kqQxFYZwrHXH9xITZFgZRjidlLqppgkmIzygHUsFjqkOstm9E3RilT6KpLIlDJqpvycyHGs9jkPbGWMz1IveVPzP66QmugoyJpLUUEHmi6KUIyPR9HnUZ4oSw8eWYKKYvRWRIVaYGBtRyYbgL768TFo11z9za3fnlXo1j6MIR3AMVfDhEupwCw1oAgEOz/AKb86j8+K8Ox/z1oKTzxzCHzifP6nljlU=</latexit>
0.5 F
1H
<latexit sha1_base64="ClOU5I0yqKDzqcax2rGILB1Y2c4=">AAAB7XicbVBNSwMxEJ2tX7V+VT16CRahBym7VdBjwUuPFewHtEvJptk2NpssSVYoS/+DFw+KePX/ePPfmG73oK0PBh7vzTAzL4g508Z1v53CxubW9k5xt7S3f3B4VD4+6WiZKELbRHKpegHWlDNB24YZTnuxojgKOO0G07uF332iSjMpHswspn6Ex4KFjGBjpY6HBpeoOSxX3JqbAa0TLycVyNEalr8GI0mSiApDONa677mx8VOsDCOczkuDRNMYkyke076lAkdU+2l27RxdWGWEQqlsCYMy9fdEiiOtZ1FgOyNsJnrVW4j/ef3EhLd+ykScGCrIclGYcGQkWryORkxRYvjMEkwUs7ciMsEKE2MDKtkQvNWX10mnXvOuavX760qjmsdRhDM4hyp4cAMNaEIL2kDgEZ7hFd4c6bw4787HsrXg5DOn8AfO5w/MAI3h</latexit>
+
<latexit sha1_base64="+A0/AXfS/wCOnWqWwc6/mSf4GC4=">AAAB53icbVBNS8NAEJ3Ur1q/qh69LBahIJREBPVW8OKxBWMLbSib7aRdu9mE3Y1QSn+BFw8qXv1L3vw3btsctPXBwOO9GWbmhang2rjut1NYW9/Y3Cpul3Z29/YPyodHDzrJFEOfJSJR7ZBqFFyib7gR2E4V0jgU2ApHtzO/9YRK80Tem3GKQUwHkkecUWOl5nmvXHFr7hxklXg5qUCORq/81e0nLItRGiao1h3PTU0wocpwJnBa6mYaU8pGdIAdSyWNUQeT+aFTcmaVPokSZUsaMld/T0xorPU4Dm1nTM1QL3sz8T+vk5noOphwmWYGJVssijJBTEJmX5M+V8iMGFtCmeL2VsKGVFFmbDYlG4K3/PIq8S9qNzWveVmpV/M0inACp1AFD66gDnfQAB8YIDzDK7w5j86L8+58LFoLTj5zDH/gfP4A2FeMaQ==</latexit>
<latexit
<latexit sha1_base64="EmVHkFNGJmpc+AEtkyjtX05M0jE=">AAAB7XicbVDLSgNBEOyNrxhfUY9eBoMQL2E3CnoMePEYwTwgWcLsZDYZMzu7zPQGQsg/ePGgiFf/x5t/4yTZgyYWNBRV3XR3BYkUBl3328ltbG5t7+R3C3v7B4dHxeOTpolTzXiDxTLW7YAaLoXiDRQoeTvRnEaB5K1gdDf3W2OujYjVI04S7kd0oEQoGEUrNcc9U8bLXrHkVtwFyDrxMlKCDPVe8avbj1kacYVMUmM6npugP6UaBZN8VuimhieUjeiAdyxVNOLGny6unZELq/RJGGtbCslC/T0xpZExkyiwnRHFoVn15uJ/XifF8NafCpWkyBVbLgpTSTAm89dJX2jOUE4soUwLeythQ6opQxtQwYbgrb68TprVindVqT5cl2rlLI48nME5lMGDG6jBPdShAQye4Ble4c2JnRfn3flYtuacbOYU/sD5/AEENI6t</latexit>
vs (t)
+
=
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2i
3⌦
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<latexit sha1_base64="9shEmRavyCHYoXlGMw+54VsUWa4=">AAAB7XicbVDLSgNBEOyNrxhfUY9eFoMQL2E3CnoMePEYwTwgWcLsZDYZMzuzzPQGQsg/ePGgiFf/x5t/4yTZgyYWNBRV3XR3hYngBj3v28ltbG5t7+R3C3v7B4dHxeOTplGppqxBlVC6HRLDBJesgRwFayeakTgUrBWO7uZ+a8y04Uo+4iRhQUwGkkecErRSc9xTZbzsFUtexVvAXSd+RkqQod4rfnX7iqYxk0gFMabjewkGU6KRU8FmhW5qWELoiAxYx1JJYmaC6eLamXthlb4bKW1LortQf09MSWzMJA5tZ0xwaFa9ufif10kxug2mXCYpMkmXi6JUuKjc+etun2tGUUwsIVRze6tLh0QTijaggg3BX315nTSrFf+qUn24LtXKWRx5OINzKIMPN1CDe6hDAyg8wTO8wpujnBfn3flYtuacbOYU/sD5/AH+CY6p</latexit>
vo (t)
<latexit sha1_base64="epvcpLQKggQcO8NxJPcwQsrGXII=">AAAB53icbVBNS8NAEJ3Ur1q/qh69LBahF0signorePHYgrGFNpTNdtKu3WzC7kYopb/AiwcVr/4lb/4bt20O2vpg4PHeDDPzwlRwbVz32ymsrW9sbhW3Szu7e/sH5cOjB51kiqHPEpGodkg1Ci7RN9wIbKcKaRwKbIWj25nfekKleSLvzTjFIKYDySPOqLFS87xXrrg1dw6ySrycVCBHo1f+6vYTlsUoDRNU647npiaYUGU4EzgtdTONKWUjOsCOpZLGqIPJ/NApObNKn0SJsiUNmau/JyY01noch7Yzpmaol72Z+J/XyUx0HUy4TDODki0WRZkgJiGzr0mfK2RGjC2hTHF7K2FDqigzNpuSDcFbfnmV+Be1m5rXvKzUq3kaRTiBU6iCB1dQhztogA8MEJ7hFd6cR+fFeXc+Fq0FJ585hj9wPn8A212Maw==</latexit>
Determine the impulse response of the circuit, where vs (t) is considered the input and vo (t)
is considered the output. Assume that there is no stored energy in the circuit prior to the
application of the impulse.
Page 4 of 9
ELEN30014 Analog and Digital Electronics Concepts, Semester 1 Assessment, 2021
Question 3 (16 marks)
(a) [4 marks] A parallel RLC resonant circuit with a resonant frequency of 20,000 rad/s has an
admittance at this frequency of 1 mS. If the capacitance of the network is 2µF , find the values
of R and L.
(b) [6 marks] The circuit below is driven by a variable frequency voltage source. The magnitude of
the current at the resonant frequency, ω0 = 1000 rad/s, is 12 A.
R
<latexit sha1_base64="kBH6JgImCWxC85gQglQkP/TMl+E=">AAAB6HicbVDLTgJBEOzFF+IL9ehlIjHhRHbRRI8kXjyCkUcCGzI79MLI7OxmZtaEEL7AiweN8eonefNvHGAPClbSSaWqO91dQSK4Nq777eQ2Nre2d/K7hb39g8Oj4vFJS8epYthksYhVJ6AaBZfYNNwI7CQKaRQIbAfj27nffkKleSwfzCRBP6JDyUPOqLFS475fLLkVdwGyTryMlCBDvV/86g1ilkYoDRNU667nJsafUmU4Ezgr9FKNCWVjOsSupZJGqP3p4tAZubDKgISxsiUNWai/J6Y00noSBbYzomakV725+J/XTU1440+5TFKDki0XhakgJibzr8mAK2RGTCyhTHF7K2EjqigzNpuCDcFbfXmdtKoV77JSbVyVauUsjjycwTmUwYNrqMEd1KEJDBCe4RXenEfnxXl3PpatOSebOYU/cD5/AKYdjMA=</latexit>
C
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+
<latexit sha1_base64="+A0/AXfS/wCOnWqWwc6/mSf4GC4=">AAAB53icbVBNS8NAEJ3Ur1q/qh69LBahIJREBPVW8OKxBWMLbSib7aRdu9mE3Y1QSn+BFw8qXv1L3vw3btsctPXBwOO9GWbmhang2rjut1NYW9/Y3Cpul3Z29/YPyodHDzrJFEOfJSJR7ZBqFFyib7gR2E4V0jgU2ApHtzO/9YRK80Tem3GKQUwHkkecUWOl5nmvXHFr7hxklXg5qUCORq/81e0nLItRGiao1h3PTU0wocpwJnBa6mYaU8pGdIAdSyWNUQeT+aFTcmaVPokSZUsaMld/T0xorPU4Dm1nTM1QL3sz8T+vk5noOphwmWYGJVssijJBTEJmX5M+V8iMGFtCmeL2VsKGVFFmbDYlG4K3/PIq8S9qNzWveVmpV/M0inACp1AFD66gDnfQAB8YIDzDK7w5j86L8+58LFoLTj5zDH/gfP4A2FeMaQ==</latexit>
<latexit
36 cos(!t + 45 ) V
<latexit sha1_base64="WUjMztwjRtDyeYi7qWehUIgWHTA=">AAACCnicbVDLSgMxFM3UV62vUZduokWoKGWmrY9lwY3LCvYBnbFk0kwbmkyGJCOU0rUbf8WNC0Xc+gXu/BvTdhbaeuDC4Zx7ufeeIGZUacf5tjJLyyura9n13Mbm1vaOvbvXUCKRmNSxYEK2AqQIoxGpa6oZacWSIB4w0gwG1xO/+UCkoiK608OY+Bz1IhpSjLSROvZh+QJ6WKiCJzjpIajhKayc33uYSnwCvTPY6Nh5p+hMAReJm5I8SFHr2F9eV+CEk0hjhpRqu06s/RGSmmJGxjkvUSRGeIB6pG1ohDhR/mj6yhgeG6ULQyFNRRpO1d8TI8SVGvLAdHKk+2rem4j/ee1Eh1f+iEZxokmEZ4vChEEt4CQX2KWSYM2GhiAsqbkV4j6SCGuTXs6E4M6/vEgapaJbLpZuK/lqIY0jCw7AESgAF1yCKrgBNVAHGDyCZ/AK3qwn68V6tz5mrRkrndkHf2B9/gCug5eg</latexit>
+
=
10 mH
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<latexit sha1_base64="9shEmRavyCHYoXlGMw+54VsUWa4=">AAAB7XicbVDLSgNBEOyNrxhfUY9eFoMQL2E3CnoMePEYwTwgWcLsZDYZMzuzzPQGQsg/ePGgiFf/x5t/4yTZgyYWNBRV3XR3hYngBj3v28ltbG5t7+R3C3v7B4dHxeOTplGppqxBlVC6HRLDBJesgRwFayeakTgUrBWO7uZ+a8y04Uo+4iRhQUwGkkecErRSc9xTZbzsFUtexVvAXSd+RkqQod4rfnX7iqYxk0gFMabjewkGU6KRU8FmhW5qWELoiAxYx1JJYmaC6eLamXthlb4bKW1LortQf09MSWzMJA5tZ0xwaFa9ufif10kxug2mXCYpMkmXi6JUuKjc+etun2tGUUwsIVRze6tLh0QTijaggg3BX315nTSrFf+qUn24LtXKWRx5OINzKIMPN1CDe6hDAyg8wTO8wpujnBfn3flYtuacbOYU/sD5/AH+CY6p</latexit>
vo (t)
<latexit sha1_base64="epvcpLQKggQcO8NxJPcwQsrGXII=">AAAB53icbVBNS8NAEJ3Ur1q/qh69LBahF0signorePHYgrGFNpTNdtKu3WzC7kYopb/AiwcVr/4lb/4bt20O2vpg4PHeDDPzwlRwbVz32ymsrW9sbhW3Szu7e/sH5cOjB51kiqHPEpGodkg1Ci7RN9wIbKcKaRwKbIWj25nfekKleSLvzTjFIKYDySPOqLFS87xXrrg1dw6ySrycVCBHo1f+6vYTlsUoDRNU647npiaYUGU4EzgtdTONKWUjOsCOpZLGqIPJ/NApObNKn0SJsiUNmau/JyY01noch7Yzpmaol72Z+J/XyUx0HUy4TDODki0WRZkgJiGzr0mfK2RGjC2hTHF7K2FDqigzNpuSDcFbfnmV+Be1m5rXvKzUq3kaRTiBU6iCB1dQhztogA8MEJ7hFd6cR+fFeXc+Fq0FJ585hj9wPn8A212Maw==</latexit>
Find: (i) C, (ii) Q (Quality Factor), (iii) the bandwidth of the filter.
(c) [6 marks] A black box contains a series RLC filter, where the output terminals are solely across
the resistor. The box is tested by applying an ideal unit impulse, δ(t), at the input and measuring
the output with an oscilloscope. The plot of the output voltage versus time (t > 0) is shown
below:
Use all of the given information to estimate the filter’s transfer function as well as all pole(s) and
zero(s). Be sure to fully justify your estimates. Unjustified answers will be considered as guesses
and will receive zero marks.
Page 5 of 9
ELEN30014 Analog and Digital Electronics Concepts, Semester 1 Assessment, 2021
Question 4 (12 marks)
(a) [6 marks] The Bode Magnitude plot for a circuit, |H(jω)| is given below
|H(j!)|
<latexit sha1_base64="3sGJuq7z13awVYPpbJvImYOFf6c=">AAAB9HicbVBNTwIxEJ3FL8Qv1KOXRmKCF7JLjHok8cIRE/lIYEO6pUCl3a5tl4Qs/A4vHjTGqz/Gm//GAntQ8CWTvLw3k5l5QcSZNq777WQ2Nre2d7K7ub39g8Oj/PFJQ8tYEVonkkvVCrCmnIW0bpjhtBUpikXAaTMY3c395pgqzWT4YCYR9QUehKzPCDZW8qfV4iPqSEEH+HLazRfckrsAWideSgqQotbNf3V6ksSChoZwrHXbcyPjJ1gZRjid5TqxphEmIzygbUtDLKj2k8XRM3RhlR7qS2UrNGih/p5IsNB6IgLbKbAZ6lVvLv7ntWPTv/UTFkaxoSFZLurHHBmJ5gmgHlOUGD6xBBPF7K2IDLHCxNiccjYEb/XlddIol7zrUvn+qlAppnFk4QzOoQge3EAFqlCDOhB4gmd4hTdn7Lw4787HsjXjpDOn8AfO5w/SopFp</latexit>
-20 dB/decade
40 dB
-40 dB/decade
-20 dB/decade
0.4
50
400 1000
<latexit sha1_base64="64Hxqr7piNENcN8740tvY+/8Y8A=">AAAB9XicbVBNSwMxEM36WetX1aOXYBHqpe4WUY8FLx4r2A9o1zKbzbahSXZJskpZ+j+8eFDEq//Fm//GtN2Dtj4YeLw3w8y8IOFMG9f9dlZW19Y3Ngtbxe2d3b390sFhS8epIrRJYh6rTgCaciZp0zDDaSdRFETAaTsY3Uz99iNVmsXy3owT6gsYSBYxAsZKD71Y0AHgioLwXJ/1S2W36s6Al4mXkzLK0eiXvnphTFJBpSEctO56bmL8DJRhhNNJsZdqmgAZwYB2LZUgqPaz2dUTfGqVEEexsiUNnqm/JzIQWo9FYDsFmKFe9Kbif143NdG1nzGZpIZKMl8UpRybGE8jwCFTlBg+tgSIYvZWTIaggBgbVNGG4C2+vExatap3Wa3dXZTrlTyOAjpGJ6iCPHSF6ugWNVATEaTQM3pFb86T8+K8Ox/z1hUnnzlCf+B8/gBFd5Gi</latexit>
!(rad/s)
Note that this diagram is not necessarily to scale but all important features are labelled with
their respective values.
Determine an expression for the frequency response H(jω) that yields this Bode Magnitude plot.
You MUST show all of your working.
(b) [6 marks] A linear circuit has a transfer function given by :
H(s) =
Vo (s)
10, 010s
= 2
Vi (s)
(s + 10, 010s + 100, 000)
Sketch the piecewise straight-line approximation of the Bode phase plot of the circuit for 1 <
ω < 106 rad/s . You MUST show all your reasoning and/or calculations and label ALL points
of interest on your plot.
Page 6 of 9
ELEN30014 Analog and Digital Electronics Concepts, Semester 1 Assessment, 2021
Question 5 (14 marks)
(a) [4 marks] Determine the y-parameters for the two-port network shown below in terms of the
circuit parameters. Show all of your work.
<latexit sha1_base64="mTcHBde9mN3jALKSO++EASyIGWs=">AAAB83icbVBNS8NAEJ3Ur1q/qh69LBahBylJFfRY8OLNCrYWmlA220m7dDcJuxuhlP4NLx4U8eqf8ea/cdvmoK0PBh7vzTAzL0wF18Z1v53C2vrG5lZxu7Szu7d/UD48auskUwxbLBGJ6oRUo+Axtgw3AjupQipDgY/h6GbmPz6h0jyJH8w4xUDSQcwjzqixku/ViX9O/DuJA9orV9yaOwdZJV5OKpCj2St/+f2EZRJjwwTVuuu5qQkmVBnOBE5LfqYxpWxEB9i1NKYSdTCZ3zwlZ1bpkyhRtmJD5urviQmVWo9laDslNUO97M3E/7xuZqLrYMLjNDMYs8WiKBPEJGQWAOlzhcyIsSWUKW5vJWxIFWXGxlSyIXjLL6+Sdr3mXdTq95eVRjWPowgncApV8OAKGnALTWgBgxSe4RXenMx5cd6dj0VrwclnjuEPnM8fBbuQTA==</latexit>
12 ⌦
3⌦
<latexit sha1_base64="2EYhiX/dtXbmTuT+4Y2cJl8tSOM=">AAAB8nicbVBNSwMxEJ2tX7V+VT16CRahBym7raDHghdvVrAfsLuUbJptQ5PskmSFUvozvHhQxKu/xpv/xrTdg7Y+GHi8N8PMvCjlTBvX/XYKG5tb2zvF3dLe/sHhUfn4pKOTTBHaJglPVC/CmnImadsww2kvVRSLiNNuNL6d+90nqjRL5KOZpDQUeChZzAg2VvIbKLhEwb2gQ9wvV9yauwBaJ15OKpCj1S9/BYOEZIJKQzjW2vfc1IRTrAwjnM5KQaZpiskYD6lvqcSC6nC6OHmGLqwyQHGibEmDFurviSkWWk9EZDsFNiO96s3F/zw/M/FNOGUyzQyVZLkozjgyCZr/jwZMUWL4xBJMFLO3IjLCChNjUyrZELzVl9dJp17zGrX6w1WlWc3jKMIZnEMVPLiGJtxBC9pAIIFneIU3xzgvzrvzsWwtOPnMKfyB8/kDleOQEg==</latexit>
6⌦
<latexit sha1_base64="NrVkZrNwt9BNcvnyoRR4ceKVbYs=">AAAB8nicbVBNSwMxEM3Wr1q/qh69BIvQg5TdKuqx4MWbFewH7C4lm862oUl2SbJCKf0ZXjwo4tVf481/Y9ruQVsfDDzem2FmXpRypo3rfjuFtfWNza3idmlnd2//oHx41NZJpii0aMIT1Y2IBs4ktAwzHLqpAiIiDp1odDvzO0+gNEvkoxmnEAoykCxmlBgr+Vc4OMfBvYAB6ZUrbs2dA68SLycVlKPZK38F/YRmAqShnGjte25qwglRhlEO01KQaUgJHZEB+JZKIkCHk/nJU3xmlT6OE2VLGjxXf09MiNB6LCLbKYgZ6mVvJv7n+ZmJb8IJk2lmQNLFojjj2CR49j/uMwXU8LElhCpmb8V0SBShxqZUsiF4yy+vkna95l3U6g+XlUY1j6OITtApqiIPXaMGukNN1EIUJegZvaI3xzgvzrvzsWgtOPnMMfoD5/MHmo2QFQ==</latexit>
(b) [10 marks] A two-port network is connected into a circuit as shown in the figure below :
12 cos(100t + 30 )V
<latexit sha1_base64="ytYEbDxtZ81MelGWVEYpQFR3l9M=">AAACBHicbVDLSgMxFM3UV62vUZfdBItQEUqmFXRZcOOygn1AO5ZMmmlDM8mQZIQydOHGX3HjQhG3foQ7/8a0nYW2HrhwOOde7r0niDnTBqFvJ7e2vrG5ld8u7Ozu7R+4h0ctLRNFaJNILlUnwJpyJmjTMMNpJ1YURwGn7WB8PfPbD1RpJsWdmcTUj/BQsJARbKzUd4teFfaI1GUPIWjgOayh+x5hipzBVt8toQqaA64SLyMlkKHRd796A0mSiApDONa666HY+ClWhhFOp4VeommMyRgPaddSgSOq/XT+xBSeWmUAQ6lsCQPn6u+JFEdaT6LAdkbYjPSyNxP/87qJCa/8lIk4MVSQxaIw4dBIOEsEDpiixPCJJZgoZm+FZIQVJsbmVrAheMsvr5JWteLVKtXbi1K9nMWRB0VwAsrAA5egDm5AAzQBAY/gGbyCN+fJeXHenY9Fa87JZo7BHzifP7JolNw=</latexit>
+
=
+
2 cos(100t + 60 )A
<latexit sha1_base64="lAp9yw6qlybWx6vGImYMsAVISqc=">AAACA3icbVDLSgMxFM3UV62vUXe6CRahIpRMFXVZceOygn1AZyyZNNOGZpIhyQilFNz4K25cKOLWn3Dn35i2s9DqgQuHc+7l3nvChDNtEPpycguLS8sr+dXC2vrG5pa7vdPQMlWE1onkUrVCrClngtYNM5y2EkVxHHLaDAdXE795T5VmUtyaYUKDGPcEixjBxkodd68CfSJ1yUMIGngMz9CdT5giR/Cy4xZRGU0B/xIvI0WQodZxP/2uJGlMhSEca932UGKCEVaGEU7HBT/VNMFkgHu0banAMdXBaPrDGB5apQsjqWwJA6fqz4kRjrUexqHtjLHp63lvIv7ntVMTXQQjJpLUUEFmi6KUQyPhJBDYZYoSw4eWYKKYvRWSPlaYGBtbwYbgzb/8lzQqZe+kXLk5LVZLWRx5sA8OQAl44BxUwTWogTog4AE8gRfw6jw6z86b8z5rzTnZzC74BefjGyLLlI8=</latexit>
<latexit sha1_base64="148mcbjyGh2B+bQ1c83cwdmPhus=">AAAB8HicbZDNSgMxFIXv1L9a/6ou3QSL0IWUmSrosuCmywpOW2mHkkkzbWiSGZKMUIY+hRsXirj1cdz5NqbtLLT1QODj3HvJvSdMONPGdb+dwsbm1vZOcbe0t39weFQ+PmnrOFWE+iTmseqGWFPOJPUNM5x2E0WxCDnthJO7eb3zRJVmsXww04QGAo8kixjBxlqPbs31UP8SNQfliuWF0Dp4OVQgV2tQ/uoPY5IKKg3hWOue5yYmyLAyjHA6K/VTTRNMJnhEexYlFlQH2WLhGbqwzhBFsbJPGrRwf09kWGg9FaHtFNiM9Wptbv5X66Umug0yJpPUUEmWH0UpRyZG8+vRkClKDJ9awEQxuysiY6wwMTajkg3BWz15Hdr1mndVq99fVxrVPI4inME5VMGDG2hAE1rgAwEBz/AKb45yXpx352PZWnDymVP4I+fzBxYIjo0=</latexit>
0.01 H
<latexit sha1_base64="4/4xFke1KIsTpGNgO1S9uME7bac=">AAAB6HicbVDLSgNBEOyNrxhfUY9eBoMQEMJuFPQY8OIxAfOAZAmzk95kzOzsMjMrhJAv8OJBEa9+kjf/xkmyB00saCiquunuChLBtXHdbye3sbm1vZPfLeztHxweFY9PWjpOFcMmi0WsOgHVKLjEpuFGYCdRSKNAYDsY38399hMqzWP5YCYJ+hEdSh5yRo2VGpf9YsmtuAuQdeJlpAQZ6v3iV28QszRCaZigWnc9NzH+lCrDmcBZoZdqTCgb0yF2LZU0Qu1PF4fOyIVVBiSMlS1pyEL9PTGlkdaTKLCdETUjverNxf+8bmrCW3/KZZIalGy5KEwFMTGZf00GXCEzYmIJZYrbWwkbUUWZsdkUbAje6svrpFWteFeVauO6VCtnceThDM6hDB7cQA3uoQ5NYIDwDK/w5jw6L86787FszTnZzCn8gfP5A2sBjJk=</latexit>
5 mF
<latexit sha1_base64="FIcyXfcGdZvnQmIrzSd58mJXSjw=">AAAB7nicbVBNSwMxEJ2tX7V+VT16CRahBym7VdFjQRCPFewHtEvJptk2NMkuSVYoS3+EFw+KePX3ePPfmG33oK0PBh7vzTAzL4g508Z1v53C2vrG5lZxu7Szu7d/UD48ausoUYS2SMQj1Q2wppxJ2jLMcNqNFcUi4LQTTG4zv/NElWaRfDTTmPoCjyQLGcHGSp0r1D9H4m5Qrrg1dw60SrycVCBHc1D+6g8jkggqDeFY657nxsZPsTKMcDor9RNNY0wmeER7lkosqPbT+bkzdGaVIQojZUsaNFd/T6RYaD0Vge0U2Iz1speJ/3m9xIQ3fspknBgqyWJRmHBkIpT9joZMUWL41BJMFLO3IjLGChNjEyrZELzll1dJu17zLmr1h8tKo5rHUYQTOIUqeHANDbiHJrSAwASe4RXenNh5cd6dj0VrwclnjuEPnM8fmreOWg==</latexit>
Two
Port
Network
1⌦
<latexit sha1_base64="gu5yuvzLWzNtNNSrK9ok+InPv3g=">AAAB8nicbVBNS8NAEN3Ur1q/qh69LBahBylJFfRY8OLNCrYWklA220m7dHcTdjdCCf0ZXjwo4tVf481/47bNQVsfDDzem2FmXpRypo3rfjultfWNza3ydmVnd2//oHp41NVJpih0aMIT1YuIBs4kdAwzHHqpAiIiDo/R+GbmPz6B0iyRD2aSQijIULKYUWKs5Hs4OMfBnYAh6VdrbsOdA68SryA1VKDdr34Fg4RmAqShnGjte25qwpwowyiHaSXINKSEjskQfEslEaDDfH7yFJ9ZZYDjRNmSBs/V3xM5EVpPRGQ7BTEjvezNxP88PzPxdZgzmWYGJF0sijOOTYJn/+MBU0ANn1hCqGL2VkxHRBFqbEoVG4K3/PIq6TYb3kWjeX9Za9WLOMroBJ2iOvLQFWqhW9RGHURRgp7RK3pzjPPivDsfi9aSU8wcoz9wPn8AkseQEA==</latexit>
<latexit sha1_base64="9shEmRavyCHYoXlGMw+54VsUWa4=">AAAB7XicbVDLSgNBEOyNrxhfUY9eFoMQL2E3CnoMePEYwTwgWcLsZDYZMzuzzPQGQsg/ePGgiFf/x5t/4yTZgyYWNBRV3XR3hYngBj3v28ltbG5t7+R3C3v7B4dHxeOTplGppqxBlVC6HRLDBJesgRwFayeakTgUrBWO7uZ+a8y04Uo+4iRhQUwGkkecErRSc9xTZbzsFUtexVvAXSd+RkqQod4rfnX7iqYxk0gFMabjewkGU6KRU8FmhW5qWELoiAxYx1JJYmaC6eLamXthlb4bKW1LortQf09MSWzMJA5tZ0xwaFa9ufif10kxug2mXCYpMkmXi6JUuKjc+etun2tGUUwsIVRze6tLh0QTijaggg3BX315nTSrFf+qUn24LtXKWRx5OINzKIMPN1CDe6hDAyg8wTO8wpujnBfn3flYtuacbOYU/sD5/AH+CY6p</latexit>
vo (t)
<latexit sha1_base64="G6HntBfAdZsGcMyIAAD1KmwUZww=">AAAB6HicbVDLSgNBEOyNrxhfUY9eBoOQi2E3CnoMePGYgHlAsoTZSW8yZnZ2mZkVQsgXePGgiFc/yZt/4yTZgyYWNBRV3XR3BYng2rjut5Pb2Nza3snvFvb2Dw6PiscnLR2nimGTxSJWnYBqFFxi03AjsJMopFEgsB2M7+Z++wmV5rF8MJME/YgOJQ85o8ZKjct+seRW3AXIOvEyUoIM9X7xqzeIWRqhNExQrbuemxh/SpXhTOCs0Es1JpSN6RC7lkoaofani0Nn5MIqAxLGypY0ZKH+npjSSOtJFNjOiJqRXvXm4n9eNzXhrT/lMkkNSrZcFKaCmJjMvyYDrpAZMbGEMsXtrYSNqKLM2GwKNgRv9eV10qpWvKtKtXFdqpWzOPJwBudQBg9uoAb3UIcmMEB4hld4cx6dF+fd+Vi25pxs5hT+wPn8AW4JjJs=</latexit>
The two-port network has Z parameters
"
#
3 2
Z=
Ω
2 3
Determine the output voltage vo (t).
Page 7 of 9
ELEN30014 Analog and Digital Electronics Concepts, Semester 1 Assessment, 2021
Question 6 (13 marks)
An asynchronous ripple counter, implemented using four J-K flip flops, is given in the diagram below,
where all J, K and CLR inputs are tied to logic 1. A clock signal is applied to the input CLK IN.
D
J
C
CLK
D
K
J
B
J
CLK
C
CLR
K
A
CLK
B
CLR
K
CLK
A
CLR
1
J
CLK_IN
1
K
CLR
(a) [5 marks] Assume that the counter is driven by a 100 MHz clock signal, connected to the
CLK IN input and that each flip flop has a propagation delay of tpd = 5ns and contamination
delay of tcd = 0ns.
Draw the waveforms at the output of each flip flop with respect to the clock for the first 7
negative-edge clock transitions of the CLK IN signal, assuming initially that DCBA = 0000.
(b) [2 marks] What is the maximum frequency that this counter can operate at, i.e. ensuring that
all possible states are reached? Neglect setup and hold times on the flip-flops.
(c) [6 marks] Suppose that a NEW synchronous counter is to be designed utilising a number of
J-K flip flops, shown in the diagram below
D
PRE
J
C
CLK
D
K
CLR
PRE
J
B
PRE
CLK
C
K
CLR
J
A
CLK
B
K
CLR
PRE
J
CLK
A
CLK_IN
K
CLR
Draw the circuit diagram to implement a MOD-12 synchronous down counter, showing all J-K
flip-flops, necessary interconnections and combinational logic. Assume that the flip-flops and
combinational logic have negligible delays. Show all of your working.
Page 8 of 9
ELEN30014 Analog and Digital Electronics Concepts, Semester 1 Assessment, 2021
Question 7 (11 marks)
In this question you will design a synchronous, recycling, MOD-5 counter that produces the repeating
sequence 001, 011, 101, 111, 100... using D flip-flops and combinational logic. All unused states that
are not part of the counting sequence must always go to 001 on the next clock pulse.
(a) [3 marks] Construct the state transition table for the counter, where CBA represents both the
state and the output of the counter, with C being the most significant bit, and C 0 B 0 A0 represents
the next state. An example layout for your table is below:
Present state
C
B
A
Next state
C
B0
A0
0
(b) [3 marks] Determine logic expressions for next state bits C 0 , B 0 , A0 in terms of the outputs
of the flip-flops C, B, A (i.e. the present state bits). Show ALL of your working. Use logic
minimisation techniques where possible.
(c) [5 marks] Draw the complete circuit diagram for the MOD-5 counter designed in parts (a) and
(b) using D flip-flops and any necessary combinational logic gates. Clearly indicate the inputs
and outputs of the counter.
END OF EXAMINATION
Page 9 of 9