FLOORPLAN
INPUTS FOR FLOORPLAN
• Netlist (.v)
• Technology file (techlef)
• Timing Library files (.lib)
• Physical library (.lef)
• Synopsys design constraints (.sdc)
• Tlu+
STEPS
• Decide core width and height for die size estimation.
• IO pad sites are created for placement of IO pad placement.
• Placement of macros.
• The standard cell rows created for standard cell placement.
• Power planning (pre routing)
• Adding physical only cells
Note:
Aspect ratio = height/width
core utilization = (macros area + std cell area +pads area)/ total core area)
Guidelines to place macros:
• Placement of macros are based on the fly-lines ( its shows the connectivity b/w macro to macro and macro to
pins) so we can minimize the interconnect length between IO pins and other cells.
• Place the macros around to the boundary of the core, leaving some space between macro to core edge so tha
during optimization this space will be used for buffer/inverter insertion and keeping large areas for placement
of standard cells during the placement stage.
• Macros that are communicating with pins/ports of core place them near to core boundary.
• Place the macros of same hierarchy together.
• Keep the sufficient channel between macros
• channel width = (number of pins * pitch )/ number of layers either horizontal or vertical
• Avoids notches while placing macros, if anywhere notches is present then use hard blockages in that area.
• Avoid crisscross connection of macro placement
• Keep keep-out margin around the four sides of macros so no standard cells will not sit near to Macro pins. This
technique avoids the congestion.
• Keep placement blockages at the corners of macros.
• For pin side of macros keep larger separation and for non-pin side, we can abut the macros with their halo so
that area will be saved and Halo of two macros can abut so that no standard cells are placed in between
macros.
• Between two macros at least one pair of power straps (power and Ground) should be present.
Types of macros:
• Hard macros: The circuit is fixed. We can’t see the functionality information about
macros. Only we know the timing information.
• Soft macros: The circuit is not fixed and we can see the functionality and which type of
gates are using inside it. Also we know the timing information
Abutted non-pin side macros with
fig: pin side macros with halo
abutted halo
fig: placement of IO pads, standard cells and macros hierarchy wise
macros to IO pin
macros to macros fly lines:
Halo(keep out margin)
create_keepout_margin -outer {10 10 10 10} macro_name -type soft/hard
create_keepout_margin -inner {10 10 10 10} macro_name -type soft/hard
Blocakges
Soft: Only buffer can be placed. Prevents from the placement of std cell and hard macro within the
specified area during coarse placement but allows placement of buffer/inv during optimization,
legalization and clock tree synthesis.
Hard: No standard cells, macros and buffer/inv can be placed within the specified area during coarse
placement, optimization, and legalization.
Partial: By default the blockage factor is 100% so no cells can be placed in that region but if we want to
reduce density without blocking 100% area, we can change the blockage factor.
• create_placement_blockages -boundary {{10 20} {100 200}} -name PB1 -type soft
• create_placement_blockages -boundry {{10 20} {100 200}} -name PB1 -type hard
• create_placement_blockages -Boundry {10 20 100 200} -type partial -blocked_percentage 40
Thank you