B.M.S COLLEGE OF ENGINEERING
Department of Electronics and Communication Engineering
(Autonomous College Affiliated to Visvesvaraya Technological University, Belgaum)
Bangalore-560019.
2022 - 2023
“SYSTEM VERILOG & VERIFICATION”
19EC6PE3SV
AAT
By:
Divya Shree K V
1BM20EC042
Course Instructor:
JEERU DINESH REDDY
Assistant Professor
Dept. of ECE
B.M.S. College of Engineering
1. Counter (4-bit) with the number of clocks to verify:
CODE FILES:
//Counter.v
module counter(count_inter.p1 rtl); always @(posedge rtl.clk , posedge rtl.rst) begin
if(rtl.rst)
rtl.count <= 4'b0;
else rtl.count <= rtl.count + 4'b0001; end
endmodule
//count_inter.sv
interface count_inter(input bit clk); logic [3:0] count;
logic rst;
modport p1(input clk, rst , output count); modport p2(output clk, rst , input count); endinterface :
count_inter
//test.sv
module test(count_inter.p2 t1);
initial
begin
t1.rst=0;
#10
t1.rst=1;
#10 t1.rst=0;
end
begin
#500;
$finish;
end
endmodule
//top.sv
module top;
bit clk;
always #5 clk =~clk;
count_inter in(clk);
counter dut(in);
test t(in);
initial
begin
$dumpfile("top.vcd");
$dumpvars;
$monitor("time=%d, clk=%b, reset=%b, count=%b", $time, clk, in.rst, in.count);
end
endmodule
Output :
Simvision Output:
Coverage:
2. ARBITER WITH 4 BIT INPUT AND 2 BIT OUTPUT
DESIGN
A B C D Y1 Y0 x
xx1 11
x1x001
x01010
100000
others Y1 Y0
CODE FILES
//arbtier.v
module arbiter(input [3:0] a, input clk,rst,output reg [1:0] y);
always @(posedge clk, posedge rst)
if(rst)
y <= 2'b0;
else
begin
case (a)
4'bxxx1 : begin
y[0]<=1;
y[1]<=1;
end
4'bx1x0 : begin
y[0]<=1;
y[1]<=0;
end
4'bx010 : begin
y[0]<=0;
y[1]<=1;
end
4'b1000 : begin
y[0]<=0;
y[1]<=0;
end
default : begin
y[1]<=y[1];
y[0]<=y[0];
end
endcase
end
endmodule
//interface.sv
interface arbiter_inter(input bit clk);
logic [3:0] a;
logic rst;
logic [1:0] y;
clocking cb @(posedge clk);
default input #1ns output #2ns;
output a;
input y;
endclocking
modport tb(clocking cb,output rst);
endinterface : arbiter_inter
//test.sv
program test(arbiter_inter.tb t);
initial
begin
t.cb.a <= 4'bxxx1; #50 t.cb.a <= 4'bx1x0; #10 t.cb.a <= 4'bx010;
#10 t.cb.a <= 4'b1000; end
initial
begin
#500
$finish;
end
initial
begin
t.rst=0;
#10 t.rst=1;
#10 t.rst=0;
end
initial
begin
#200 t.cb.a <=4'b0000;
repeat(50) #5 t.cb.a<=t.cb.a + 4'b0001;
end
endprogram
//top.sv
module top;
bit clk;
always #5 clk = ~clk;
arbiter_inter i1(clk);
arbiter Dut(.rst(i1.rst),.a(i1.a), .y(i1.y), .clk(clk));
test T1(i1);
initial
begin
$dumpfile("top.vcd");
$dumpvars;
end
endmodule
SIMVISION OUTPUT
COVERAGE RESULTS
3.JK /D/T/SR Flip flop
CODE FILES
//design.v
module ff(input j,k,s,r,d,t,rst,clk,output reg qjk,qsr,qd,qt);
always @(posedge clk, posedge rst)
begin
if(rst)
begin
qjk <= 0;
qsr <= 0;
qd <=0;
qt <= 0;
end
else
begin
case({j,k})
2'b00 : qjk <= qjk;
2'b01 : qjk <= 0;
2'b10 : qjk <= 1;
2'b11 : qjk <= !qjk;
default : qjk <= qjk;
endcase
case({s,r})
2'b00 : qsr <= qsr;
2'b01 : qsr <= 0;
2'b10 : qsr <= 1;
2'b11 : qsr <= 1'bx;
default : qsr <= qsr;
endcase
qd <= d ;
if(t)
qt <= ~qt ;
else
qt <= qt;
end
end
endmodule
//interface.sv
interface ff_intf(input bit clk);
logic rst,d,t,qsr,qjk,qd,qt;
logic s,r,j,k;
clocking cb@(posedge clk);
output d,t, s,r,j,k;
input qsr,qjk,qd,qt
endclocking
modport TEST_MP(clocking cb,output rst);
endinterface
//driver.sv
class driver;
virtual ff_intf.TEST_MP T1;
function new(virtual ff_intf.TEST_MP T2);
this.T1=T2;
endfunction
task drive_data();
T1.cb.s <= $random();
T1.cb.r <= $random();
T1.cb.j <= $random();
T1.cb.k <= $random();
T1.cb.d <= $random();
T1.cb.t <= $random();
endtask
endclass
//test.sv
`include "driver.sv"
program test_ff(ff_intf.TEST_MP test_intf);
driver drv_inp;
initial
begin
test_intf.rst <= 0;
#10 test_intf.rst <= 1;
#10 test_intf.rst <= 0;
end
initial
begin
drv_inp = new(test_intf);
end
initial
begin
repeat(1000)
#10 drv_inp.drive_data();
end
initial
begin
#500 $finish;
end
endprogram
SIMVISION OUTPUT
COVERAGE RESULTS
4.FSM Design
CODE FILES
//interface.sv
interface inter_fsm(input bit clk);
logic reset,x;
logic d,z;
clocking cb@(posedge clk);
default input #2ns output #3ns;
input z,d;
output x;
endclocking
modport TB(clocking cb,output reset);
endinterface
//fsm.v
module fsm(input x, clk,reset, output reg z,d);
reg [2:0] cst, nst;
real cov_percent;
parameter S0 = 3'b000, W0 = 3'b001, W1 = 3'b010, W2 = 3'b011, OT = 3'b100,
DE =3'b101;
always @(cst or x)
begin
case (cst)
S0: if (x == 1'b0)
begin
nst = S0;
z=1'b0;
d=1'b0;
end
else
begin
nst = W0;
z=1'b0;
d=1'b0;
end
W0:
begin
nst = W1;
z=1'b0;
d=1'b0;
end
W1:
begin
nst = W2;
z=1'b0;
d=1'b0;
end
W2:
begin
nst = OT;
z=1'b1;
d=1'b0;
end
OT:
begin
nst = DE;
z=1'b0;
d=1'b1;
end
DE:
begin
nst = S0;
z=1'b0;
d=1'b0;
end
endcase
end
always@(posedge clk)
begin
if (reset)
cst <= S0;
else
cst <= nst;
cov_percent= $get_coverage;
$display(“coverage is :”, cov_percent);
end
endmodule
property p1;
@(posedge clk)
(cst == S0 && x == 1'b0) |-> (z == 1'b0 && d == 1'b0);
endproperty
property p2;
@(posedge clk)
(cst == W0) |-> (z == 1'b0 && d == 1'b0);
endproperty
property p3;
@(posedge clk)
(cst == W1) |-> (z == 1'b0 && d == 1'b0);
endproperty
property p4;
@(posedge clk)
(cst == W2) |-> (z == 1'b1 && d == 1'b0);
endproperty
property p5;
@(posedge clk)
(cst == OT) |-> (z == 1'b0 && d == 1'b1);
endproperty
// Assertion statements
assert property(p1)$display("P1 passed");
assert property(p2)$display("P2 passed");
assert property(p3)$display("P3 passed");
assert property(p4)$display("P4 passed");
assert property(p5)$display("P5 passed");
// Coverage
covergroup fsm_coverage @(posedge clk);
fsm_trans : coverpoint cst;
fsm_input : coverpoint x;
fsm_output : coverpoint { z, d };
endgroup
//driver.sv
class driver;
virtual inter_fsm.TB T1;
function new(virtual inter_fsm.TB T2);
this.T1=T2;
endfunction
task drive_data();
T1.cb.x <=$random(); endtask
endclass
//test.sv
`include "driver_fsm.sv"
program tb_fsm(inter_fsm.TB T3);
driver drv_fsm;
initial
begin
T3.reset=0;
#10 T3.reset=1;
#10 T3.reset=0;
end
initial begin drv_fsm=new(T3);
repeat(100)@(T3.cb) drv_fsm.drive_data();
end
initial begin
#1000
$finish; end
endprogram
//top.sv
module top;
bit clk;
always #5 clk=~clk;
inter_fsm i1(clk);
tb_fsm TBench(i1);
fsm DUT(.clk(clk), .x(i1.x), .z(i1.z), .reset(i1.reset),.d(i1.d));
initial
begin
$dumpfile("fsm123.vcd");
$dumpvars; end
endmodule
SIMVISION OUTPUT
COVERAGE RESULTS