DFT TEST – 01
Maximum marks : 100
Maximum time : 3hrs
Note : All the questions are compulsory.
Q.NO
QUESTION
MARKS
1.
What is the relation between defect, fault and error ?
2 marks
2.
3.
What is compression ratio ?
What are the input and output files required for scan ?
2 marks
2 marks
4.
What is controllability and observability?
2 marks
5.
6.
7.
What is DFT? What is scan insertion?
What is edge mixing ? Why should you add a lock-up latch in
between +ve flop and -ve flop?
Explain scan flow.
2 marks
2+3
5 marks
5 marks
8.
Explain compressor logic in EDT.
5 marks
9.
Explain the need of compression with an example.
5 marks
10.
Explain scan chain operation with an example.
5 marks
11.
Differentiate between full scan and partial scan.
Differentiate between top down and bottom up approach.
What is lockup latch ? How will you take care when there are
multiple clock domains in your design ?
What is scan chain balancing? What will happen if we don’t
balance scan chains ?
What does TCD file contain?
2.5 + 2.5
5 marks
2+3
5 marks
2+2
4 marks
1 mark
15.
What is DRC ? What is bus contention ?
What logic will the tool insert to correct bus contention violation?
1+1+3
5 marks
16.
5 marks
17.
Explain the mechanism to bypass EDT logic along with a
diagram.
Which of the 2 approaches is suitable when there are sub-blocks
in the design?
Justify your answer.
18.
How will you deal with pre-existing scan chains in the design ?
5 marks
19.
What are the advantages of scan ?
5 marks
12.
13.
14.
1+4
5 marks
20.
Explain the need and working of integrated clock gating cell.
5 marks
21.
Explain the difference between pin, port and pad.
5 marks
22.
How will you decide the no. of scan chains ?
5 marks
23.
What is the difference between combinational and sequential
ATPG ?
Given a 2 input AND gate. What a verification engineer and DFT
engineer do?
What is the use of EDT update signal?
2 marks
2 marks
How will you correct the following DRCs?
i.
2+2
4 marks
24.
25.
26.
ii.
2 marks