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Design DC and ac Load Lines - Fall 2019

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University of Tripoli
Faculty of Engineering
Electrical and Electronic Engineering Department
EE219 Basic Electronic Circuits
Fall 2019 (Groups A & B)
Eng. Taissir Y. Elganimi
Design of Bipolar Junction Transistor (BJT) Amplifiers
1. BJT Amplifier Biasing Design:
For the amplifier circuit shown in Figure (A) as an example, the DC equivalent circuit as shown in Figure
(B) can be simplified by Thevenin theorem as shown in Figure (C).
Figure (A)
Figure (B)
Figure (C)
By applying Thevenin theorem,
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EE219 - Basic Electronic Circuits
Design of BJT Amplifiers
𝑅𝐡 = 𝑅1 //𝑅2 =
𝑅1 𝑅2
𝑅1 + 𝑅2
∴ 𝑉𝐡𝐡 = 𝑉𝐢𝐢
&
𝑉𝐡𝐡 = 𝑉𝐢𝐢
𝑅𝐡
𝑅1
Prepared by Eng. Taissir Y. Elganimi
𝑅2
𝑅1
𝑅2
= 𝑉𝐢𝐢
𝑅1 + 𝑅2 𝑅1
𝑅1 + 𝑅2
(𝑅1 𝐷𝑒𝑠𝑖𝑔𝑛 πΈπ‘žπ‘’π‘Žπ‘‘π‘–π‘œπ‘›)
And it can be rewritten as follows:
𝑉𝐡𝐡 = 𝑉𝐢𝐢
𝑅2
𝑅1 + 𝑅2
𝑉𝐢𝐢
𝑅1
=1+
𝑉𝐡𝐡
𝑅2
→
∴ 𝑅2 =
→ 𝑅2 =
𝑅𝐡
1 − (𝑉𝐡𝐡 ⁄𝑉𝐢𝐢 )
𝑅1
𝑅𝐡 (𝑉𝐢𝐢 ⁄𝑉𝐡𝐡 )
=
(𝑉𝐢𝐢 ⁄𝑉𝐡𝐡 ) − 1 (𝑉𝐢𝐢 ⁄𝑉𝐡𝐡 ) − 1
(𝑅2 𝐷𝑒𝑠𝑖𝑔𝑛 πΈπ‘žπ‘’π‘Žπ‘‘π‘–π‘œπ‘›)
And for stability, choose:
𝑅𝐡 ≤ 0.1𝛽𝑅𝐸
(𝑅𝐡 𝐷𝑒𝑠𝑖𝑔𝑛 πΆπ‘œπ‘›π‘‘π‘–π‘‘π‘–π‘œπ‘›)
--------------------------------------------------------------------------------------------------2. DC and ac Load Lines:
To find the DC operating point (𝑉𝐢𝐸𝑄 , 𝐼𝐢𝑄 ) of this circuit, KVL can be applied with considering each
capacitor acts as an open circuit, and the ac voltage source is a short circuit:
𝑉𝐢𝐢 − 𝐼𝐢 𝑅𝐢 − 𝑉𝐢𝐸 − 𝐼𝐸 𝑅𝐸 = 0
ο‚·
In order to draw the DC load line, find two points on this DC load line equation:
The first point is when 𝐼𝐢 = 0
→
The second point is when 𝑉𝐢𝐸 = 0
𝑉𝐢𝐸 = 𝑉𝐢𝐢 .
→
𝐼𝐢 =
𝑉𝐢𝐢
𝑅
𝑅𝐢 + 𝐸
𝛼
ο‚·
In order to draw the ac load line, find the ac load line equation with considering each capacitor acts as
a short circuit, and the DC and ac voltage sources are short circuit.
By writing the KVL expression as:
0 − 𝑖𝑐 (𝑅𝐢 //𝑅𝐿 ) − 𝑣𝑐𝑒 = 0
where 𝑖𝑐 is the ac collector current, and 𝑣𝑐𝑒 is the ac collector-to-emitter voltage.
Since the total instantaneous collector current can be expressed as:
𝑖𝐢 = 𝐼𝐢𝑄 + 𝑖𝑐
And the total instantaneous collector-to-emitter voltage can be expressed as:
𝑣𝐢𝐸 = 𝑉𝐢𝐸𝑄 + 𝑣𝑐𝑒
The last KVL expression can be rewritten as follows:
0 − (𝑖𝐢 − 𝐼𝐢𝑄 )(𝑅𝐢 //𝑅𝐿 ) − (𝑣𝐢𝐸 − 𝑉𝐢𝐸𝑄 ) = 0
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EE219 - Basic Electronic Circuits
Design of BJT Amplifiers
Or:
𝑖𝐢 = 𝐼𝐢𝑄 +
Prepared by Eng. Taissir Y. Elganimi
𝑉𝐢𝐸𝑄
𝑣𝐢𝐸
−
𝑅𝐢 //𝑅𝐿 𝑅𝐢 //𝑅𝐿
This is the ac load line equation.
We need to find two points on the ac load line equation to draw it with the DC load line equation as follows:
The first point is when 𝑖𝐢 = 0
→
𝑣𝐢𝐸 = 𝑉𝐢𝐸𝑄 + 𝐼𝐢𝑄 π‘…π‘Žπ‘ .
where π‘…π‘Žπ‘ = 𝑅𝐢 //𝑅𝐿 .
The second point is when 𝑣𝐢𝐸 = 0
𝑉𝐢𝐸𝑄
→
𝑖𝐢 = 𝐼𝐢𝑄 + 𝑅
𝐢 //𝑅𝐿
.
Note that at the Q-point with 𝑣𝐢𝐸 = 𝑉𝐢𝐸𝑄 , the currents 𝑖𝐢 and 𝐼𝐢𝑄 will be equal. Therefore, the ac load line
passes through the Q-point of the DC load line as shown below.
Then, the DC and ac load lines can be plotted as follows:
𝑖𝐢 (π‘šπ΄)
𝑉𝐢𝐸𝑄
𝐢 //𝑅𝐿
𝐼𝐢𝑄 + 𝑅
ac Load Line
𝐼𝐢𝑄
Q-point
DC Load Line
0
𝑉𝐢𝐸𝑄
𝑉𝐢𝐸𝑄
𝑉𝐢𝐢
𝑣𝐢𝐸 (𝑉)
𝐼𝐢𝑄 π‘…π‘Žπ‘
As it is shown, the ac load line limits the voltage swing to the minimum 𝑉𝐢𝐸𝑄 and 𝐼𝐢𝑄 π‘…π‘Žπ‘ . Thus, the
maximum voltage variation from the Q-point is the minimum of 𝑉𝐢𝐸𝑄 and 𝐼𝐢𝑄 π‘…π‘Žπ‘ , without clipping at the
output voltage waveform.
When a sinusoidal wave signal is applied to the base of a BJT amplifier, it will vary the base current 𝑖𝐡
which will produce 𝑖𝐡 (𝑝𝑝) and therefore 𝑖𝐢 (𝑝𝑝) and 𝑣𝐢𝐸 (𝑝𝑝). Then, 𝑣𝐢𝐸 (𝑝𝑝) will become the output
voltage at the collector of this circuit (Common Emitter Amplifier without 𝑅𝐸 ).
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EE219 - Basic Electronic Circuits
Design of BJT Amplifiers
Prepared by Eng. Taissir Y. Elganimi
If the Q-point is at a high collector current 𝐼𝐢𝑄 , the lower half cycle of the output voltage wave will be
clipped due to the saturate 𝐼𝐢 as shown above.
Similarly, if the Q-point is at a low collector current 𝐼𝐢𝑄 , the upper half cycle of the output voltage wave
will be clipped due to the cutoff 𝐼𝐢 as shown below:
𝑖𝐢 (π‘šπ΄)
𝑉𝐢𝐸𝑄
𝐢 //𝑅𝐿
𝐼𝐢𝑄 + 𝑅
ac Load Line
𝐼𝐢𝑄
Q-point
DC Load Line
0
𝑉𝐢𝐸𝑄
𝑉𝐢𝐸𝑄
𝑉𝐢𝐢
𝑣𝐢𝐸 (𝑉)
𝐼𝐢𝑄 π‘…π‘Žπ‘
--------------------------------------------------------------------------------------------------3. BJT Optimum Q-point Design:
For maximum output voltage swing, we need 𝑖𝐢 = 2𝐼𝐢𝑄 when 𝑣𝐢𝐸 = 0. In other words, we need 𝑉𝐢𝐸𝑄 to be
equal to 𝐼𝐢𝑄 π‘…π‘Žπ‘ .
∴ 𝑉𝐢𝐸𝑄 = 𝑉𝐢𝐢 − 𝐼𝐢𝑄 𝑅𝐷𝐢 = 𝐼𝐢𝑄 π‘…π‘Žπ‘
where 𝑅𝐷𝐢 = 𝑅𝐢 +
𝑅𝐸
𝛼
in this example.
∴ 𝐼𝐢𝑄 =
𝑉𝐢𝐢
𝑅𝐷𝐢 + π‘…π‘Žπ‘
(π‘‚π‘π‘‘π‘–π‘šπ‘’π‘š 𝐼𝐢𝑄 𝐷𝑒𝑠𝑖𝑔𝑛 πΈπ‘žπ‘’π‘Žπ‘‘π‘–π‘œπ‘›)
If the input wave increases the base current wave 𝑖𝐡 , then both 𝑖𝐢 and 𝑣𝐢𝐸 will be increased where both half
cycles of the output voltage waveform will be clipped simultaneously due to cutoff and saturation in the
case of the optimum collector current, and the peak-to-peak output voltage swing (before clipping) will be
equal to 2𝐼𝐢𝑄 π‘…π‘Žπ‘ as shown below:
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EE219 - Basic Electronic Circuits
Design of BJT Amplifiers
Prepared by Eng. Taissir Y. Elganimi
𝑖𝐢 (π‘šπ΄)
𝑉𝐢𝐸𝑄
𝐢 //𝑅𝐿
𝐼𝐢𝑄 + 𝑅
ac Load Line
𝐼𝐢𝑄
Q-point
DC Load Line
0
𝑉𝐢𝐸𝑄
𝑉𝐢𝐸𝑄
𝑉𝐢𝐢
𝑣𝐢𝐸 (𝑉)
𝐼𝐢𝑄 π‘…π‘Žπ‘
Good luck…
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