6/29/2020 Spectre Tech Tips: Optimizing Spectre APS Performance - Custom IC Design - Cadence Blogs - Cadence Community PRODUCTS Login New User Spectre Tech Tips: Optimizing Spectre APS Performance SOLUTIONS SUPPORT As an analog/mixed-signal designer, verification engineer, or CAD expert, you use Spectre® APS for analyzing your designs. Do you sometimes wonder if it were possible to optimize Spectre APS further for accuracy or performance? If yes, then this blog is for you. In this blog, you'll get to know how you can optimize Spectre APS performance for analog and mixed-signal designs using some important options. You'll also understand how you can address some typical setup problems that cause performance issues and how to use some of the advanced methods to optimize simulation performance. COMPANY Pre-layout Simulation Accuracy/Performance Trade-Off For pre-layout simulation, you can use the following two options to adjust accuracy and performance: The option with values , , and , defines the solver tolerances. While is the most accurate, provides the highest performance. The option can be specified in the netlist, or at the command line with and (i.e. ) options. The command-line option provides performance optimization for each setting. It typically provides 1.5-2x performance gain over the same simulation with , with no or minor degradation in accuracy. When running the simulation on a new analog/mixed-signal design, we recommended that you start with the setting and use the default values for all other solver options. If Spectre APS accuracy isnʼt sufficient, you can improve the accuracy incrementally by moving to , , and till errpreset conservative moderate conservative liberal liberal errpreset +aps ++aps ++aps=moderate ++aps er- rpreset +aps ++aps=moderate +aps=moderate ++aps=conservative https://community.cadence.com/cadence_blogs_8/b/cic/posts/spectre-optimizing-spectre-aps-performance +aps=conservative 1/12 6/29/2020 Spectre Tech Tips: Optimizing Spectre APS Performance - Custom IC Design - Cadence Blogs - Cadence Community the required accuracy is achieved. If the run provides good accuracy, and you want more performance, move to and to improve the performance incrementally while ensuring that the highest performance setting still provides sufficient accuracy. ++aps=moderate +aps=liberal ++aps=liberal You can also set the and options in the High-Performance Simulation Options form in Virtuoso® ADE, as shown below. errpreset ++aps Use the command-line option to enable multithreading, which provides additional Spectre APS performance gains over a single-threaded simulation run ( ). For small-to-medium sized designs, 4 core simulations ( ) provide the best performance, while for large and post-layout designs, 8 ( ) or 16 ( ) core simulations are recommended. By default, Spectre APS uses 8 cores (if available on the machine), however, it reduces the number of cores based on the design size. You can use the command-line option to identify the number of cores recommended for a given design without running the actual simulation. This information is provided in the Pre-Simulation Summary section of the Spectre log file, as shown below. +mt -mt +mt=4 +mt=8 +mt=16 +query=mtinfo ~~~~~~~~~~~~~~~~~~~~~~ Pre-Simulation Summary ~~~~~~~~~~~~~~~~~~~~~~ - (APS) Multi-threading. The recommended number of threads is 16, consider adding +mt=16 on command line. ~~~~~~~~~~~~~~~~~~~~~~ https://community.cadence.com/cadence_blogs_8/b/cic/posts/spectre-optimizing-spectre-aps-performance 2/12 6/29/2020 Spectre Tech Tips: Optimizing Spectre APS Performance - Custom IC Design - Cadence Blogs - Cadence Community The number of threads can also be defined in the High-Performance Simulation Options form in Virtuoso ADE. The Auto selection uses the default Spectre multithreading behavior. When running a multithreaded simulation on a compute farm, set #Threads to lsf to allow LSF to allocate the cores. Spectre reports the number of threads used in the log file with the following message. Multithreading Enabled: 16 threads in the system with 36 available processors. Post-layout Simulation Accuracy/Performance Trade-Off While , , and multithreading also apply to post-layout designs, using the option is the key for achieving good Spectre APS post-layout simulation performance. The option enables optimized simulation technology to calculate the DC operating point for large designs, performs RC reduction including coupling cap handling, and deploys enhanced matrix solving for RC-dominated designs. For most analog/mixed signal designs, the (high precision analog) setting provides the best performance and accuracy trade-off because it uses conservative RC reduction. For very sensitive designs and extreme accuracy measurements, you can use the (ultra precision analog) setting, which disables RC reduction, however, it still takes advantage of all other Spectre APS post-layout technologies. For high performance requirements in functional verification, may be used, which uses more aggressive RC reduction. errpreset ++aps +postlayout +postlayout +postlayout=hpa +postlayout=upa +postlayout The post-layout settings can also be defined in the High-Performance Simulation Options form in the Virtuoso ADE. The setting is called Default in Virtuoso ADE. +postlayout https://community.cadence.com/cadence_blogs_8/b/cic/posts/spectre-optimizing-spectre-aps-performance 3/12 6/29/2020 Spectre Tech Tips: Optimizing Spectre APS Performance - Custom IC Design - Cadence Blogs - Cadence Community When RC reduction is enabled with or is reported in the Spectre log file, as shown below. +postlayout , the reduction rate +postlayout=hpa Parasitics Reduction Enabled. (Resistors reduced by 80.53% Capacitors reduced by 88.36%, 71.97% of capacitors are coupling after RC reduction). High Voltage Applications High voltage applications are challenging for circuit simulation because with in and mode, voltage references are used globally over all signals. A maximum voltage of 10V from a high-voltage domain may impact the simulation accuracy of the neighboring 1V voltage domain. This problem may also be visible in non-high voltage applications where Verilog-A blocks create large voltage/current values artificially, or in designs with dangling nodes carrying large voltages. The related scenarios can be identified by checking the maximum value quantities in the Spectre log file: relref=sigglobal moderate liberal Maximum value achieved for any signal of each quantity: V: V(I4.net01) = 25.93 V I: I(V1:p) = 103 mA ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Post-Transient Simulation Summary ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - The circuit contains signals of the voltage > 10V, consider to set highvolt- age=yes to get better accuracy and convergence ability. If a high voltage scenario is identified, it is recommended to use the option. This option introduces voltage binning for different voltage domains ( ), excludes Verilog-A terminals from convergence checking (default since highvoltage=yes bin_rel- ref=yes https://community.cadence.com/cadence_blogs_8/b/cic/posts/spectre-optimizing-spectre-aps-performance 4/12 6/29/2020 Spectre Tech Tips: Optimizing Spectre APS Performance - Custom IC Design - Cadence Blogs - Cadence Community Spectre 17.1 ISR10), excludes dangling node voltages from quantity checking (default since Spectre 17.1 ISR4), and overcomes the high-voltage related challenges. The option can also be set in the Main tab of the Simulator Options form, as shown below. highvoltage Typical Spectre APS Setup Issues While debugging customer cases for performance and accuracy issues, weʼve noticed that many such problems are due to an incorrect Spectre APS set up. These problems significantly slow down the simulation or degrade simulation accuracy. They can be addressed easily by understanding their impact on the simulation and taking the corrective action. Some of the problems and their solutions are listed below. Simulator settings from previous simulations not being appropriate for the current design Too tight settings (for example, ) cause many Spectre APS performance issues. Since Spectre APS is optimized for accuracy, using the default value for is sufficient for most designs. Unreasonable values used for and may cause Spectre APS accuracy issues, which can be addressed by setting their values to default. It is recommended to use the default values for , , , , , and . If tuning is needed, then for most cases, it should be sufficient to change and / . The following figure shows the default Spectre tolerance values in Virtuoso ADE. reltol reltol=1e-5 reltol gmin cmin reltol vabstol iabstol method gmin cmin errpreset +aps ++aps https://community.cadence.com/cadence_blogs_8/b/cic/posts/spectre-optimizing-spectre-aps-performance 5/12 6/29/2020 Spectre Tech Tips: Optimizing Spectre APS Performance - Custom IC Design - Cadence Blogs - Cadence Community Note that there may be high-precision designs, or simulation/measurement requirements, that need custom tolerances. In addition, you might encounter convergence challenges for which you require special / settings. It is fine to tune these settings if you are not able to achieve what you need with the recommended settings with default tolerances. Simulating post-layout designs without setting the option Many users assume that Spectre APS does post-layout optimization and RC reduction by default. However, Spectre APS, by default, does not enable any post-layout optimization/reduction, and may therefore be extremely slow on RC dominated post-layout designs. Check the Post-layout Simulation Accuracy/Performance Trade-Off section for proper post-layout settings. Too many node voltages, device, or subckt terminal currents saved Saving large numbers of waveforms, especially current waveforms, degrades Spectre APS performance significantly. Therefore, you should save only the waveforms you need and avoid saving everything ( , , ), if not required. The Spectre log file provides information about how many waveforms are created and prints a warning if performance degradation is expected. gmin cmin errpreset +postlayout save=all currents=all sub- cktprovelvl=10 Output and IC/nodeset summary: save 355350(current) save 130338(voltage) WARNING (SPECTRE-294): Too many saved signals. Slow initialization is expected! Features not needed being enabled Spectre provides some powerful features, such as asserts for device voltage and current checking, info for design information printing, and design checks for analyzing design problems like high impedance nodes or leakage paths. These features, although important, degrade Spectre APS performance. https://community.cadence.com/cadence_blogs_8/b/cic/posts/spectre-optimizing-spectre-aps-performance 6/12 6/29/2020 Spectre Tech Tips: Optimizing Spectre APS Performance - Custom IC Design - Cadence Blogs - Cadence Community Therefore, if you do not require these features you should disable them for maximum performance gain. The enabled features are listed in the Spectre log file, as shown below. Analysis and control statement inventory: info 6 Design checks inventory: dyn_highz 3 dyn_dcpath 1 static_voltdomain 1 assert 2139 Maxstep limiting simulation time steps Sometimes, is used to increase simulation accuracy or to improve periodic measurement (i.e. FFT) precision. It is recommended to use to tune the simulation accuracy. If you want to enforce time steps at periodic measurement points, use instead of . Extremely small rise and fall times Extremely small rise and fall times in Spectre source elements, or in Verilog-A modules, may cause Spectre time step rejections and significantly degrade Spectre APS performance. Therefore, it is recommended to use similar rise and fall times, as the circuit being simulated. Verilog-A behavioral modelling issues While Verilog-A behavioral modelling provides great flexibility for writing behavioral models, it may significantly degrade Spectre APS simulation performance, if written inappropriately. Typical problems include initial calculations being performed at each time step, transition statements like / / limiting and rejecting time steps, transition filter functions missing, and using resistance instead of conductance equations. maxstep errpreset strobeperiod maxstep cross above boundstep https://community.cadence.com/cadence_blogs_8/b/cic/posts/spectre-optimizing-spectre-aps-performance 7/12 6/29/2020 Spectre Tech Tips: Optimizing Spectre APS Performance - Custom IC Design - Cadence Blogs - Cadence Community Therefore, it is highly recommended to run the Spectre AHDL linter ( ) utility on any newly-written Verilog-A model, and address any reported modelling issue. The AHDL linter utility can also be enabled in the Miscellaneous tab of the Simulator Options form in Virtuoso ADE, as shown below. - ahdllint=warn Using an older version of Spectre With every release, Spectre APS is enhanced for better performance. As a result, when you use an older version of Spectre, you miss out the performance enhancements that have been made in the latest version. Therefore, we recommend that you use the latest Spectre release for your designs. Hardware issues Spectre APS performance is impacted when a machine is heavily overloaded, if there are network performance issues, or if sufficient memory isn't available. Insufficient memory can lead to swapping and slow down the simulation. You can check the available memory in the header of the Spectre log file. Machine loading and network communication problems can be observed by checking the CPU load or the utilization reported in the Spectre log file. A CPU load close to 100% could point to a heavily overloaded machine. A utilization below 90% for a single core simulation, below 150% for a 4 core job, or a utilization below 300% for a 8 core simulation may point to an overloaded machine, or network problems. User: stefanw Memory Host: lnx-stefanw available: 10.1099 GB HostID: CD0A11B8 PID: 11716 physical: 16.6440 GB During simulation, the CPU load for active processors is : Spectre 0 (99.9 %) 1 (99.7 %) https://community.cadence.com/cadence_blogs_8/b/cic/posts/spectre-optimizing-spectre-aps-performance 2 (99.7 %) 3 (99.7 %) 8/12 6/29/2020 Spectre Tech Tips: Optimizing Spectre APS Performance - Custom IC Design - Cadence Blogs - Cadence Community 4 (99.7 %) 5 (99.7 %) Time used: CPU = 10.8 ks (2h 59m 57s), elapsed = 18 ks (4h 59m 49s), util. = 60%. Tips for Further Performance Improvements Following are some tips that will enable you to enhance the performance of Spectre APS further after you have already followed the steps on how to resolve any setup issue. Using performance optimized DC For designs that take a long time in calculating the operating point, use the command-line option which provides a performance-optimized DC calculation. The option may cause minor degradation in the accuracy of the DC solution and is therefore not a solution for designs that are highly sensitive to an accurate DC solution. The option can also be set in the Environment Options form in Virtuoso ADE, as shown below. +dcopt +dcopt Changing simulation settings dynamically The dynamic parameter feature enables you to define different solver settings for different time windows. If your design has different accuracy requirements for different time windows, you can use the dynamic parameters to speed up the overall simulation. Dynamic parameters can be defined by selecting transient analysis (tran) in the Choosing Analyses form in Virtuoso ADE, as shown below. https://community.cadence.com/cadence_blogs_8/b/cic/posts/spectre-optimizing-spectre-aps-performance 9/12 6/29/2020 Spectre Tech Tips: Optimizing Spectre APS Performance - Custom IC Design - Cadence Blogs - Cadence Community Using the save/recover simulation state If multiple simulations have the same start-up sequence, you can use the and options to run the start-up sequence once, save the simulation state at the end of the start-up sequence, and then restart all other simulations based on the saved state. The value or the file can be set in the State File tab of the Transient Options form in Virtuoso ADE, as shown below. savetime savetime recover recover Using Spectre XPS MS If some portions of the design are digital, and you can afford some accuracy degradation on the digital blocks, you can improve the simulation performance by using Spectre XPS MS. Spectre XPS MS shares the use model with Spectre APS and enhances the performance by using the Spectre XPS FastSPICE tool for the digital portion of the design. The accuracy of the analog portion is still maintained by using the Spectre APS engine. Spectre XPS MS requires the power supplies of the digital blocks to be ideal voltage sources, otherwise, digital detection will require setting up voltage generator nodes and voltages. Spectre XPS MS can also be enabled in the High-Performance Simulation Options form in Virtuoso ADE, as shown below. Debugging Spectre APS Performance Issues https://community.cadence.com/cadence_blogs_8/b/cic/posts/spectre-optimizing-spectre-aps-performance 10/12 6/29/2020 Spectre Tech Tips: Optimizing Spectre APS Performance - Custom IC Design - Cadence Blogs - Cadence Community By utilizing the tips given above, you can address a majority of your Spectre APS performance issues. In addition, Spectre APS provides a simulation diagnostic mode, which can be enabled by using the command-line option, or the netlist option. The diagnostic mode analyzes the simulation statistics over the transient simulation time and reports detailed information on which signals/devices/elements cause convergence problems, time step reductions/rejections, and slow down simulation performance. The diagnostics mode can also be enabled in the Check tab of the Simulator Options form in Virtuoso ADE, as shown below. +diagnose +diagnose=detailed If you run into Spectre APS performance issues, which you cannot resolve, it is recommended that you run the simulation using the command-line option and discuss the diagnostics report with your Cadence support AE. +diagnose Related Resources Spectre Classic Simulator, Spectre Accelerated Parallel Simulator (APS), and Spectre Extensive Partitioning Simulator (XPS) User Guide Virtuoso ADE Explorer User Guide Getting the Most Out Of Spectre APS You may also contact your Cadence support AE for guidance. For more information on Cadence products and services, visit www.cadence.com. About Spectre Tech Tips Spectre Tech Tips is a blog series aimed at exploring the capabilities and potential of Spectre®. In addition to providing insight into the useful features and enhancements in Spectre, this series broadcasts the voice of different bloggers and experts, who https://community.cadence.com/cadence_blogs_8/b/cic/posts/spectre-optimizing-spectre-aps-performance 11/12 6/29/2020 Spectre Tech Tips: Optimizing Spectre APS Performance - Custom IC Design - Cadence Blogs - Cadence Community share their knowledge and experience on all things related to Spectre. Enter your email address in the Subscriptions box at the top of the page and click SUBSCRIBE NOW to receive notifications about our latest Spectre Tech Tips posts. Tags: Virtuosity: What's New in Run Plan – Part III Virtuosity: Introducing the Pin Tool Related Posts • Spectre Xplored - The New Spectre X Simulator • Spectre Tech Tips: Spectre Assert and Design Check Overview • Spectre Tech Tips: Spectre Local Options Connect with us © 2020 Cadence Design Systems, Inc. All Rights Reserved. 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