University of California, San Diego
Department of Electrical and Computer Engineering
ECE 283 – Power Management Integrated Circuits (PMICs)
Project Review 1
Content:
1. OBJECTIVE ...................................................................................................................... 1
2. PRESENTATION SLIDES (20-30 MINUTES PRESENTATION) ................................................ 1
3. REPORT .......................................................................................................................... 2
4. REFERENCE DESIGNS ...................................................................................................... 2
1. Objective
-
The objective of this proposal is to present
o a complete macro model simulation the converter,
o a complete optimization and switch sizing to achieve target efficiency, and
o some completed sub-blocks at the transistor levels and simulation including these
sub-blocks,
o a progress update and a plan how you are going to finish the project.
2. Presentation slides (20-30 minutes presentation)
-
-
Slide 1: Title of the project, your group name, group members and affiliation
Next 1-2 slides: Motivation for the topic – why do you need to design this converter?
Next 1 slide: Repeat specifications, possible discussions.
Next 1 slide: The converter topology (Buck or 3-level) you are developing and its
characteristics.
Next 1 slide: Block diagram of your converter.
Next 1-2 slide: A macro-/idealized-model simulations with idealized components in
analogLib library. (Refer to Lecture 4)
Next 1-3 slide: Converter simulations with idealized components for the control circuit
(amplifiers, PWM generator, etc.) but using practical transistor-level designs for the
following blocks:
o Power switches (sizes are optimized from a loss analysis)
o Gate driver circuits
o Level shifters
o Logic generation with deadtime control
o Show achievable efficiency.
o Note: this simulation can be open-loop if closed-loop stability is difficult to
achieve.
Next n slide, where n depends on the number of blocks in your system:
o Gate driver circuits
1
©Prof. Hanh-Phuc Le
hanhphuc@ucsd.edu
http://ipower3es.ucsd.edu/
o Level shifters
o Logic generation with deadtime control
-
o Target specifications, and progress if started, for other blocks.
▪ The specifications are set in consideration of the whole system, and
particularly the interface with other connected blocks, i.e., input/output pins,
signal range and other electrical specifications.
Next 1-2 slides: a timeline, e.g., a Gantt chart, that shows a complete projected plan with
task assignments, aiming at the project final review/report deadline.
o Make sure you assign team members to the tasks.
3. Report
-
The presentation slides.
4. Reference designs
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
G. W. Wester and R. D. Middlebrook, “Low-frequency characterization of switched DC-DC
converters,” in 1972 IEEE Power Processing and Electronics Specialists Conference, May
1972, pp. 9–20, doi: 10.1109/PPESC.1972.7094882.
E. A. Burton et al., “FIVR — Fully integrated voltage regulators on 4th generation Intel®
CoreTM SoCs,” in 2014 IEEE Applied Power Electronics Conference and Exposition - APEC
2014, Mar. 2014, pp. 432–439, doi: 10.1109/APEC.2014.6803344.
H. K. Krishnamurthy et al., “A 500 MHz, 68% efficient, fully on-die digitally controlled
buck Voltage Regulator on 22nm Tri-Gate CMOS,” in 2014 Symposium on VLSI Circuits
Digest of Technical Papers, Jun. 2014, pp. 1–2, doi: 10.1109/VLSIC.2014.6858438.
C. Schaef et al., “8.5 A Fully Integrated Voltage Regulator in 14nm CMOS with PackageEmbedded Air-Core Inductor Featuring Self-Trimmed, Digitally Controlled Variable OnTime Discontinuous Conduction Mode Operation,” in 2019 IEEE International Solid- State
Circuits Conference - (ISSCC), Feb. 2019, pp. 154–156, doi: 10.1109/ISSCC.2019.8662294.
Cheung Fai Lee and P. K. T. Mok, “A monolithic current-mode CMOS DC-DC converter
with on-chip current-sensing technique,” IEEE Journal of Solid-State Circuits, vol. 39, no.
1, pp. 3–14, Jan. 2004, doi: 10.1109/JSSC.2003.820870.
P. Hazucha et al., “A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing aircore inductors on package,” IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 838–
845, Apr. 2005, doi: 10.1109/JSSC.2004.842837.
Chi Yat Leung, P. K. T. Mok, Ka Nang Leung, and M. Chan, “An integrated CMOS currentsensing circuit for low-Voltage current-mode buck regulator,” IEEE Transactions on
Circuits and Systems II: Express Briefs, vol. 52, no. 7, pp. 394–397, Jul. 2005, doi:
10.1109/TCSII.2005.850403.
Xun Liu, Cheng Huang and P. K. T. Mok, "A 50MHz 5V 3W 90% efficiency 3-level buck
converter with real-time calibration and wide output range for fast-DVS in 65nm
CMOS," 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 2016, pp. 1-2, doi:
10.1109/VLSIC.2016.7573475.
2
©Prof. Hanh-Phuc Le
hanhphuc@ucsd.edu
http://ipower3es.ucsd.edu/
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
[18]
[19]
[20]
[21]
[22]
X. Liu, P. K. T. Mok, J. Jiang and W. Ki, "Analysis and Design Considerations of Integrated 3Level Buck Converters," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol.
63, no. 5, pp. 671-682, May 2016, doi: 10.1109/TCSI.2016.2556098.
L. Chu, S. Chen, K. Chen, Y. Lin, S. Lin and T. Tsai, "A Pseudo-Ramp Controlled Three Level
Buck Converter with an Auto-Ripple Cancellation Technique for Low Output Voltage
Ripple in Sub-Threshold Applications," ESSCIRC 2018 - IEEE 44th European Solid State
Circuits Conference (ESSCIRC), 2018, pp. 122-125, doi: 10.1109/ESSCIRC.2018.8494303.
Y. Karasawa, T. Fukuoka and K. Miyaji, "A 92.8% Efficiency Adaptive-On/Off-Time Control
3-Level Buck Converter for Wide Conversion Ratio with Shared Charge Pump Intermediate
Voltage Regulator," 2018 IEEE Symposium on VLSI Circuits, 2018, pp. 227-228, doi:
10.1109/VLSIC.2018.8502403.
G. Schrom et al., “A 100MHz Eight-Phase Buck Converter Delivering 12A in 25mm2 Using
Air-Core Inductors,” in APEC 07 - Twenty-Second Annual IEEE Applied Power Electronics
Conference and Exposition, Feb. 2007, pp. 727–730, doi: 10.1109/APEX.2007.357595.
P. Y. Wu, S. Y. S. Tsui, and P. K. T. Mok, “Area- and Power-Efficient Monolithic Buck
Converters With Pseudo-Type III Compensation,” IEEE Journal of Solid-State Circuits, vol.
45, no. 8, pp. 1446–1455, Aug. 2010, doi: 10.1109/JSSC.2010.2047451.
S. Bandyopadhyay, Y. K. Ramadass, and A. P. Chandrakasan, “20 μ A to 100 mA DC–DC
Converter With 2.8-4.2 V Battery Supply for Portable Applications in 45 nm CMOS,” IEEE
Journal of Solid-State Circuits, vol. 46, no. 12, pp. 2807–2820, Dec. 2011, doi:
10.1109/JSSC.2011.2162914.
S. S. Kudva and R. Harjani, “Fully-Integrated On-Chip DC-DC Converter With a 450X
Output Range,” IEEE Journal of Solid-State Circuits, vol. 46, no. 8, pp. 1940–1951, Aug.
2011, doi: 10.1109/JSSC.2011.2157253.
V. Yousefzadeh, E. Alarcon, and D. Maksimovic, “Three-level buck converter for envelope
tracking applications,” IEEE TPEL, vol. 21, no. 2, Mar. 2006,
G. Villar and E. Alarcon, “Monolithic integration of a 3-level DCM-operated low-floatingcapacitor buck converter for DC-DC step-down conversion in standard CMOS,” in 2008
IEEE PESC, Jun. 2008.
W. Kim, D. Brooks, and G. Y. Wei, “A Fully-Integrated 3-Level DC-DC Converter for
Nanosecond-Scale DVFS,” IEEE JSSC, Jan. 2012.
R. Das, et. al, “Demystifying Capacitor Voltages and Inductor Currents in Hybrid
Converters,” in 2019 20th Workshop on Control and Modeling for Power Electronics
(COMPEL), Jun. 2019.
P. Mahmoudidaryan, et. Al , “27.5 A 91%-Efficiency Envelope-Tracking Modulator Using
Hysteresis-Controlled Three-Level Switching Regulator and Slew-Rate-Enhanced Linear
Amplifier for LTE-80MHz Applications,” in 2019 (ISSCC), Feb. 2019.
D. Ma, et. al, “Single-inductor multiple-output switching converters with timemultiplexing control in discontinuous conduction mode,” IEEE JSSC, Jan. 2003
H.-P. Le, et. al, “A Single-Inductor Switching DC–DC Converter With Five Outputs and
Ordered Power-Distributive Control,” IEEE JSSC, Dec. 2007.
3
©Prof. Hanh-Phuc Le
hanhphuc@ucsd.edu
http://ipower3es.ucsd.edu/