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EEX5536 Computer Architecture Assignment

The Open University of Sri Lanka
Department of Electrical and Computer Engineering
TMA 01
EEX5536 Computer Architecture
Academic Year:
Academic and Course Coordinator:
Contact Details:
2021 – 2022
N. A. R. Priyanka
Tel: 011 2881483; Email: napri@ou.ac.lk
Information for ASSIGNMENTS
Assignments, information, and all correspondence for this course will be available in LearnOUSL.
Preparation of answers to assignments
Answer all the questions in each assignment. Answers should be clear, readable and of high
quality. Unclear, unreadable, copied and direct reproduction from textbooks will not gain any
points for your answers. Use only one side of A4 paper or use PDF file format for electronic
Instructions for submission of assignment
Upload your answers to the assignment drop box of Course Content & Activities of Moodle.
Course coordinator will acknowledge about viva schedule.
Structure of Assignments
Each assignment will cover a specific area of the syllabus. There are no theoretical questions in
assignments. However, some questions are included to work out where you can demonstrate
your ability of applying your theoretical knowledge to solve problems. Further you should be
able to show your analytical skills when answering assignments.
Evaluation method of assignments
Answers for each assignment will be evaluated by a viva and marks will be given according to
the answers you give at the viva. Though there are no descriptive theory based specific
questions, coordinator may ask some questions covering the study area relevant to that
assignment. There you have to describe theory as well as to show your ability to apply them
analytically for solving the problem.
TMA 01 2021/2022
The Open University of Sri Lanka
Department of Electrical and Computer Engineering
ASSIGNMENT 1. Academic Year 2021/2022
Due date: 04/07/2022 (MON)
Answers for the assignment will be evaluated by viva which will be notified in due course.
In this assignment we will cover the following topics:
Performance of a computer: performance models such as CPI, IPC; Means and weighted
means; Amdahl’s law; steady state performance, evaluating processor/ computer system
Instruction Set Architectures: Different ISAs: stack, accumulator, register, memory-memory;
RISC vs. CISC architectures; analyse different ISA of commercially available processors; how to
access instructions and operands from the memory, Addressing Modes, compare addressing
modes in different processors; identify different categories of instructions; types & size of
operands; Encoding of an instruction; design an ISA for given a requirement.
Pipelining: Instruction-level parallelism; classification of pipeline processing, parallelism vs.
pipelining, performance issues in pipelining; pipeline partitioning; bottleneck of a pipeline,
replication, and subdivision stages; static/dynamic pipelines.
More sections in pipelining will be covered in the 2nd assignment.
After learning the above topics answer the following questions indicating the relevant theoretical
background for your answer.
Question 01
Now a days we input almost everything to the computer system. As an undergraduate computer
engineering student, you are asked to demonstrate to the school children how these inputs
recognise by computer. Your task is to select one input and show all the physical path integrating
the components using appropriate diagrams. You need to clearly show your selected input
device, how it connects with computer and all the signal path (inside motherboard) when
communicate with CPU, and input recognition process. Please show your demonstration using
PowerPoint presentation and appropriate diagrams with clear explanation.
Question 02
Design and present all the components in the computer processor (8086) and memory to execute
an instruction (Refer 8086 Instruction Set Architecture) using an advance power point
presentation or flash presentation. You must clearly show all the steps in an instruction cycle
(Instruction fetch, Instruction decode, Instruction execute, Memory and Write-back) and mention
all the registers that involve in instruction processing. You should demonstrate your presentation
during the TMA 01 viva session.
TMA 01 2021/2022
The Open University of Sri Lanka
Department of Electrical and Computer Engineering
Question 03
i.) Describe the Flynn's classification (SISD, SIMD, MISD and MIMD) on computer
organisation giving block diagrams for each organization.
ii.) A SIMD computer has 8 synchronized processor elements (PE) which are connected to each
other via interconnection network. Each PE has a set of working registers and a data-routing
register R to transfer and to receive data to and from other PEs.
a) Design an algorithm for the SIMD computer to calculate the sum of an array (A) of 8
elements. Assume that element Ai is stored in the local memory of PEi, where i = 1, 2,
3, ..., 8.
b) Briefly describe how the control unit of the SIMD computer controls the PEs according
to your algorithm.
Question 04
A design of an instruction execution path has 𝐿 logic delays. So it will take 𝐿 time to execute an
instruction in one-stage pipeline. However, the logic path can be divided into a number of stages.
In the multistage pipeline it is assume that logic delay 𝐿 is equally subdivided. Accordingly in
each stage the minimum clock period is calculated as
𝑇𝑐𝑙𝑜𝑐𝑘 = 𝑡𝑚𝑎𝑥 + 𝜏; where 𝑡𝑚𝑎𝑥 is approximated to the largest delay of a stage and 𝜏 is the
sum of setup time of a latch and clock skew. Let 𝑘 as the length of the instruction sequence and 𝑠
as the number of stages.
(i) What is the clock period 𝑇𝑐𝑙𝑜𝑐𝑘 in terms of 𝑳, 𝒔 and 𝝉?
(ii) What is the execution time of the 𝒌 number of instructions?
(iii) Derive an equation to calculate the optimum number of stages in the pipeline?
(iv) Prove the minimum execution time of 𝒌 number of instructions is (√𝑳 + √𝝉(𝒌 − 𝟏) )𝟐
Question 05
1. An enhancement in a computer system improves only some part of the system. Accordingly,
improvement of the performance depends on the impact of the enhancement part. The f denotes
the fraction of the computational time in the old system that can be improved with the
enhancement mad; Se is the achievable speedup only if the enhanced part of the system is used.
(i) If the old time of the system (without improvement) is Told formulate the new time Tnew
of the system after the enhancement.
(ii) The speedup of the new system (after the improvement) is
TMA 01 2021/2022
The Open University of Sri Lanka
Department of Electrical and Computer Engineering
𝑆𝑛𝑒𝑤 =
Accordingly derive an equation for Snew in terms of f, Se, which is Amdahl’s law.
(iii) Implementations of floating-point (FP) square root vary significantly in performance.
Suppose FP square root is responsible for 20% of the execution time of a critical
benchmark on a machine. One proposal is to add FP square root hardware that will speed
up this operation by a factor of 10. The other alternative is just to try to make all FP
instructions run faster; FP instructions are responsible for a total of 50% of the execution
time. The design team believes that they can make all FP instructions run two times faster
with the same effort as required for the fast square root.
a. Compare these two design alternatives giving all calculations.
b. What percentage of the FP instructions’ execution time would make the hardware
solution better?
Recommended reading
These books are available in the library.
Computer Architecture & Implementation, Havey G Cragon, Cambridge University Press
Computer Architecture a Quantitative Approach, 2nd edition, David A. Patterson, John L.
Computer architecture and organization, John Hayes,McGraw-Hill Science, 2nd edition
IEEE Computer
IEEE Micro
IEEE Transaction on Computers
Online resources
a. www.cs.wisc.edu/~arch/www
TMA 01 2021/2022