On Chip Variations(OCV)
1.During fabrication the chips on the same Die may suffer from variation due to process, voltage and temperature.
2.Due to this some of the cells/transistor operate in slow or fast mode because of all the cell/transistor does not have the
identical properties.
3.Hence while using the different dies on a chip the timing violation are occurs in the chip.
4.Due to variation in the timing paths of the system the Setup and Hold time violations are occurs which are more use in the
capture the data.
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The following are the sources of the variation in the chip
1.Etching: defines the structure of the cells/transistor
2.Oxide thickness: which controls the drain current.
There are two types of variation
i.
Global variation : Die to Die variations, they depends on the process,voltage and temperature.
ii.
Local variation :These variations are intra-chip variations, and local variations are taken by timing derates which are
multiplying the cell delays and wire delays to account OCV
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Advance On Chip Variations(AOCV)
1.In case of OCV constant derates are applied across the timing path.
2.But in the AOCV we can multiply the cell and the wire delays with different derates factors .
3.The AOCV works depending upon the distance and depth.
4.For smaller path depth the ocv gives optimistic results compare to the AOCV.
5.For long path depth the OCV tends to be more pessimistic then AOCV that is AOCV gives more accurates results.
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Parametric On Chip Variations(POCV)
1.At the very low node technology the AOCV cannot reduces pessimism.
2.To reduce variation in cell delay we go for POCV.
3.POCV models a cell delay using the Gaussian distribution instead of adding a derate value.
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