146
IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 23, NO. 3, MARCH 2013
A Back-Gate Coupling Quadrature Voltage-Control
Oscillator Embedded With Self Body-Bias Schema
Janne-Wha Wu, Member, IEEE, Han-Hsin Wu, Kai-Cheng Hsu, Student Member, IEEE, and Chang-Chun Chen
Abstract—A quadrature voltage-controlled oscillator was
designed with back-gate coupling and embedded self body-bi1P6M CMOS
asing and implemented with the TSMC 0.18
technology. Without using any extra negative bias-pin in the current-reuse structure, this embedded body-bias schema makes the
switching transistors become forward body-biased in the duration
of turn-on. It is not only beneficial for low-voltage operation,
but also achieves a high oscillating output power (
)
with less supply power (2.5 mW). The percentage of frequency
tuning range is 17.5% (from 4.60 to 5.48 GHz). The phase noise
is
at 1-MHz offset from the carrier frequency of
5.48 GHz.
Index Terms—Back-gate coupling, CMOS, current-reuse,
quadrature voltage-controlled oscillator (QVCO).
I. INTRODUCTION
S
YNTHEESIS of quadrature (“I” and “Q”) signals is prerequisite for the implementation of CMOS transceiver
with image-rejection (low-IF) or direct conversion (zero-IF)
architecture. The most commonly used quadrature voltage-controlled oscillator (QVCO) employs two voltage-controlled
oscillators (VCOs) of symmetrically gate-modulated LC-tank
to cross-couple to each other. The way of coupling between
these two VCOs can be in parallel [1] or in series [2]. Parallel-coupled one usually shows bad phase noise and takes
higher power consumption [2]. Series-coupled one requires
more supply voltage headroom and is unsuitable for low-voltage
operation. In the aspects of phase noise and power dissipation,
the presence of the additional coupling transistors used for
quadrature coupling between two differential VCOs is inferior.
One approach to achieve quadrature coupling without additional coupling transistors is transformer-feedback. A feedback
coupling method by an on-chip transformer [3] is capable
for low voltage operation, but behaves with narrow frequency
tuning range. At the same time, there were some efforts devoted
to the study of back-gate (body) coupling [4] in QVCO. No
extra transistor is used for the quadrature coupling between
two differential VCOs. Therefore, the penalty of the additional
Manuscript received October 25, 2012; accepted January 10, 2013. Date of
publication February 22, 2013; date of current version March 07, 2013. This
work was supported in part by the National Science Council of Taiwan under
Grant NSC 99-2622-E-194-006-CC3.
J.-W. Wu is with the Department of Communications Engineering and Department of Electrical Engineering, National Chung Cheng University, Chia-Yi
62102, Taiwan (e-mail: jwwu@ee.ccu.edu.tw).
H.-H. Wu, K.-C. Hsu, and C.-C. Chen are with the Department of Electrical
Engineering, National Chung Cheng University, Chia-Yi 62102, Taiwan.
Color versions of one or more of the figures in this letter are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LMWC.2013.2242325
coupling transistor over the phase noise is removed and also the
power consumption is reduced due to fewer transistors being
used in the chip. Another way to reduce the power consumption
is the current-reuse topology that uses series stacking of Nand P-MOSFETs [5]. In [6], a back-gate coupling QVCO with
current-reuse structure was demonstrated. However, it uses
two different external dc voltages
and
for the
body bias and then the body bias would be fixed to forward
or reverse such that the threshold voltage is also fixed. This
letter proposes a QVCO topology employing an embedded self
body-bias to enhance the current driven ability of the switching
transistor without using any extra bias pin and negative voltage
supply. Meanwhile, higher oscillating output power is available
even with less dc power consumption. This feature is good for
the frequency synthesizer to play the role of LO supplier. The
proposed circuit was implemented with the TSMC 0.18 mm
1P6M CMOS technology.
II. PROPOSED QVCO DESIGN
Fig. 1 is the schematic drawing of the proposed QVCO. It
adopts two pairs of series connected P-/N-MOS switching transistors ( and
- ). Each pair of switching transistors
with LC tank (
and ) constitutes a current-reused differential VCO. Two pairs of MOS-varactors are used in the LC tank.
The body of switching transistor is not only tied to the drain
node of itself through a resistor, but also connected to the drain
node of another switching transistor via a capacitor. Therefore,
the body of each switching transistor also plays as the quadrature-phase coupling node. The corresponding node voltages and
the drain current around the transistor
as circled with dashed
line in Fig. 1 are shown in Fig. 2.
In this design,
is not fixed-biased, but dynamically varied.
It is simultaneously dependent on the drain voltage of
itself
( ) and that of
(
). The relationship between them can
be expressed as
(1)
For the operation of MOSFET, the threshold voltage (
) not only depends on the
,
body-effect coefficient and the substrate’s Fermi potential
. In the dashedbut also varies according to the body voltage
becomes
arrow-line region II of Fig. 2, it is clearly seen that
becoming higher than
. It reforward body-biased as
. More oscilsults in the reduction of the threshold voltage
lating current and voltage headroom is available at this moment.
Higher oscillating current is beneficial for the achievement of
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WU et al.: A BACK-GATE COUPLING QUADRATURE VOLTAGE-CONTROL OSCILLATOR EMBEDDED WITH SELF BODY-BIAS SCHEMA
147
Fig. 3. Chip photograph of the proposed QVCO. (Size: 1.25
including pads).
0.677
,
Fig. 1. Schematic of proposed back-gate-coupled and self-body-biased QVCO
).
(If not specified in the figure, the transistor gate length is 0.18
Fig. 4. Tuning ranges of proposed QVCO.
Fig. 2. The simulated node voltages and drain current of transistor
cled with dashed line in Fig. 1.
as cir-
higher oscillating power. In the region I & III,
or
being
less than
, the drain current is suppressed.
Ideally, the current-reuse structure should have NMOS
clearly shutdown outside the dashed-arrow-line region of
Fig. 2. Compared with the fixed body-biasing, the NMOS body
of the proposed topology happens to be reverse-biased and
also becomes lower in this duration. Consequently, the current
flow is suppressed more due to the increase of
. Similarly,
it also applies to the operation of PMOS. So, this embedded
body-bias schema can save the dc power consumption more
than that of the conventional current-reuse structure with fixed
body-bias.
In this asymmetric structure, the coupling strength must be
set by properly choosing the transistor sizes, the values of the
capacitors (
) and the resistors (
). The coupling strength will impact on the phase error and phase noise
significantly. The resistors should be large enough to prevent
from the coupling signal passing through it. Different resistor
values are used for NMOS and PMOS so as to adjust the coupling strength. In order to clarify that the dynamic body bias
will not worsen the phase noise too much, the source resistive
degeneration technique [7] was not used in this design.
Fig. 5. Measured phase noise at
frequency : 5.48 GHz).
and
(carrier
III. EXPERIMENTAL RESULTS
The chip photograph of the proposed QVCO is shown in
Fig. 3. The chip area is 0.85
(1.25 0.677
) including
pads. This circuit was fabricated by the TSMC 0.18
1P6M
CMOS technology. As shown in Fig. 4, the proposed QVCO
can be tuned from 4.60 to 5.48 GHz with the control voltage
from 1.7 V to 0 V. The total tuning range available is 840 MHz
(17.5%). Fig. 5 shows the simulated and measured phase noise
at the frequency of 5.48 GHz. The measured phase noise is
at 1 MHz offset from the carrier frequency of
5.48 GHz.
Although the current swing is large but distorted due to the
time-varied threshold voltages and node-voltages, as checking
the spectrum, all of the undesired harmonics are more than
20 dB below the fundamental one. The simulated phase error
is 1.6 . The measured one after calibration is around 5 . By
analyzing with simulation, phase error can be improved by
properly choosing the PMOS/NMOS feature size, the resistors
(
) and the capacitors (
) to minimize the
imbalance of coupling strength.
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148
IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 23, NO. 3, MARCH 2013
COMPARISON
OF
TABLE I
QVCOS’ PERFORMANCE.
Table I summarizes the major performances of the proposed
QVCO compared to those of some reported QVCOs in the frequency range of 5 to 7 GHz. Most of the reported results about
the VCO output power are the direct readings after the output
buffers [9]–[11]. In order to spotlight the output power ability
of the core circuit, the buffer stage in this study is intentionally
designed with no gain. Since the measured oscillating output
power after the buffer stage is
(
), the
output power of this QVCO core circuit definitely equals to
. Hence, a marking “0 dB buffer gain” is specified
in the Table I to discriminate this data from other works. The
core circuit takes 2.5 mW from 1 V power supply. Even though
the contribution of buffer stage is not taken into consideration,
it shows better conversion efficiency between output power and
dc power consumption. The overall performance is evaluated by
three different figure-of-merits (FoM) in Table I. The 2nd and
3rd ones (FoM_P & FoM_PTR) take more considerations over
the factors of output power and tuning range in percentage.
IV. CONCLUSION
In the RF circuit integration, the output power of VCO
must meet the requirement of mixer’s LO input. Although the
addition of buffer amplifier can well support the requirement of
LO input, it should be fair to include the power dissipation of
the buffer amplifier into the overall power consumption. On the
other hand, any effort devoted to the output power enhancement
of VCO core circuit will bring about new challenges on the
phase noise and the dc power dissipation. This is the reason
why FoM_P and FoM_PTR are referred in Table I. Two works
[8], [12] referenced in Table I have the same or better FoM
performance than this structure under the considerations of
output power and tuning range. Both of them use four sets
of PMOS/NMOS pair in parallel. As a consequently, they
take more dc power consumption than this work. But, more
flexibility is available for them to achieve good phase noise. In
this work, two sets of PMOS/NMOS pair are used in parallel.
An embedded body bias schema simplifies the body bias. No
external body bias is required and the adjustment of
is
dynamic. A dynamic threshold voltage adjustment makes this
circuit be beneficial for high oscillating current and less current
consumption as the current-reuse structure being in off stage.
ACKNOWLEDGMENT
The authors would like to thank the Staff of the Chip Implementation Center (CIC) for their support on the chip fabrication
and measurement.
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