Through Silicon Vias – a 3D Electronic Packaging Technology Thomas Fritzsch, Piotr Mackowiak, Kai Zoschke Fraunhofer IZM, Berlin, Dept. Wafer Level System Integration CERN EP-ESE Electronics Seminars, April 12th, 2022 CERN EP-ESE Electronics Seminars, April 12th, 2022 Outline • • • • • • • • CERN EP-ESE Electronics Seminars, April 12th, 2022 Advanced Electronic Packaging 3D/2.5D Package for High-End Performance Applications CPU/GPU HBM Interposer IC Substrate PCB Datacenter Networking High-Performance Computing Autonomous Vehicles CERN EP-ESE Electronics Seminars, April 12th, 2022 Electronic Packaging Front-End Wafer Manufacturing „Middle End“ Wafer Level Packaging Back-End Assembly & Test Advanced Packaging Implant PVD CVD Etch Cleaning Wafer test RDL / wiring Bumping 2.5D Interposer 3D TSV FO-WLP W2W Bonding CERN EP-ESE Electronics Seminars, April 12th, 2022 C2C, C2S Bonding Underfill Molding Test “Middle End” Wafer Level Packaging – System Integration 2D Wafer Level Packaging Fine Pitch Bumping Redistribution 2.5D System Integration 3D System Integration TSV Silicon Interposer Integrated Passives Chip Embedding Complexity / Functionality / Integration CERN EP-ESE Electronics Seminars, April 12th, 2022 TSV active IC Outline • • • • • • • • CERN EP-ESE Electronics Seminars, April 12th, 2022 TSV Geometry - Landscape 450 Ø40 AR3 Ø20 AR5 400 Ø20 AR5 Via Depth / µm 350 Ø10, AR10 300 Aspect Ratio 250 AR2 200 AR5 150 AR10 Interposer via middle Via last frontside Ø5,AR12 Via Backside 100 50 0 CVD (Cu, W) Via middle via last Cu liner ECD fill Via first, middle 5 10 20 40 Via Diameter / µm 80 CERN EP-ESE Electronics Seminars, April 12th, 2022 160 AR15 TSV Integration Schemes Via middle Front Side - Via last Back Side - Via last TSV integration after complete wafer processing Requires TSV adapted landing pad design in BEOL for TSV connection TSV integration after FEOL / before BEOL Processes established at IDMs, in production for HBM stacks TSV integration after complete wafer processing TSV through thick BEOL oxide Requires keep out zones in FEOL and BEOL for TSV integration Support wafer bonding Wafer backside thinning TSV reveal Backside RDL and bump formation Support wafer de-bonding CERN EP-ESE Electronics Seminars, April 12th, 2022 Support wafer bonding Wafer backside thinning TSV formation with access to landing pads Metall liner and back side RDL formation Support wafer de-bonding Basic Process Steps of TSV Formation – TSV Frontside – Via Last 11. Passivation 1. TSV blind hole etch and isolation 12. BGA Bump Pad Formation 2. TSV filling 3. Front side RDL 9. Passivation Opening 4. Front Side Passvation / IO Formation 10. Back Side RDL 5. Temporary bonding 7. TSV Reveal 6. Si- wafer thinning 8. Back Side Passivation © DISCO CERN EP-ESE Electronics Seminars, April 12th, 2022 Front Side Via Last Integration Examples for Keep Out Zones (KOZ) for TSV Integration into CMOS Wafers CERN EP-ESE Electronics Seminars, April 12th, 2022 Front Side Via Last – Principal Process Flow – CMOS Side Process 1 • Start at CMOS Wafer • TSV formation by lithography and oxide + silicon dry etching • TSV isolation by SACVD 2 • Barrier + seed layer deposition by PVD (HIS) • Copper filling by ECD + Annealing 3 • Copper CMP • Seed Layer Etching 4 • Passivation opening over original IO pads by lithography + oxide dry etching 5 • RDL formation by semiadditive or subtractive structuring of metal 6 Copper filled TSVs in CMOS wafer • Passivation by polymer or PECVD Oxide • Pad formation by sputtering + lithography + ECD CERN EP-ESE Electronics Seminars, April 12th, 2022 Front Side Via Last – Principal Process Flow – Backside Process 7 • Coating of adhesive layer onto front side of TSV wafer / adhesive cure • Temporary bonding to carrier wafer • Back grinding + polish + dry etching • Back side passivation by PECVD 8 9 • Back side passivation opening by lithography + dry etching or mask less by CMP • RDL formation by semi-additive or subtractive structuring of metal • Passivation by polymer or PECVD Oxide • Pad formation by sputtering + lithography + ECD CERN EP-ESE Electronics Seminars, April 12th, 2022 Front Side Via Last – Principal Process Flow – Backside Process 7 • Coating of adhesive layer onto front side of TSV wafer / adhesive cure • Temporary bonding to carrier wafer • Back grinding + polish + dry etching • Back side passivation by PECVD 8 9 • Back side passivation opening by lithography + dry etching or mask less by CMP • RDL formation by semi-additive or subtractive structuring of metal • Passivation by polymer or PECVD Oxide • Pad formation by sputtering + lithography + ECD CERN EP-ESE Electronics Seminars, April 12th, 2022 Basic Process Steps of TSV Formation – Back Side Via Last 8. Backside Passivation and Bond Pad UBM 1. Frontside process / carrier wafer bonding 2. Si- wafer thinning 3. TSV silicon etching DRIE BOSCH Process © DISCO 7. TSV Cu filling + RDL Cu by ECD 6. Barrier-/Seed-Layer Ti (TiW, TiN, Ta(N)) / Cu HI-PVD 4. TSV and wafer surface oxide passivation TEOS, PE-CVD, SA-CVD 5. Oxide Etch at via bottom CERN EP-ESE Electronics Seminars, April 12th, 2022 Deep Reactive Ion Etching (DRIE) in Silicon Deep Reactive Ion Etching (DRIE) Bosch Process Switched Process Image: SPTS CERN EP-ESE Electronics Seminars, April 12th, 2022 Image: IZM Chemical Vapor Deposition (CVD) – TSV Passivation Basics Silicon-oxide / Silicon-nitride Deposition Thermal Oxidation Temperatures: 700-1250°C (Batch) O2 / H2 + O2 LPCVD (Low Pressure Chemical Vapor Deposition) Temperatures: 700-900°C (Batch) SiH4, N2O, SiH2Cl2 SACVD (Sub Atmospheric Chemical Vapor Deposition) Temperatures: 350-600°C (Single Wafer) TEOS, O3 PECVD (Plasma Enhanced Chemical Vapor Deposition) Temperatures: 100-400°C (Single Wafer) TEOS / SiH4, N2O CERN EP-ESE Electronics Seminars, April 12th, 2022 CVD – TSV Passivation: Layer Conformity Silicon-oxide / Silicon-nitride Thermal Oxidation Conformity: High μ μ PECVD Silan SiO2 6% min coverage LPCVD (Low Pressure Chemical Vapor Deposition) Conformity: High Excellent electrical properties <200°C AR < 2 : 1 SACVD (Sub Atmospheric Chemical Vapor Deposition) Conformity: Medium PECVD (Plasma Enhanced Chemical Vapor Deposition) Conformity: low-medium PECVD TEOS SiO2 30% min coverage Up to 5x step coverage Increased temperature (vs. Silane) CERN EP-ESE Electronics Seminars, April 12th, 2022 Back Side Via Last – Critical Steps - Oxide Layer Plasma Etching CERN EP-ESE Electronics Seminars, April 12th, 2022 Back Side Via Last – Critical Steps - TSV-Filling by Electroplating Cu filling – bottom up: Copper base chemistry Additives: accelerator, inhibitor Cu electrolyte with bottom up filling behavior TSV size <5…20µm diameter Cu Si-Substrat - Cu2+ - Inhibitor - Accelerator Cu liner filling: Conformal Cu plating behavior Similar to RDL plating TSV size 20… >100µm diameter TSV backside - via last process CERN EP-ESE Electronics Seminars, April 12th, 2022 Back Side Via Last – Critical Feature - Oxide Layer Integrity CERN EP-ESE Electronics Seminars, April 12th, 2022 Back Side Via Last – Critical feature – Landing Pad Structure MEDIPIX3 meshed Cu landing pad structure Increase robustness of the oxide etch process window Modified M1 landing pad design in TIMEPIX4 CERN EP-ESE Electronics Seminars, April 12th, 2022 TSV Passivation - Electrical Properties breakdown voltage as a function of oxide layer thickness Oxide layer thickness 1 µm … 5µm TEOS based Oxide deposited at 175°C TEOS based Oxide deposited at 175°C Breakdown Voltage [V] Breakdown Voltage [V] breakdown voltage as a function of TSV Diameter Via diameter 10…120µm Oxide Layer Thickness Via Diameter CERN EP-ESE Electronics Seminars, April 12th, 2022 Cu filled TSV - Electrical Properties [T. Fritzsch et al. 2022 JINST 17 C01029] CERN EP-ESE Electronics Seminars, April 12th, 2022 Ω Outline • • • • • • • • CERN EP-ESE Electronics Seminars, April 12th, 2022 2.5D Integration - Silicon Interposer TSV micro-channel micro sealing: 2 half-shells forming a microchannel cooler • Interposer on 200mm wafer • Cu-TSV density > 10000/cm² • 42,459 TSVs per Device fluid port micro-channel CERN EP-ESE Electronics Seminars, April 12th, 2022 Cu/Sn TLPB W2W bond or AuSn TLPB W2W bond micro-seal (TSV connection) Glass Interposer with Through Glass Vias (TGV) CERN EP-ESE Electronics Seminars, April 12th, 2022 Readout Electronic with TSV in HEP and X-ray Imaging Standard camera module with wire bond connection: Wire bonds Sensor ROC TSV Sensor Gaps between the modules due to wire bonding area PCB Loss of image information ROC Sensor Sensor ROC ROC PCB Camera module with TSV: Gap-less full area image Four side stitchable module matrix arrangement possible CERN EP-ESE Electronics Seminars, April 12th, 2022 TSV Frontside – Via Last Process: Ultra Fast Xray Pixel Matrix Chip UFXC32k Readout Chip developed by AGH Crakow, Poland Cross section of Bare Module, with Cu filled TSVs in ROC Kai Zoschke et al. “Fabrication of 3D Hybrid Pixel Detector Modules Based on TSV Processing and Advanced Flip Chip Assembly of Thin Read Out Chips”, ECTC 2017, Lake Buena Vista, Florida, May 30 to June 2, 2017. Silicon Bare Module, with sensor and two UFXC32k TSV-ROCs X-ray Detector Module: Sensor + TSV-ROC + LTCC Board; x-ray image of chip package CERN EP-ESE Electronics Seminars, April 12th, 2022 TSV Back Side – Via Last Process: ATLAS FE-I4 Readout Chip • • • • • • • • • • CERN EP-ESE Electronics Seminars, April 12th, 2022 ATLAS FE-I4 TSV - Hybrid Module Assembly • • • • • CERN EP-ESE Electronics Seminars, April 12th, 2022 ATLAS FE-I4 TSV - Bare Chip and Hybrid Module Test • • • • • • F. Hügging et. al., Advanced Through Silicon Vias for Hybrid Pixel Detector Modules, DOI: 10.1016/j.nima.2018.08.067 CERN EP-ESE Electronics Seminars, April 12th, 2022 TSV Back Side – Via Last Process: MEDIPIX3 Readout Chip • • • • • • • • • • CERN EP-ESE Electronics Seminars, April 12th, 2022 MEDIPIX3 TSV Module - Test on Evaluation Board MEDIPIX TSV Module Test MEDIPIX3 TSV Hybrid Module Standard PCB technology Size: 64mm x 67mm Terminating resistors and decoupling capacitor on the board Samtec connector 28 pin pairs Bump bonding (BGA) between Mpx3 chip and PCB Imaging with Medipix3RX TSV module: PCB sample imaged with X-ray tube, Mo target, 51 kV and 31 mA, 100 s exposure, flat-field corrected, presented on linear scale where black color is zero counts and white is the maximum (left) Background radiation after 30 min exposure time, white pixels have zero counts and black have one count (right). Milija Sarajlić, David Pennicard, Sergej Smoljanin, Thomas Fritzsch, Kai Zoschke, Heinz Graafsma: „Progress on TSV technology for Medipix3RX chip”; IWORID 2017, Cracow, July 2017. CERN EP-ESE Electronics Seminars, April 12th, 2022 TIMEPIX4 TSV Process Evaluation – Preliminary Status • • • • • • • • • • • • • • CERN EP-ESE Electronics Seminars, April 12th, 2022 Outline • • • • • • • • CERN EP-ESE Electronics Seminars, April 12th, 2022 Ultra Thin Hybrid Pixel Detectors Backside RDL with interconnect pads Active R/O DMAPS active sensor CERN EP-ESE Electronics Seminars, April 12th, 2022 3D TSV Advanced Packaging Applications 3D Stacking - HBM Active Interposer CERN EP-ESE Electronics Seminars, April 12th, 2022 Sensor / MEMS Industry Technology Trend: Processor Chiplet Assembly on Active Interposer CERN EP-ESE Electronics Seminars, April 12th, 2022 Industry Technology Trend: Photonic Integration Technology Tolga Tekin, Fraunhofer IZM New technological paths for high performance chips targeting HPC and edge, EXDCI Workshop, Brussels, 05. - 06.11.2019 CERN EP-ESE Electronics Seminars, April 12th, 2022 Summary CERN EP-ESE Electronics Seminars, April 12th, 2022 thank you for your attention Thomas Fritzsch Fraunhofer IZM, Berlin, Dept. Wafer Level System Integration Email: thomas.fritzsch@izm.fraunhofer.de Phone: +49 (0)30 46403 681 CERN EP-ESE Electronics Seminars, April 12th, 2022
