Low Power Digital Circuit Design
S. Qureshi
Department of Electrical Engineering
Indian Institute of Technology Kanpur
Kanpur-208016
India
6/24/2023
S Qureshi
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Low Power Circuit Design
 Motivation
 Historical perspective
 Sources of power dissipation
Low power design methodology
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Motivation - Why Low Power Design?
• Need for low power chips in industry
- Low power Consumer electronics is powered by batteries
- Craving for smaller, lighter and durable electronic products which
translates into low power chip design
- Battery life is a differentiator in many electronic products
- Growth experienced by portable systems not been matched by
growth in battery technology, therefore need to reduce energy
consumption in chips
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Motivation- Why Low Power Design?
• Need low power chips for high performance computing
- High performance computing systems characterized by large power
dissipation also drives low power needs
- A typical computing server can consume as high as 20 KW in server
farm
- Power dissipation having direct impact on packaging cost of chip
and cooling cost of system
- Low power methodologies needed to reduce packaging and cooling
cost
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Power Density (W/cm2)
10000
1000
100
Why Low Power Design?
Rocket
Nozzle
Nuclear
Reactor
8086
10 4004
Hot Plate
P6
8008 8085
Pentium® proc
386
286
486
8080
1
1970
1980
1990
2000
2010
Year
Power density too high to keep junctions at low temp
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Courtesy, Intel
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Motivation- Why Low Power Design?
• Reliability of a Silicon chip
- Reliability of chip closely related to power dissipation
- Every 10 degree Centigrade rise in temperature doubles failure rate
• Need low power chips to address environmental concern
-
Large office equipment consumes huge power
Computers are fast growing electricity loads
7% of energy is consumed in office equipment in the US
Electricity generation is major source of air pollution
Efficient energy usage in computers is highly desirable
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Historical Perspective
•
•
•
•
•
•
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Pocket calculators
Hearing aids
Implantable pace makers
Portable military equipment
Wristwatches
Portable computing
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Recent Advances in Low Power Applications
•
•
•
•
•
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Multi-media
Video display and capture
Audio reproduction
Notebook computing
Cell phones
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Sources of Power Dissipation
Sources of Power dissipation
 Dynamic Power
• Switching power
• Short circuit power
• Glitching power
 Static power
•
•
•
•
Reverse biased PN junction diode leakage
Subthrehold leakage current
Gate leakage current
Other effects !
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Dynamic Power dissipation
• Charging of Capacitance
- Applying a step input, Energy drawn from source
R
V
t
E01   p (t ) dt
0
t
  v i dt
0
V
dvC
E01  V  C
dt
0
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C
1
EC  C V 2
2
dt  C V 2
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Dynamic Power dissipation
• Charging of Capacitance
- Energy stored in capacitor
R
V
t
EC   p (t ) dt
0
t
  v i dt
0
V
dvC
  vC C
dt
0
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C
1
EC  C V 2
2
1
dt  C V 2
2
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Dynamic Power dissipation
• Dynamic Power
Power  Energy per transition x Transition rate
 C L VDD 2 f01
 C L VDD 2 f 01
where 01 is swithching activity
01 is also called transition activity
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Dynamic Power dissipation
• Switching Power dissipation
- Due to charging of load and parasitic capacitances
Vdd
Vin
Vout
CL
Pdynamic  01 CL VDD2 f
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Dynamic Power dissipation
• Short Circuit Power Dissipation
- When input signal switches and lies between threshold voltage of
NMOS and PMOS transistors both transistors are ON. This causes
short circuit between Vdd and ground resulting in short circuit
power dissipation
vo
Vt n Vt p vi
- Short circuit power dissipation depends upon rise and fall time of
input signal
- Loading capacitance of gate
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Dynamic Power dissipation
• Short circuit power dissipation
- Exact analysis of short-circuit dissipation of inverter is complex.
 Simplified analysis:
r
T
VDD
f
Vin
VDD
I Max
t1t2 t3
Short circuit current
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Vout
t
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Dynamic Power dissipation
• Short circuit power dissipation
 Simplified analysis:
Assume  n   p ;VTn  VTp . Inverter is symmetric. During time
t1 to t 2 current increases from 0 to I max .
V

I  (Vin  VT ) 2 . I becomes max imum at Vin  DD and is
2
2
symmetric about t 2 .
1T
2 t2 
Average current I av   I (t ) dt  2  Vin (t )  VT 2 dt
T0
T t1 2
V
V

Vin (t )  DD t ; t1  T ; t 2 

VDDS Qureshi 2
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Dynamic Power dissipation
• Short circuit power dissipation
 Simplified analysis (cont):
/ 2
2
 VT
t av  2
( t  VT ) 2 dt

T (VT / VDD )  2 
V
Let   ( T )t  VT ; then

2  (VT / VDD ) 
I av 
 d

T
/ 2
1 
3 

(VDD  VT )
12 VDD
T

3 
Pshort circuit  (VDD  VT )
12
T
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Dynamic Power dissipation
• Short Circuit Power Dissipation
Pshort 

 (VDD  VT ) 3 f
12
  transconduc tan ce parameter
VT  threshold voltage
  signal rise time
f  frequency
 Psc is minimum when input and output have equal
rise and fall times
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Veendrick 84
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Dynamic Power dissipation
• Short Circuit Power Dissipation
Vd d
Vin
Vout
CL
IVDD (mA)
0.15
0.10
0.05
0.0
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1.0
2.0
3.0
Vin (V)
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4.0
5.0
Rabaey 2003
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Dynamic Power dissipation
• Short Circuit Power Dissipation
- Dependence of short circuit current on load capacitance
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Rabaey 2003
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Dynamic Power dissipation
• Glitching power
 Glitches arise due to delays through different paths
(Spurious transitions)
t 0
t 1
t 1 t 2
d 1
Steady 0
t 0
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d 1
t 0
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Static Power dissipation
• Leakage mechanisms in deep submicron transistor
Gate
I7 , I 8
Drain
Source
n
I5
n
I 2 , I 3, I 6
I4
I1
Well
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Static Power dissipation
• Reverse-Bias Diode Leakage (I1)
Gate
Source
Drain
Diode leakage
qVd
(e nKT
I diode  I rsat
 1)
Vd  diode voltage
n  ideality factor
KT
 thermal voltage
q
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Static Power dissipation
• Subthreshold Leakage Current
Source
Gate
(I2)
Drain
Subthreshold leakage current I sub
I sub  I S e
(VGS VT )
n KT / q
(1  e

VDS
kT / q
)
I s  parameter
n  parameter
KT
 Thermal voltage
q
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Static Power dissipation
• Subthreshold Leakage Current
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Rabaey 2003
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Static Power dissipation
• Drain-induced barrier lowering effect (I3)
 DIBL occurs when depletion region of drain interacts with
source to lower source barrier potential.
 Source injects carriers into channel without gate playing role
 DIBL lowers threshold voltage without affecting subthreshold
slope
 DIBL can be measured at constant VG as change in ID as VD
changes
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Static Power dissipation
• Drain-induced barrier effect
V D  4 .0 V
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VD  0.1 V
V D  2.7 V
DIBL
ID (A)
1E  02
1E  03
1E  04
1E  05
1E  06
1E  07
1E  08 GIDL
1E  09
1E  10
1E  11
1E  12
1E  13
1E  14
 0.5
(I3)
0
0.5
VG (V)
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1
1.5
2
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Static Power dissipation
• Gate-induced drain leakage GIDL current (I4)
 GIDL current arises in the high electric field under the gate/drain
overlap region causing deep depletion
 GIDL current occurs at high VD bias which generates
carriers in the substrate
 Thinner tox, higher VDD and lightly doped substrate enhance
electric field and GIDL current
 GIDL current is a major obstacle in IOFF
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Static Power dissipation
• Punch through (I5)
 Punch through occurs when drain and source depletion region
approach each other electrically
 Punch through gives rise to current deep inside substrate
 Punch through causes current on which gate has no control
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Static Power dissipation
•Narrow width (I6)
• Gate oxide tunneling (I7)
 High electric field can cause direct tunneling through the gate
• Hot carrier injection (I8)
 Injection of hot carriers (electrons and holes) into oxide
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Contributions to Power dissipation
• Component wise contribution
100 %
0%
Switching power
80 %
Leakage power
30%
Short circuit power
5%
- With technology scaling leakage component is becoming
increasingly dominant
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Metric for low power design
 Power (Watt )
 Power per MIPS ( W / MIPS )
 Energy Delay ( Joule s)
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Design Abstraction Levels
SYSTEM
MODULE
+
GATE
CIRCUIT
DEVICE
G
S
n+
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D
n+
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Design Abstraction
• Simulation at various levels of abstraction is Key in
VLSI design
• Main difference between various levels of abstraction
- Trade-off between computing resources and accuracy
 Simulation at lower level has better accuracy but increased
computing resources needed
 Circuit simulator has better accuracy but cannot simulate full chip
 Logic level can handle full chip but accuracy not good
 Behavioral level simulation offers rapid analysis at the cost of
accuracy
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Design Abstraction
• Layered approach
 Design optimization in general follows meet-in-the-middle
strategy
- Specifications and requirements propagate from top down
- Constraints propagate upwards from lowest abstraction
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Circuit Level Approach
• Power Reduction Techniques at circuit level has
good impact on overall power saving
• Major impact especially in cell based design as
cells are repeated thousands of times on a chip
• Circuit level techniques even with small
percentage improvement in power saving not to
be ignored
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Circuit design style
• Look at Circuit Design from power dissipation point of
view
• Non-clocked logic
- Fully complementary logic
 Excellent from ease of design, low power dissipation,
low sensitivity to noise and process variations
 Poorer performance
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Circuit design style
• Fully complementary logic
VDD
 Dynamic power
PULLUP
NETWORK
- Switching power
- Short circuit power
- Glitching power
Output
Input
PULLDOWN
NETWORK
 Standby power
- Due to leakage through transistor
- For large VT transistor leakage power can be
neglected
- Low threshold voltage gives better performance
for ultra low power designs
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Circuit design style
• Pseudo NMOS logic style
- PMOS load
VDD
 Power dissipation higher than
Complementary CMOS
- Suffers from Static power dissipation
when pull down network is ON
Output
Inputs
PULLDOWN
NETWORK
 Faster speed due to reduced capacitance
-
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Circuit design style
• Differential Cascade Voltage Switch Logic (DCVSL)
 Eliminates static power dissipation
 Provides output and its
complement
VDD
output
 Increase in area and switched
inputs
capacitance
output
PULLDOWN
PULLDOWN
NETWORK inputs NETWORK
 Increase in dynamic power dissipation
in comparison to pseudo-NMOS
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Circuit design style
B
• Pass Transistor Logic (PTL / CPL)
A
- Transistors in series as switches or in parallel


B
Advantage is logic is fast and can
implement complex logic with few
transistors
NMOS does not transmit strong 1
hence level restorers are used
F  AB
0
B
A
B
F  AB
B
 Reduced voltage swing hence
reduced power dissipation possible
A
F  AB
B
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Circuit design style
• Pass Transistor Logic (PTL/
CPL)
- Other Example of CPL
B
A
B
B
F  A B
A
B
A
F  A B
A
F  A B
A
B
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B
F  A B
A
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Circuit design style
• Clocked Logic Family
- Clocked logic family generally faster than
static logic but consumes more power
-
VDD
CLK
Domino Logic

OUT
Domino circuits are noninverting and not easy to use
A
B
 Power dissipation high
CLK
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Power consumption in logic gates
• Power dissipation strong function of
 Transistor sizing which affects physical capacitance
 Input and output rise time which determines short-circuit power
 Device threshold voltage having impact on leakage power
 Switching activity or transition activity  01
Pdynamic  01 CL VDD2 f
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Power consumption in logic gates
• Switching activity or transition activity of gate 01
 Strong function of logic function being implemented
 For static CMOS gates switching activity is probability p0
that output is in zero state multiplied by probability p1
that output is 1 in next cycle
01  p0 p1  p0 (1  p0 )
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Power consumption in logic gates
• Signal probability p
- probability signal assumes value of 1 that is p ( g=1)
• For NOT gate if input signal probability is p1
- Output signal probability is 1- p1
p1
p1
p1 p2
p2
• For AND gate if input signal probability is p1 and p2
- Output signal probability is p1 p2
• For Or gate if input signal probability is p1 and p2
- Output signal probability is 1- (1- p1)(1- p2 )
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1  p1
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p1
1  (1  p1 ) (1  p2 )
p2
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Signal Switching Activity
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Gate
01
AND
(1  pa pb ) pa pb
OR
(1  pa ) (1  pb ) [1  (1  pa ) (1  pb )]
XOR
[1  ( pa  pb  2 pa pb )] ( pa  pb  2 pa pb )
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Techniques for reducing switching activity
• Shifter
instead of Multiplier
 In XOR gate every input transition causes output transition
 Not so for AND, NAND, OR, NOR
 XOR Gate more power hungry
 Multipliers and Adder use large number of XOR Gates
- Single input transition causes number of transitions internal to Adder
Multiplier
 User left Shift instead to have multiplication and right shift for division
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Techniques for reducing switching activity
• Operand
Isolation
 Addition of two 32 bit signals
 All 32 bits do not arrive same time
Arrival of Each bit can cause switching
activity in adder with power dissipation
Latching each input will reduce the
problem of unnecessary switching
activity
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32
A
33 SUM
B
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Techniques for reducing switching activity
• Operand
Isolation
 Latching operands
 All operands come from registers
almost same time
 Area penalty
Increase by one clock cycle in latency
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A
32
32
33
B
32
32
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Techniques for reducing switching activity
• Avoid
Comparison
 Comparison of large Data busses
A[0 ]
B[0 ]
A[1]
using comparators
 Comparator operations involve XORs
B[1]
 Avoid comparisons of all bits in one go.
- compare MSB to avoid power loss
due to intermediate transitions
- only lower bits be involved if MSB is
non-diagnostic
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A[31]
B[31]
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Techniques for reducing switching activity
• Compare
MSB
 Comparison of MSB done first
 If comparison is sufficient other
bits are prevented from taking
part
 if MSB not sufficient other bits
allowed to go to XOR Gates
 Additional area required
A 31
31
31
31
B
31
A[31]
B[31]
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Techniques for reducing switching activity
• Clock
Gating
 Most effective method to reduce
switching activity
 For positive-edge triggered F/F no
change in output for negative- edge
 When output is not sampled positive
clock edge will only cause power
dissipation
0
1
CLK
SEL
 When input is not changing there is
no point in sampling
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Techniques for reducing switching activity
• Clock
Gating
0
 When F/F output is not used it is
blocked at NAND Gate unless
select is enabled
1
CLK
SEL
Gated CLK
 No switching activity when select
not enabled
CLK
SEL
Gated CLK
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Techniques for reducing switching activity
• Pulse
Clipping and Spurious Clocking
 Due to gating 1, 2, 7, 8, 9 are blocked
to reach F/F clock thus saving power
At point A falling edge should come at
6 but comes earlier and causes pulse
chopping; At point B positive edge can
cause timing violation
CLK
SEL
Gated CLK
CLK
1
2
3
4
5
6
7
8
9 10 11 12
SEL
GATED CLK
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A
B
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Techniques for reducing switching activity
• Preventing
Clipping and Spurious Clocking
 Enable signal reaches gate
ENABLE D
CLK Latch
G
only when clock is low
Gated CLK
CLK
1
2
3
4
5
6
7
8
9 10 11 12
ENABLE
LATCH OUTPUT
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GATED
CLK
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Low Power Design Methodology
• There is need to apply low power design methodologies through
entire design process from system level to layout
• Design flow starts with system specification followed by
following steps to get to layout
 System level specificat ion  System level design
 Behavioral descript ion  High level synthesis
 Structural RTL descript ion  Logic level synthesis
 Logic level netlist  Layout synthesis  Layout
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Low Power Design Metodology
• System Level Low Power Design Flow
 Create design in System Verilog
 Simulate design
 Create / Synthesize different versions
 Evaluate Power
Choose Lower Power Version
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S Qureshi
802.11a transmitter,
Dave 06 , MIT
58
Low Power Design Metodology
• Key Low Power Design Objectives in Design
Phase
 Minimization of effective frequency f eff
 Does not mean reduce clock frequency but how often
clock toggles, in other words f eff   f
 Clock gating
 Data gating
 Memory system design
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Low Power Design Methodology
• Clock
Gating
0
1
CLK
SEL

0
1
CLK
SEL
Gated CLK
Local Gating
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Low Power Design Methodology
• Clock
Gating
en F
FSM
en D
DATA
en M
MEMORY
CONTROL
Global Gating
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Low Power Design Methodology
• Data
Gating
 Inputs to Multiplier feeding ALU
 Inputs prevented to ripple
through multiplier saving power
giving low power version
X

X
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Principles of Low Power design
 Use lowest possible voltage
 Use smallest geometry, highest frequency devices operated
at lowest possible frequency
 Use parallelism and pipelining to lower required frequency of
operation
 Energy Power management by disconnecting power source when
system is idle
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Supply Voltage Scaling Approach
• Scaling of Supply voltage of CMOS inverter
–Theoretical limit VDD > 2…4 KT/q
2.5
0.2
2
0.15
Vout(V)
Vout (V)
1.5
1
0.1
0.05
0.5
0
0
0.5
1
1.5
2
0
0
2.5
V (V)
0.1
V (V)
0.15
0.2
in
in
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0.05
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Rabaey 2003
Supply Voltage Scaling Approach
• Supply voltage scaling for low power
Factor of two reduction in supply voltage yields factor of four
decrease in energy
- Theoretical lower limit of supply voltage for CMOS is 0.2 V
- Trade-off for supply voltage lowering is increase in delay leading to
dramatic reduction in performance
Normalized Delay
Normalized Energy
-
VDD
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VDD
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Supply Voltage Scaling Approach
• Delay increases due to voltage reduction
• Increase in delay can be compensated by scaling down
device sizes
• Submicron capacitances do not scale proportionately and
can become dominant
L
1 L
S
t
2 tox '  ox
S
3 Nd ' N D x S
Source
'
W
4 W 
SX
j
5 X j '
S
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6 N A' N A x S
'
Gate
Drain
4
5
3
Oxide 2
1
3
Substrate 6
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Architectural Approach with Voltage Scaling
• Architectural transformation to compensate for delay is
attractive while achieving lower power dissipation. Use
two approaches
 Parallelism
 pipelining
- Illustrate with a data path
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Architectural Approach with Voltage Scaling
• Parallelism
INPUT
DATA PATH
OUTPUT
f
PREF  C VDD 2 f
C  Total Capaci tan ce Switched
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Architectural Approach with Voltage Scaling
• Parallelism
Area overhead
DATA PATH
MUX
INPUT
OUTPUT
f /2
DATA PATH
f
Cap  2.2 C
Voltage  0.6 VDD
Frequency  0.5 f
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f /2
PParallel  (2.2 C ) (S0Qureshi
.6 VDD ) 2 (0.5 f )
69
CLK
b
CLK
CLK
log
REG
REG
CLK
REG
CLK
Out
REG
log
REG
b
REG
CLK
a
REG
a
REG
Pipelining
CLK
CLK
Pipelined
Reference
Rabaey 2003
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Out
Architectural Approach with Voltage Scaling
INPUT
REGISTER
• Un-pipelined
DATA PATH
OUTPUT
Cap  C
f
Voltage  VDD
Frequency  f
PREF  C VDD 2 f
C  Total Capaci tan ce Switched
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Architectural Approach with Voltage Scaling
INPUT
HALF DATA
PATH
REGISTER
REGISTER
• Pipelined
HALF DATA
PATH
f
Cap  1.2 C , Voltage  0.6 VDD , Frequency  f
PPipe  (1.2 C ) (0.6 VDD ) 2 f
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S Qureshi
72
Threshold Voltage Scaling
• Deep submicron device design issues
 Scaling down of feature size leads to improved performance and high
device density
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S Qureshi
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Threshold Voltage Scaling
• Subthreshold Leakage Current
I sub  I S e
(VGS VT )
n KT / q
(1  e

VDS
kT / q
)
I s  parameter
n  parameter
KT
 Thermal voltage
q
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Threshold Voltage Scaling
• Threshold voltage scaling done in low power circuits to
improve performance
VT   Delay  and Leakage Current 
Performace is improved
VT   Delay  and Leakage Current 
Subthreshold leakage reduces
LOW VT USED TO IMPROVE PERFORMANC E
HIGH VT USED TO REDUCE SUBTHRESHOLD LEAKAGE
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75
Threshold Voltage Scaling
• Fabrication of Multiple Threshold Voltage Circuits
- Different Threshold Voltage used during different
modes of operation
 Multiple channel doping
 Multiple oxide thickness
 Multiple channel length
 Multiple body bias
• Various Approaches used
 Variable-threshold Voltage CMOS (VTCMOS)
 Multi-threshold Voltage CMOS (MTCMOS) approach
6/24/2023
Dual-threshold Voltage CMOSS Qureshi
approach
76
Threshold Voltage Scaling
• VTCMOS Approach by changing body bias
VBp (active)
VTp  0.2 V ( Active)
1.8 V V ( S tan dby )
Bp
VTp  0.6 V ( S tan dby )
Vin
Vout
Body Bias
Control
Circuit
VTn  0.1V ( Active)
VTn  0.6 ( S tan dby )
VBn (active)
VBn ( S tan dby )
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Threshold Voltage Scaling
• MTCMOS Approach uses both both high and low
threshold MOSFETs in single chip obtained by
implantation and sleep control scheme
SL
VDD
MP
VDDV
Low VT MOSFET
High VT MOSFET
SL
GNDV
MN
Sleep Control Transistor
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Threshold Voltage Scaling
• MTCMOS approach uses both both high and low
threshold MOSFETs in single chip obtained by
implantation and sleep control scheme
 In active mode SL is high and Mp and Mn are ON. VDDV and GNDV are
real power and ground.
 In sleep mode SL is low. Mn and Mp are OFF. VDDV and GNDV are
floating.
 Leakage current is suppressed by high threshold voltage MOSFETs
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Threshold Voltage Scaling
• MTCMOS Performance
Conv. CMOS
4.0
3.0
2.0
1.0 MTCMOS
0.0
0.5 1.0 1.5
VDD
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1.2
Normalized Energy
Normalized Delay
5.0
2.0
1.0
Conv. CMOS
0.8
0.6
0.4 MTCMOS
0.2
0.5 1.0 1.5
2.0
VDD
S Qureshi
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Threshold Voltage Scaling
• MTCMOS Advantages and limitations
 Technique is simple and easily implemented
 MTCMOS reduces standby power only
 Sleep control transistors can be large in size and increase area and delay
 Extra memory circuitry required to maintain data in sleep mode
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S Qureshi
81
Sub-threshold Design for Low Power
• Sub-threshold circuits ideal for applications
where performance is not critical
• Minimum energy consumption is key
- Examples:
Hearing-aid application,
Ultra-low power registers,
SRAMS
6/24/2023
S Qureshi
82
Sub-threshold Design for Low Power
• Sub-threshold
0
10
operation
1E  1
I on at 1.8 V
Normalized ID (A)
1E  2
1E  3
1E  4
I on in Sub  VT
1E  5
1E  6
1E  7
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I off
0
0.5
S Qureshi
1
VG (V)
1.5
2
83
Sub-threshold Design for Low Power
• Sub-threshold Leakage Current Model
I sub  I S e
(VGS VT )
n KT / q
(1  e

VDS
kT / q
)
I s  parameter
n  parameter
KT
 Thermal voltage
q
6/24/2023
S Qureshi
84
Sub-threshold Design for Low Power
• Sub-threshold Leakage Current Model
Normalized ID
1.0
VDD  500 mV
0.8
VGS  0.5 V
0.6
VGS  0.4 V
0.4
VGS  0.3 V
0.2
0
0
0.1
0.2
0.3
0.4
0.5
VDS (V)
I D vs VDS curves in sub  threshold region
6/24/2023
S Qureshi
85
Sub-threshold Design for Low Power
• Digital Logic
 Inverter Operation in Sub-threshold region
K C L VDD
Gate propagati on delay t d 
VDD  VT
I 0 exp (
)
n KT / q
VDD
Vin
Vout
 VDD scaling in sub-threshold region has limit ~ 3- 4 KT/q
 Reason for degradation is low Ion/Ioff
 Small Ion implies slower speed
6/24/2023
S Qureshi
86
Sub-threshold Design for Low Power
• Digital Logic
 VTC of Inverter in Sub-threshold region
VDD
Normalized I
100
Vout
10 2
10 4
10 6
0
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Vin
0.05 0.1 0.15 0.2 0.25
0.3
VIN (V)
S Qureshi
87
Sub-threshold Design for Low Power
• Digital Logic
 VTC for Inverter in Sub-threshold region
VOUT (V)
0.3
0.25
0.2
0.15
0.1
0.05
0
0
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0.05 0.1 0.15 0.2 0.25
0.3
VIN (V)
S Qureshi
88
Sub-threshold Design for Low Power
• Digital Logic
 9 stage Ring Oscillator using inverter
Ring osc output (mV)
100
6/24/2023
80
60
40
20
0
0
1
2
Normalized time
S Qureshi
89
Sub-threshold Design for Low Power
• Digital Logic
 XOR Gate using transmission gate for sub-threshold region
B
A
B
Z
A
B
6/24/2023
S Qureshi
90
Thank You !!!
6/24/2023
S Qureshi
91