iPhoneX Intel Edition SCH 051-02221 051-02247 PCB 820-00863-09 820-00869-06
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ALL INFORMATION COMPILED FOR USERS OF FORUM HTTP://WWW.MOBILEGSM.IN.UA PCB 820-00863-09 X891 Intel Edition TOP MLB D D * C3928C3961C3901C3900C3908C3907C3996C3990C3994C3992C3991 FD0401 C3041 C4125 C4126 C3906 C4122 C3951 L4120 * C3940 C3941 C4192 R3907 C3931 * L4100 * C4105 C3925 FL3903 C4303 * C3717 U3700 C3750 * C4310 C4491 R4309 C3909 C4090 XW4400 C4823 J4000 * J4600 C4028 C4618 C2763 C4809 C4031 C4822 R4000 C4801 2 R4601 C4093 R4600 C4805 C4814 R4619 R4710 C3622 C2622 R3620 * * * * * * * * * * * * * * * * * * * * * * * * * * C2611 C2626 * C2635 * * * * C2601 C2617 C2643 C2651 * C2618 C2624 C2647 C5660C5652 C5645 C5134 C2910 R3074 C2971 C2911 C5653 * U5600 C5125 * * * * * * C2970 * C5136 C3361 * * * C3351 C5128C5129C5142C5126 * * C2800C5127 C5655 * C5621 C5651 XW2991 L5100 L2790 * * * L2800 C5611 * C2801 * * * C2790 L5600 C5130 * C2802 * C2641 XW2780 0 3 7 2 W X U5900 XW5900 * * * * L2730 * C2645 C2632 C2649 C2615 X 1 3 7 1 W X R2600C2610C2623 * C2644 C2606 C2600 C2612 C2646 C2614 C2640 C2620 C1863 C2642 0 1 5 0 W 0 6 7 1 W X C1791 C1707 * * C1712 * R5901 U6100 FL5782 L5710 * C2731 * R3600 * U3600 C2605 C3600C3601 C3602 C1805 * C1813 C1762 C1773 C1772 C1710 * C1793 C1792 * C1704 * C1709 * * * C1713 * * C1192 C1750 * * C1764 * C1706 * C1705 * * XW6110 R5903 C5900 DZ5900 * * C1199 C2745 C1861 FL1092 * C1812 * C1191 C1801 * C1880 XW0 511 XW1701 C1708 C1095C1090 C1711 C1720C1722 XW5785 C1763 C1804 R6421R6416R6418 FL6400 J6400 R6466 C4574 C4562 FL4561R4560 C3620 FL4003 Q3700 R3801 C4204 C6486 FL4204 R4221 FL4200 J4200 C4575 FL4574FL5780 XW5784 * * * FL6454 * J5700 * C4632 C4635 C6485 * L5720 * L2760 * * L5700 * C3360 * C3307C3306 C3308R3062 * C3350 * C3305 Q3350 R3350 * C2761 C3324 C3320 * C3322 U3300 C2752 C3301 C3325 C3323 C3311 * C3312C3315 * C2762 C3317 C3340 Y3000 C2721 C3316 C2990 C2852 * * R3316 C3391 * C3313C3314 R3202 * L2720 C3310 C3202 L3340 * * * L5740 C6291 L5730 C6290 U6200 L3341 R3045 C3045 C2913 * C2750 3 C3352 3 7 0 * C3293 C6391 C6395 C6200 C3343 R3332 * L6301 C2991 * C6210 C6292 C2851 R3360 B C6311 C3341 C2751 XW3200 * C1490 R1471 L6300 C6390 R6211 C6312 C2992 L2740 L2750 C3031 C3353C3292 XW R1482 * U6300 C6330 R6210 R0623 R0620 C2850 * R3001 C3002 J3200 R1602 R1601C6300R6300R3061 J4530 C3110 * C1870 U1490 * C2771 J3500 * U3100 L3100 R1010 R1470 * C3500 * R3044 C3044 R1861 C1840 C1832 R0621 C1850 C3390 R6200 R3331 C2900 C2857 C2980 R3020 C2866 C2914 C2861 C3010 C2981 C2863 C2770 C2701 C2856 5 9 * 2 * *9 * W * C2901 U5100 C2704 * C2909 C3030 X * SB0401 C1852 L2700 C3020 C2865 XW3000 C2732 * PP0550 * R3330C2920 L2721 C3294 C2858 R0622 R1400 * * C2772 C2811 L2770 * C1831 C1843 FD0404 R1604 C3342 C2862 C2760C2730 R1100 C2705 C2706 * C2722 C5642 PP0500 C2906 R1462 * C2700 U2700 C5135 PP0521 XW2990 R3010 C2907 C2702 * L2811 L2741 * C5612C5631C5632C5654 C5650 C5692 CL0403 C2864 * C2860 C2854 C2723 DZ3300 * Q3200 FD0402 R1870 R3071 * C2813 C2855 * Q3201 R1130 C2703 * R1401 * R2604R1862C3071 R2601 R3000 C1833 C2810 C5640 C5691 * C2903 C6492 C3201 R3201 C1125 C1395 R3070R3011 C2740 C2720 C3370 C1124 R1860 C1290 R1603 R1020 R1622 L2810 C6497 C4815 R1000 R1252 C1841 2 5 4 R3370 C2791 R1431 R1620 C1291 4 0 FL3550 L2701 R1131 R1621 FD0410 * 0 3 R3552 3 W X C2792 W X 4 C2744 4 0 C2743 C3511 C3550 C5641 PP0505 PP0506 R1232 R1623 R1250 C2859 C5690 * 3 C6495 C3552 C5131 W L2702 X C6490 C2636 C2637 R3551 C3510 C5137 R1411 R5108R1440 C1860 C5139 R1430 C1391 * L2703 XW2740 R1231 U1000 C1295 R1441 C2812 PP0504 PP0513 C2627 R1212 C1390 * C2741 XW3041 C2742 C5138 R1480 C2915 R1481 XW2800 C5124 C1120 C1301 C2616 FL5702 C3551 C1121 C1396 R0601 R1251 C1853 * * DZ3520 C1122 C2710 R0600 R1461 C1394 * R3520 C1123 R1222 R1201 C1130 C1131 R1211 R1202 C1133 C1132 C1730 R1011C1010 R1465 SH0400 R3540 FD0411 * C2724 PP0560 C5702 C1739 R5902 SB0402 * R1460 C1296 C1733 PP0586 FL3553 C5902 L2712 Y1000 C1100 C1392 * C5704 PP0522 * C3114 C1101 C1393 C1732 FL5704 C6100 R1300 C5782 R5700 C6110 R6116 * R5701 C3553 DZ3540 C6117 L6110 * C5701 R3530 * C2716 C5783 FL5700 DZ3530 C6111 * PP0501 FL5783 C5700 PP0592 C1794 C6112 * C1011 C1103 C1738 C5784 C5703 PP0520 L2711 C3113 R1150 C1736 * B FL5703 * C3112 R1451 * C5786 C4560C5781 C2714 C5785 C2711 U6110 * R1450 L2710 PP0563 C1862 C6496 * C2713 C4573 C2715 C4564 C6491 PP0564 L2780 C2712 * C4563 * C3303 * * R4563 C4570 * C3302 0 C4572 9 XW4570 PP0512 U2600 7 C3304 1 * W PP0515 X C6470 0 C6473 7 C6471 PP0561 * C6494 7 C6472 C6493 2 PP0516 C6465 PP0591 XW1870 R6465 W C1811 C6413 X FL6452 C6454 PP0590 C6466 C1782 C1690 C6419 PP0562 C1702 SH0401 C6421 C1703 FL6413 C6452 C1721 C1737 C6416 C6450 C1691 C1735 FL6450 R1880 C1881 C3115 C3111 R1410 C1102 C2780 C1734 C6418 C1781 C6420 * C1723 C2619 C6400 C1803 C2613 R6431C6431 C1761 * R6432C6432 PP0546 FL6433 C6433 C1760 XW2790 C2781 C6410 C1802 R1464 C1731 C2782 FL6430 C6430 * C1093 0 R6410 5 C6411 FL6460 7 FL6411 C6460 R4212 * C6462 C4210 R1198 J_INT_BOT R1420 R1421 2 C1092 C1198 FL6462 R4210 FL4572 C1842 C2634 W PP0531 C4571 C2628 X PP0530 C6464 C4212 R6420 C2629 C2621 R1194 C1193 FL6464 C4211 R6419 C2630 * * PP0587 FL6482 C4205 * C1194 C6482 R4211 C4817 R3100 C3190 * * C6480 C4201 CL0402 PP0545 PP0544 C2650 R1221 C2652 C1830 R1240 C1810 C1851 R1500 R3601 * PP0503 PP0514 C2631 C2603 C2609 FL6480 C4221 PP0547 R1241 C6483 C4220 C2602 R1243 * C6484 R4220 R3110 R4800R4830 CL0400 * R1242 C4200 C4202 FD0420 PP0502 PP0542 R1871 C4203 R1121 R1101 U3620 R1863 FL4202 * PP0541 PP0540 * SB0400 R4003 * C4630 R4831 * * * PP0583 R3042C3042 PP0582 * FL4644 C4811 FL4643 R4700 C4820C4813 DZ4644 R4701 C4025 C4804 C4631 C4634 DZ4643 U4700 C4821 R4634 * R4633 * C4633 C4701C4700 0 8 4 FL4619 W X FL4618 * W X C4825 C4600 C4808 C4824 C4030 * 6 7 2 C4812 C4060 * 0 FL4554 C4061 C4601 R3073 C4554 C4041 C4617 C C4400 R4553 C4553 C4040 C4008 C4650 C4802 R3072 C4000 C4803 DZ4640 C4490 C4496 C4401 C3790 C4595 C4051 C4420 * C4001 C4422 C4007 FL4642 C4593 C4050 C4412 C4010 C4660 XW4600 C4411 R4005 C4006 R4617 FL4640 U4400 L4400 C4091 C4405 C4493 * C4092 * FL3901 C4300 * L4401 C4301 C4421 C4492 C4596 C4498 * FL4301 DZ4642 C4613 C4497 * C4410 * * FD0412 C4326 R4007 C4636 C3701 * C4597 FL4330 C4094 C3530 * C4494 PP0571 PP0570 C4017 C3501 C4495 R3810 R4400 R4308 R4001 C3540 R3811 C3709 R3803 FD0403 R3820 * C4324 C4320 FL4650 C3520 L3700 C4330 R4310 C4096 C4614 C3700 C4302 * C3702 * C4304 C3798 J4300 C3810 C3720 C4305 R3800 C3722 C4308 C3721 C3715 * C3800 C3704 * C4309 * C4102 FL4303 C4307 C3795 C4101 C3796 U4100 C3719 R4330 * R3802 * C3710 C3718 C3993 R4010 R4611 C3797 * C3960 FL3995 FL4001 FL4555 DZ4641 C4106 C3930 C4594 FL4641 * R3908 DZ4310 C C4191 J3900 C3950 C4306 C4552 C4592C4555C4556 R4552 FL4305 FL4556 * C4121 C3995 FL4307 J4500 U4120 R3905 C4322 XW3700 C4196 FD0405 R3900 TP0540FL4306 TP0543 * R3901 * CL0401 R3041 A A TITLE APPLE PCBF, X891 TOP MLB THIS IS THE PROPERTY OF APPLE AND IT MUST BE RETURNED ORIG DIV DESIGNER DATE SCALE KEN KIPLINGER 03/31/17 1:1 TOP SIDE ASSEMBLY DRAWING NUMBER 820-00863-09 NOTICE OF PROPRIETARY PROPERTY NOTES: ARTWORK VIEWED FROM COMPONENT SIDE. PCB SHALL CONFORM THE TO STANDARDS AS DEFINED IN APPLE SPECIFICATION PROPRIETARY 080-2265 (FLEXIBLE PRINTED CIRCUIT BOARDS) OR INFORMATION THE POSSESSOR (I) TO CONTAINED PROPERTY AGREES HEREIN OF APPLE TO THE IS THE FOLLOWING 062-0073 (MULTI- LAYER BOARDS) AS APPLICABLE. MAINTAIN THIS DOCUMENT IN CONFIDENCE (II) NOT TO REPRODUCE OR COPY IT (III) NOT TO REVEAL OR PUBLISH IT 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 1. ALL INFORMATION COMPILED FOR USERS OF FORUM HTTP://WWW.MOBILEGSM.IN.UA PCB 820-00869-06 X893 Intel Edition TOP MLB D D * FD0403 L1405_KL1404_K * FD0413 JUAT1_K C1404_KC1403_K QUADP_K * R1402_K R1404_K R1403_K C1503_K L1501_K FD0415 FD0406 L1401_KC1401_K L1402_K * GLNA_K MHBLN_K TP0790 * PP1648_K R1302_K LBLN_K * L1300_K C1305_K C1304_K L1701_K C1302_K C1306_K C1303_K L1700_K * PP1620_K * C7511_S * * C7533_S * PP7510_S PP7505_S * C7517_S * C7503_S C7526_S C7521_S * C7506_S PP7508_S PP1624_K C7522_S C7520_S Q7501_S C7531_S C7514_S C7530_S L7500_S PP1619_K NFC_DCDC_S L7502_S R1500_K Q7502_S L7503_S FL1400_K C1407_K C7515_S C7518_S C7510_S R1303_K R1405_K C1402_K PP1656_K * C7532_S C7512_S C7523_S PP7514_S PP7504_S C PP7503_S PP7506_S C PP1655_K PP1623_K PP1622_K C1406_K C7516_S PP1604_K PP1621_K PP7507_S R7508_S C7507_S C1701_K PP1625_K * R1700_K C1700_K GNSS_K * * R1406_K GPOUAT_K C1405_K * PP1618_K PP1658_K PP0700 T7500_S PP1612_K * PP0704 PP1635_K PP1611_K PP7509_S R0630 R203_K C200_K C520_K * L500_K C515_K C437_K R401_K C3407 C3462 PP1614_K PP1643_K PP1640_K X C428_K C401_K C3461 PP1613_K K _ 2 C502_K 0 5 W L501_K R1609_K C403_K C429_K PP0701 PP1609_K PP1601_K PP1610_K PP1642_K PP1641_K C514_K * C504_K C413_K C415_K R1608_K D3402 C506_K C503_K * * C404_K C521_K R3420 R3421 R1604_K C517_KC419_K C439_K C201_K C426_K * R208_K C511_K R1610_K C434_K C417_K C500_K C518_K C510_K R207_K C5015 C5019 C5012 * L502_K C3444 C3443 R3408 R3422 C3417 X XW3401 W 3 4 0 0 C3445 * C3405 D3403 * * C5028 PP1602_K PP1634_K * U5530 C516_K C5026 C3419 C3416 C3411 C3440 C3418 C7513_S L5000 C522_K C5530 C3403 * C3402 K _ MC_K 4 * C441_K C400_K 0 BBPMU_K PP0703 XW501_K * C5006 C3442 * * * * C5008 * * * R3401 PP0702 TP0721 C501_K XW503_K C5024 C3413 D3401 L503_K 5 C5011 XW3402C3415 * W U3400 D3400 C3453 C3454 TP0720 C519_K C505_K X C3452 C3456 PP7512_S TP7506_S PP1657_K C513_K C508_K C523_K C509_K XW500_K * C5025 C3406 * R3450 C5029 R209_K C512_K R204_K * R3407 C3404 PP1633_K TP7505_S PP7513_S * C3441 U5000 * EPROM_K R501_K * * C3451 C3455 C5016 C5018 J_INT_TOP C5000 R5001 * R7502_S C7504_S C5001 * C3412 * C7502_S * NFC_S C7505_S C5027 PP7511_S L7501_S PP1607_K PP1603_K C4934 C420_K R206_K C4926 C440_K C409_K C4925 C4929 C4922 C4914 PP1600_K R400_K C300_K C3464 U_BB_K C425_K C3465 R3460 C423_K TP0730 PP1627_K C301_K C431_K C427_K C3466 C422_K * FD0405 PP1628_K PP1661_K C421_K C3463 U4900 R3406 C433_K C418_K FD0414 PP1660_K C4927 R202_K R201_K C4904 C4932 C4903 C407_K * R1607_K * R200_K C424_K C435_K * C7608_W R205_KC438_KC410_K C408_K * C507_K C4931 R1601_K C7607_W R1600_K R1603_K R1602_K R1612_K R1611_K C432_K R1606_K R1605_K C7601_W C430_K C7600_W C7603_W C405_K R7600_W C7711_W C416_K * C436_K C411_K TP0708 PP7623_W PP7616_W * C7602_W C4905 PP7622_W * R300_K * * R7711_W R7702_W * * C7709_W PP1606_K PP1615_K L4900 C402_K R1615_K W5BPF_W TP0731 C4909 C412_K * R1614_K C406_K * R1613_K C4907 TCXO_K * R1617_K C4930 * R302_K PP1605_K C4928 * R1616_K * C303_K C414_K PP7621_W PP7620_W PP7630_W TP0713 PP7624_W PP7631_W PP7609_W R7700_W * C7705_W L7704_W PP7626_W PP7607_W PP7600_WPP7617_W PP7605_W * * ET_K W25DI_W L7600_W C7701_W TP0709 FD0401 PP7612_W PP7614_W PP7615_W FD0410 R7703_W C7716_W * TP0701 * TP0703 * XW3043 C723_K C722_K XW701_K * * * C7606_W C7609_W C7611_W C7612_W C720_K C721_K * W2XSW_W PP7618_W PP7613_W TP0702 L7701_W L7700_W * PP7604_W PP7601_W PP7629_W PP7627_W PP7610_W * C7604_W B PP7608_W PP7611_WPP7606_W PP7619_W PP7628_W PP7625_W W2BPF_W UWLAN_W * B J_DEBUG_K PP7603_W C7708_W TP0715 TP0714 TP0705 TP0752 TP0700 TP0710 TP0764 TP0761 PP1608_K TP0780 TP0754 TP0755 TP0751 TP0763 PP1631_K TP0750 PP1630_K PP1632_K PP1629_K PP1647_K R5807 PP1646_K FL5809 R615_K * * C5945_K DZ1609_K C643_K C644_K C650_KC642_KC633_K DZ1606_K L1026_K L1020_K L1025_K L1019_K L1018_K L1015_K C634_K C636_K R616_K C624_K C629_K XCVR1_K * C621_K C622_K R607_K C631_K * C626_K * C625_K L800_K PP1652_K TP0762 TP0759 TP0758 TP0756 TP0771 TP0757 TP0772 TDDPA_K TP0767 R801_K * C801_K C808_K C815_K GSMPA_K C811_KC807_K C805_K J_SIM_K R800_K L900_K * C1116_K C901_K C1115_K GPOLAT_K TP0760 PP1651_K L803_K C803_K C1706_K C1705_K * C1114_K * SB0400 A LATDI_K C1711_K C1710_K C1708_K FL1102_K PP1654_K PP1653_K PP1650_K C812_K * * C1707_K L1703_K TP0766 PP1649_K * * C1703_K * L1702_K C1704_K C1103_K LBPA_K C902_K C1100_K L901_K * * R1100_K L1100_K MHBPA_K FL1100_K LATCP_K C1109_K * JLAT1_K R7701_W TP0768 * C7712_W TP0515 * C1105_K * * C1107_K C1111_K * * GSMDI_K * L1014_K DZ1605_K C7703_W * * FD0412 TP0707 C800_K C906_KC900_K C630_K C905_K R600_K L1012_K L1009_K L1013_K L1016_K C1001_K L1021_K L1023_K L1000_K L1024_K L1017_K C903_K * C804_K C809_K SWTX1_K C813_KC904_K C806_K C810_K L1005_K * L1011_K L1007_K L1003_K L1006_K R1000_K C614_K L1027_K L1008_K C1600_K C627_K R610_K C628_K C1203_K C1204_K C637_K C1201_K R1201_K C632_K R609_K C638_K C635_K R1202_K C1202_K C1200_K R1200_K DSM_K C645_K C649_K R603_K R606_K C620_K C615_K C907_K C616_K C605_K C610_K * R614_K C602_K XCVR0_K R604_K C611_K C603_K L1001_K * L1010_K TP0522 PP1616_K PP1617_K * * DZ1607_K DZ1600_K L1004_K FL600_K DZ1608_K FD0404 L1030_K L902_K * C1108_K FL1101_K L903_K C1104_K C1106_K * C3043 * * FL5840 FL5891 FL5841 * C909_KC1112_K R3043 * R5821 * C5841 * C5840 C5821 * C5892 R5820 * R5842 C5820 TP0706 * C5847 FL5847 R601_K UATCP_K C5893 C5842 C619_K FL5893 C608_KC609_K C613_K C601_K C617_K C612_K C5894 C908_K C606_K C5860 R5801 C641_K C639_K J5800 C5896 FL5894 C5850 FL5850 * C640_K * C5891 FL5896 * * C5803 FL5890 FL5803 R5845 * R602_K C5845 FL5845 FL601_K * C5804 FL5804 C5890 C623_K * C5895 R5844 C604_K * FL5895 C5844 * * FL5805 R605_K VTCXO_K * C1601_K C5802 C5805 C600_K * C5810 FL5802 C5800 XW600_K * C5806 FL5800 * C607_K TP0753 * * C5809 FL5810 * C5807 FL5806 XW800_K A * C1102_K FD0402 C1101_K R1102_K R1101_K FD0411 TITLE APPLE PCBF, X893 MLB BOT THIS IS THE PROPERTY OF APPLE AND IT MUST BE RETURNED ORIG DIV DESIGNER TIM REID DATE SCALE 04/06/17 1:1 TOP SIDE ASSEMBLY DRAWING NUMBER 820-00869-06 NOTICE OF PROPRIETARY PROPERTY NOTES: ARTWORK VIEWED FROM COMPONENT SIDE. PCB SHALL CONFORM THE TO STANDARDS AS DEFINED IN APPLE SPECIFICATION PROPRIETARY 080-2265 (FLEXIBLE PRINTED CIRCUIT BOARDS) OR INFORMATION THE POSSESSOR (I) TO CONTAINED PROPERTY AGREES HEREIN OF APPLE TO THE IS THE FOLLOWING 062-0073 (MULTI- LAYER BOARDS) AS APPLICABLE. MAINTAIN THIS DOCUMENT IN CONFIDENCE (II) NOT TO REPRODUCE OR COPY IT (III) NOT TO REVEAL OR PUBLISH IT 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 1 REV ECN CK APPD DESCRIPTION OF REVISION 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. 9 0008409760 ENGINEERING RELEASED 2017-04-05 X891/X893 MLB Top: EVT LAST_MODIFICATION=Mon Apr D PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 C B A CSA 1 2 4 5 6 10 11 12 13 14 15 16 17 18 19 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 56 57 58 59 CONTENTS TABLE OF CONTENTS SYSTEM:BOM Tables SYSTEM: Mechanical Components SYSTEM: Testpoints (Top) BOOTSTRAPPING SOC: JTAG,USB,XTAL SOC: PCIE SOC: MIPI & ISP SOC: LPDP SOC: Serial SOC: GPIO & UART SOC: AOP SOC: Power (1/3) SOC: Power (2/3) SOC: Power (3/3) NAND SYSTEM POWER: PMU Bucks (1/4) SYSTEM POWER: PMU Bucks (2/4) SYSTEM POWER: PMU LDOs (3/4) SYSTEM POWER: PMU (4/4) SYSTEM POWER: Boost SYSTEM POWER: B2B Battery SYSTEM POWER: Charger SYSTEM POWER: Iktara SYSTEM POWER: B2B Cyclone + Button SENSORS CAMERA: PMU (1/2) CAMERA: PMU (2/2) CAMERA: B2B Wide (WY) CAMERA: B2B Tele (MT) CAMERA: Strobe Drivers CAMERA: B2B FCAM CAMERA: B2B Strobe + Hold Button PEARL: Power PEARL: B2B Romeo + Juliet PEARL: B2B Rosaline + Misc AUDIO: CODEC (1/2) AUDIO: CODEC (2/2) AUDIO: Speaker Amp Bottom AUDIO: Speaker Amp Top ARC: Driver CG: Power Supplies - Touch & Display CG: B2B Display CG: B2B Orb & Touch I/O: Overvoltage Cut-Off Circuit SYNC DATE test_mlb 10/13/2016 test_mlb test_mlb test_mlb test_mlb test_mlb test_mlb test_mlb test_mlb test_mlb test_mlb test_mlb test_mlb test_mlb test_mlb test_mlb test_mlb test_mlb test_mlb test_mlb test_mlb 10/13/2016 10/13/2016 10/17/2016 10/17/2016 10/13/2016 10/13/2016 10/17/2016 10/13/2016 10/17/2016 10/17/2016 10/17/2016 10/17/2016 10/13/2016 10/13/2016 10/13/2016 10/13/2016 11/01/2016 10/13/2016 10/13/2016 10/13/2016 test_mlb test_mlb test_mlb test_mlb test_mlb test_mlb test_mlb test_mlb test_mlb test_mlb test_mlb test_mlb test_mlb test_mlb 10/13/2016 10/13/2016 10/13/2016 10/13/2016 10/13/2016 10/13/2016 10/13/2016 10/13/2016 10/13/2016 10/13/2016 10/13/2016 10/13/2016 10/13/2016 10/13/2016 08/25/2015 08/25/2015 10/13/2016 10/13/2016 10/13/2016 08/25/2015 01/10/2017 test_mlb test_mlb test_mlb sync 3 13:03:06 2017 PAGE 46 47 48 49 50 51 CSA 61 62 63 64 65 80 CONTENTS I/O: Accessory Buck I/O: USB PD I/O: Hydra I/O: B2B Dock I/O: Interposer (Bottom) RADIOS SYNC test_mlb test_mlb test_mlb test_mlb test_mlb D DATE 10/17/2016 10/13/2016 10/13/2016 10/13/2016 10/13/2016 06/04/2015 C B BOM:639-04583 (Ultimate) BOM:639-03409 (Extreme) MCO:056-04077 TABLE OF CONTENTS A DRAWING TITLE SCH,MLB,TOP,X891 DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 TABLE_5_HEAD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION NO COMMON TABLE_5_ITEM 051-02221 1 SCH,MLB_TOP,X891 SCH NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 TABLE_5_ITEM 820-00863 1 PCB,MLB_TOP,X891 PCB NO 1 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE COMMON II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 1 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D 8 7 6 5 EEEE Codes 4 QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION NO ULTIMATE 2 1 Soft-Term Cap Sub BOMs Global Ferrites TABLE_5_HEAD PART# 3 TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES TABLE_5_HEAD COMMENTS: TABLE_CRITICAL_HEAD CRITICAL PART# PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION CRITICAL COMMON CRITICAL BOM OPTION COMMENT TABLE_5_ITEM 1 825-7691 EEEE_J2WJ EEEE FOR (MLB_TOP,639-04583,ULTIMATE) TABLE_5_ITEM TABLE_ALT_ITEM 155S00194 155S0610 BOM_TABLE_ALTS ALL TABLE_CRITICAL_ITEM 1 SUBBOM_CAP SUBBOM,MLB,TOP,CAP,TYPICAL,X891 FERR BD, 150OHM, 01005 155S0610 FERR BD, 150OHM, TDK 685-00155 TABLE_5_ITEM 1 825-7691 EEEE_HP26 EEEE FOR (MLB_TOP,639-03409,EXTREME) NO EXTREME TABLE_ALT_ITEM 155S00200 155S0610 BOM_TABLE_ALTS ALL Agnes Input FERR BD, 150OHM, TY TABLE_5_HEAD PART# D SOC QTY DESCRIPTION REFERENCE DESIGNATOR(S) D TABLE_5_ITEM 138S00159 4 CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA C2970,C2971,C2980,C2981 CRITICAL SOFT_CAP 138S0831 4 CAP,TYPICAL,2.2UF,6.3V,0201,MURATA C2970,C2971,C2980,C2981 CRITICAL TYPICAL_CAP CRITICAL BOM OPTION TABLE_5_ITEM TABLE_5_HEAD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL TABLE_5_ITEM 339S00358 1 U1000 SKYE+3GB, B0, M, DEV CRITICAL Agnes Output Global R/C Alternates BOM OPTION COMMON TABLE_5_HEAD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) TABLE_5_ITEM TABLE_ALT_HEAD PART NUMBER TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES 339S00359 339S00358 BOM_TABLE_ALTS U1000 DDR-H,3G, B0 339S00360 339S00358 BOM_TABLE_ALTS U1000 DDR-S-20,3G, B0 ALTERNATE FOR PART NUMBER BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENTS: 118S0717 BOM_TABLE_ALTS ALL RES, 3.92K, 0.1%, 0201 138S0648 138S0652 BOM_TABLE_ALTS ALL CAP,X5R,4.7UF,6.3V,0.65MM,0402,TAIYO 9 CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA C2900,C2901,C2903,C2906,C2907,C2910,C2911,C2913,C2914 CRITICAL SOFT_CAP 138S0831 9 CAP,TYPICAL,2.2UF,6.3V,0201,MURATA C2900,C2901,C2903,C2906,C2907,C2910,C2911,C2913,C2914 CRITICAL TYPICAL_CAP CRITICAL BOM OPTION COMMENT TABLE_ALT_ITEM 118S0764 138S00159 TABLE_CRITICAL_HEAD TABLE_5_ITEM TABLE_CRITICAL_ITEM 118S0717 RES, 3.92K, 0.1%, 0201 138S0652 CAP,X5R,4.7UF,6.3V,0.65MM,0402 TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_CRITICAL_ITEM Sensors TABLE_5_HEAD TABLE_ALT_ITEM TABLE_ALT_ITEM 138S0739 138S0706 BOM_TABLE_ALTS ALL TABLE_CRITICAL_ITEM QTY DESCRIPTION REFERENCE DESIGNATOR(S) CAP,CER,X5R,0.22UF,20%,6.3V,20% 138S0706 CAP,CER,X5R,0.22UF,20%,6.3V,20% PART# TABLE_5_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM 339S00361 339S00358 BOM_TABLE_ALTS U1000 DDR-S-18,3G, B0 132S0436 132S0400 BOM_TABLE_ALTS ALL TABLE_CRITICAL_ITEM 2 CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA C3602,C3622 CRITICAL SOFT_CAP 138S0831 2 CAP,TYPICAL,2.2UF,6.3V,0201,MURATA C3602,C3622 CRITICAL TYPICAL_CAP CRITICAL BOM OPTION CAP,CER,X5R,0.22UF,20%,6.3V,01005 132S0400 CAP,CER,X5R,0.22UF,20%,6.3V,01005 138S00159 TABLE_5_ITEM TABLE_ALT_ITEM 138S00049 NAND 138S0831 BOM_TABLE_ALTS ALL TABLE_CRITICAL_ITEM CAP,CER,X5R,2.2UF,20%,6.3V,0201 138S0831 CAP,CER,X5R,2.2UF,20%,6.3V,0201 RCAM B2Bs TABLE_5_HEAD Global Inductors Ultimate PART# DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL PART NUMBER BOM OPTION ALTERNATE FOR PART NUMBER BOM OPTION 152S00617 BOM_TABLE_ALTS REF DES COMMENTS: COMMENT 152S00617 IND,MLD,0.1UH,20%,6.1A,29MOHM,H=.65,1608 TABLE_ALT_ITEM 1 HYNIX, 3DV3, ULTIMATE U2600 CRITICAL 152S00710 ULTIMATE ALL IND,MLD,0.1UH,20%,6.1A,29MOHM,H=.65,1608 TABLE_CRITICAL_ITEM 3 CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA C3909,C3925,C4025 CRITICAL SOFT_CAP 138S0831 3 CAP,TYPICAL,2.2UF,6.3V,0201,MURATA C3909,C3925,C4025 CRITICAL TYPICAL_CAP CRITICAL BOM OPTION CRITICAL SOFT_CAP Strobe B2B TABLE_5_HEAD TABLE_ALT_ITEM 152S00712 C 138S00159 TABLE_CRITICAL_HEAD CRITICAL PART# TABLE_5_ITEM 335S00287 REFERENCE DESIGNATOR(S) TABLE_5_ITEM TABLE_5_HEAD QTY DESCRIPTION TABLE_5_ITEM TABLE_ALT_HEAD PART# QTY 152S00620 BOM_TABLE_ALTS ALL TABLE_CRITICAL_ITEM 152S00620 IND,MLD,0.1UH,20%,7.2A,17MOHM,H=0.8,2012 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) IND,MLD,0.1UH,20%,7.2A,17MOHM,H=0.8,2012 C TABLE_5_ITEM TABLE_ALT_HEAD TABLE_ALT_ITEM PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES COMMENTS: 152S00713 152S00621 BOM_TABLE_ALTS ALL TABLE_CRITICAL_ITEM 152S00621 IND,MLD,0.47UH,20%,3.5A,53MO,H=.65,2012 138S00159 1 C4303 CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA IND,MLD,0.47UH,20%,3.5A,53MO,H=.65,2012 TABLE_5_ITEM TABLE_ALT_ITEM TABLE_CRITICAL_ITEM TABLE_ALT_ITEM 335S00284 335S00287 BOM_TABLE_ALTS U2600 TOSHIBA, 1Z, ULTIMATE 335S00285 335S00287 BOM_TABLE_ALTS U2600 TOSHIBA, BICS3, ULTIMATE 152S00714 152S00622 BOM_TABLE_ALTS ALL IND,MLD,1.0UH,20%,2.1A,100MO,H=.65,2012 152S00716 152S00626 BOM_TABLE_ALTS ALL IND,MLD,1.5UH,20%,1.1A,160MO,H=.65,2012 152S00622 IND,MLD,1.0UH,20%,2.1A,100MO,H=.65,2012 152S00626 IND,MLD,1.5UH,20%,1.1A,160MO,H=.65,2012 TABLE_ALT_ITEM 138S0831 1 C4303 CAP,TYPICAL,2.2UF,6.3V,0201,MURATA CRITICAL TYPICAL_CAP CRITICAL BOM OPTION TABLE_CRITICAL_ITEM Audio TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_CRITICAL_ITEM TABLE_5_HEAD TABLE_ALT_ITEM 335S00286 335S00287 BOM_TABLE_ALTS U2600 SANDISK, BICS3, ULTIMATE 152S00717 152S00631 BOM_TABLE_ALTS ALL IND,MLD,1.0UH,20%,2.5A,78MO,H=0.8,2012 152S00718 152S00632 BOM_TABLE_ALTS ALL IND,MLD,1.0UH,20%,3.2A,60MO,H=0.8,2016 152S00720 152S00640 BOM_TABLE_ALTS ALL IND,MLD,0.47UH,3.8A,55MO,H=0.65MM,2012 152S00721 152S00641 BOM_TABLE_ALTS ALL IND,MLD,0.47UH,4A,48MO,H=0.8MM,2012 152S00715 152S00623 BOM_TABLE_ALTS ALL IND,MLD,1UH,3.6A,60MO,H=0.8MM,2016 152S00631 IND,MLD,1.0UH,20%,2.5A,78MO,H=0.8,2012 152S00632 IND,MLD,1.0UH,20%,3.2A,60MO,H=0.8,2016 152S00640 IND,MLD,0.47UH,3.8A,55MO,H=0.65MM,2012 152S00641 IND,MLD,0.47UH,4A,48MO,H=0.8MM,2012 152S00623 IND,MLD,1UH,3.6A,60MO,H=0.8MM,2016 TABLE_ALT_ITEM PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) TABLE_CRITICAL_ITEM TABLE_5_ITEM TABLE_ALT_ITEM 335S00288 335S00287 BOM_TABLE_ALTS U2600 SAMSUNG, 3DV4, ULTIMATE TABLE_ALT_ITEM Extreme QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL 1 HYNIX, 3DV3, EXTREME U2600 CRITICAL C4809,C4805 CRITICAL SOFT_CAP 138S0831 2 CAP,TYPICAL,2.2UF,6.3V,0201,MURATA C4809,C4805 CRITICAL TYPICAL_CAP CRITICAL BOM OPTION TABLE_5_ITEM Pearl B2B TABLE_CRITICAL_ITEM TABLE_5_HEAD PART# BOM OPTION TABLE_ALT_ITEM 152S00653 TABLE_5_ITEM 335S00240 CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA TABLE_CRITICAL_ITEM TABLE_ALT_ITEM PART# 2 TABLE_CRITICAL_ITEM TABLE_ALT_ITEM TABLE_5_HEAD 138S00159 152S00651 BOM_TABLE_ALTS ALL EXTREME 152S00650 BOM_TABLE_ALTS L3340,L3341 TABLE_5_ITEM 138S00159 1 CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA C4613 CRITICAL SOFT_CAP 138S0831 1 CAP,TYPICAL,2.2UF,6.3V,0201,MURATA C4613 CRITICAL TYPICAL_CAP CRITICAL BOM OPTION TABLE_CRITICAL_ITEM IND,0.47UH,6.6A,3225,0.8Z 152S00650 IND,0.47UH,6.6A,3225,0.8Z REFERENCE DESIGNATOR(S) IND,1.2UH, 3A, 2016, 0.65Z TABLE_ALT_ITEM 152S00649 DESCRIPTION TABLE_CRITICAL_ITEM 152S00651 IND,1.2UH,3A,2016,0.65Z QTY TABLE_5_ITEM TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES COMMENTS: 335S00228 335S00240 BOM_TABLE_ALTS U2600 TOSHIBA, BICS3, EXTREME 335S00247 335S00240 BOM_TABLE_ALTS U2600 SANDISK, BICS3, EXTREME 335S00276 335S00240 BOM_TABLE_ALTS U2600 SAMSUNG, 3DV4, EXTREME Acorn XTAL Alternate TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_5_HEAD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) TABLE_5_ITEM 138S00160 2 CAP,SOFT-TERM,10UF,10V,0402,MURATA C5641,C5653 CRITICAL SOFT_CAP 138S0979 2 CAP,TYPICAL,10UF,10V,0402,MUR/KYO C5641,C5653 CRITICAL TYPICAL_CAP CRITICAL BOM OPTION CRITICAL SOFT_CAP TABLE_ALT_HEAD TABLE_ALT_ITEM PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION 197S0446 BOM_TABLE_ALTS REF DES COMMENTS: TABLE_CRITICAL_HEAD CRITICAL PART# COMMENT TABLE_ALT_ITEM 197S0612 Global Capacitors Y1000 TABLE_CRITICAL_ITEM 197S0446 XTAL, 24M, 1612 TABLE_5_ITEM XTAL, 24M, 1612 CODEC TABLE_5_HEAD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) TABLE_5_ITEM B TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES COMMENTS: B TABLE_CRITICAL_HEAD CRITICAL PART# 138S00160 COMMENT 2 C4811,C4808 CAP,SOFT-TERM,10UF,10V,0402,MURATA TABLE_5_ITEM TABLE_CRITICAL_ITEM TABLE_ALT_ITEM 138S00148 138S00149 BOM_TABLE_ALTS ALL 0402-3T,10.5uF@1V, Kyocera 138S00150 138S00149 BOM_TABLE_ALTS ALL 0402-3T,10.5uF@1V, SEMCO 138S00149 0402-3T,10.5uF@1V TABLE_ALT_ITEM Multi-Vendor Criticals TABLE_CRITICAL_HEAD 138S0979 2 C4811,C4808 CAP,TYPICAL,10UF,10V,0402,MUR/KYO CRITICAL TYPICAL_CAP CRITICAL BOM OPTION Ansel TABLE_CRITICAL_HEAD TABLE_5_HEAD TABLE_ALT_ITEM 138S00151 138S00149 BOM_TABLE_ALTS ALL CRITICAL PART# 0402-3T,10.5uF@1V, TY COMMENT CRITICAL PART# TABLE_CRITICAL_ITEM TABLE_ALT_HEAD 377S0106 SUPPR,TRANS,VARISTOR,12V,33PF,01005 ALTERNATE FOR PART NUMBER BOM OPTION REF DES COMMENTS: 197S0446 XTAL,24MHZ,30PPM,9.5PF,60 OHM MAX,1612 155S0576 FERR BD,10 OHM,50%,750MA,0.07 DCR,01005 155S00168 FLTR,NOISE,65 OHMZ,3.4OHM,0.7-2GHZ,0605 QTY DESCRIPTION REFERENCE DESIGNATOR(S) TABLE_CRITICAL_ITEM 132S0288 CAP,CER,X5R,0.1UF,10%,16V,0201 132S0275 CAP,CER,X5R,470PF,10%,10V,01005 132S0249 CAP,CER,X7R,220PF,10%,10V,01005 132S0245 CAP,CER,X5R,0.01UF,10%,6.3V,01005 TABLE_5_ITEM 138S00160 1 CAP,SOFT-TERM,10UF,10V,0402,MURATA C3710 CRITICAL SOFT_CAP 138S0979 1 CAP,TYPICAL,10UF,10V,0402,MUR/KYO C3710 CRITICAL TYPICAL_CAP TABLE_CRITICAL_HEAD TABLE_CRITICAL_ITEM PART NUMBER PART# COMMENT CRITICAL PART# COMMENT 138S00144 0402,16uF@1V TABLE_CRITICAL_ITEM TABLE_5_ITEM TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_ALT_ITEM 138S00143 138S00144 BOM_TABLE_ALTS ALL 0402,16uF@1V, Kyocera TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_ALT_ITEM 138S00144 138S00163 BOM_TABLE_ALTS ALL 0402,16uF@1V, Taiyo TABLE_CRITICAL_ITEM 138S0979 ALTERNATE FOR PART NUMBER BOM OPTION REF DES COMMENTS: 685-00156 685-00155 BOM_TABLE_ALTS SUBBOM_CAP SUBBOM,MLB,TOP,CAP,SOFT,X891 TABLE_CRITICAL_ITEM 132S00093 CAP,CER,X5R,10UF,20%,10V,0402,H=0.65MM TABLE_ALT_HEAD PART NUMBER CAP,X5R,0.022UF,20%,6.3V,01005 TABLE_ALT_ITEM TABLE_ALT_HEAD TABLE_CRITICAL_HEAD TABLE_CRITICAL_ITEM PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT 138S0692 CAP,CER,X5R,1UF,20%,6.3V,0201 TABLE_CRITICAL_ITEM 132S00025 CAP,CER,X5R,0.047UF,20%,6.3V,01005 132S00008 CAP,CER,0.1UF,10%,50V,X7R,0402 TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_ALT_ITEM 138S00138 138S00139 BOM_TABLE_ALTS ALL 0201,3uF@1V, Kyocera 138S00164 138S00139 BOM_TABLE_ALTS ALL 0201,3uF@1V, Taiyo 138S00139 0201,3uF@1V 138S0683 CAP,CER,X5R,1UF,10%,25V,0402 138S0652 CAP,CER,X5R,4.7UF,20%,6.3V,H=0.65MM,0402 TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_ALT_ITEM 131S0883 CAP,CER,NP0/C0G,220PF,2%,50V,0201 131S0804 CAP,CER,27PF,5%,C0G,25V,0201 131S0307 CAP,CER,NP0/C0G,100PF,5%,16V,01005 131S0225 CAP,CER,NP0/C0G,15PF,5%,16V,01005 131S0223 CAP,CER,NP0/C0G,27PF,5%,16V,01005 131S0220 CAP,CER,NP0/C0G,12PF,5%,16V,01005 131S0216 CAP,CER,NP0/C0G,47PF,5%,16V,01005 TABLE_CRITICAL_ITEM TABLE_ALT_HEAD 138S00070 CAP,X5R,4.7UF,20%,25V,0402 138S00014 CAP,CER,1UF,20%,16V,X5R,0201,H=0.39MM TABLE_CRITICAL_ITEM TABLE_CRITICAL_HEAD TABLE_CRITICAL_ITEM PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT 138S00146 0402,5.1uF@3V TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_ALT_ITEM 138S00145 138S00146 BOM_TABLE_ALTS ALL 0402,5.1uF@3V, Kyocera 132S0664 CAP,CER,0.047UF,10%,25V,X5R,0201 132S0663 CAP,CER,X5R,1UF,10%,25V,0402 132S0534 CAP,CER,X5R,0.1UF,10%,25V,0201 132S0436 CAP,CER,X5R,0.22UF,20%,6.3V,01005 TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_ALT_ITEM 138S00165 138S00146 BOM_TABLE_ALTS ALL 0402,5.1uF@3V, Taiyo TABLE_CRITICAL_ITEM TABLE_ALT_HEAD A PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES COMMENTS: TABLE_CRITICAL_ITEM TABLE_CRITICAL_HEAD CRITICAL PART# COMMENT TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM SYNC_MASTER=test_mlb TABLE_ALT_ITEM 138S00140 138S00141 BOM_TABLE_ALTS ALL 138S00141 0201,1.1uF@3V TABLE_CRITICAL_ITEM 132S0396 0201,1.1uF@3V, Kyocera CAP,CER,X5R,1000PF,10%,10V,01005 TABLE_ALT_ITEM 138S00142 138S00141 BOM_TABLE_ALTS ALL 0201,1.1uF@3V, SEMCO 138S00166 138S00141 BOM_TABLE_ALTS ALL 0201,1.1uF@3V, Taiyo 131S00053 CAP,CER,C0G,220PF,5%,10V,01005 118S00068 RES,MF,1.3 MOHM,1%,200PPM,1/20W,0201 TABLE_CRITICAL_ITEM 132S0316 CAP,CER,X5R,0.1UF,20%,6.3V,01005 132S0304 CAP,CER,X5R,0.22UF,20%,6.3V,0201 SYNC_DATE=10/13/2016 TABLE_CRITICAL_ITEM PAGE TITLE SYSTEM:BOM Tables TABLE_CRITICAL_ITEM DRAWING NUMBER TABLE_ALT_ITEM TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM 117S0055 RES,MF,1/20W,2M OHM,5,0201,SMD TABLE_CRITICAL_ITEM 132S0296 107S0257 CAP,CER,X5R,1000PF,10%,6.3V,01005 Apple Inc. TABLE_CRITICAL_ITEM 051-02221 REVISION THERMISTOR,NTC,10K OHM,1%,B=3435,01005 9.0.0 TABLE_CRITICAL_ITEM 132S0318 CAP,CER,X5R,820PF,10%,10V,01005 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 2 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 2 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 FIDUCIALS FD0401 FID 0P5SQ-CROSS-NSP 1 ROOM=ASSEMBLY FD0402 CL0400 FID 2.10R1.60-NSP 0P5SQ-CROSS-NSP 1 1 D D ROOM=ASSEMBLY FD0403 FID 0P5SQ-CROSS-NSP 1 ROOM=ASSEMBLY FD0404 FID 0P5SQ-CROSS-NSP 1 ROOM=ASSEMBLY FD0420 FID 0P5SQ-CROSS-NSP 1 ROOM=ASSEMBLY FD0405 FID 0P5SQ-SMP3SQ-NSP 1 ROOM=ASSEMBLY FD0410 FID 0P5SQ-SMP3SQ-NSP 1 ROOM=ASSEMBLY FD0411 FID C C 0P5SQ-SMP3SQ-NSP 1 ROOM=ASSEMBLY FD0412 FID 0P5SQ-SMP3SQ-NSP 1 ROOM=ASSEMBLY CRITICAL SB0400 CL0401 STDOFF-2.9OD1.4ID-0.77H-SM 2.10R1.60-NSP 1 1 CRITICAL SB0402 STDOFF-MLB-TUBE 1 CL0402 2.10R1.60-NSP 1 B B CRITICAL 1 SH0401 SM SHLD-EMI-HARD-X891 CL0403 2.10R1.60-NSP 1 CRITICAL 1 SH0400 SM CRITICAL SB0401 STDOFF-2.9OD1.4ID-0.77H-SM SHIELD-EMI-TOP-X891 1 A A PAGE TITLE SYSTEM: Mechanical Components DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 4 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 3 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D 8 7 6 5 4 3 Test Points SOC Debug TP0540 P2MM-NSM D 35 34 1 SM PP ROOM=TEST 20 6 TP0543 P2MM-NSM 35 34 PP_ROMEO_CATHODE 1 IN AP_TO_PMU_TEST_CLKOUT Sensors PP0500 P2MM-NSM 1 SM PP 26 12 IN PP0540 P2MM-NSM SPI_AOP_TO_IMU_SCLK 1 ROOM=TEST ROOM=TEST 11 5 BOARD_ID0 1 IN 26 12 1 IN PP0502 P2MM-NSM AP_TO_FCAM_SHUTDOWN_L 1 IN 26 12 IN SPI_IMU_TO_AOP_MISO 1 ROOM=TEST IN AP_DEBUG3 1 DFU_STATUS 1 SM PP 26 12 IN 20 11 6 IN ACCEL_GYRO_TO_AOP_DATARDY 1 SM 26 12 IN ACCEL_GYRO_TO_AOP_INT 1 PP PP0506 P2MM-NSM IN AP_TO_PMU_SOCHOT_L 1 SM 17 13 17 13 PP_GPU 1 2 XW0511 SHORT-10L-0.05MM-SM PP_CPU_PCORE 1 2 PP0586 P2MM-NSM SM PP 47 10 IN PP ROOM=TEST PP0587 P2MM-NSM SM PP SM 1 AP_BI_CCG2_SWDIO 47 10 IN SM 1 AP_TO_CCG2_SWCLK PP ROOM=TEST PP0546 P2MM-NSM 49 25 12 IN COMPASS_TO_AOP_INT 1 SM PP SOC I2C1_AOP ROOM=TEST PP PP0547 P2MM-NSM SOC CPU/GPU XW0510 SHORT-10L-0.05MM-SM SM PP ROOM=TEST ROOM=TEST C PP ROOM=TEST PP0545 P2MM-NSM ROOM=TEST 20 6 SM 1 PDM_CODEC_TO_ARC_DATA ROOM=TEST PP0505 P2MM-NSM 1 IN PP0544 P2MM-NSM ROOM=TEST PMU_TO_AP_PRE_UVLO_L 41 37 SM ROOM=TEST IN PP0583 P2MM-NSM PP PP0504 P2MM-NSM 11 PP ROOM=TEST SM PP D SM 1 ROOM=TEST PP0503 P2MM-NSM 8 PDM_CODEC_TO_ARC_CLK IN PP0542 P2MM-NSM SM PP 41 37 ROOM=TEST ROOM=TEST 32 8 PP PP0541 P2MM-NSM SPI_AOP_TO_IMU_MOSI SM PP PP0582 P2MM-NSM SM ROOM=TEST PP0501 P2MM-NSM SM PP 1 Probe Points POWER PP_ROMEO_DENSE_ANODE 2 26 12 IN PHOSPHORUS_TO_AOP_INT 1 PP0590 P2MM-NSM SM PP ROOM=TEST 50 49 41 25 12 IN SM 1 I2C1_AOP_SCL PP C ROOM=TEST PP_GPU_LVCC Hydra VBUS 50 PP_CPU_PCORE_LVCC PP0591 P2MM-NSM 48 23 50 50 49 41 25 12 IN I2C1_AOP_SDA PP0550 P2MM-NSM HYDRA_TO_TIGRIS_VBUS1_VALID_L 1 IN SM 1 PP ROOM=TEST SM PP ROOM=TEST PP0512 P2MM-NSM 20 13 IN AP_CPU_PCORE_SENSE 1 NAND SM PP ROOM=TEST PP0513 P2MM-NSM 20 13 IN AP_VDD_GPU_SENSE 1 SM 16 12 PP IN PP0560 P2MM-NSM SWD_AP_BI_NAND_SWDIO 1 IN 1 SM 50 16 12 PP IN SWD_AOP_TO_MANY_SWCLK 1 TP_VSS_CPU_SENSE 1 SM 16 10 5 PP IN SPI_S4E_TO_AP_MISO_BOOT_CONFIG2 1 15 IN SM 16 PP IN NAND_ANI1_VREF 1 PMU 14 12 IN 16 IN NAND_ANI0_VREF 1 PP0520 P2MM-NSM AOP_TO_DDR_SLEEP1_READY 1 SM B PP PP0570 P2MM-NSM SPMI_PMU_BI_PMGR_SDATA 1 34 28 SM CAMPMU_TO_RIGEL_ENABLE 1 IN PMU_TO_AP_HYDRA_ACTIVE_READY 1 SM PP ROOM=TEST PP PP0522 P2MM-NSM IN SM PP Rigel SM PP PP0571 P2MM-NSM ROOM=TEST 48 20 6 SM PP ROOM=TEST PP0521 P2MM-NSM IN SM PP PP0564 P2MM-NSM ROOM=TEST 20 10 ROOM=TEST ROOM=TEST ROOM=TEST B PP PP0563 P2MM-NSM PP0516 P2MM-NSM 1 SM 1 ROOM=TEST ROOM=TEST TP_VSS_SENSE CCG2_TO_SMC_INT_L PP0562 P2MM-NSM PP0515 P2MM-NSM IN IN ROOM=TEST ROOM=TEST 15 47 10 PP0561 P2MM-NSM PP0514 P2MM-NSM TP_SOC_SENSE SM PP PP0592 P2MM-NSM ROOM=TEST ROOM=TEST 13 CCG2 34 20 8 IN RIGEL_TO_ISP_INT 1 SM SM PP ROOM=TEST PP ROOM=TEST PCIE Refclk 16 7 IN 90_PCIE_AP_TO_NAND_REFCLK_P PP0530 P2MM-NSM 1 SM PP ROOM=TEST PP0531 P2MM-NSM 16 7 IN 90_PCIE_AP_TO_NAND_REFCLK_N 1 SM PP ROOM=TEST A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016 PAGE TITLE SYSTEM: Testpoints (Top) DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 5 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 4 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 D D BOOTSTRAPPING:BOARD REV BOARD ID BOOT CONFIG R0623 11 OUT BOARD_REV3 1 1.00K 2 PP1V8_IO 6 7 8 10 14 16 17 27 28 29 30 32 34 35 43 5% 1/32W MF 01005 ROOM=SOC R0622 NOSTUFF 11 OUT BOARD_REV2 1 1.00K 2 5% 1/32W MF 01005 ROOM=SOC R0621 11 C OUT BOARD_REV1 1 1.00K 2 C 5% 1/32W MF 01005 ROOM=SOC SELECTED --> R0620 11 OUT BOARD_REV0 1 1.00K 2 5% 1/32W MF 01005 ROOM=SOC 11 50 10 B 11 11 OUT OUT OUT OUT BOARD_ID4 No connect CKPLUS_WAIVE=SINGLE_NODENET BOARD_ID3 On mlb_bot CKPLUS_WAIVE=SINGLE_NODENET PP1V8_IO B SELECTED --> MAKE_BASE=TRUE PP1V8_IO D221 Baseband Selected on RF Board 11 4 OUT BOARD_ID0 No connect SELECTED --> 16 10 4 OUT SPI_S4E_TO_AP_MISO_BOOT_CONFIG2 A No connect R0601 16 10 OUT SPI_AP_TO_S4E_MOSI_BOOT_CONFIG1 1 4.7K SYNC_MASTER=test_mlb 2 BOOTSTRAPPING 1% 1/32W MF 01005 DRAWING NUMBER Apple Inc. ROOM=SOC R0600 NOSTUFF 16 10 OUT SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0 1 4.7K SYNC_DATE=10/13/2016 PAGE TITLE 051-02221 REVISION 9.0.0 2 1% 1/32W MF 01005 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 6 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE ROOM=SOC II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 5 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 SOC - USB, JTAG, XTAL VDD11_XTAL:1.06-1.17V @ 2mA MAX VDD18_USB: 1.62V - 1.98V @ 20mA MAX PP1V8_IO 1 5 7 8 10 14 16 17 27 28 29 30 32 34 35 43 C1090 0.1UF 20% 2 6.3V X5R-CERM 01005 D D ROOM=SOC FL1092 240-OHM-25%-0.20A-0.9DCR PP1V8_XTAL 1 1 C1092 2 01005 ROOM=SOC 0.1UF 1 C1093 4UF 20% 2 6.3V X5R-CERM 01005 USB Reference 20% 2 6.3V CER-X5R 0201 ROOM=SOC ROOM=SOC 6 3.14-3.46V @ 12mA MAX PP3V3_USB 1 AP_USB_REXT 1 19 R1000 200 1% 1/32W MF 2 01005 C1095 0.1UF ROOM=SOC 20% 2 6.3V X5R-CERM 01005 ROOM=SOC (Analog) 0.765V - 0.84V @ 5mA MAX U1000 7 8 9 13 14 17 VDD_FIXED_USB AN15 OMIT_TABLE VDD33_USB AN14 C VDD18_XTAL AU28 VDD12_UH1_HSIC0 AT7 VDD18_USB AP14 PP0V8_SOC_FIXED_S1 C TMIT78B0-C4 WLCSP SYM 1 OF 16 ROOM=SOC BA4 NC AY4 NC GND MAKE_BASE=TRUE R1020 1 B 20 IN 10K 5% 1/32W MF 01005 PMU_TO_SYSTEM_COLD_RESET_L 48 BI 48 IN 2 48 20 4 IN 20 4 OUT 16 OUT 16 OUT MAKE_BASE=TRUE AT8 AV6 NC AT9 NC AT12 NC AT10 AT13 SWD_DOCK_BI_AP_SWDIO SWD_DOCK_TO_AP_SWCLK PMU_TO_SYSTEM_COLD_RESET_R_L AU7 PMU_TO_AP_HYDRA_ACTIVE_READY AT34 AV5 AP_TO_PMU_TEST_CLKOUT AP_TO_NAND_RESET_L AP_TO_NAND_FW_STRAP CRITICAL UH1_HSIC0_DATA UH1_HSIC0_STB JTAG_SEL JTAG_TRST* JTAG_TDO JTAG_TDI JTAG_TMS JTAG_TCK ANALOGMUX_OUT AP_TO_PMU_AMUX_OUT AT27 USB_DP USB_DM AY6 BA6 90_USB_AP_DATA_P 90_USB_AP_DATA_N USB_VBUS AV7 USB_VBUS_DETECT USB_ID AW6 USB_REXT AU8 V2 TST_CLKOUT AF34 SSD_RESET* AG38 SSD_BFH GND W5 HOLD_RESET GND W4 TESTMODE 20 BI 48 BI 48 IN 23 PMU_TO_AP_THROTTLE_PCORE_L PMU_TO_AP_THROTTLE_ECORE_L IN 20 IN 20 IN 20 IN 20 NC COLD_RESET* CFSB CFSB_AON OUT AP_USB_REXT CPU_TRIGGER0 CPU_TRIGGER1 AT22 AW21 GPU_TRIGGER0 GPU_TRIGGER1 AD2 AD3 PMU_TO_AP_THROTTLE_GPU0_L PMU_TO_AP_THROTTLE_GPU1_L SOCHOT1 A30 AP_TO_PMU_SOCHOT_L DROOP B31 PMU_TO_AP_PRE_UVLO_L WDOG AW5 AP_TO_PMU_WDOG_RESET XI0 XO0 BA28 BA27 XTAL_AP_24M_IN XTAL_AP_24M_OUT 6 OUT IN OUT B 4 20 4 11 20 20 NOSTUFF 1 R1010 ROOM=SOC 511K 1% 1/32W MF 2 01005 ROOM=SOC Y1000 1.60X1.20MM-SM R1011 1 24.000MHZ-30PPM-9.5PF-60OHM SOC_24M_O 1 3 1.00K 2 5% 1/32W MF 01005 ROOM=SOC 1 C1010 2 4 1 12PF C1011 12PF 5% 2 16V CERM 01005 5% 2 16V CERM 01005 ROOM=SOC ROOM=SOC A SYNC_MASTER=test_mlb SYNC_DATE=10/17/2016 PAGE TITLE SOC: JTAG,USB,XTAL DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 10 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 6 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 SOC - PCIE INTERFACES D R1198 19 14 13 9 PP1V2_SOC 1 PCIe Clock Request Pull-Ups 1 C1198 1 0.1UF R1130 1 5% 1/32W MF 01005 2 ROOM=SOC 5% 1/32W MF 01005 2 ROOM=SOC PP0V8_SOC_FIXED_S1 100K R1121 1 R1131 1 5% 1/32W MF 01005 2 ROOM=SOC 5% 1/32W MF 01005 2 ROOM=SOC 5% 1/32W MF 01005 2 ROOM=SOC VDD18_PCIE AM29 VDD18_PCIE AM31 PP0V8_SOC_FIXED_PCIE_REFBUF R1101 1 100K 1 R1194 PCIE_AP_TO_WLAN_RESET_L PCIE_AP_TO_BB_RESET_L PCIE_AP_TO_NAND_RESET_L C VDD_FIXED_PCIE_REFBUF:0.765V - 0.84V @ 9mA MAX VDD_FIXED_PCIE_ANA:0.765V - 0.84V @ 131mA MAX ROOM=SOC PCIE_NAND_BI_AP_CLKREQ_L PCIE_WLAN_BI_AP_CLKREQ_L 100K (Analog) 100K 1 VDD_FIXED_PCIE_REFBUF AM27 VDD_FIXED_PCIE_REFBUF AP27 16 7 C1199 20% 2 6.3V CER-X5R 0201 VDD_FIXED_PCIE_ANA AN30 VDD_FIXED_PCIE_ANA AP29 VDD_FIXED_PCIE_ANA AP31 50 7 5 6 7 8 10 14 16 17 27 28 29 30 32 34 35 43 4UF 20% 2 6.3V X5R-CERM 01005 PCIe Reset Pull-Downs 50 7 PP1V8_IO ROOM=SOC R1100 1 D 1.62V - 1.98V @ 81mA MAX PP1V2_SOC_PCIE_REFBUF VDD12_PCIE_REFBUF AN26 VDD12_PCIE_REFBUF AP26 50 7 ROOM=SOC PP1V8_IO 100K 16 7 2 0% 1/32W MF 01005 PCIe BB CLKREQ PU on BB domain 29 28 27 17 16 14 10 8 7 6 5 43 35 34 32 30 0.00 (Analog) VDD12_PCIE_REFBUF:1.08V - 1.26V @ 30mA MAX C1194 0.1UF 20% 2 6.3V X5R-CERM 01005 1 0.00 C1193 0.1UF 20% 2 6.3V X5R-CERM 01005 2 0% 1/32W MF 01005 1 C1192 1.0UF 20% 2 6.3V X5R 0201-1 ROOM=SOC 1 6 8 9 13 14 17 C1191 4UF 20% 2 6.3V CER-X5R 0201 ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC U1000 C TMIT78B0-C4 WLCSP SYM 2 OF 16 16 IN IN 90_PCIE_NAND_TO_AP_RXD_P 90_PCIE_NAND_TO_AP_RXD_N 16 4 OUT 16 4 OUT 2 6.3V 01005 1 20% X5R 90_PCIE_AP_TO_NAND_REFCLK_P 90_PCIE_AP_TO_NAND_REFCLK_N AW27 AV27 PCIE_CLKREQ0* PCIE_REF_CLK0_P PCIE_REF_CLK0_N PCIE_CLKREQ3* AJ36 PCIE_WLAN_BI_AP_CLKREQ_L PCIE_REF_CLK3_P PCIE_REF_CLK3_N AY24 BA24 90_PCIE_AP_TO_WLAN_REFCLK_P 90_PCIE_AP_TO_WLAN_REFCLK_N BI 7 50 OUT 50 OUT 50 C1100 C1130 GND_VOID 90_PCIE_NAND_TO_AP_RXD_C_P 90_PCIE_NAND_TO_AP_RXD_C_N ROOM=SOC 0.22UF AL38 PCIE_NAND_BI_AP_CLKREQ_L C1101 AV29 AW29 PCIE_RX0_P PCIE_RX0_N PCIE_RX3_P PCIE_RX3_N BA36 AY36 90_PCIE_WLAN_TO_AP_RXD_C_P 90_PCIE_WLAN_TO_AP_RXD_C_N GND_VOID 1 2 0.1UF 20% 6.3V X5R-CERM 01005 ROOM=SOC C1131 GND_VOID GND_VOID 16 16 OUT OUT 90_PCIE_AP_TO_NAND_TXD_P 90_PCIE_AP_TO_NAND_TXD_N 2 6.3V 01005 IN 50 IN 50 90_PCIE_AP_TO_WLAN_TXD_P 90_PCIE_AP_TO_WLAN_TXD_N OUT 50 OUT 50 90_PCIE_AP_TO_BB_REFCLK_P 90_PCIE_AP_TO_BB_REFCLK_N OUT 50 OUT 50 ROOM=SOC 1 20% X5R C1132 C1102 GND_VOID ROOM=SOC 0.22UF 90_PCIE_WLAN_TO_AP_RXD_P 90_PCIE_WLAN_TO_AP_RXD_N 1 2 0.1UF 20% 6.3V X5R-CERM 01005 ROOM=SOC 2 0.22UF 6.3V 01005 PCIE LINK 3 PCIE LINK 0 16 1 20% X5R BI 1 20% X5R C1103 GND_VOID 16 7 OUT 90_PCIE_AP_TO_NAND_TXD_C_P 90_PCIE_AP_TO_NAND_TXD_C_N AY30 BA30 PCIE_AP_TO_NAND_RESET_L AJ37 PCIE_TX0_P PCIE_TX0_N PCIE_PERST0* PCIE_TX3_P PCIE_TX3_N AV35 AW35 PCIE_PERST3* AH36 90_PCIE_AP_TO_WLAN_TXD_C_P 90_PCIE_AP_TO_WLAN_TXD_C_N PCIE_AP_TO_WLAN_RESET_L GND_VOID 1 2 0.1UF 6.3V 20% X5R-CERM 01005 ROOM=SOC C1133 OUT 7 50 GND_VOID 1 2 0.1UF 20% 6.3V X5R-CERM 01005 ROOM=SOC ROOM=SOC LINK0 LINK3 1 B NC AL37 AW26 NC AY26 NC PCIE_CLKREQ1* PCIE_REF_CLK1_P PCIE_REF_CLK1_N PCIE_CLKREQ2* AK37 PCIE_REF_CLK2_P PCIE_REF_CLK2_N AV25 AW25 PCIE_BB_BI_AP_CLKREQ_L BI C1124 4.7PF 50 +/-0.1PF 2 16V NP0-C0G 01005 ROOM=SOC 1 C1125 4.7PF B +/-0.1PF 2 16V NP0-C0G 01005 ROOM=SOC PCIE LINK 2 2 6.3V 01005 0.22UF 16 7 C1120 AV31 NC AW31 NC PCIE_RX2_P PCIE_RX2_N PCIE_RX1_P PCIE_RX1_N BA34 AY34 90_PCIE_BB_TO_AP_RXD_C_P 90_PCIE_BB_TO_AP_RXD_C_N GND_VOID 0.1UF 1 2 6.3V 20% X5R-CERM 01005 90_PCIE_BB_TO_AP_RXD_P 90_PCIE_BB_TO_AP_RXD_N ROOM=SOC C1121 GND_VOID 1 2 0.1UF 20% 6.3V X5R-CERM 01005 IN 50 IN 50 OUT 50 OUT 50 ROOM=SOC C1122 AY32 NC BA32 NC PCIE_TX1_P PCIE_TX1_N AK38 NC PCIE_PERST1* PCIE_TX2_P PCIE_TX2_N PCIE_PERST2* LINK1 AU30 AT30 AV33 AW33 90_PCIE_AP_TO_BB_TXD_C_P 90_PCIE_AP_TO_BB_TXD_C_N GND_VOID C1123 OUT LINK2 90_PCIE_AP_TO_BB_TXD_P 90_PCIE_AP_TO_BB_TXD_N ROOM=SOC PCIE_AP_TO_BB_RESET_L AJ38 0.1UF 1 2 20% 6.3V X5R-CERM 01005 7 50 GND_VOID 1 2 6.3V 20% X5R-CERM 01005 0.1UF ROOM=SOC PCIE_EXT_REF_CLK_P PCIE_EXT_REF_CLK_N PCIE_REXT AU32 AP_PCIE_RCAL 1 A R1150 200 SYNC_MASTER=test_mlb 1% 1/32W MF 2 01005ROOM=SOC SYNC_DATE=10/17/2016 PAGE TITLE SOC: PCIE DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 11 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 7 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 SOC - MIPI & ISP INTERFACES ISP I2C0 PP1V8_IO 29 28 27 17 16 14 10 8 7 6 5 43 35 34 32 30 1 1 R1201 1.00K 17 14 13 9 7 6 ROOM=SOC PP1V8_IO ROOM=SOC C1291 1 1 1 2.2UF 0.1UF 20% 6.3V X5R-CERM 2 01005 ROOM=SOC C1295 2.2UF 20% 2 6.3V X5R-CERM 0201 ROOM=SOC 0.1UF 20% 2 6.3V X5R-CERM 01005 ROOM=SOC ISP I2C1 PP1V8_IO 29 28 27 17 16 14 10 8 7 6 5 43 35 34 32 30 1 VDD18_MIPI VDD_FIXED_MIPI D C1296 F11 F13 G12 G14 20% 6.3V X5R-CERM 2 0201 ROOM=SOC 1 I2C0_ISP_SCL 8 I2C0_ISP_SDA 29 8 5 6 7 8 10 14 16 17 27 28 29 30 32 34 35 43 29 C1290 5% 1/32W MF 2 01005 1.62V - 1.98V @ 10mA MAX PP0V8_SOC_FIXED_S1 D 1.00K 5% 1/32W MF 2 01005 (Analog) 0.765V - 0.84V @ 40mA MAX MIPI Lane & Polarity Swapping R1202 1 R1211 1.00K R1212 1.00K 5% 1/32W MF 2 01005 5% 1/32W MF 2 01005 1 1 ROOM=SOC ROOM=SOC I2C1_ISP_SCL 8 I2C1_ISP_SDA 30 8 U1000 30 TMIT78B0-C4 WLCSP 35 Juliet MIPI 35 35 35 BI BI IN IN 35 IN 90_MIPI_JULIET_TO_AP_DATA0_P 90_MIPI_JULIET_TO_AP_DATA0_N MAKE_BASE MAKE_BASE 90_MIPI_JULIET_TO_AP_DATA1_P 90_MIPI_JULIET_TO_AP_DATA1_N IN 35 SYM 3 OF 16 MAKE_BASE MAKE_BASE 90_MIPI_JULIET_TO_AP_CLK_N 90_MIPI_JULIET_TO_AP_CLK_P 90_MIPI_JULIET_TO_AP_DATA0_P 90_MIPI_JULIET_TO_AP_DATA0_N B12 A12 90_MIPI_JULIET_TO_AP_DATA1_P 90_MIPI_JULIET_TO_AP_DATA1_N B14 A14 90_MIPI_JULIET_TO_AP_CLK_N 90_MIPI_JULIET_TO_AP_CLK_P MAKE_BASE MAKE_BASE A13 B13 D12 D13 MIPI0C_REXT 8 MIPI1C_REXT C 8 32 FCAM MIPI 32 90_MIPI_FCAM_TO_AP_DATA0_N 90_MIPI_FCAM_TO_AP_DATA0_P BI BI 90_MIPI_FCAM_TO_AP_DATA0_N 90_MIPI_FCAM_TO_AP_DATA0_P MAKE_BASE MAKE_BASE B17 A17 MIPI0C_DPDATA0 MIPI0C_DNDATA0 MIPI0C_DPDATA1 MIPI0C_DNDATA1 MIPI0C_DPCLK MIPI0C_DNCLK MIPI0C_REXT MIPI1C_REXT ROOM=SOC ISP_I2C0_SCL ISP_I2C0_SDA W35 V38 I2C0_ISP_SCL I2C0_ISP_SDA ISP_I2C1_SCL ISP_I2C1_SDA W36 Y36 I2C1_ISP_SCL I2C1_ISP_SDA I2C2_ISP_SCL I2C2_ISP_SDA ISP_I2C2_SCL ISP_I2C2_SDA Y34 Y38 ISP_I2C3_SCL ISP_I2C3_SDA AA37 AB38 I2C3_ISP_SCL I2C3_ISP_SDA OUT ISP I2C2 8 29 8 29 BI PP1V8_IO 29 28 27 17 16 14 10 8 7 6 5 43 35 34 32 30 OUT 8 30 8 30 BI OUT 1.00K 8 32 MIPI1C_DPDATA0 MIPI1C_DNDATA0 32 32 IN 32 IN 90_MIPI_FCAM_TO_AP_DATA1_N 90_MIPI_FCAM_TO_AP_DATA1_P MAKE_BASE MAKE_BASE B15 A15 MIPI1C_DPDATA1 MIPI1C_DNDATA1 SENSOR_INT AB36 RIGEL_TO_ISP_INT IN 33.2 AP_TO_WIDE_CLK 2 OUT 1% 1/32W MF 01005 4 20 34 ISP I2C3 29 PP1V8_IO 29 28 27 17 16 14 10 8 7 6 5 43 35 34 32 30 ROOM=SOC 32 32 43 43 90_MIPI_FCAM_TO_AP_CLK_P 90_MIPI_FCAM_TO_AP_CLK_N IN IN 90_MIPI_FCAM_TO_AP_CLK_P 90_MIPI_FCAM_TO_AP_CLK_N MAKE_BASE MAKE_BASE A16 B16 90_MIPI_AP_TO_DISPLAY_DATA0_P 90_MIPI_AP_TO_DISPLAY_DATA0_N BI BI A10 B10 MIPI1C_DPCLK MIPI1C_DNCLK MIPID_DPDATA0 MIPID_DNDATA0 C I2C2_ISP_SCL 8 I2C2_ISP_SDA R1240 1 90_MIPI_FCAM_TO_AP_DATA1_N 90_MIPI_FCAM_TO_AP_DATA1_P ROOM=SOC 32 8 8 28 31 34 35 BI 5% 1/32W MF 2 01005 ROOM=SOC 8 28 31 34 35 R1222 1.00K 5% 1/32W MF 2 01005 8 32 BI OUT R1221 SENSOR0_CLK SENSOR1_CLK SENSOR2_CLK 1 R1241 AP_TO_WIDE_CLK_R AP_TO_TELE_CLK_R AP_TO_FCAM_JULIET_RIGEL_CLK_R U38 R38 R37 1 33.2 AP_TO_TELE_CLK 2 1 R1231 1.00K OUT 1.00K 5% 1/32W MF 2 01005 30 1% 1/32W MF 01005 R1232 5% 1/32W MF 2 01005 ROOM=SOC ROOM=SOC Display MIPI ROOM=SOC 43 OUT 43 OUT 43 OUT 43 OUT 43 OUT 43 OUT 43 43 OUT OUT 90_MIPI_AP_TO_DISPLAY_DATA1_P 90_MIPI_AP_TO_DISPLAY_DATA1_N MAKE_BASE 90_MIPI_AP_TO_DISPLAY_DATA3_P 90_MIPI_AP_TO_DISPLAY_DATA3_N MAKE_BASE MAKE_BASE MAKE_BASE 90_MIPI_AP_TO_DISPLAY_CLK_N 90_MIPI_AP_TO_DISPLAY_CLK_P MAKE_BASE MAKE_BASE 50 28 21 20 12 A9 A7 B7 90_MIPI_AP_TO_DISPLAY_DATA2_N 90_MIPI_AP_TO_DISPLAY_DATA2_P A6 B6 90_MIPI_AP_TO_DISPLAY_CLK_N 90_MIPI_AP_TO_DISPLAY_CLK_P A8 B8 AP_TO_MANY_BSYNC DISPLAY_TO_AP_ALIVE OUT 43 B9 90_MIPI_AP_TO_DISPLAY_DATA3_P 90_MIPI_AP_TO_DISPLAY_DATA3_N MAKE_BASE 90_MIPI_AP_TO_DISPLAY_DATA2_N 90_MIPI_AP_TO_DISPLAY_DATA2_P B 90_MIPI_AP_TO_DISPLAY_DATA1_P 90_MIPI_AP_TO_DISPLAY_DATA1_N MAKE_BASE IN NC 8 MIPID_REXT MIPID_DPDATA2 MIPID_DNDATA2 MIPID_DPCLK MIPID_DNCLK DISP_TOUCH_BSYNC0 DISP_TOUCH_BSYNC1 AB6 DISP_TOUCH_EB D11 MIPID_REXT Y4 SENSOR0_RST SENSOR1_RST SENSOR2_RST SENSOR3_RST SENSOR4_RST V34 U35 AB34 AC37 NC AA35 AP_TO_JULIET_SHUTDOWN_L AP_TO_TELE_SHUTDOWN_L AP_TO_WIDE_SHUTDOWN_L R1242 OUT 35 OUT 30 OUT 29 OUT 4 32 1 SENSOR0_ISTRB SENSOR1_ISTRB SENSOR0_XSHUTDOWN SENSOR1_XSHUTDOWN AP_DEBUG3 OUT 4 35 34 31 28 OUT 32 35 OUT 34 R1243 33.2 AP_TO_RIGEL_CLK 2 1% 1/32W MF 01005 ROOM=SOC NC U37 NC T37 AP_TO_FCAM_JULIET_CLK 2 ROOM=SOC 1 V36 U36 33.2 I2C3_ISP_SCL 8 I2C3_ISP_SDA 35 34 31 28 8 1% 1/32W MF 01005 AP_TO_FCAM_SHUTDOWN_L MIPID_DPDATA3 MIPID_DNDATA3 AA3 AB4 AA4 NC AA5 NC NC MIPID_DPDATA1 MIPID_DNDATA1 ISP_TO_DISPLAY_FLASH_INT B OUT 43 DISP_I2C_SCL DISP_I2C_SDA DISP_POL MIPI Reference A MIPI0C_REXT 8 MIPI1C_REXT 8 MIPID_REXT 8 R12501 R12511 R12521 1% 1/32W MF 01005 2 1% 1/32W MF 01005 2 1% 1/32W MF 01005 2 200 200 ROOM=SOC ROOM=SOC SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016 PAGE TITLE 200 SOC: MIPI & ISP DRAWING NUMBER ROOM=SOC Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 12 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 8 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 SOC - LPDP (Analog) VDD12_PLL_LPDP VDD12_LPDP 1.14V - 1.26V @ 10mA 1.14V - 1.26V @ 72mA VDD_FIXED_PLL_LPDP VDD_FIXED_LPDP_TX VDD_FIXED_LPDP_RX MAX MAX 0.765V - 0.84V @ 3mA 0.765V - 0.84V @ 16mA 0.765V - 0.84V @ 30mA PP1V2_SOC PP0V8_SOC_FIXED_S1 19 14 13 7 1 D MAX MAX MAX C1390 2.2UF 20% 2 6.3V X5R-CERM 0201 1 C1391 1 2.2UF 0.1UF 20% 2 6.3V X5R-CERM 01005 20% 2 6.3V X5R-CERM 0201 ROOM=SOC C1392 ROOM=SOC ROOM=SOC 1 C1393 0.01UF 10% 2 6.3V X5R 01005 ROOM=SOC 1 C1394 1 C1395 2.2UF 15PF 20% 2 6.3V X5R-CERM 0201 ROOM=SOC 5% 2 16V NP0-C0G-CERM 01005 1 6 7 8 9 13 14 17 C1396 D 2.2UF 20% 6.3V 2 X5R-CERM 0201 ROOM=SOC ROOM=SOC 29 IN 29 IN 90_LPDP_WIDE_TO_AP_D0_P 90_LPDP_WIDE_TO_AP_D0_N A26 B26 LPDPRX_RX_D0_P LPDPRX_RX_D0_N U1000 VDD_FIXED_LPDP_RX G16 G18 VDD_FIXED_LPDP_TX P9 VDD_FIXED_PLL_LPDP R9 VDD12_PLL_LPDP T9 VDD12_LPDP_RX F15 F17 F16 VDD12_LPDP_TX M9 Desense for Wifi frequencies LPDP_TX0P LPDP_TX0N M3 NC M4 NC TMIT78B0-C4 WLCSP SYM 4 OF 16 C 29 IN 29 IN 29 IN 29 IN 30 IN 30 IN 30 IN 30 IN 30 IN 30 IN 29 B 30 BI BI MAKE_BASE=TRUE 17 14 13 9 8 7 6 90_LPDP_WIDE_TO_AP_D1_P 90_LPDP_WIDE_TO_AP_D1_N A25 B25 LPDPRX_RX_D1_P LPDPRX_RX_D1_N LPDP_TX1P LPDP_TX1N L4 L5 90_LPDP_WIDE_TO_AP_D2_P 90_LPDP_WIDE_TO_AP_D2_N A24 B24 LPDPRX_RX_D2_P LPDPRX_RX_D2_N LPDP_TX2P LPDP_TX2N K3 NC K4 NC 90_LPDP_TELE_TO_AP_D0_P 90_LPDP_TELE_TO_AP_D0_N A21 B21 LPDPRX_RX_D3_P LPDPRX_RX_D3_N LPDP_TX3P LPDP_TX3N J4 J5 90_LPDP_TELE_TO_AP_D1_P 90_LPDP_TELE_TO_AP_D1_N A20 B20 LPDPRX_RX_D4_P LPDPRX_RX_D4_N 90_LPDP_TELE_TO_AP_D2_P 90_LPDP_TELE_TO_AP_D2_N A19 B19 LPDPRX_RX_D5_P LPDPRX_RX_D5_N LPDP_WIDE_BI_AP_AUX D21 D20 NC D19 NC D17 D16 NC D15 NC LPDP_TELE_BI_AP_AUX GND GND PP0V8_SOC_FIXED_S1 LPDPRX_AUX_D0_P LPDPRX_AUX_D1_P LPDPRX_AUX_D2_P LPDPRX_AUX_D3_P LPDPRX_AUX_D4_P LPDPRX_AUX_D5_P A22 B22 LPDPRX_BYP_CLK_P LPDPRX_BYP_CLK_N B23 LPDPRX_RCAL_P NC NC C NC NC LPDP_AUX_P LPDP_AUX_N G4 NC G5 NC LPDP_CAL_DRV_OUT LPDP_CAL_VSS_EXT H3 NC H6 NC EDP_HPD DP_WAKEUP Y6 NC Y2 NC B R1300 1 300 1% 1/32W MF 01005-1 2 ROOM=SOC C1301 AP_LPDPRX_RCAL_NEG A23 LPDPRX_RCAL_N D18 LPDPRX_EXT_C 1 100PF NC 5% 16V NP0-C0G 2 01005 ROOM=SOC A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016 PAGE TITLE SOC: LPDP DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 13 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 9 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 SOC - SERIAL INTERFACES AP I2C0 29 28 27 17 16 14 10 8 7 6 5 43 35 34 32 30 PP1V8_IO R1400 1 R1401 1 5% 1/32W MF 01005 2 ROOM=SOC 5% 1/32W MF 01005 2 ROOM=SOC 2.2K 2.2K I2C0_AP_SCL I2C0_AP_SDA 10 49 46 20 10 49 46 20 D D AP I2C1 R1460 38 OUT I2S_AP_TO_CODEC_MCLK1 1 33.2 29 28 27 17 16 14 10 8 7 6 5 43 35 34 32 30 2 1% 1/32W MF 01005 38 38 OUT ROOM=SOC 38 IN 38 OUT OUT I2S_AP_TO_CODEC_MCLK1_R I2S_AP_TO_CODEC_ASP3_BCLK I2S_AP_TO_CODEC_ASP3_LRCLK I2S_CODEC_ASP3_TO_AP_DIN I2S_AP_TO_CODEC_ASP3_DOUT AV23 AW23 AT24 AT25 AT26 I2S0_MCK I2S0_BCLK I2S0_LRCK I2S0_DIN I2S0_DOUT I2C0_AP_SCL I2C0_AP_SDA I2C0_SCL I2C0_SDA AG3 AG2 I2C1_SCL I2C1_SDA AD38 AD36 I2C1_AP_SCL I2C1_AP_SDA I2C2_SCL I2C2_SDA A34 B34 I2C2_AP_SCL I2C2_AP_SDA OUT I2C3_SCL I2C3_SDA AC36 AC38 I2C3_AP_SCL I2C3_AP_SDA OUT SMC_I2CM0_SCL SMC_I2CM0_SDA AY16 AW16 I2C0_SMC_SCL I2C0_SMC_SDA OUT SMC_I2CM1_SCL SMC_I2CM1_SDA AT20 AU20 I2C1_SMC_SCL I2C1_SMC_SDA OUT 10 48 IN 10 48 IN 4 47 IN 50 U1000 TMIT78B0-C4 WLCSP SYM 6 OF 16 ROOM=SOC OUT BI OUT BI PP1V8_IO 10 20 46 49 R1410 1 R1411 1 5% 1/32W MF 01005 ROOM=SOC 2 5% 1/32W MF 01005 ROOM=SOC 2 2.2K 10 20 46 49 10 33 49 2.2K 10 33 49 I2C1_AP_SCL I2C1_AP_SDA 10 49 33 10 AH34 NC AG36 NC AG35 NC AH38 NC AG37 NC I2S1_MCK I2S1_BCLK I2S1_LRCK I2S1_DIN I2S1_DOUT R1464 50 OUT I2S_AP_TO_SPKRAMP_TOP_MCLK 1 33.2 I2S_AP_TO_SPKRAMP_TOP_MCLK_R 2 1% 1/32W MF 01005 ROOM=SOC 47 4 BI 47 4 OUT 38 C IN 50 OUT 50 OUT 50 IN 50 OUT AP_BI_CCG2_SWDIO AP_TO_CCG2_SWCLK CODEC_TO_AP_INT_L AT35 AT36 NC AR36 AR34 AR35 AG4 NC AG5 AH2 AH6 AH4 I2S_BB_TO_AP_BCLK I2S_BB_TO_AP_LRCLK I2S_BB_TO_AP_DIN I2S_AP_TO_BB_DOUT I2S2_MCK I2S2_BCLK I2S2_LRCK I2S2_DIN I2S2_DOUT SMC_UART0_RXD SMC_UART0_TXD I2S3_MCK I2S3_BCLK I2S3_LRCK I2S3_DIN I2S3_DOUT SEP_SPI0_SCLK SEP_SPI0_MISO SEP_SPI0_MOSI BI BI BI CCG2_TO_SMC_INT_L IKTARA_TO_SMC_INT AW19 AW15 AL6 NC AM5 NC AM4 10 50 49 33 10 50 AP I2C2 10 42 50 29 28 27 17 16 14 10 8 7 6 5 43 35 34 32 30 10 42 50 10 21 22 23 47 50 R1421 1 5% 1/32W MF 01005 2 ROOM=SOC 5% 1/32W MF 01005 2 ROOM=SOC I2C2_AP_SCL I2C2_AP_SDA 10 AP I2C3 PP1V8_IO 20 R1430 1 R1431 1 5% 1/32W MF 01005 ROOM=SOC 2 5% 1/32W MF 01005 ROOM=SOC 2 2.2K SEP_I2C_SCL SEP_I2C_SDA I2C4_AP_SCL I2C4_AP_SDA AL2 CKPLUS_WAIVE=I2C_PULLUP AM3 CKPLUS_WAIVE=I2C_PULLUP 2.2K 50 10 29 28 27 17 16 14 10 8 7 6 5 43 35 34 32 30 IN R1420 1 2.2K 10 21 22 23 47 50 50 PMU_TO_SEP_DOUBLE_CLICK_DET PP1V8_IO 10 C 2.2K 10 I2C3_AP_SCL I2C3_AP_SDA 10 50 42 10 R1465 16 5 OUT SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0 1 0.00 16 5 4 IN 16 5 OUT 50 5 IN 2 0% 1/32W MF 01005 SPI_S4E_TO_AP_MISO_BOOT_CONFIG2 SPI_AP_TO_S4E_MOSI_BOOT_CONFIG1 SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0_R BOARD_ID3 AV22 BA21 BA22 AU22 50 42 SPI0_MISO SPI0_MOSI SPI0_SCLK SPI0_SSIN SMC I2C 48 47 46 38 22 20 17 14 12 10 50 49 ROOM=SOC R1461 50 OUT SPI_AP_TO_RACER_SCLK 1 0.00 50 50 IN OUT 2 0% 1/32W MF 01005 50 OUT SPI_RACER_TO_AP_MISO SPI_AP_TO_RACER_MOSI SPI_AP_TO_RACER_SCLK_R SPI_AP_TO_RACER_CS_L AU23 AY22 AW22 AT23 R1482 SPI1_MISO SPI1_MOSI SPI1_SCLK SPI1_SSIN SPMI_SCLK SPMI_SDATA DWI_CLK DWI_DO ROOM=SOC R1462 38 OUT SPI_AP_TO_CODEC_SCLK 1 0.00 38 IN 38 OUT 2 0% 1/32W MF 01005 38 OUT SPI_CODEC_TO_AP_MISO SPI_AP_TO_CODEC_MOSI SPI_AP_TO_CODEC_SCLK_R SPI_AP_TO_CODEC_CS_L AE4 AE2 AD5 AE6 SPI2_MISO SPI2_MOSI SPI2_SCLK SPI2_SSIN SPMI_PMGR_TO_PMU_SCLK_R SPMI_PMU_BI_PMGR_SDATA AV21 AW20 1 BI 2 OUT 20 SPI3_MISO SPI3_MOSI SPI3_SCLK SPI3_SSIN CLK24M_OUT 5% 1/32W MF 01005 2 ROOM=SOC R1450 1 R1451 1 5% 1/32W MF 01005 2 ROOM=SOC 5% 1/32W MF 01005 2 ROOM=SOC AP_TO_RACER_REF_CLK OUT 4.7K 50 NAND_SYS_CLK AP_TO_NAND_SYS_CLK_R BA20 48 0.00 2 AP_TO_NAND_SYS_CLK OUT AP I2C4 16 0% 1/32W MF 01005 Place series terminations close to SoC Pins 29 28 27 17 16 14 10 8 7 6 5 43 35 34 32 30 PP1V8_IO ROOM=SOC R1470 1 R1471 1 5% 1/32W MF 01005 ROOM=SOC 2 5% 1/32W MF 01005 2 ROOM=SOC 4.7K 10 10 I2C4_AP_SCL I2C4_AP_SDA A1 C1490 0.47UF VCC 20% 2 6.3V X5R 01005 U1490 ROOM=SOC B1 A SCL WLCSP I2C4_AP_SDA I2C4_AP_SCL SDA A2 OMIT_TABLE 10 10 SYNC_MASTER=test_mlb SYNC_DATE=10/17/2016 PAGE TITLE VSS SOC: Serial ROOM=SOC REFERENCE DESIGNATOR(S) CRITICAL B2 TABLE_5_HEAD DESCRIPTION BOM OPTION CRITICAL DRAWING NUMBER Apple Inc. TABLE_5_ITEM 335S00234 1 WLCSP U1490 CRITICAL 4.7K PP1V8_IO 1 QTY COMMON 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION 335S00234 BOM_TABLE_ALTS REF DES COMMENTS: U1490 14 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE TABLE_ALT_ITEM 335S00233 U1490 II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 10 OF 51 IV ALL RIGHTS RESERVED 8 7 6 B I2C1_SMC_SCL I2C1_SMC_SDA 10 48 10 R1480 SPI: Route as Daisy-Chain. No T's Allowed PART# 4.7K ROOM=SOC 1 29 28 27 17 16 14 10 8 7 6 5 43 35 34 32 30 2.2K PP1V8_S2 0% 1/32W MF 01005 AP_TO_RACER_REF_CLK_R AV19 5% 1/32W MF 01005 2 ROOM=SOC I2C0_SMC_SCL I2C0_SMC_SDA 10 48 47 46 38 22 20 17 14 12 10 50 49 R1481 2 R1441 1 50 47 23 22 21 10 50 47 23 22 21 0.00 R1440 1 2.2K SPMI_PMGR_TO_PMU_SCLK ROOM=SOC AE36 NC AF36 NC ROOM=SOC B 0.00 0% 1/32W MF 01005 4 20 1 AE38 NC AE35 NC AF38 NC AE37 NC PP1V8_S2 5 4 3 2 . 1 SIZE D A 8 7 6 5 4 3 2 1 D D SOC - GPIO INTERFACES U1000 TMIT78B0-C4 WLCSP SYM 5 OF 16 43 28 OUT 50 OUT 50 OUT 50 OUT 50 C OUT OUT 28 IN 50 OUT 50 OUT 50 OUT 50 50 OUT OUT 5 4 IN 50 IN 20 IN 50 OUT 50 OUT 5 IN 50 48 20 IN 4 OUT 5 IN 5 IN 20 IN 50 OUT 50 IN 5 IN 5 IN 5 IN 5 IN AP_TO_DISPLAY_RESET_L NC AP_TO_CAMPMU_RESET_L AP_TO_NFC_DEV_WAKE AP_TO_BB_COREDUMP AP_TO_BB_RESET_L NC AP_TO_BB_IPC_GPIO1 NC CAMPMU_TO_AP_IRQ_L AP_TO_GNSS_WAKE NC AP_TO_BT_WAKE AP_TO_SPKRAMP_TOP_RESET_L NC AP_TO_NFC_FW_DWLD_REQ NC AP_TO_RACER_RESET_L BOARD_ID0 SPKRAMP_TOP_TO_AP_INT_L PMU_TO_AP_BUTTON_VOL_UP_L AP_TO_BBPMU_RADIO_ON_L AP_TO_WLAN_DEVICE_WAKE NC NC PP1V8_IO PMU_HYDRA_TO_AP_FORCE_DFU DFU_STATUS PP1V8_IO BOARD_ID4 AP_TO_PMU_AMUX_SYNC AP_TO_BB_TIME_MARK BB_TO_AP_RESET_DETECT_L NC BOARD_REV3 BOARD_REV2 BOARD_REV1 BOARD_REV0 AL4 T35 R36 P38 R35 N37 L37 K38 K34 L35 D33 C34 D32 D29 B33 A32 P6 P4 R4 R3 R2 T5 T4 T3 T2 U6 U4 U2 V5 V4 V3 AJ3 AJ4 AJ5 AJ6 AK3 AK4 AK5 GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 GPIO_16 GPIO_17 GPIO_18 GPIO_19 GPIO_20 GPIO_21 GPIO_22 GPIO_23 GPIO_24 GPIO_25 GPIO_26 GPIO_27 GPIO_28 GPIO_29 GPIO_30 GPIO_31 GPIO_32 GPIO_33 GPIO_34 GPIO_35 GPIO_36 GPIO_37 NOSTUFF ROOM=SOC TMR32_PWM0 TMR32_PWM1 TMR32_PWM2 D28 C30 A28 PMU_TO_AP_PRE_UVLO_L JULIET_PMU_TO_RIGEL_STROBE_R WLAN_TO_AP_TIME_SYNC UART0_RXD UART0_TXD AF3 AF2 UART_AP_DEBUG_RXD UART_AP_DEBUG_TXD UART1_CTS* UART1_RTS* UART1_RXD UART1_TXD P34 L36 P36 M37 UART_BT_TO_AP_CTS_L UART_AP_TO_BT_RTS_L UART_BT_TO_AP_RXD UART_AP_TO_BT_TXD UART2_CTS* UART2_RTS* UART2_RXD UART2_TXD B28 B29 C28 B30 UART_GNSS_TO_AP_CTS_L UART_AP_TO_GNSS_RTS_L UART_GNSS_TO_AP_RXD UART_AP_TO_GNSS_TXD UART3_CTS* UART3_RTS* UART3_RXD UART3_TXD D30 B32 C32 D31 UART_NFC_TO_AP_CTS_L UART_AP_TO_NFC_RTS_L UART_NFC_TO_AP_RXD UART_AP_TO_NFC_TXD UART4_CTS* UART4_RTS* UART4_RXD UART4_TXD K36 M35 N36 N35 UART_WLAN_TO_AP_CTS_L UART_AP_TO_WLAN_RTS_L UART_WLAN_TO_AP_RXD UART_AP_TO_WLAN_TXD UART6_RXD UART6_TXD AF5 AF4 UART_ACCESSORY_TO_AP_RXD UART_AP_TO_ACCESSORY_TXD UART7_RXD UART7_TXD R5 NC P2 NC IN 4 6 20 R1500 1 IN 50 IN 48 OUT 48 IN 50 OUT 50 IN 50 OUT 50 IN 50 OUT 50 IN 50 OUT 50 IN 50 OUT 50 IN 50 OUT 50 IN 50 OUT 50 IN 50 OUT 50 IN 48 OUT 48 200K 2 JULIET_PMU_TO_RIGEL_STROBE OUT 34 35 1% 1/32W MF 01005 ROOM=SOC C B B 20 IN 20 IN PMU_TO_AP_BUTTON_POWER_KEY_L PMU_TO_AP_BUTTON_VOL_DOWN_L AB2 AC4 REQUEST_DFU1 REQUEST_DFU2 A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016 PAGE TITLE SOC: GPIO & UART DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 15 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 11 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 SOC - AOP 1.8V @ 15mA MAX 48 47 46 38 22 20 17 14 12 10 50 49 PP1V8_S2 1 C1690 4UF 20% 2 6.3V CER-X5R 0201 ROOM=SOC C1691 0.1UF 20% 2 6.3V X5R-CERM 01005 D ROOM=SOC VDDIO18_AOP VDDIO18_AOP VDDIO18_AOP VDDIO18_AOP AP13 AP15 AP17 AP19 D 1 14 4 AOP I2C Pull-Ups 1 R1620 1.00K 5% 1/32W MF 2 01005 ROOM=SOC 1 R1621 1.00K 5% 1/32W MF 2 01005 ROOM=SOC 1 R1622 1.00K 5% 1/32W MF 2 01005 ROOM=SOC 26 IN 1 26 4 R1623 35 1.00K 5% 1/32W MF 2 01005 OUT IN OUT IN 50 IN 38 OUT 50 28 21 20 8 ROOM=SOC IN 4 12 25 41 49 50 20 4 12 25 41 49 50 IN 50 41 OUT 38 OUT 49 41 38 OUT 12 36 36 IN 50 IN 36 IN 49 25 4 IN 50 IN 50 41 38 IN 26 4 IN 26 4 OUT R1603 I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK 1 49.9 2 OUT 50 41 12 36 C IN BI 26 10 12 14 17 20 22 38 46 47 48 49 50 I2C1_AOP_SCL I2C1_AOP_SDA I2C0_AOP_SCL I2C0_AOP_SDA 50 49 41 38 26 4 26 4 PP1V8_S2 OUT 1% 1/32W MF 01005 ROOM=SOC R1604 50 49 41 38 IN I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK 1 49.9 AOP_TO_DDR_SLEEP1_READY ACCEL_GYRO_TO_AOP_DATARDY SPI_AOP_TO_ACCEL_GYRO_CS_L ACCEL_GYRO_TO_AOP_INT SPI_AOP_TO_PHOSPHORUS_CS_L PHOSPHORUS_TO_AOP_INT ROMEO_TO_AOP_B2B_DETECT RACER_TO_AOP_INT_L AOP_TO_CODEC_RESET_L AP_TO_MANY_BSYNC PMU_TO_AOP_IRQ_L AOP_TO_SPKRAMP_BOT_ARC_RESET_L SPKRAMP_BOT_ARC_TO_AOP_INT_L AOP_TO_CODEC_CLP_EN I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT PROX_BI_AP_AOP_INT_L HALL3_TO_AOP_IRQ_L ALS_TO_AOP_INT_L COMPASS_TO_AOP_INT HALL2_TO_AOP_IRQ_L I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK_R I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK_R I2S_CODEC_ASP1_TO_AOP_AMPS_DIN AT11 AU14 NC AU13 NC AW10 AW11 AT16 AV11 AY10 AV12 AY11 AU16 AV16 AT17 NC AV13 AW12 AV14 AW13 AU17 AV15 AY13 NC BA11 AV17 BA10 NC AT18 AW14 AV18 BA12 AY14 AON_DDR_RESET* U1000 TMIT78B0-C4 AOP_FUNC_0 WLCSP SYM 7 OF 16 AOP_FUNC_1 AOP_PDM_CLK0 ROOM=SOC AOP_FUNC_2 AOP_PDM_DATA0 AOP_FUNC_3 AOP_PDM_DATA1 AOP_FUNC_4 SPI SCM AOP_FUNC_5 RT_CLK32768 AOP_FUNC_6 AOP_SWD_TCK_OUT AOP_FUNC_7 AOP_FUNC_8 AOP_SWD_TMS0 AOP_FUNC_9 AOP_SWD_TMS1 AOP_FUNC_10 SWD_TMS2 AOP_FUNC_11 SWD_TMS3 AOP_FUNC_12 AOP_FUNC_13 AOP_I2CM0_SCL AOP_FUNC_14 AOP_I2CM0_SDA AOP_FUNC_15 AOP_PDM_CLK4 AOP_FUNC_16 AOP_I2CM1_SCL AOP_FUNC_17 AOP_I2CM1_SDA I2C0 SCM AOP_FUNC_18 AOP_FUNC_19 AOP_FUNC_20 AOP_FUNC_21 AOP_FUNC_22 I2C1 SCM AOP_FUNC_23 AOP_FUNC_24 AOP_FUNC_25 AOP_FUNC_26 BA16 AW18 AW17 NC BA18 AV20 AY17 AT21 AC5 AC2 NC CODEC_TO_AOP_GPIO1 CODEC_TO_AOP_GPIO2 PMU_TO_AOP_CLK32K SWD_AOP_TO_MANY_SWCLK SWD_AOP_BI_RACER_SWDIO SWD_AOP_BI_BB_SWDIO SWD_AP_BI_NAND_SWDIO IN 38 IN 38 IN 20 OUT 4 16 50 BI 50 BI 50 BI 4 16 BA9 AV9 I2C0_AOP_SCL I2C0_AOP_SDA OUT AV10 AW9 I2C1_AOP_SCL I2C1_AOP_SDA OUT DOCK_ATTENTION BA17 HYDRA_TO_NUB_INT DOCK_CONNECT AY19 HYDRA_TO_NUB_DOCK_CONNECT BI BI 12 36 12 36 4 12 25 41 49 50 C 4 12 25 41 49 50 2 1% 1/32W MF 01005 ROOM=SOC R1601 26 4 OUT SPI_AOP_TO_IMU_SCLK 1 49.9 2 1% 1/32W MF 01005 ROOM=SOC B R1602 38 OUT I2S_AOP_TO_CODEC_MCLK2 1 33.2 1% 1/32W MF 01005 ROOM=SOC 50 IN 50 OUT 50 OUT 50 OUT 50 IN 50 OUT 38 OUT 38 IN 38 OUT 38 OUT 2 SPI_IMU_TO_AOP_MISO SPI_AOP_TO_IMU_MOSI SPI_AOP_TO_IMU_SCLK_R AW7 AU10 AV8 AOP_SPI_MISO AOP_SPI_MOSI AOP_SPI_SCLK UART_BB_TO_AOP_RXD UART_AOP_TO_BB_TXD AT14 AY8 AOP_UART0_RXD AOP_UART0_TXD AOP_TO_WLAN_CONTEXT_A AOP_TO_WLAN_CONTEXT_B BA8 AW8 AOP_UART1_RXD AOP_UART1_TXD UART_RACER_TO_AOP_RXD UART_AOP_TO_RACER_TXD AU11 AT15 AOP_UART2_RXD AOP_UART2_TXD I2S_AOP_TO_CODEC_ASP2_BCLK I2S_CODEC_ASP2_TO_AOP_DIN I2S_AOP_TO_CODEC_MCLK2_R I2S_AOP_TO_CODEC_ASP2_LRCLK BA14 AT19 AU19 BA15 AOP_I2S0_BCLK AOP_I2S0_DIN AOP_I2S0_MCK AOP_I2S0_LRCK I2S_AOP_TO_CODEC_ASP2_DOUT BA13 AOP_I2S0_DOUT IN 48 IN 48 B A SYNC_MASTER=test_mlb SYNC_DATE=10/17/2016 PAGE TITLE SOC: AOP DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 16 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 12 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 SOC - CPU, GPU & SOC RAILS 1.06V @ 11.0A MAX 0.8V @ 6A MAX 0.575V @ 2.7A MAX 17 4 PP_CPU_PCORE C1702 1 4UF C1703 4UF 20% 2 4V X5R 0201 ROOM=SOC 20% 2 4V X5R 0201 ROOM=SOC 1.06V @ 18.3A MAX 0.8V @ 10.6A MAX 0.575V @ 3.4A MAX OMIT XW1701 SHORT-20L-0.05MM-SM 2 1 D BUCK0_FB OUT PP_GPU 17 ROOM=SOC 1 1 ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC C1704 C1705 C1706 C1707 14UF 14UF 14UF 14UF 20% 4V X5R 0402-D2X-1 1 3 2 4 ROOM=SOC ROOM=SOC 20% 4V X5R 0402-D2X-1 1 3 20% 4V X5R 0402-D2X-1 1 3 2 4 20% 4V X5R 0402-D2X-1 1 3 2 4 2 4 ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC C1708 C1709 C1710 C1711 C1712 C1713 20% 4V X5R 0402-D2X-1 20% 4V X5R 0402-D2X-1 14UF 14UF 14UF 1 1 20% 4V X5R 0402-D2X-1 1 3 14UF 14UF 3 2 14UF 4 3 2 4 2 4 20% 4V X5R 0402-D2X-1 1 3 20% 4V X5R 0402-D2X-1 1 3 2 4 20% 4V X5R 0402-D2X-1 1 3 2 4 2 4 4UF AA14 AA16 AB11 AB13 AB15 AB17 AB19 AC20 AD15 AE14 AF20 AG9 AG15 AH10 AH12 AH14 AH16 AH18 AH20 U1000 TMIT78B0-C4 WLCSP SYM 8 OF 16 ROOM=SOC VDD_CPU VDD_GPU C 0.7V @ 75mA MAX 19 PP0V7_VDD_LOW_S2 1 C1730 1 C1750 F25 J16 F31 G20 G22 G24 G26 J28 H11 H15 H19 H23 H31 J12 J18 J22 J24 J26 J30 L16 K17 K29 L12 L18 L22 L28 M23 L24 N22 N24 N28 C1731 XW1731 SHORT-20L-0.05MM-SM 20% 2 4V X5R 0201 ROOM=SOC 1 1.01V @ 2.1A MAX 0.735V @ 0.6A MAX 17 PP_CPU_SRAM ROOM=SOC ROOM=SOC C1772 C1773 14UF 14UF 20% 4V X5R 0402-D2X-1 1 3 2 1.06V @ 1.1A MAX 0.80V @ 0.63A MAX 0.675V @ 0.19A MAX B 17 20 4 OUT 20% 4V X5R 0402-D2X-1 1 3 2 4 4 AP_CPU_PCORE_SENSE ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC C1732 C1733 C1734 C1735 C1736 14UF 14UF 14UF 20% 4V X5R 0402-D2X-1 1 3 14UF 14UF 20% 4V X5R 0402-D2X-1 1 3 2 4 20% 4V X5R 0402-D2X-1 1 3 2 4 2 4 ROOM=SOC ROOM=SOC ROOM=SOC C1737 C1738 C1739 14UF 20% 4V X5R 0402-D2X-1 1 3 14UF 20% 4V X5R 0402-D2X-1 1 3 2 4 20% 4V X5R 0402-D2X-1 1 3 C1781 C1782 14UF 14UF 20% 4V X5R 0402-D2X-1 1 3 2 4 20 4 OUT 20% 4V X5R 0402-D2X-1 1 3 2 4 AP_VDD_GPU_SENSE 2 4 AA9 AA18 AA22 AA24 AA28 AA30 AB21 AB25 AB27 AC22 AC24 AC28 AC30 AD9 AD21 AD25 AD27 AD29 AE22 AE24 AE28 AF25 AF27 AG22 AG24 AG28 AH25 AH27 AJ16 AJ18 AJ22 AJ24 AJ28 AK13 AK15 AK19 AK21 AK25 AK27 AL12 AL16 AL18 AL22 AL24 AL28 AL30 AM13 AM25 AN12 AN22 AN24 F22 2 4 14UF 2 4 OMIT XW1790 SHORT-20L-0.05MM-SM 1 BUCK11_FB OUT 18 20 1.06V @ 4.3A MAX 0.8V @ 2.8A MAX 0.575V @ 1.4A MAX PP_CPU_ECORE ROOM=SOC ROOM=SOC ROOM=SOC C1791 C1792 C1793 AH21 VDD_CPU_SENSE VDD_ECPU 20% 4V X5R 0402-D2X-1 1 3 AA10 U10 U12 V13 V15 Y13 Y15 14UF 20% 4V X5R 0402-D2X-1 1 3 2 4 1 20% 4V X5R 0402-D2X-1 1 3 2 4 2 VDD_GPU_SRAM VDD_GPU_SENSE 18 C1794 4UF 14UF 20% 2 4V X5R 0201 ROOM=SOC 4 (Analog) 0.8V @ 6mA MAX 0.8V @ 6mA MAX 0.8V @ 10mA MAX VDD_FIXED_CPU W14 VDD_FIXED_PLL_GPU VDD_FIXED_PLL_SOC K21 VDD12_PLL_CPU VDD12_PLL_GPU VDD12_PLL_SOC W16 L21 M20 6 7 8 9 14 17 (Analog) 1.2V @ 7mA MAX (CPU) 1.2V @ 7mA MAX (GPU) 1.2V @ 20mA MAX (SOC) L20 PP1V2_SOC 1 C1720 0.1UF 20% 2 6.3V X5R-CERM 01005 ROOM=SOC 1 C1721 0.1UF 20% 6.3V 2 X5R-CERM 01005 ROOM=SOC 1 C1722 0.1UF 20% 2 6.3V X5R-CERM 01005 ROOM=SOC 1 XW1760 4UF SHORT-20L-0.05MM-SM 1 2 BUCK2_FB OUT 17 ROOM=SOC NO_XNET_CONNECTION ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC C1762 C1763 C1764 14UF 14UF 14UF 20% 4V X5R 0402-D2X-1 1 3 2 4 VDD_LOW VDD_CPU_SRAM C1761 20% 2 4V X5R 0201 ROOM=SOC ROOM=SOC AA12 AB18 AC9 AC14 AE20 AF14 U14 N23 17 20% 4V X5R 0402-D2X-1 1 3 2 4 14UF N26 H13 H17 H21 H25 K11 K19 K23 G30 M29 OUT D 17 OMIT 20% 4V X5R 0402-D2X-1 1 3 2 4 2 4 20% 4V X5R 0402-D2X-1 1 3 PP0V8_SOC_FIXED_S1 ROOM=SOC BUCK1_FB 20% 2 4V X5R 0201 1 20% 4V X5R 0402-D2X-1 1 3 2 AM15 AM17 AM19 AM21 AN16 AN18 AN20 C1760 4UF NO_XNET_CONNECTION PP_GPU_SRAM ROOM=SOC 2 1 ROOM=SOC 4UF 20% 2 6.3V CER-X5R 0201 ROOM=SOC PP_SOC_S1 4 17 OMIT 4UF 20% 2 4V X5R 0201 ROOM=SOC 0.765V @ 4.9A MAX 0.635V @ 2.6A MAX 7 9 14 19 C1723 4UF 20% 2 6.3V CER-X5R 0201 ROOM=SOC A G13 J20 L19 M13 M15 M21 N10 N12 N16 N18 N29 P13 P15 P19 P21 P25 P27 R10 R12 R16 R18 R22 R24 R28 T13 T15 T19 T21 T25 T27 U16 U18 U22 U24 U28 U30 V19 V21 V25 V27 W18 W22 W24 W28 W30 Y19 Y25 Y21 Y27 U1000 TMIT78B0-C4 WLCSP SYM 9 OF 16 ROOM=SOC VDD_SOC VDD_SOC_SENSE C B P23 TP_SOC_SENSE OUT 4 SYNC_MASTER=test_mlb SYNC_DATE=10/17/2016 PAGE TITLE SOC: Power (1/3) DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 17 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 13 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 SOC - POWER SUPPLIES DDR IMPEDANCE CONTROL 18 14 0.6V @ 262mA MAX 18 14 PP0V6_VDDQL_S1 1 D C1830 1 C1831 1 4UF 1 4UF 20% 2 4V X5R 0201 C1832 1 4UF 20% 2 4V X5R 0201 ROOM=SOC 1% 1/32W MF 01005 2ROOM=SOC 20% 2 4V X5R 0201 ROOM=SOC ROOM=SOC AD1 AF1 AH1 AK9 AP9 AT1 AV1 0.8V @ 0.9A MAX PP0V8_SOC_FIXED_S1 ROOM=SOC C1801 14UF 20% 4V X5R 0402-D2X-1 1 3 2 4 1 C1802 4UF 20% 2 4V X5R 0201 ROOM=SOC 1 C1803 4UF 1 C1804 1 4UF 4UF 20% 2 4V X5R 0201 ROOM=SOC 20% 2 4V X5R 0201 ROOM=SOC C1805 20% 2 4V X5R 0201 ROOM=SOC C B AA20 AA26 AB9 AB23 AB29 AC26 AD23 AD31 AE26 AF23 AF29 AG26 AH23 AH29 AJ14 AJ20 AJ26 AK17 AK23 AL14 AL20 AL26 AM11 AM23 AP11 AP21 AP24 F19 F23 M11 M17 N14 N20 P11 P17 P29 R14 R20 R26 T11 T17 T23 T31 U20 U26 V17 V23 V29 W20 W26 Y9 Y17 Y23 Y29 U1000 TMIT78B0-C4 WLCSP SYM 10 OF 16 ROOM=SOC PP1V2_LPADC 1 C1870 2.2UF LPADC_REF_P LPADC_REF_M ROOM=SOC 42 19 17 14 PP1V1_S2 (Analog) 1.2V @ 16mA MAX 19 13 9 7 PP1V2_SOC 0.875V @ 0.8A MAX 0.730V @ 0.51A MAX 0.600V @ 0.35A MAX 17 PP_DCS_S1 C1860 WLCSP 1.8V @ 60mA MAX SYM 12 OF 16 26UF 20% 2 4V X5R 0402-0.1MM ROOM=SOC 1 C1811 4UF 20% 2 6.3V CER-X5R 0201 ROOM=SOC 1 C1812 4UF 20% 2 6.3V CER-X5R 0201 1 C1813 VDD18_TSADC_CPU0 VDD18_TSADC_CPU1 VDD18_TSADC_CPU2 VDD18_TSADC_CPU3 T12 AF21 AJ9 Y16 VDDIO18_GRP2 VDD18_TSADC_GPU0 G21 VDDIO18_GRP3 VDD18_TSADC_SOC0 VDD18_TSADC_SOC1 VDD18_TSADC_SOC2 AJ12 AD30 J31 VDD18_EFUSE1 VDD18_EFUSE2 VDD18_FMON VDD18_LPOSC H12 AT6 AN13 AN19 ROOM=SOC VDDIO18_GRP1 4UF 20% 2 6.3V CER-X5R 0201 ROOM=SOC ROOM=SOC AB31 V31 Y31 F21 D23 AF9 V9 A VDDIO18_GRP4 1 C1861 4UF 20% 2 4V X5R 0201 ROOM=SOC 1 C1862 1 4UF C1863 4UF 20% 2 4V X5R 0201 ROOM=SOC 20% 2 4V X5R 0201 ROOM=SOC Place caps on SoC Corners DCS Voltage Sense -> 1.8V @ 5.3mA MAX (CPU) 1.8V @ 1.1mA MAX (GPU) 1.8V @ 3.3mA MAX (SOC) TMIT78B0-C4 C1810 VDDQL_DDR0 WLCSP SYM 11 OF 16 AP5 AN35 E5 H35 DDR0_RET* DDR1_RET* DDR2_RET* DDR3_RET* AR5 AM35 E3 G35 240 1% 1/32W MF 2 01005 ROOM=SOC 1 R1862 1 240 1% 1/32W MF 01005 2ROOM=SOC R1863 240 1% 1/32W MF 01005 2ROOM=SOC 1 R1870 240 1% 1/32W MF 01005 2ROOM=SOC 1 R1871 D 240 1% 1/32W MF 01005 2ROOM=SOC DDR0_RREF DDR1_RREF DDR2_RREF DDR3_RREF ROOM=SOC AOP_TO_DDR_SLEEP1_READY IN 4 12 IN 16 20 23 VDDQL_DDR1 DDR0_ZQ DDR3_ZQ VDDQL_DDR2 DDR0_SYS_ALIVE DDR1_SYS_ALIVE DDR2_SYS_ALIVE DDR3_SYS_ALIVE AJ2 N38 DDR0_ZQ DDR3_ZQ VDD1 VDDQL_DDR3 PP1V8_IO AR6 AN34 E6 G34 VDDIO11_RET_DDR0 VDDIO11_RET_DDR1 VDDIO11_RET_DDR2 VDDIO11_RET_DDR3 AJ11 AK29 D9 T29 VDDIO12_PLL_DDR0 VDDIO12_PLL_DDR1 VDDIO12_PLL_DDR2 VDDIO12_PLL_DDR3 AJ10 AP10 AE30 AK30 NC SYSTEM_ALIVE AP6 AM34 E4 H34 C 1.8V @ 200mA MAX 1.06V - 1.17V @ (Inc in VDD2) U1000 1 D1 F1 F9 H1 K9 T1 V1 C4 D39 F39 K31 P31 P39 T39 V39 20% 2 4V X5R 0201 ROOM=SOC AP23 AP25 NC VDD_FIXED 4UF PP1V8_IO 6 7 8 9 13 14 17 VDDQL Voltage Sense -> 1 34 32 27 17 8 7 6 5 16 14 10 30 29 28 43 35 ROOM=SOC PP0V8_SOC_FIXED_S1 AK11 AJ29 D8 R29 TMIT78B0-C4 DDR0_RREF DDR1_RREF DDR2_RREF DDR3_RREF R1861 XW1870 SHORT-20L-0.05MM-SM LPADC_GND 1 2 (Analog) 0.8V @ 8mA MAX VDD_FIXED_PLL_DDR0 VDD_FIXED_PLL_DDR1 VDD_FIXED_PLL_DDR2 VDD_FIXED_PLL_DDR3 U1000 1 OMIT 20% 2 6.3V X5R-CERM 0201 BA19 AY20 AD39 AF31 AF39 AK31 AP39 AT39 AV39 19 R1860 240 4UF 20% 2 4V X5R 0201 ROOM=SOC C1833 Place caps on SoC Corners 9 8 7 6 17 14 13 PP0V6_VDDQL_S1 F10 L10 A4 K30 R30 VDD2 VDD_DCS_DDR0 VDD_DCS_DDR1 VDD_DCS_DDR2 AB3 AB37 AW3 AW37 B3 B37 Y3 Y37 AA2 AA38 AC39 AH39 AJ1 AK39 AM1 AN39 AP1 AV2 AV37 AW2 AW38 C2 C3 C38 D38 H39 J1 K39 M1 N39 P1 W1 PP1V8_S2 1 C1840 2.2UF 20% 2 6.3V X5R-CERM 0201 1 C1841 2.2UF 20% 2 6.3V X5R-CERM 0201 ROOM=SOC ROOM=SOC 1 C1842 2.2UF 20% 2 6.3V X5R-CERM 0201 1 C1843 2.2UF 20% 2 6.3V X5R-CERM 0201 ROOM=SOC ROOM=SOC 1.06V - 1.17V @2.2A MAX PP1V1_S2 1 C1850 4UF 20% 2 4V X5R 0201 ROOM=SOC 1 C1851 4UF 20% 2 4V X5R 0201 ROOM=SOC 1 C1852 4UF 20% 2 4V X5R 0201 ROOM=SOC 1 PP1V8_IO PP1V8_LPOSC_S2 C1880 56PF 5% 2 25V NP0-C0G-CERM 01005 ROOM=SOC 4UF 20% 2 4V X5R 0201 ROOM=SOC VDD_DCS_DDR3 5 6 7 8 10 14 16 17 27 28 29 30 32 34 35 43 1 C1881 0.47UF 20% 2 6.3V X5R 01005 5 6 7 8 10 14 16 17 27 28 29 30 32 34 35 43 R1880 1.8V 1 300 2 @ 1mA MAX SYNC_MASTER=test_mlb PP1V8_S2 SYNC_DATE=10/17/2016 PAGE TITLE 10 12 14 17 20 22 38 46 47 48 49 50 SOC: Power (2/3) 5% 1/32W MF 01005 DRAWING NUMBER ROOM=SOC Apple Inc. 051-02221 REVISION 9.0.0 ROOM=SOC NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 18 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 14 OF 51 IV ALL RIGHTS RESERVED 6 B C1853 II NOT TO REPRODUCE OR COPY IT 7 14 17 19 42 1.8V @ 1mA MAX 1 8 10 12 14 17 20 22 38 46 47 48 49 50 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 SOC - POWER SUPPLIES D C B A1 A2 A3 A5 A11 A18 A27 A29 A31 A33 A35 A36 A37 A38 A39 AA1 AA6 AA11 AA13 AA15 AA17 AA19 AA21 AA23 AA25 AA27 AA29 AA31 AA34 AA36 AA39 AB1 AB5 AB10 AB12 AB14 AB16 AB20 AB22 AB24 AB26 AB28 AB30 AB35 AB39 AC1 AC3 AC6 AC15 AC21 AC23 AC25 AC27 AC29 AC31 AC34 AC35 AD4 AD6 AD14 AD20 AD22 AD24 AD26 AD28 AD34 AD35 AD37 AE1 AE3 AE5 AE9 AE15 AE21 AE23 AE25 AE27 AE29 U1000 TMIT78B0-C4 WLCSP SYM 13 OF 16 ROOM=SOC VSS VSS AE31 AE34 AE39 AF6 AF15 AF22 AF24 AF26 AF28 AF30 AF35 AF37 AG1 AG6 AG14 AG20 AG23 AG25 AG27 AG29 AG34 AG39 AH3 AH5 AH9 AH11 AH13 AH15 AH17 AH19 AH22 AH24 AH26 AH28 AH35 AH37 AJ13 AJ15 AJ17 AJ19 AJ21 AJ23 AJ25 AJ27 AJ34 AJ35 AJ39 AK1 AK2 AK6 AK10 AK12 AK14 AK16 AK18 AK20 AK22 AK24 AK26 AK28 AK34 AK35 AK36 AL1 AL3 AL5 AL11 AL13 AL15 AL17 AL19 AL21 AL23 AL25 AL27 AL29 AL31 AL34 AL35 AL36 AL39 AM2 AM6 AM12 AM14 AM16 AM18 AM20 AM22 AM24 AM26 AM28 AM30 AM36 AM37 AM38 AM39 AN1 AN2 AN3 AN4 AN5 AN6 AN11 AN17 AN21 AN23 AN25 AN29 AN31 AN36 AN37 AN38 AP2 AP3 AP4 AP12 AP16 AP18 AP20 AP22 AP28 AP34 AP35 AP36 AP37 AP38 AR1 AR2 AR3 AR4 AR37 AR38 AR39 AT2 AT3 AT4 AT5 AT28 AT29 AT31 AT32 AT33 AT37 AT38 AU1 AU2 AU12 AU15 AU18 AU21 AU24 AU25 AU26 AU27 U1000 TMIT78B0-C4 WLCSP SYM 14 OF 16 ROOM=SOC VSS VSS AU29 AU3 AU4 AU5 AU6 AU9 AU31 AU33 AU34 AU35 AU36 AU37 AU38 AU39 AV3 AV4 AV24 AV26 AV28 AV30 AV32 AV34 AV36 AV38 AW1 AW4 AW24 AW28 AW30 AW32 AW34 AW36 AW39 AY1 AY2 AY3 AY5 AY7 AY9 AY12 AY15 AY18 AY21 AY23 AY25 AY27 AY28 AY29 AY31 AY33 AY35 AY37 AY38 AY39 B1 B2 B4 NC <B5 B11 B18 B27 B35 B36 B38 B39 BA1 BA2 BA3 BA5 BA7 BA23 BA25 BA26 BA29 BA31 BA33 BA35 BA37 BA38 DDR Vss V Sense BA39 C1 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C29 C31 C33 C35 C36 C37 C39 D10 D14 D2 D3 D4 D5 D6 D7 D22 D24 D25 D26 D27 D34 D35 D36 D37 E1 E2 E34 E35 E36 E37 E38 E39 F12 F14 F18 F2 F3 F4 F5 F6 F20 F24 F26 F30 F34 F35 F36 F37 F38 G1 U1000 TMIT78B0-C4 WLCSP SYM 15 OF 16 ROOM=SOC VSS VSS G2 G3 G6 G11 G15 G17 G19 G23 G25 G31 G36 G37 G38 G39 H2 H4 H5 H14 H16 H18 H20 H22 H24 H26 H30 H36 H37 H38 J2 J3 J6 J11 J17 J19 J21 J23 J25 J27 J29 J34 J35 J36 J37 J38 J39 K1 K2 K5 K6 K10 K12 K16 K18 K20 K22 K24 K28 K35 K37 L1 L2 L3 L6 L9 L11 L17 L23 L29 L34 L38 L39 M10 M12 M14 M16 M18 M19 M2 M5 M6 M22 M24 M28 M34 M36 M38 M39 N1 N2 N3 N4 N5 N6 N9 N11 N13 N15 N17 N19 N21 N25 N27 N34 P3 P5 P10 P12 P14 P16 P18 P20 P22 P26 P28 P30 P35 P37 R1 R6 R11 R13 R15 R17 R19 R21 R23 R25 R27 R31 R34 R39 T6 T10 T14 T16 T18 T20 T22 T24 T26 T28 T30 T34 T36 T38 U1 U3 U5 U9 U11 U13 U15 U17 U19 U21 U23 U25 U27 U29 U31 U34 U39 V6 V14 V16 V18 V20 V22 V24 V26 V28 V30 V35 V37 W2 W3 W6 W9 W13 W15 W17 W19 W21 W23 W25 W27 W29 W31 W34 W37 W38 W39 Y1 Y5 Y14 Y18 Y20 Y22 Y24 Y26 Y28 Y30 Y35 Y39 U1000 TMIT78B0-C4 WLCSP SYM 16 OF 16 ROOM=SOC VSS VSS_CPU_SENSE VSS_SENSE AG21 P24 D C TP_VSS_CPU_SENSE TP_VSS_SENSE OUT 4 OUT 4 B A SYNC_MASTER=test_mlb SYNC_DATE=10/17/2016 PAGE TITLE SOC: Power (3/3) DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 19 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 15 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 391mA 28 27 17 16 14 10 8 7 6 5 43 35 34 32 30 29 7 6 5 4 3 2 1 MAX S4E NAND PP1V8_IO 1 C2626 1 4UF C2610 0.1UF 20% 2 4V X5R 0201 ROOM=NAND 20% 2 6.3V X5R-CERM 01005 ROOM=NAND D D 1 C2629 1 18UF 18UF 20% 2 6.3V CER-X5R 0402-0.1MM ROOM=NAND C2624 1 1 4UF C2641 1 4UF 20% 2 4V X5R 0201 1 220PF 932mA 19 C2617 1 20% 2 4V X5R 0201 ROOM=NAND C2623 1 C2612 47PF 5% 2 16V CERM 01005 5% 6.3V 2 NP0-C0G 01005 ROOM=NAND C2647 4UF 68PF 5% 2 16V NP0-C0G 01005 ROOM=NAND 1 ROOM=NAND 100PF 5% 2 10V C0G-CERM 01005 C2645 20% 2 4V X5R 0201 ROOM=NAND C2611 20% 2 6.3V CER-X5R 0402-0.1MM ROOM=NAND 4UF 20% 2 4V X5R 0201 ROOM=NAND 1 1 4UF 20% 2 4V X5R 0201 ROOM=NAND C2643 C2630 ROOM=NAND ROOM=NAND MAX PP0V9_NAND 1 C2602 1 26UF 1 26UF 20% 2 4V X5R 0402-0.1MM C2600 1 4UF ROOM=NAND C2601 4UF 20% 2 4V X5R 0201 20% 2 4V X5R 0402-0.1MM ROOM=NAND C C2605 20% 2 4V X5R 0201 ROOM=NAND ROOM=NAND 1100mA C MAX (1us peak power) PP3V0_NAND 1 C2622 4UF 20% 2 4V X5R 0201 1 4UF 20% 2 4V X5R 0201 ROOM=NAND 1 C2603 220PF 5% 2 10V C0G-CERM 01005 C2627 1 C2606 220PF 5% 2 10V C0G-CERM 01005 ROOM=NAND ROOM=NAND 1 4UF 1 1 100PF C2614 1 ROOM=NAND C2620 1 IN 7 4 IN R2604 3.01K BI 7 IN 7 IN 1% 1/32W MF 2 01005 ROOM=NAND 7 OUT 7 OUT C2621 18UF ROOM=NAND ROOM=NAND ROOM=NAND C2649 4UF 20% 2 6.3V CERM-X5R 0201 ROOM=NAND 1 C2650 4UF 20% 2 6.3V CERM-X5R 0201 ROOM=NAND 1 C2651 4UF 20% 2 6.3V CERM-X5R 0201 ROOM=NAND 1 C2652 4UF 20% 2 6.3V CERM-X5R 0201 ROOM=NAND ROOM=NAND C2615 5% 16V 2 CERM 01005 ROOM=NAND NAND_ANI1_VREF NAND_ANI0_VREF AP_TO_NAND_SYS_CLK M3 90_PCIE_AP_TO_NAND_REFCLK_P 90_PCIE_AP_TO_NAND_REFCLK_N 47PF 5% 2 16V CERM 01005 ROOM=NAND 1 C2631 68PF 5% 2 6.3V NP0-C0G 01005 ROOM=NAND 1 C2632 100PF 5% 2 16V NP0-C0G 01005 ROOM=NAND 1 C2634 220PF 5% 2 10V C0G-CERM 01005 ROOM=NAND 1 C2635 220PF 5% 2 10V C0G-CERM 01005 ROOM=NAND 1 C2636 1 220PF C2637 100PF 5% 2 10V C0G-CERM 01005 5% 2 16V NP0-C0G 01005 ROOM=NAND ROOM=NAND VPP F3 VDD_PLL R4 D3 E12 G4 L12 R2 VCC VDDIO E2 E10 J2 K9 N2 T5 P9 VDD ANI0_VREF G12 ANI1_VREF J4 AVDD18_PLL L2 PCI_VDD_1 N8 PCI_VDD_2 J8 PCI_AVDD_H J6 G6 G8 L6 L8 R6 R8 WFLGA ROOM=NAND PCIE_NAND_BI_AP_CLKREQ_L P5 PCIE_CLKREQ_N PCIE_NAND_RESREF H7 PCI_RESREF M11 N12 PCIE_RX0_P PCIE_RX0_M R12 T11 B U2600 CLK_IN PCIE_REFCLK_P PCIE_REFCLK_M 90_PCIE_NAND_TO_AP_RXD_P 90_PCIE_NAND_TO_AP_RXD_N C2618 THGBX7G8D2LLFXG K11 J12 90_PCIE_AP_TO_NAND_TXD_P 90_PCIE_AP_TO_NAND_TXD_N 1 NC PCI_AVDD_CLK_1 N6 PCI_AVDD_CLK_2 M9 7 4 7 1 IN 18UF ROOM=NAND 1 B 10 1 20% 2 6.3V CER-X5R 0402-0.1MM 22PF OUT 18UF C2619 20% 2 6.3V CER-X5R 0402-0.1MM C2628 1 4 1 20% 2 6.3V CER-X5R 0402-0.1MM 22PF ROOM=NAND OUT C2616 20% 2 6.3V CER-X5R 0402-0.1MM 5% 2 16V CERM 01005 4 1 ROOM=NAND 5% 2 16V CERM 01005 ROOM=NAND C2613 18UF 20% 2 4V X5R 0201 47PF 5% 2 6.3V NP0-C0G 01005 1 C2646 4UF ROOM=NAND 68PF 5% 2 16V NP0-C0G 01005 1 20% 2 4V X5R 0201 ROOM=NAND C2609 C2644 4UF 20% 2 4V X5R 0201 ROOM=NAND 1 C2642 4UF 20% 2 4V X5R 0201 ROOM=NAND 1 C2640 19 BOMOPTION=OMIT_TABLE CRITICAL EXT_D0/BOOT0 EXT_D1/BOOT1 EXT_D2/BOOT2/SPINAND_SCLK EXT_D3/SWD_UID0/SPINAND_MISO EXT_D4/UART_RX EXT_D5/SWD_UID1/SPINAND_MOSI EXT_D6/UART_TX EXT_D7/SPF PCIE_TX0_P PCIE_TX0_M B3 C4 B5 C6 B7 NC C8 B9 NC B11 PMU_TO_NAND_LOW_BATT_BOOT_L AP_TO_NAND_FW_STRAP SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0 SPI_S4E_TO_AP_MISO_BOOT_CONFIG2 SPI_AP_TO_S4E_MOSI_BOOT_CONFIG1 SYSTEM_ALIVE EXT_NCE/PERST* E8 PCIE_AP_TO_NAND_RESET_L EXT_NRE/JTAG_TMS D7 SWD_AP_BI_NAND_SWDIO EXT_NWE/JTAG_TCK E6 SWD_AOP_TO_MANY_SWCLK IN 20 IN 6 IN 5 10 OUT 4 5 10 IN 5 10 IN 14 20 23 IN 7 BI IN 4 12 4 12 50 EXT_RNB/JTAG_TDO E4 EXT_CLE/JTAG_TDI D5 NC EXT_ALE/JTAG_SEL D9 DROOP_N T3 6 IN AP_TO_NAND_RESET_L A L4 Board trace <= 0.2Ohm G10 RESET* PP1V8_IO WP_N G2 5 6 7 8 10 14 16 17 27 28 29 30 32 34 35 43 TRST* SYNC_MASTER=test_mlb NAND_ZQ_C NAND_ZQ_N K3 C10 SYNC_DATE=10/13/2016 PAGE TITLE ZQ_C ZQ_N NAND CKPLUS_WAIVE=MISS_P_DIFFPAIR 1 R2600 100 DRAWING NUMBER R2601 Apple Inc. 300 0.1% 1/32 MF 01005 2ROOM=NAND 051-02221 REVISION 9.0.0 VSS A2 A4 A6 A8 A10 A12 B1 B13 C2 C12 D1 D11 D13 F1 F5 F7 F9 F11 F13 H1 H3 H5 H9 H11 H13 J10 K1 K5 K7 K13 L10 M1 M5 M7 M13 N4 N10 P1 P3 P7 P11 P13 R10 T1 T7 T9 T13 U2 U4 U6 U8 U10 U12 0.1% 1/32W MF 01005 2ROOM=NAND 1 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 26 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 16 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 L2740 42 19 14 1 C2745 4.9A MAX 26UF 1 C2743 1 26UF C2742 26UF 1 C2741 26UF 20% 2 4V X5R 0402-0.1MM 20% 2 4V X5R 0402-0.1MM 20% 2 4V X5R 0402-0.1MM 20% 2 4V X5R 0402-0.1MM 20% 2 4V X5R 0402-0.1MM ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU 1 C2740 ROOM=PMU 220PF 5% 2 10V C0G-CERM 01005 CRITICAL BUCK0_LX0 1 PP_CPU_PCORE PIWA20160H-SM 1 ROOM=PMU L2741 0.47UH-20%-3.3A-0.053OHM 1 2 BUCK4_LX1 PIWA2012FE-SM ROOM=PMU V9 W9 Y9 BUCK0_LX1 N16 N17 N18 BUCK0_LX1 1 C2700 220PF CRITICAL 5% 2 10V C0G-CERM 01005 0.47UH-20%-3.3A-0.053OHM CRITICAL 2 1 26UF T8 1.7A MAX BUCK5 C2752 26UF 20% 2 4V X5R 0402-0.1MM ROOM=PMU 1 C2751 26UF 20% 2 4V X5R 0402-0.1MM ROOM=PMU 1 C2750 ROOM=PMU BUCK0_LX2 BUCK4_FB R16 R17 R18 BUCK0_LX2 1 20% 2 4V X5R 0402-0.1MM ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU PIWA20160H-SM ROOM=PMU V3 W3 Y3 BUCK0_LX3 BUCK5_LX0 U16 U17 U18 BUCK0_LX3 1 2 PINA1608-SM ROOM=PMU OMIT XW2750 SHORT-20L-0.05MM-SM 2 1 BUCK0_FB BUCK5_FB T4 R13 BUCK0_FB IN 13 BUCK5_FB CRITICAL L2710 1.2A MAX BUCK6 20% 2 6.3V X5R 0402-0.1MM-1 ROOM=PMU C C2761 15UF 20% 2 6.3V X5R 0402-0.1MM-1 ROOM=PMU C2760 ROOM=PMU A15 B15 BUCK1_LX0 1 BUCK6_LX0 1 H4 BUCK6_FB BUCK1_LX1 ROOM=PMU (Place Close to Ansel) 5% 2 10V C0G-CERM 01005 ROOM=PMU 0.47UH-20%-4A-0.048OHM BUCK6_FB A13 B13 C13 BUCK1_LX1 1 C2710 220PF L2711 XW2760 SHORT-20L-0.05MM-SM 2 1 ROOM=PMU OMIT ROOM=PMU PP_GPU 2 0806 ROOM=PMU 220PF 5% 2 10V C0G-CERM 01005 BUCK1_LX0 2 1 C2711 26UF 1 C2712 26UF 1 C2713 26UF C2714 1 26UF 1 4 13 C2715 26UF 20% 2 4V X5R 0402-0.1MM 20% 2 4V X5R 0402-0.1MM 20% 2 4V X5R 0402-0.1MM 20% 2 4V X5R 0402-0.1MM 20% 2 4V X5R 0402-0.1MM ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU PIWA20120H-SM CRITICAL ROOM=PMU BUCK2 15UF PIWA2016FE-SM H1 H2 BUCK1 20% 2 6.3V X5R 0402-0.1MM-1 C2762 0.67V - 0.92V 1.03V for overdrive only 1UH-20%-3.6A-0.062OHM 4.9A MAX 15UF 1 ROOM=PMU 13.8A MAX C2763 1 D 20% 2 4V X5R 0402-0.1MM ROOM=PMU L2760 1 C2706 L2703 1UH-20%-2.4A-0.06OHM 2 1 BUCK6_LX0 1 26UF 20% 2 4V X5R 0402-0.1MM 26UF 2 CRITICAL 27 19 C2705 20% 2 4V X5R 0402-0.1MM 1 PINA1608-SM ROOM=PMU PP1V25_S2 26UF 1 0.1UH-20%-6.1A-0.031OHM 220PF 5% 10V 2 C0G-CERM 01005 26UF C2704 1 CRITICAL 1UH-20%-2.5A-0.052OHM 2 1 BUCK5_LX0 1 C2703 20% 2 4V X5R 0402-0.1MM ROOM=PMU L2702 L2750 PP0V8_SOC_FIXED_S1 26UF 1 ROOM=PMU ROOM=PMU 14 13 9 8 7 6 C2702 CRITICAL XW2740 BUCK4_FB 1 20% 2 4V X5R 0402-0.1MM 0.1UH-20%-6.1A-0.031OHM SHORT-20L-0.05MM-SM 2 1 C2701 4 13 PIWA2012FE-SM BUCK4_LX1 OMIT C CRITICAL L2770 0.80V - 1.06V 1UH-20%-2.5A-0.052OHM 2 1 BUCK7_LX0 PP_CPU_SRAM 2.1A MAX BUCK7 13 1 C2772 26UF 1 C2771 26UF 20% 2 4V X5R 0402-0.1MM 20% 2 4V X5R 0402-0.1MM ROOM=PMU ROOM=PMU 1 C2770 PIWA20160H-SM ROOM=PMU 220PF 5% 2 10V C0G-CERM 01005 ROOM=PMU L2712 W16 W17 W18 BUCK7_LX0 BUCK1_LX2 BUCK7_FB W14 BUCK7_FB BUCK1_LX3 1 1.2A MAX BUCK8 1UH-20%-2.5A-0.078OHM 2 1 BUCK8_LX0 PP_GPU_SRAM C2782 26UF 20% 2 4V X5R 0402-0.1MM ROOM=PMU 1 C2781 26UF 20% 2 4V X5R 0402-0.1MM ROOM=PMU 1 C2780 PIWA20120H-SM A17 B17 BUCK8_LX0 BUCK1_FB 2 1 BUCK8_FB 1.2A MAX BUCK9 26UF C2791 26UF 20% 2 4V X5R 0402-0.1MM 20% 2 4V X5R 0402-0.1MM ROOM=PMU ROOM=PMU 1 C2790 PIWA2012FE-SM A6 B6 1 ROOM=PMU 2 0.67V/0.80V BUCK2_LX0 1 PP_SOC_S1 2 PIWA20160H-SM 1 ROOM=PMU 5% 2 10V C0G-CERM 01005 L2721 F4 V7 W7 Y7 C2720 220PF 0.47UH-20%-3.3A-0.053OHM BUCK2_LX1 BUCK9_FB V5 W5 Y5 BUCK9_LX0 OMIT XW2790 SHORT-20L-0.05MM-SM 13 IN CRITICAL ROOM=PMU 220PF 5% 2 10V C0G-CERM 01005 BUCK1_FB BUCK8_FB BUCK2_LX0 1UH-20%-2.1A-0.1OHM BUCK9_LX 2 1 1 F15 1UH-20%-3.2A-0.06OHM L2790 C2792 ROOM=PMU L2720 E17 CRITICAL 1 ROOM=PMU CRITICAL ROOM=PMU PP_DCS_S1 20% 2 4V X5R 0402-0.1MM PINA2012-SM OMIT XW2780 SHORT-20L-0.05MM-SM ROOM=PMU 14 26UF 2 A9 NC B9 NC C9 NC ROOM=PMU 220PF 5% 2 10V C0G-CERM 01005 BUCK1_LX2 1 XW2770 SHORT-20L-0.05MM-SM 2 1 CRITICAL 13 A11 B11 C11 C2716 OMIT L2780 0.80V - 0.92V 1 0.1UH-20%-7.2A-0.018OHM ROOM=PMU B 0.625V - 1.06V 2 L2701 ROOM=PMU (Place in TTS) BUCK4_LX0 BUCK0_LX0 L17 L18 BUCK0 D C2744 PIWA20160H-SM L2700 1UH-20%-3.2A-0.06OHM WLCSP SYM 2 OF 5 ROOM=PMU 1 CRITICAL D2422B0 V11 W11 Y11 2 13.8A MAX BUCK4 26UF 1 3 U2700 1UH-20%-3.2A-0.06OHM 2 1 BUCK4_LX0 PP1V1_S2 4 BUCK2_LX1 1 1 C2721 26UF 1 C2722 26UF 1 C2723 26UF 1 C2724 26UF 20% 2 4V X5R 0402-0.1MM 20% 2 4V X5R 0402-0.1MM 20% 2 4V X5R 0402-0.1MM 20% 2 4V X5R 0402-0.1MM ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU 13 B 2 (Place in TTS) PIWA2012FE-SM ROOM=PMU BUCK9_FB ROOM=PMU BUCK2_FB T7 BUCK2_FB IN 13 L2730 1UH-20%-2.4A-0.06OHM BUCK3_LX0 1 PP1V8_S2 2 PIWA2016FE-SM 1 ROOM=PMU 220PF OMIT 5% 2 10V C0G-CERM 01005 ROOM=PMU XW2730 SHORT-20L-0.05MM-SM BUCK3_FB G4 BUCK3_FB 1 C2730 2 1 C2731 15UF 20% 2 6.3V X5R 0402-0.1MM-1 ROOM=PMU 1 10 12 14 20 22 38 46 47 48 49 50 C2732 15UF 20% 2 6.3V X5R 0402-0.1MM-1 BUCK3 F1 F2 1.7A MAX BUCK3_LX0 ROOM=PMU ROOM=PMU VBUCK3_SW C1 C2 BUCK3_SW1 A2 B1 B2 SWITCH OUTPUTS A PP1V8_IO SYNC_MASTER=test_mlb 5 6 7 8 10 14 16 27 28 29 30 32 34 35 43 SYNC_DATE=10/13/2016 PAGE TITLE SYSTEM POWER: PMU Bucks (1/4) DRAWING NUMBER Apple Inc. BUCK3_SW2 BUCK3_SW3 PP1V8_TOUCH_RACER_S2 PP1V8_IMU_S2 D1 D2 051-02221 REVISION 9.0.0 42 50 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE 25 26 49 evt-1 27 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 17 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 D D CRITICAL U2700 L2800 D2422B0 1UH-20%-2.1A-0.1OHM WLCSP 18UF 20% 2 6.3V CER-X5R 0402-0.1MM 1 18UF 20% 2 6.3V CER-X5R 0402-0.1MM ROOM=PMU 1 C2854 4UF 20% 2 6.3V CERM-X5R 0201 1 4UF 20% 2 6.3V CERM-X5R 0201 ROOM=PMU 1 C2859 4UF 20% 2 6.3V CERM-X5R 0201 C ROOM=PMU C2855 C2860 4UF 20% 2 6.3V CERM-X5R 0201 ROOM=PMU 1 1 C2856 4UF 20% 2 6.3V CERM-X5R 0201 20% 2 6.3V CER-X5R 0402-0.1MM C2861 4UF 20% 2 6.3V CERM-X5R 0201 BUCK10_LX 1 1 C2857 1 1 4UF ROOM=PMU C2863 ROOM=PMU 1 C2865 4UF 20% 2 6.3V CERM-X5R 0201 ROOM=PMU 1 C2866 4UF 20% 2 6.3V CERM-X5R 0201 ROOM=PMU A10 B10 C10 D10 V6 W6 Y6 E1 E2 V10 W10 Y10 V2 W2 Y2 J1 J2 Y15 Y16 Y17 B 5% 2 10V C0G-CERM 01005 OMIT XW2800 BUCK10_FB E4 C2801 1 26UF C2802 26UF 20% 2 4V X5R 0402-0.1MM ROOM=PMU 20% 2 4V X5R 0402-0.1MM ROOM=PMU ROOM=PMU SHORT-20L-0.05MM-SM 2 1 BUCK10_FB 1 CRITICAL L2810 1UH-20%-3.2A-0.06OHM VDD_BUCK0_01 BUCK11_LX0 G17 G18 BUCK11_LX0 1 PP_CPU_ECORE 2 PIWA20160H-SM 1 5% 2 10V C0G-CERM 01005 L2811 VDD_BUCK0_23 0.47UH-20%-4A-0.048OHM J17 J18 BUCK11_LX1 1 C2810 220PF CRITICAL BUCK11_LX1 A14 B14 C14 D14 20% 2 6.3V CERM-X5R 0201 ROOM=PMU 20% 2 6.3V CERM-X5R 0201 T15 T16 T17 T18 4UF 20% 2 6.3V CERM-X5R 0201 4UF C2800 220PF ROOM=PMU ROOM=PMU C2862 C2864 C2858 20% 2 6.3V CERM-X5R 0201 ROOM=PMU 1 M15 M16 M17 M18 4UF 20% 2 6.3V CERM-X5R 0201 ROOM=PMU 1 ROOM=PMU 14 ROOM=PMU 4UF 1 PP0V6_VDDQL_S1 2 PIWA2012FE-SM ROOM=PMU ROOM=PMU 1 C2852 18UF ROOM=PMU ROOM=PMU 1 C2851 A4 B4 1 C2811 26UF 1 C2812 26UF 1 13 C2813 26UF 20% 20% 20% 4V 4V 2 4V 2 2 X5R X5R X5R 0402-0.1MM 0402-0.1MM 0402-0.1MM ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU 2 PIWA20120H-SM ROOM=PMU C VDD_BUCK1_01 BUCK11_FB J15 BUCK11_FB IN 13 20 VDD_BUCK1_23 VDD_BUCK2 VDD_BUCK3 BUCK INPUT C2850 VDD_MAIN_1 VDD_MAIN_2 VDD_MAIN_3 VDD_MAIN_4 VDD_MAIN_5 VDD_MAIN_6 BUCK10_LX0 BUCK11 1 E5 K5 R7 U14 L14 F14 SYM 3 OF 5 ROOM=PMU BUCK10 PP_VDD_MAIN VDD_MAIN_SNS BAT/USB P7 3.0A MAX 45 43 42 41 34 31 27 23 21 19 50 46 IN VDD_MAIN_SNS 1.2A MAX 19 VDD_BUCK4 VDD_BUCK5 VDD_BUCK6 B VDD_BUCK7 B18 C18 VDD_BUCK8 A7 B7 VDD_BUCK9 A3 B3 VDD_BUCK10 H17 H18 VDD_BUCK11 A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016 PAGE TITLE SYSTEM POWER: PMU Bucks (2/4) DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 28 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 18 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 PP_VDD_MAIN 43 42 41 34 31 27 23 21 19 18 50 46 45 OMIT XW2990 18 OUT SHORT-20L-0.05MM-SM 2 1 VDD_MAIN_SNS ROOM=PMU 1 C2990 18UF 1 C2991 18UF 1 C2992 18UF 20% 2 6.3V CER-X5R 0402-0.1MM 20% 2 6.3V CER-X5R 0402-0.1MM 20% 2 6.3V CER-X5R 0402-0.1MM ROOM=PMU ROOM=PMU ROOM=PMU OMIT XW2991 20 OUT PMU_PRE_UVLO_DET SHORT-20L-0.05MM-SM 2 1 ROOM=PMU D D 50 38 34 27 21 19 PP_VDD_BOOST OMIT_TABLE OMIT XW2995 SHORT-20L-0.05MM-SM 20 PMU_LDO5_UVLO_DET OUT 2 1 ROOM=PMU 1 C2970 2.2UF OMIT_TABLE 1 C2971 2.2UF 20% 2 6.3V X5R-CERM 0201 20% 2 6.3V X5R-CERM 0201 ROOM=CAM_PMU ROOM=CAM_PMU U2700 C C D2422B0 WLCSP D2422B0 PP_VDD_MAIN PP_VDD_BOOST WLCSP B A A1 A12 A16 A18 A5 A8 B12 B16 B5 B8 C12 C15 C16 C17 C3 C4 C5 C6 C7 C8 D11 D12 D13 D15 D16 D17 D18 D8 D9 E11 E12 E13 E18 E3 F16 F17 F18 F3 F5 G1 G15 G16 G2 G3 G5 H16 H3 H5 J13 J14 J16 J5 K14 K16 SYM 5 OF 5 ROOM=PMU VSS VSS K17 K18 L16 L6 M7 M11 N7 N15 N8 N9 P10 P11 P15 P16 P17 P18 P8 P9 R15 R8 T3 T5 T6 T9 U10 U11 U12 U15 U3 U4 U5 U6 U7 U8 U9 V12 V15 V16 V17 V18 V4 V8 N12 W12 W15 W4 W8 Y1 Y12 Y13 Y14 Y18 Y4 Y8 42 17 14 PP1V1_S2 OMIT_TABLE C2980 2.2UF OMIT_TABLE 1 20% 6.3V X5R-CERM 2 0201 ROOM=PMU 27 17 C2981 1 2.2UF 20% 6.3V X5R-CERM 2 0201 ROOM=PMU PP1V25_S2 PP2V5_LDO0_S2 19 K4 N4 M4 R5 N1 V1 W1 L1 VDD_LDO0 VDD_LDO1 VDD_LDO2 VDD_LDO3 VDD_LDO4 VDD_LDO5 VDD_LDO5 K1 VDD_BYPASS M1 R2 M6 R6 R4 L4 R3 T1 VDD_LDO7 VDD_LDO8 VDD_LDO9 VDD_LDO10 VDD_LDO11 VDD_LDO12 VDD_LDO13 VDD_LDO14 M5 VDD_VBUF J4 E14 PMU_VSS_RTC SYM 1 OF 5 ROOM=PMU VDD_LDO6 K3 N3 M3 P5 N2 U1 PP2V5_LDO0_S2 PP3V3_USB PP1V8_AUDIO_VA_S2 PP3V0_CONVOY PP0V7_VDD_LOW_S2 PP3V0_NAND VLDO6 L2 PP_ACC_VAR VLDO0 VLDO1 VLDO2 VLDO3 VLDO4 VLDO5 19 16 LDO1 LDO2 LDO3 LDO4 LDO5 46 48 LDO6 6 38 41 50 13 VBYPASS K2 PP3V0_S2 PP0V9_NAND PP1V8_ALWAYS VLDO7 M2 VLDO8 P2 VLDO9 N6 VLDO10 VLDO11 VLDO12 VLDO13 VLDO14 LDO 43 42 41 34 31 27 23 21 19 18 50 46 45 50 38 34 27 21 19 LDO INPUT U2700 P6 P4 L3 NC P3 T2 36 45 47 48 50 16 20 23 PP3V0_DISPLAY PP1V2_SOC 43 PP1V2_CODEC_S2 PP1V0_DISPLAY_DVDD 38 7 9 13 14 43 LDO7 LDO8 LDO9 LDO10 LDO11 LDO12 LDO13 LDO14 VCC_LDOG VPP_OTP 20 B PP1V2_LPADC VBUF_1V2 N5 NC T14 14 VBUF_1V2 TP_DET OMIT_TABLE 1 VPUMP D3 PMU_VPUMP OMIT_TABLE C2901 1 2.2UF C2920 47NF 20% 2 6.3V X5R-CERM 01005 ROOM=PMU 1 C2906 2.2UF 20% 2 6.3V X5R-CERM 0201 20% 2 6.3V X5R-CERM 0201 ROOM=PMU ROOM=PMU OMIT_TABLE 1 C2900 2.2UF OMIT_TABLE 1 1.0UF ROOM=PMU C2903 2.2UF C2907 2.2UF OMIT_TABLE 1 C2913 2.2UF 20% 6.3V 2 X5R-CERM 0201 20% 2 6.3V X5R-CERM 0201 ROOM=PMU ROOM=PMU OMIT_TABLE OMIT_TABLE 1 C2911 2.2UF 20% 2 6.3V X5R 0201-1 OMIT_TABLE 1 C2909 1 1 C2910 2.2UF OMIT_TABLE 1 C2914 2.2UF 20% 2 6.3V X5R-CERM 0201 20% 2 6.3V X5R-CERM 0201 20% 2 6.3V X5R-CERM 0201 20% 2 6.3V X5R-CERM 0201 20% 2 6.3V X5R-CERM 0201 ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU 1 C2915 0.22UF 20% 2 6.3V X5R 01005-1 ROOM=PMU VPUMP: 10nF min. @4.6V SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016 PAGE TITLE SYSTEM POWER: PMU LDOs (3/4) DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 29 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 19 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 6 5 4 3 2 Ansel AMUX R3010 CAMPMU_TO_PMU_AMUX 1 CRITICAL U2700 20 28 C3071 WLCSP 1000PF 10% 2 10V X5R 01005 ROOM=PMU 6 IN 48 IN 6 4 IN 20 6 OUT AP_TO_PMU_WDOG_RESET HYDRA_TO_PMU_HOST_RESET AP_TO_PMU_SOCHOT_L PMU_TO_SYSTEM_COLD_RESET_L P13 P12 N13 R12 RESET_IN1 RESET_IN2 RESET_IN3 RESET* H15 SHDN NC COLD_RESET & SYSTEM_ALIVE SYM 4 OF 5 ROOM=PMU 200K 2 1% 1/20W MF 201 D2422B0 ROOM=PMU IREF R10 PMU_IREF C3010 0.22UF REFS 1 1 D RESETS D 7 VREF R9 PMU_VREF 1 2 20% 6.3V X5R 0201 ROOM=PMU PP1V8_S2 100K R3062 48 6 4 100K 5% 1/32W MF 2 01005 5% 1/32W MF 2 01005 ROOM=PMU R3000 ROOM=PMU SYSTEM_ALIVE PMU_TO_SYSTEM_COLD_RESET_L C 14 16 20 23 23 20 16 14 SYSTEM_ALIVE OUT 100 1 6 20 OUT 12 OUT 50 OUT 2 1% 1/32W MF 01005 50 28 21 12 8 10 OUT ROOM=PMU 12 OUT IN 49 46 10 IN 49 46 10 BI 10 IN 10 4 NTCs OUT PMU_TO_AP_HYDRA_ACTIVE_READY M12 ACTIVE_RDY PMU_TO_AOP_CLK32K PMU_TO_TOUCH_CLK32K_RESET_L G6 SLEEP_32K H6 OUT_32K SYSTEM_ALIVE_R AP_TO_MANY_BSYNC PMU_TO_SEP_DOUBLE_CLICK_DET PMU_TO_AOP_IRQ_L COMPARATOR 1 R3061 K13 SYS_ALIVE M13 FORCE_SYNC L12 DBL_CLICK_DET N14 IRQ* I2C0_AP_SCL I2C0_AP_SDA SPMI_PMGR_TO_PMU_SCLK SPMI_PMU_BI_PMGR_SDATA M8 L8 K7 L7 SCL SDA SCLK SDATA IN 1 C3041 OMIT 1 R3041 100PF 10KOHM-1% 5% 16V 2 NP0-C0G 01005 FOREHEAD_NTC FOREHEAD_NTC_RETURN 01005 2 ROOM=PMU XW3041 28 20 1 48 20 ROOM=PMU R3011 1% 1/32W MF 2 01005 1 OMIT 10KOHM-1% 5% 16V 2 NP0-C0G 01005 01005 2 11 IN 43 IN 50 IN ROOM=PMU 50 20 XW3042 SHORT-20L-0.05MM-SM 1 IN 42 20 200K REAR CAMERA NTC 100PF AMUX_B0 AMUX_B1 AMUX_B2 AMUX_B3 AMUX_B4 AMUX_B5 AMUX_B6 AMUX_B7 AMUX_BY HYDRA_TO_PMU_USB_BRICK_ID IN OUT 1 REAR_CAMERA_NTC RCAM_NTC_RETURN F6 G7 G8 F7 E9 E10 F8 H7 NC H8 NC NC 2 ROOM=PMU R3042 ACORN_TO_PMU_ADC AP_TO_PMU_AMUX_SYNC DISPLAY_TO_PMU_AMUX TOUCH_TO_AMUX_PP1V8 PMU_TO_WLAN_CLK32K RIGEL_TO_ISP_INT AP_TO_PMU_TEST_CLKOUT NC SHORT-20L-0.05MM-SM 50 1 AMUX_A0 AMUX_A1 AMUX_A2 AMUX_A3 AMUX_A4 AMUX_A5 AMUX_A6 AMUX_A7 AMUX_AY CAMPMU_TO_PMU_AMUX IN 46 C3042 ACC_BUCK_TO_PMU_AMUX PMU_AMUX_AY NC D4 D5 D6 D7 F9 F10 E6 E7 E8 34 8 4 IN 6 4 IN 2 ROOM=PMU 50 ROOM=PMU OUT PMU_AMUX_BY AMUX 6 AP_TO_PMU_AMUX_OUT ADC FOREHEAD NTC BUTTONS 1 10 12 14 17 22 38 46 47 48 49 50 20 20 1 C3020 1 100PF 20 19 3.92K 5% 2 16V NP0-C0G 01005 RADIO PA NTC on MLB Bottom R3020 0.1% 1/20W MF 2 0201 ROOM=PMU ROOM=PMU R3001 23 20 19 PP1V8_ALWAYS 1 0.00 0% 1/32W MF 01005 AP NTC 2 1 PP1V8_ALWAYS_XO ROOM=PMU 0.22UF 20% 2 6.3V X5R 0201 1 C3002 ROOM=PMU 1 R3044 100PF 5% 16V 2 NP0-C0G 01005 ROOM=PMU 10KOHM-1% AP_NTC AP_NTC_RETURN 01005 2 L5 VDD_RTC PMU_VDD_REF J3 VDD_REF 1 C3031 1UF 20% 2 6.3V X5R 0201 ROOM=PMU 20% 2 6.3V X5R-CERM OMIT 1 VDD ROOM=PMU VDROOP0 P14 VDROOP1 E16 VDROOP11 L15 PMU_TO_AP_THROTTLE_PCORE_L PMU_TO_AP_THROTTLE_GPU0_L PMU_TO_AP_THROTTLE_ECORE_L VDROOP0_DET R14 VDROOP1_DET E15 VDROOP11_DET K15 AP_CPU_PCORE_SENSE AP_VDD_GPU_SENSE BUCK11_FB PRE_UVLO_DET L13 LDO5_UVLO_DET U2 PMU_PRE_UVLO_DET PMU_LDO5_UVLO_DET IBAT VBAT BRICK_ID1 BRICK_ID2 ADC_IN BUTTON1 BUTTON2 BUTTON3 BUTTON4 T11 NC T10 NC N11 N10 NC R11 G14 H14 F13 G13 BUTTONO1 K6 BUTTONO2 J7 BUTTONO3 J6 HYDRA_TO_PMU_USB_BRICK_ID OUT 4 6 11 OUT 6 OUT 6 OUT 6 IN 4 13 IN 4 13 IN 13 18 IN 19 IN 19 IN 20 48 C PP1V8_ALWAYS 19 1 ACORN_TO_PMU_ADC BUTTON_VOL_DOWN_L BUTTON_POWER_KEY_L BUTTON_VOL_UP_L BUTTON_RINGER_A PMU_TO_AP_BUTTON_VOL_DOWN_L PMU_TO_AP_BUTTON_POWER_KEY_L PMU_TO_AP_BUTTON_VOL_UP_L IN 20 42 IN 25 IN 25 IN 25 OUT 11 OUT 11 OUT 11 20 23 R3074 NOSTUFF 31.6K 1% 1/32W MF 2 01005 ROOM=PMU IN 33 F11 F12 G9 G10 G11 G12 NC H9 H10 H11 H12 J8 J9 NC J10 NC J11 J12 K8 NC K9 K10 K11 K12 L9 L10 L11 M9 M10 NC FAULT_OUT* H13 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 PMU_TO_NFC_EN_R PMU_TO_AP_THROTTLE_GPU1_L TIGRIS_TO_PMU_INT_L WLAN_TO_PMU_HOST_WAKE NFC_TO_PMU_HOST_WAKE PMU_TO_GNSS_EN_R PMU_TO_WLAN_CLK32K PMU_TO_BT_REG_ON BT_TO_PMU_HOST_WAKE CODEC_TO_PMU_WAKE 1 OUT 6 IN 23 IN 50 IN 50 OUT 50 OUT 50 ROOM=PMU R3072 50 IN 50 IN 38 100 PMU_TO_GNSS_EN 2 5% 1/32W MF 01005 20 50 OUT PMU_TO_NFC_EN 2 5% 1/32W MF 01005 1 OUT 100 B ROOM=PMU R3071 PMU_TO_WLAN_REG_ON PMU_TO_BB_USB_VBUS_DETECT PMU_TO_AP_FORCE_DFU_R PMU_TO_CCG2_RESET_L PMU_TO_BBPMU_RESET_R_L PMU_TO_NAND_LOW_BATT_BOOT_L BB_TO_PMU_PCIE_HOST_WAKE_L PMU_TO_IKTARA_EN_EXT_1P8V PMU_TO_BOOST_EN PMU_TO_DISPLAY_PANICB PMU_TO_IKTARA_RESET_L 1 OUT 50 OUT 50 20.0K 2 PMU_HYDRA_TO_AP_FORCE_DFU BI 11 48 50 5% 1/32W MF 01005 ROOM=PMU OUT 47 R3070 1 OUT 16 IN 50 OUT 50 OUT 21 OUT 43 OUT 50 1.00K 2 PMU_TO_BBPMU_RESET_L OUT 50 5% 1/32W MF 01005 ROOM=PMU Y3000 01005 XW3044 SHORT-20L-0.05MM-SM R1 XTAL1 P1 XTAL2 PMU_VDD_RTC 3 0.1UF 1 C3044 C3030 PMU_VSS_RTC TCXO_PMU_32K NTC B 50 GPIO 20 TDEV1 TDEV2 TDEV3 TDEV4 TDEV5 TCAL XTAL 20 T12 T13 U13 V13 W13 V14 PMU_TO_AP_PRE_UVLO_L R3073 ROOM=PMU FOREHEAD_NTC REAR_CAMERA_NTC RADIO_PA_NTC AP_NTC CHARGER_NTC PMU_TCAL PRE_UVLO M14 32.768KHZ-10PPM 2 CSP ROOM=PMU NC ROOM=PMU 1 NC CLKOUT 2 CRITICAL ROOM=PMU 4 GND A 20 19 PMU_VSS_RTC CHARGER NTC SYNC_MASTER=test_mlb 1 C3045 R3045 100PF 5% 16V NP0-C0G 2 01005 ROOM=PMU OMIT I609 1 10KOHM-1% CHARGER_NTC CHARGER_NTC_RETURN 01005 2 ROOM=PMU SYSTEM POWER: PMU (4/4) SHORT-20L-0.05MM-SM 1 XW3000 XW3045 SHORT-20L-0.05MM-SM 1 SYNC_DATE=11/01/2016 PAGE TITLE 2 DRAWING NUMBER OMIT Apple Inc. 2 051-02221 REVISION 9.0.0 ROOM=PMU ROOM=PMU NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 30 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT NOTE:100PF CAPS ARE THE SAMPLING CAPS FOR PMU ADC III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 20 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 D D Boost Enable Pull 21 20 PMU_TO_BOOST_EN 1 R3100 511K 1% 1/32W MF 2 01005 ROOM=BOOST BOOST C 45 43 42 41 34 31 27 23 19 18 50 46 PP_VDD_MAIN 1 C 353S01124 C3190 1 ROOM=BOOST 18UF 20% 2 6.3V CER-X5R 0402-0.1MM When VDD_MAIN < 3.4, boosts to 3.4 Otherwise tracks VDD_MAIN L3100 0.47UH-20%-4A-0.048OHM ROOM=BOOST A3 A4 PIWA20120H-SM VIN VIN SN61280E SYS_BOOST_LX C3 C4 SW SW PMU_TO_BOOST_EN A1 EN I2C0_SMC_SCL B2 SCL I2C0_SMC_SDA_BOOST C2 SDA B1 VSEL C1 BYP* A2 GPIO 2 U3100 VOUT VOUT CSP ROOM=BOOST R3110 50 47 23 22 10 BI I2C0_SMC_SDA 1 39.2 50 47 23 22 10 IN IN 2 1% 1/32W MF 01005 ROOM=BOOST 50 28 20 12 8 IN AP_TO_MANY_BSYNC CRITICAL D2 D3 D4 PGND PP_VDD_BOOST 1 C3110 18UF 1 C3111 18UF 1 C3112 18UF 1 C3113 18UF 1 C3114 18UF 20% 2 6.3V CER-X5R 0402-0.1MM 20% 2 6.3V CER-X5R 0402-0.1MM 20% 2 6.3V CER-X5R 0402-0.1MM 20% 2 6.3V CER-X5R 0402-0.1MM 20% 2 6.3V CER-X5R 0402-0.1MM ROOM=BOOST ROOM=BOOST ROOM=BOOST ROOM=BOOST ROOM=BOOST 1 19 27 34 38 50 C3115 220PF 5% 2 10V C0G-CERM 01005 ROOM=BOOST AGND D1 21 20 B3 B4 B B A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016 PAGE TITLE SYSTEM POWER: Boost DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 31 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 21 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 D D BATTERY CONNECTOR Gas gauge I2C level translator <-- This one on MLB Rcpt: 516S00232 Plug: 516S00233 SYM_VER_1 Q3200 RV1C002UN SM ROOM=B2B_BATTERY 23 C OUT I2C0_SMC_BI_GG_SDA 2 VBATT_SENSE R3202 S I2C0_SMC_BI_GG_SDA_CONN D XW3200 SHORT-20L-0.05MM-SM 2 1 3 CRITICAL 1 CKPLUS_WAIVE=I2C_PULLUP 1 ROOM=B2B_BATTERY J3200 B2B-BATT-RCPT F-ST-SM I2C0_SMC_SDA 2 10 21 23 47 50 BI 5% 1/32W MF 01005 C3202 56PF G NO_XNET_CONNECTION=1 1 PLACE_NEAR=J3200:2mm 33 C 5% ROOM=B2B_BATTERY 2 25V NP0-C0G-CERM 01005 9 ROOM=B2B_BATTERY 1 C3292 56PF 5% 2 25V NP0-C0G-CERM 01005 ROOM=B2B_BATTERY 1 C3293 330PF 10% 2 16V CER-X7R 01005 1 3 2 4 7 8 C3294 220PF 10% 2 10V X7R-CERM 01005 ROOM=B2B_BATTERY 1 PP1V8_S2 10 10 ROOM=B2B_BATTERY 12 14 17 20 38 46 47 48 49 50 1 PP_BATT_VCC 6 G 50 23 5 ROOM=B2B_BATTERY R3201 2 1 C3201 56PF RV1C002UN SM 5% 2 25V NP0-C0G-CERM 01005 SYM_VER_1 Q3201 33 I2C0_SMC_SCL 1 2 S CKPLUS_WAIVE=I2C_PULLUP D I2C0_SMC_TO_GG_SCL 3 I2C0_SMC_TO_GG_SCL_CONN IN 10 21 23 47 50 5% 1/32W MF 01005 ROOM=B2B_BATTERY ROOM=B2B_BATTERY ROOM=B2B_BATTERY CRITICAL B B A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016 PAGE TITLE SYSTEM POWER: B2B Battery DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 32 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 22 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 TIGRIS2 CHARGER D D PP_VDD_MAIN 18 19 21 27 31 34 41 42 43 45 46 50 1 TIGRIS_PMID1 DZ3300 18UF 1 K R3316 1 BZT52C20LP DFN10062 1 4.7UF 1% 1/32W MF 01005 2 ROOM=CHARGER 20% 25V 2 X5R 0402 ROOM=CHARGER C3317 C3310 1 4.7UF 1 20% 25V 2 X5R 0402 5% 2 25V COG 01005 20% 25V 2 CER-X5R 0402 ROOM=CHARGER C3312 220PF 4.7UF 20% 2 25V CER-X5R 0402 4.7UF C3311 1 ROOM=CHARGER 1 C3313 220PF 5% 2 25V COG 01005 ROOM=CHARGER 1 C3314 1 220PF 220PF 5% 2 25V COG 01005 ROOM=CHARGER C3315 5% 2 25V COG 1 C3391 18UF 20% 2 6.3V CER-X5R 0402-0.1MM 20% 2 6.3V CER-X5R 0402-0.1MM ROOM=CHARGER ROOM=CHARGER 01005 ROOM=CHARGER ROOM=CHARGER ROOM=CHARGER C TIGRIS_PMID2 220PF 4.7UF 5% 2 25V COG 01005 20% 2 25V CER-X5R 0402 ROOM=CHARGER C3324 1 220PF 220PF 5% 2 25V COG 01005 5% 2 25V COG 01005 ROOM=CHARGER C3325 ROOM=CHARGER ROOM=CHARGER 1 C3302 220PF 5% 2 25V COG 01005 1 C3303 1 C3305 220PF 5% 2 25V COG 01005 ROOM=CHARGER 1 C3306 220PF 1UF 10% 2 25V X5R 402 ROOM=CHARGER 220PF 5% 2 25V COG 01005 ROOM=CHARGER ROOM=CHARGER 1 C3307 220PF 5% 2 25V COG 01005 5% 2 25V COG 01005 ROOM=CHARGER ROOM=CHARGER 1 C3308 220PF 5% 2 25V COG 01005 ROOM=CHARGER PP1V8_ALWAYS 1 50 47 22 21 10 R3330 50 47 22 21 10 100K 5% 1/32W MF 2 01005 20 16 14 48 4 ROOM=CHARGER BI IN IN IN I2C0_SMC_SDA I2C0_SMC_SCL 1 100 SYSTEM_ALIVE HYDRA_TO_TIGRIS_VBUS1_VALID_L 2 R3332 OUT PMID1 PMID1 PMID1 PMID1 PMID1 F6 G6 H6 PMID2 PMID2 PMID2 A5 B5 C5 D5 E5 VBUS1 VBUS1 VBUS1 VBUS1 VBUS1 F5 G5 H5 VBUS2 VBUS2 VBUS2 F4 4UF 20% 10% 2 10V X7R-CERM 01005 2 6.3V CERM-X5R 0201 ROOM=CHARGER CRITICAL S ROOM=CHARGER Q3350 CSD68841W H3 BOOT H4 BUCK_SW BUCK_SW BUCK_SW BUCK_SW BUCK_SW BUCK_SW BUCK_SW BUCK_SW A7 B7 C7 D7 E7 F7 G7 H7 BATT BATT BATT BATT BATT A1 B1 C1 D1 E1 BATT_SNS F1 VBATT_SENSE ACT_DIODE A3 TIGRIS_ACTIVE_DIODE U3300 WCSP ROOM=CHARGER CRITICAL SDA SCL SYS_ALIVE TIGRIS_VBUS_DETECT C4 VBUS1_DET D4 TEST E4 NTC BATTERY_NTC HDQ_HOST HDQ_GAUGE B4 VBUS1_VALID* B3 VBUS2_VALID* E3 INT* 23 30.1K 2 1 BGA C3340 LDO SN2500A1YEWR TIGRIS_TO_PMU_INT_R_L ROOM=CHARGER 6 C3361 ROOM=CHARGER 0.047UF TIGRIS_BOOT 1 D 2 10% 25V X5R 0201 ROOM=CHARGER NO_XNET_CONNECTION CRITICAL CRITICAL L3340 L3341 0.47UH-6.8A-0.046OHM 0.47UH-6.8A-0.046OHM 1 2 TIGRIS_LX_MID 1 2 TIGRIS_LX 3225 3225 ROOM=CHARGER ROOM=CHARGER C3341 220PF 1 5% 10V C0G-CERM 2 01005 ROOM=CHARGER C3342 1 220PF 5% 10V C0G-CERM 2 01005 ROOM=CHARGER C3343 1 330PF 10% 16V CER-X7R 2 01005 ROOM=CHARGER PP_BATT_VCC IN 22 1 10% 2 16V CER-X7R 01005 R33501 A4 NC0 NC1 NC2 NC3 D3 G1 H1 H2 ROOM=CHARGER 1 C3351 4UF 20% 2 6.3V CERM-X5R 0201 ROOM=CHARGER 1 C3352 4UF 20% 2 6.3V CERM-X5R 0201 22 50 1 C3353 B 220PF 5% 2 10V C0G-CERM 01005 ROOM=CHARGER ROOM=CHARGER 100K 5% 1/32W MF 01005 2 R3360 GND PP_VBUS1_E75_RVP_R 2 10 1 PP_VBUS1_E75_RVP ROOM=CHARGER 45 47 48 5% 1/32W MF 01005 ROOM=CHARGER AGND A8 C8 D8 E8 F8 G8 H8 1% 1/32W MF 01005 G3 G4 AUX1 C3350 330PF NOSTUFF 1% 1/32W MF 01005 USB_VBUS_DETECT A6 B6 C6 D6 E6 F3 G2 R3331 TIGRIS_TO_PMU_INT_L 1 220PF G C3304 PP_VBUS2_IKTARA 1 OUT C3360 C1 C2 C3 C3301 ROOM=CHARGER 20 1 A1 10% 2 25V X5R 402 20 19 5% 2 25V COG 01005 1 PP_VBUS1_E75 1UF B C3323 220PF ROOM=CHARGER 1 50 1 B8 49 C3322 A2 A3 B1 B2 B3 1 VDD_MAIN5 F2 C3320 A2 B2 C2 D2 E2 1 TIGRIS_LDO VDD_MAIN VDD_MAIN VDD_MAIN VDD_MAIN VDD_MAIN C C3316 50K A C3390 ROOM=CHARGER BATTERY NTC A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016 PAGE TITLE SYSTEM POWER: Charger 1 C3370 OMIT I251 1 R3370 100PF 10KOHM-1% 5% 16V NP0-C0G 2 01005 BATTERY_NTC BATTERY_NTC_RETURN 01005 2 ROOM=CHARGER 23 DRAWING NUMBER XW3370 SHORT-20L-0.05MM-SM 1 2 Apple Inc. 051-02221 REVISION 9.0.0 ROOM=CHARGER ROOM=CHARGER NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 33 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 23 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 D D C C Iktara Components on MLB Bottom B B A A PAGE TITLE SYSTEM POWER: Iktara DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 34 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 24 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D 8 7 6 5 4 3 2 1 Cyclone + Button Connnector Rcpt: 516S00289 Plug: 516S00290 J3500 Cyclone Filtering AA36D-S04VA1 D 25 50 <-- This one on MLB IKTARA_COIL2 IKTARA_COIL2 25 25 F-ST-SM BUTTON_VOL_DOWN_CONN_L 9 IKTARA_COIL2 5 BUTTON_VOL_UP_CONN_L BUTTON_RINGER_A_CONN 1 3 IKTARA_COIL1 7 D 10 PWR 6 MAKE_BASE=TRUE 1 C3500 C3501 1 220PF 220PF 2% 2 50V C0G 0201 25 2% 2 50V C0G 0201 ROOM=B2B_BUTTON 25 ROOM=B2B_BUTTON 25 25 PP1V8_IMU_COMPASS_BTN_CONN PWR 11 2 4 COMPASS_TO_AOP_INT_BTN_CONN I2C1_AOP_TO_COMPASS_SCL_BTN_CONN 8 I2C1_AOP_BI_COMPASS_SDA_BTN_CONN 25 25 25 12 ROOM=B2B_BUTTON IKTARA_COIL1 50 IKTARA_COIL1 25 MAKE_BASE=TRUE 1 C3510 C3511 1 220PF 220PF 2% 2 50V C0G 0201 2% 2 50V C0G 0201 ROOM=B2B_BUTTON C ROOM=B2B_BUTTON C BUTTONS R3520 20 BUTTON_RINGER_A OUT 100 1 C3520 5% 1/32W MF 01005 1 27PF 5% 6.3V 2 NP0-C0G 0201 BUTTON_RINGER_A_CONN 25 BUTTON_VOL_DOWN_CONN_L 25 2 1 DZ3520 0201 ROOM=B2B_BUTTON 5.5V-6.2PF ROOM=B2B_BUTTON 2 ROOM=B2B_BUTTON R3530 20 BUTTON_VOL_DOWN_L OUT 100 1 C3530 2 5% 1/32W MF 01005 1 220PF 5% 10V 2 C0G-CERM 01005 1 DZ3530 12V-33PF 01005-1 ROOM=B2B_BUTTON 2 ROOM=B2B_BUTTON ROOM=B2B_BUTTON R3540 B 20 BUTTON_VOL_UP_L OUT 100 1 C3540 5% 1/32W MF 01005 1 220PF ROOM=B2B_BUTTON 5% 10V 2 C0G-CERM 01005 ROOM=B2B_BUTTON BUTTON_VOL_UP_CONN_L 2 1 25 B DZ3540 12V-33PF 01005-1 2 ROOM=B2B_BUTTON Compass (Button Flex Location) FL3550 150OHM-25%-200MA-0.7DCR 49 26 17 PP1V8_IMU_S2 2 1 01005 ROOM=B2B_DOCK 1 PP1V8_IMU_COMPASS_BTN_CONN 25 I2C1_AOP_TO_COMPASS_SCL_BTN_CONN 25 C3550 220PF 5% 2 10V C0G-CERM 01005 ROOM=B2B_DOCK R3551 50 49 41 12 4 IN I2C1_AOP_SCL 2 0.00 1 CKPLUS_WAIVE=I2C_PULLUP 0% 1/32W MF 01005 1 C3551 56PF 5% 2 25V NP0-C0G-CERM 01005 ROOM=B2B_DOCK ROOM=B2B_DOCK R3552 50 49 41 12 4 BI I2C1_AOP_SDA 2 0.00 25 CKPLUS_WAIVE=I2C_PULLUP 0% 1/32W MF 01005 A I2C1_AOP_BI_COMPASS_SDA_BTN_CONN 1 1 C3552 56PF SYNC_MASTER=test_mlb 5% 2 25V NP0-C0G-CERM 01005 ROOM=B2B_DOCK FL3553 SYNC_DATE=10/13/2016 PAGE TITLE SYSTEM POWER: B2B Cyclone + Button ROOM=B2B_DOCK DRAWING NUMBER 150OHM-25%-200MA-0.7DCR 49 12 4 OUT COMPASS_TO_AOP_INT 2 COMPASS_TO_AOP_INT_BTN_CONN 1 01005 ROOM=B2B_DOCK 1 Apple Inc. 25 051-02221 REVISION 9.0.0 C3553 220PF 5% 2 10V C0G-CERM 01005 ROOM=B2B_DOCK NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 35 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 25 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 D D Graphite - Accel & Gyro Magnesium - Compass (On Dock or Button Flex) APN: 338S00304 PP1V8_IMU_S2 49 26 25 17 PP1V8_IMU_S2 1 C3600 1 0.1UF R3601 17 25 26 49 OMIT_TABLE 100K 5% 1/32W MF 01005 2 C3602 2.2UF 20% 2 6.3V X5R-CERM 01005 ROOM=CARBON 20% 2 6.3V X5R-CERM 0201 ROOM=CARBON ROOM=CARBON 1 16 1 0.1UF 20% 2 6.3V X5R-CERM 01005 1 C3601 VDD VDDIO ROOM=CARBON CRITICAL U3600 BMI262BB LGA 12 12 4 OUT 12 4 OUT ROOM=CARBON 5 CSB 15 SM ACCEL_GYRO_TO_AOP_DATARDY ACCEL_GYRO_TO_AOP_INT 6 INT 7 MOTION_INT SCLK 2 SPI_AOP_TO_IMU_SCLK MOSI 3 MISO 4 SPI_AOP_TO_IMU_MOSI SPI_IMU_TO_AOP_MISO IN 4 12 26 IN 4 12 26 OUT 4 12 26 C 13 14 8 9 10 11 12 GND GND GND GND GND GND GND C IN SPI_AOP_TO_ACCEL_GYRO_CS_L CARBON_REGOUT 1 R3600 0.00 0% 1/32W MF 2 01005 ROOM=CARBON B B Phosphorus BOSCH (APN:338S00188) ST (APN:338S00230) 49 26 25 17 PP1V8_IMU_S2 PP1V8_IMU_S2 17 25 26 49 OMIT_TABLE 1 0.1UF R36201 20% 2 6.3V X5R-CERM 01005 100K 5% 1/32W MF 01005 2 A C3620 ROOM=PHOSPHORUS 1 C3622 2.2UF 20% 2 6.3V X5R-CERM 0201 ROOM=PHOSPHORUS 8 6 ROOM=CARBON VDD VDDIO SYNC_MASTER=test_mlb U3620 12 IN IN IN ROOM=PHOSPHORUS BMP284AA 3 SDI 4 SCK 2 CS* LGA SDO 5 SPI_IMU_TO_AOP_MISO CRITICAL IRQ 7 PHOSPHORUS_TO_AOP_INT SENSORS OUT 4 12 26 OUT 4 12 DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 GND 1 26 12 4 26 12 4 SPI_AOP_TO_IMU_MOSI SPI_AOP_TO_IMU_SCLK SPI_AOP_TO_PHOSPHORUS_CS_L SYNC_DATE=10/13/2016 PAGE TITLE NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 36 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 26 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 Camera PMU 45 43 42 41 34 31 23 21 19 18 50 46 PP_VDD_MAIN D 1 C3790 See 2831115 for C3791 removal D CRITICAL 18UF 20% 2 6.3V CER-X5R 0402-0.1MM U3700 CRITICAL D2462 ROOM=CAM_PMU L3700 WLCSP 1UH-20%-2.5A-0.078OHM SYM 1 OF 4 ROOM=CAM_PMU J7 VDD_BUCK9 J8 VDD_BUCK9 VCC MAIN BUCK9_LX0 BUCK9_LX0 BUCK9_FB CAMPMU_BUCK_LX0 H7 H8 H5 1 PP2V85_VAR_CAM_VCM_PVDD 2 PIWA20120H-SM 1 ROOM=CAM_PMU C3700 18UF XW3700 SHORT-20L-0.05MM-SM BUCKS CAMPMU_BUCK_FB 1 2 1 C3701 18UF 20% 2 6.3V CER-X5R 0402-0.1MM 20% 2 6.3V CER-X5R 0402-0.1MM ROOM=CAM_PMU ROOM=CAM_PMU 1 29 C3702 330PF 10% 2 16V CER-X7R 01005 ROOM=CAM_PMU ROOM=CAM_PMU OMIT C5 VDD_MAIN E2 VDD_MAIN G4 VDD_MAIN U3700 D2462 WLCSP 19 17 C3796 4UF 20% 2 6.3V CERM-X5R 0201 20% 2 6.3V CERM-X5R 0201 ROOM=CAM_PMU ROOM=CAM_PMU 1 2.2UF 20% 2 6.3V X5R-CERM 0201 ROOM=CAM_PMU PP1V25_S2 1 C3797 4UF 20% 2 4V X5R 0201 ROOM=CAM_PMU 1 C3704 B6 VDD_LDO10 B5 VDD_LDO15 C3798 1 PP1V1_CAM_TELE_JULIET_DVDD C3709 20% 2 6.3V X5R-CERM 0201 ROOM=CAM_PMU DMN1017UCP3 X3-DSN1010-3 VLDO10 A6 VLDO15 A5 OMIT_TABLE 1 20% 2 4V X5R 0201 C3710 10UF LDO INPUT ROOM=CAM_PMU 20% 2 10V X5R-CERM 0402-0.1MM ROOM=CAM_PMU LDO OUTPUT A2 VDD_LDO4_17 B4 VDD_LDO18 C3715 C3717 20% 2 6.3V X5R-CERM 0201 ROOM=CAM_PMU 2.2UF 20% 2 6.3V X5R-CERM 0201 ROOM=CAM_PMU 1 CRITICAL CAMPMU_TELE_DVDD_DISABLE_L IN 28 35 C3718 2.2UF 20% 2 6.3V X5R-CERM 0201 ROOM=CAM_PMU PP1V8_HAWKING 33 PP2V85_CAM_WIDE_AVDD 29 VLDO19 A3 VLDO20 B8 1 C3719 2.2UF 20% 2 6.3V X5R-CERM 0201 ROOM=CAM_PMU A8 VDD_LDO20_21 H1 VDD_LDO22 30 ROOM=CAM_PMU 2.2UF PP2V85_CAM_TELE_AVDD 30 PP1V1_CAM_WIDE_DVDD 29 1 B 1 VLDO17 B1 VLDO18 A4 B3 VDD_LDO19 A7 VDD_LDO20_21 PP1V1_CAM_TELE_DVDD PP1V1_FCAM_DVDD 32 4UF 35 Q3700 2.2UF 3 4UF 1 G C3795 C PP2V85_FCAM_AVDD 32 PP_CAM_WIDE_ADC 29 VLDO4 B2 VLDO9 J2 1 1 SYM 2 OF 4 A1 VDD_LDO4_17 H2 VDD_LDO9 S PP_VDD_BOOST D 50 38 34 21 19 2 C 1 C3720 2.2UF 20% 2 6.3V X5R-CERM 0201 ROOM=CAM_PMU PP3V3_SVDD 28 PP_CAM_TELE_ADC 30 VLDO21 B7 VLDO22 G1 1 C3721 2.2UF 20% 2 6.3V X5R-CERM 0201 ROOM=CAM_PMU B 1 29 30 35 C3722 2.2UF 20% 2 6.3V X5R-CERM 0201 ROOM=CAM_PMU For GPIO pullups only 30 29 28 17 16 14 10 8 7 6 5 43 35 34 32 H3 VBUCK3 PP1V8_IO BUCK3_SW1 J3 SW INPUT NC NC SW OUTPUT J4 VPUMP ON_BUF F2 CAMPMU_ON_BUF C3750 1 0.22UF 20% 6.3V 2 X5R 01005 ROOM=CAM_PMU A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016 PAGE TITLE CAMERA: PMU (1/2) DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 37 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 27 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 Pull Downs AP_TO_CAMPMU_RESET_L 1 11 28 R3801 100K 5% 1/32W MF 2 01005 ROOM=CAM_PMU D D PP3V3_SVDD 1 27 29 30 35 R3820 100K 5% 1/32W MF 01005 2 ROOM=CAM_PMU U3700 D2462 WLCSP R3802 35 34 31 8 11 BI OUT I2C3_ISP_SDA 1 33.2 1% 1/32W MF 01005 CAMPMU_TO_AP_IRQ_L 35 34 31 8 IN 2 I2C3_ISP_SCL I2C3_ISP_SDA_U3700 SYM 3 OF 4 E8 F8 SCL SDA D8 IRQ* D6 CRASH* I2C R3803 1 49.9 CAMPMU_TO_AP_IRQ_R_L 2 1% 1/32W MF 01005 NC 28 11 C IN AP_TO_CAMPMU_RESET_L F5 RESET RESET_IN CAMPMU_VREF C1 CAMPMU_IREF D1 IREF CAMPMU_VRTC E1 VREF GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO9 GPIO10 GPIO11 GPIO12 GPIO15 F6 E6 D7 E4 D4 D3 F7 F3 G3 G2 E3 CAMPMU_TO_STROBE_DRIVER_HWEN NC NC NC NC CAMPMU_TO_RIGEL_ENABLE PP1V8_IO AP_TO_MANY_BSYNC YOGI_TO_RIGEL_STATUS_R CAMPMU_TELE_DVDD_DISABLE_L MAMA_BEAR_BI_RIGEL_STATUS_R OUT 31 OUT 4 34 MAKE_BASE=TRUE IN PP1V8_IO 5 6 7 8 10 14 16 17 27 29 30 32 34 35 43 8 12 20 21 50 R3811 1 OUT 10K YOGI_TO_RIGEL_STATUS 2 IN 34 36 5% 1/32W MF 01005 27 C ROOM=CAM_PMU 1 1 C3800 R3800 200K 0.22UF 1% 1/32W MF 2 01005 20% 2 6.3V X5R 01005 ROOM=CAM_PMU ROOM=CAM_PMU 1 REFERENCE VRTC GPIO R3810 C3810 1 0.1UF 20% 2 6.3V X5R 01005 J5 NC G5 NC C6 NC ROOM=CAM_PMU TDEV1 TDEV2 10K 2 MAMA_BEAR_BI_RIGEL_STATUS IN 34 35 5% 1/32W MF 01005 ROOM=CAM_PMU TEMPERATURE TCAL AMUX_AY C8 CAMPMU_TO_PMU_AMUX OUT 20 ATM E7 U3700 B B D2462 WLCSP C2 C3 C4 C7 D2 D5 E5 F1 VSS VSS VSS VSS VSS VSS VSS VSS SYM 4 OF 4 VSS VSS VSS VSS VSS VSS VSS VSS G6 G7 G8 H4 H6 J1 J6 F4 A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016 PAGE TITLE CAMERA: PMU (2/2) DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 38 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 28 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 Power Filtering Wide Camera Connector Rcpt: 516S00313 <-- This one on MLB FL3901 33-OHM-25%-1500MA 2 PP2V85_VAR_CAM_VCM_PVDD 1 Plug: 516S00314 27 PP_CAM_VCM_PVDD_CONN 1 ROOM=B2B_WIDE_RCAM J3900 29 31 27 D 29 29 29 29 90_LPDP_WIDE_TO_AP_D0_CONN_N 90_LPDP_WIDE_TO_AP_D0_CONN_P GND_VOID 90_LPDP_WIDE_TO_AP_D1_CONN_N 90_LPDP_WIDE_TO_AP_D1_CONN_P 29 90_LPDP_WIDE_TO_AP_D2_CONN_N 90_LPDP_WIDE_TO_AP_D2_CONN_P 29 AP_TO_WIDE_CLK_CONN 29 GND_VOID GND_VOID GND_VOID GND_VOID GND_VOID 20% 2 6.3V X5R-CERM 0201 F-ST-SM PP1V1_CAM_WIDE_DVDD_CONN 28 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 29 32 C3909 2.2UF AA26DK-S026VA1 PP1V1_CAM_WIDE_DVDD_CONN 29 30 OMIT_TABLE 0201 FL3995 29 30 28 27 17 16 14 10 8 7 6 5 43 35 34 32 LPDP_WIDE_BI_AP_AUX_CONN I2C0_ISP_BI_WIDE_RCAM_OIS_SDA_CONN I2C0_ISP_TO_WIDE_RCAM_OIS_SCL_CONN WIDE_AND_TELE_TO_LED_DRIVER_STROBE_EN_CONN AP_TO_WIDE_SHUTDOWN_CONN_L WIDE_TO_TELE_SYNC_J3900_CONN PP1V8_CAM_WIDE_VDDIO_CONN PP_CAM_VCM_PVDD_CONN PP3V3_SVDD PP2V85_CAM_WIDE_AVDD PP_CAM_WIDE_ADC ROOM=B2B_WIDE_RCAM 10-OHM-750MA PP1V8_IO 1 PP1V8_CAM_WIDE_VDDIO_CONN 2 01005-1 1 ROOM=B2B_WIDE_RCAM C3995 1 0.1UF 29 29 C3996 220PF 20% 2 6.3V X5R-CERM 01005 29 5% 2 10V C0G-CERM 01005 ROOM=B2B_WIDE_RCAM 29 30 35 30 29 28 27 29 30 29 29 27 29 30 29 27 27 28 29 30 35 30 29 D 29 ROOM=B2B_WIDE_RCAM PP3V3_SVDD PP2V85_CAM_WIDE_AVDD PP_CAM_WIDE_ADC PP_CAM_VCM_PVDD_CONN 27 29 1 C3990 1 220PF 27 29 1 220PF ROOM=B2B_WIDE_RCAM C3992 1 220PF 5% 2 10V C0G-CERM 01005 5% 2 10V C0G-CERM 01005 30 C3991 220PF 5% 2 10V C0G-CERM 01005 ROOM=B2B_WIDE_RCAM C3994 5% 2 10V C0G-CERM 01005 ROOM=B2B_WIDE_RCAM ROOM=B2B_WIDE_RCAM ROOM=B2B_WIDE_RCAM FL3903 33-OHM-25%-1500MA 27 PP1V1_CAM_WIDE_DVDD 1 PP1V1_CAM_WIDE_DVDD_CONN 2 OMIT_TABLE 0201 1 ROOM=B2B_TELE_CAM C3925 1 2.2UF C3993 220PF 5% 2 10V C0G-CERM 01005 20% 2 6.3V X5R-CERM 0201 ROOM=B2B_TELE_RCAM C I2C0_ISP_SCL 1 0.00 I2C0_ISP_TO_WIDE_RCAM_OIS_SCL_CONN 2 1 5% 2 16V NP0-C0G-CERM 01005 ROOM=B2B_WIDE_RCAM 0.1UF C3900 9 BI 90_LPDP_WIDE_TO_AP_D0_P 1 0.00 ROOM=B2B_WIDE_RCAM 90_LPDP_WIDE_TO_AP_D0_CONN_N 29 90_LPDP_WIDE_TO_AP_D1_CONN_P 29 90_LPDP_WIDE_TO_AP_D1_CONN_N 29 0.1UF I2C0_ISP_BI_WIDE_RCAM_OIS_SDA_CONN 2 0% 1/32W MF 01005 29 C3931 R3901 1 90_LPDP_WIDE_TO_AP_D0_CONN_P GND_VOID=TRUE 20% 6.3V X5R-CERM 01005 5% 2 25V NP0-C0G-CERM 01005 ROOM=B2B_WIDE_RCAM I2C0_ISP_SDA 2 ROOM=B2B_WIDE_RCAM 56PF ROOM=B2B_WIDE_RCAM BI 15PF C3930 29 CKPLUS_WAIVE=I2C_PULLUP 0% 1/32W MF 01005 8 C3928 LPDP Filters R3900 IN ROOM=B2B_WIDE_RCAM 1 C ISP I2C 8 29 NOSTUFF 9 BI 29 90_LPDP_WIDE_TO_AP_D0_N 1 CKPLUS_WAIVE=I2C_PULLUP 1 2 GND_VOID=TRUE ROOM=B2B_WIDE_RCAM 20% 6.3V X5R-CERM 01005 C3901 56PF 5% 2 25V NP0-C0G-CERM 01005 C3940 0.1UF ROOM=B2B_WIDE_RCAM 9 IN 90_LPDP_WIDE_TO_AP_D1_P 1 2 GND_VOID=TRUE ROOM=B2B_WIDE_RCAM 20% 6.3V X5R-CERM 01005 C3941 0.1UF 9 IN 90_LPDP_WIDE_TO_AP_D1_N 1 2 GND_VOID=TRUE ROOM=B2B_WIDE_RCAM B 20% 6.3V X5R-CERM 01005 B C3950 0.1UF 9 IN 90_LPDP_WIDE_TO_AP_D2_P 1 IO Filters IN AP_TO_WIDE_CLK 1 49.9 AP_TO_WIDE_CLK_CONN 2 NOSTUFF 1 90_LPDP_WIDE_TO_AP_D2_CONN_N 29 LPDP_WIDE_BI_AP_AUX_CONN 29 0.1UF 9 29 IN 90_LPDP_WIDE_TO_AP_D2_N 1 2 GND_VOID=TRUE C3906 ROOM=B2B_WIDE_RCAM 56PF ROOM=B2B_WIDE_RCAM 5% 2 25V NP0-C0G-CERM 01005 20% 6.3V X5R-CERM 01005 C3960 ROOM=B2B_WIDE_RCAM LPDP_WIDE_BI_AP_AUX 9 BI 0.1UF 1 2 1 20% 6.3V X5R-CERM 01005 R3907 AP_TO_WIDE_SHUTDOWN_L 1 0.00 AP_TO_WIDE_SHUTDOWN_CONN_L 2 0% 1/32W MF 01005 1 C3961 56PF ROOM=B2B_WIDE_RCAM IN 29 C3951 1% 1/32W MF 01005 8 90_LPDP_WIDE_TO_AP_D2_CONN_P GND_VOID=TRUE 20% 6.3V X5R-CERM 01005 R3905 8 2 ROOM=B2B_WIDE_RCAM 5% 2 25V NP0-C0G-CERM 01005 ROOM=B2B_WIDE_RCAM 29 C3907 220PF ROOM=B2B_WIDE_RCAM A 5% 2 10V C0G-CERM 01005 ROOM=B2B_WIDE_RCAM SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016 PAGE TITLE CAMERA: B2B Wide (WY) R3908 31 OUT WIDE_AND_TELE_TO_STROBE_DRIVER_STROBE 1 0.00 WIDE_AND_TELE_TO_LED_DRIVER_STROBE_EN_CONN 2 0% 1/32W MF 01005 ROOM=B2B_WIDE_RCAM 1 DRAWING NUMBER 29 30 Apple Inc. C3908 051-02221 REVISION 9.0.0 220PF 5% 2 10V C0G-CERM 01005 ROOM=B2B_WIDE_RCAM NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 39 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 29 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 Tele Camera Connector Rcpt: 516S00313 Plug: 516S00314 <-- This one on MLB Power Filtering FL4001 ROOM=B2B_TELE_RCAM J4000 10-OHM-750MA AA26DK-S026VA1 30 31 27 PP1V1_CAM_TELE_DVDD_CONN F-ST-SM 29 28 27 17 16 14 10 8 7 6 5 43 35 34 32 PP1V1_CAM_TELE_DVDD_CONN 28 PP1V8_IO 1 PP1V8_CAM_TELE_VDDIO_CONN 2 01005-1 30 1 ROOM=B2B_TELE_RCAM C4017 D 30 30 30 30 30 30 30 90_LPDP_TELE_TO_AP_D0_CONN_N 90_LPDP_TELE_TO_AP_D0_CONN_P GND_VOID 90_LPDP_TELE_TO_AP_D1_CONN_N 90_LPDP_TELE_TO_AP_D1_CONN_P GND_VOID GND_VOID 90_LPDP_TELE_TO_AP_D2_CONN_N 90_LPDP_TELE_TO_AP_D2_CONN_P AP_TO_TELE_CLK_CONN 35 30 27 PP_CAM_TELE_ADC PP2V85_CAM_TELE_AVDD 30 29 PP_CAM_VCM_PVDD_CONN 30 27 GND_VOID GND_VOID GND_VOID 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 29 32 30 35 30 29 28 27 PP3V3_SVDD 30 35 30 27 30 30 29 PP2V85_CAM_TELE_AVDD PP_CAM_TELE_ADC PP_CAM_VCM_PVDD_CONN 30 1 30 C4090 1 220PF 27 28 29 30 35 1 220PF 5% 2 10V C0G-CERM 01005 30 C4091 C4092 1 220PF 5% 2 10V C0G-CERM 01005 ROOM=B2B_TELE_RCAM PP_CAM_VCM_PVDD_CONN ROOM=B2B_TELE_RCAM 29 30 30 27 AP_TO_TELE_SHUTDOWN_CONN_L WIDE_TO_TELE_SYNC_J4000_CONN PP3V3_SVDD PP1V8_CAM_TELE_VDDIO_CONN 5% 2 10V C0G-CERM 01005 ROOM=B2B_TELE_RCAM 30 D 220PF 20% 2 6.3V X5R-CERM 01005 LPDP_TELE_BI_AP_AUX_CONN WIDE_AND_TELE_TO_LED_DRIVER_STROBE_EN_CONN I2C1_ISP_TO_TELE_RCAM_OIS_SCL_CONN I2C1_ISP_BI_TELE_RCAM_OIS_SDA_CONN C4096 1 0.1UF 30 220PF 5% 2 10V C0G-CERM 01005 ROOM=B2B_TELE_RCAM C4094 5% 2 10V C0G-CERM 01005 ROOM=B2B_TELE_RCAM ROOM=B2B_TELE_RCAM 29 30 FL4003 33-OHM-25%-1500MA 27 PP1V1_CAM_TELE_DVDD 1 R4003 1 PP1V1_CAM_TELE_DVDD_CONN 2 OMIT_TABLE 0201 1 ROOM=B2B_TELE_CAM 1 C4093 220PF 5% 2 10V C0G-CERM 01005 20% 2 6.3V X5R-CERM 0201 1% 1/32W MF 01005 2 ROOM=B2B_TELE_CAM ISP I2C C4025 2.2UF 20K 30 NOSTUFF ROOM=B2B_TELE_RCAM ROOM=B2B_TELE_RCAM 1 C4028 15PF 5% 2 16V NP0-C0G-CERM 01005 ROOM=B2B_TELE_RCAM R4000 C 8 IN I2C1_ISP_SCL 1 0.00 I2C1_ISP_TO_TELE_RCAM_OIS_SCL_CONN 2 0% 1/32W MF 01005 1 C4000 LPDP 56PF ROOM=B2B_TELE_RCAM C 30 CKPLUS_WAIVE=I2C_PULLUP 5% 2 25V NP0-C0G-CERM 01005 C4030 0.1UF ROOM=B2B_TELE_RCAM R4001 8 I2C1_ISP_SDA BI 1 0.00 9 I2C1_ISP_BI_TELE_RCAM_OIS_SDA_CONN 2 0% 1/32W MF 01005 1 BI 90_LPDP_TELE_TO_AP_D0_P 1 30 90_LPDP_TELE_TO_AP_D0_CONN_N 30 90_LPDP_TELE_TO_AP_D1_CONN_P 30 90_LPDP_TELE_TO_AP_D1_CONN_N 30 20% 6.3V X5R-CERM 01005 30 56PF ROOM=B2B_TELE_RCAM 90_LPDP_TELE_TO_AP_D0_CONN_P GND_VOID ROOM=B2B_TELE_RCAM CKPLUS_WAIVE=I2C_PULLUP C4001 2 C4031 5% 2 25V NP0-C0G-CERM 01005 0.1UF 9 ROOM=B2B_TELE_RCAM BI 90_LPDP_TELE_TO_AP_D0_N 1 2 ROOM=B2B_TELE_RCAM 20% 6.3V X5R-CERM 01005 GND_VOID C4040 0.1UF 9 OUT 90_LPDP_TELE_TO_AP_D1_P 1 2 ROOM=B2B_TELE_RCAM 20% 6.3V X5R-CERM 01005 GND_VOID C4041 0.1UF 9 B OUT 90_LPDP_TELE_TO_AP_D1_N 1 2 ROOM=B2B_TELE_RCAM 20% 6.3V X5R-CERM 01005 IO Filters GND_VOID B C4050 0.1UF R4005 8 IN AP_TO_TELE_CLK 1 49.9 9 AP_TO_TELE_CLK_CONN 2 1% 1/32W MF 01005 1 OUT 90_LPDP_TELE_TO_AP_D2_P 1 20% 6.3V X5R-CERM 01005 30 NOSTUFF C4006 56PF ROOM=B2B_TELE_RCAM OUT 90_LPDP_TELE_TO_AP_D2_N 1 R4007 AP_TO_TELE_SHUTDOWN_L 1 0.00 AP_TO_TELE_SHUTDOWN_CONN_L 2 0% 1/32W MF 01005 1 2 90_LPDP_TELE_TO_AP_D2_CONN_N 30 20% 6.3V X5R-CERM 01005 GND_VOID C4060 30 0.1UF C4007 9 220PF ROOM=B2B_TELE_RCAM 30 GND_VOID 0.1UF 9 ROOM=B2B_TELE_RCAM IN 90_LPDP_TELE_TO_AP_D2_CONN_P C4051 5% 2 25V NP0-C0G-CERM 01005 ROOM=B2B_TELE_RCAM 8 2 ROOM=B2B_TELE_RCAM OUT LPDP_TELE_BI_AP_AUX 1 ROOM=B2B_TELE_RCAM 5% 2 10V C0G-CERM 01005 ROOM=B2B_TELE_RCAM LPDP_TELE_BI_AP_AUX_CONN 2 20% 6.3V X5R-CERM 01005 1 30 C4061 56PF 5% 2 25V NP0-C0G-CERM 01005 ROOM=B2B_TELE_RCAM 30 29 BI WIDE_AND_TELE_TO_LED_DRIVER_STROBE_EN_CONN 1 C4008 220PF 5% 2 10V C0G-CERM 01005 A ROOM=B2B_TELE_RCAM SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016 PAGE TITLE CAMERA: B2B Tele (MT) R4010 29 IN WIDE_TO_TELE_SYNC_J3900_CONN 1 0.00 DRAWING NUMBER WIDE_TO_TELE_SYNC_J4000_CONN 2 0% 1/32W MF 01005 ROOM=B2B_TELE_RCAM 1 30 Apple Inc. C4010 051-02221 REVISION 9.0.0 220PF 5% 2 10V C0G-CERM 01005 ROOM=B2B_TELE_RCAM NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 40 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 30 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 D 4 3 2 1 D LED STROBE DRIVERS (NEON) APN:353S00558 I2C Address (7-bit): 0x63 45 43 42 41 34 27 23 21 19 18 50 46 PP_VDD_MAIN PP_LED1_BOOST_OUT C4191 C4192 1 18UF 1 L4100 1UH-20%-3.6A-0.062OHM ROOM=STROBE A2 IN 35 34 31 28 8 BI 35 34 31 28 8 B1 SW CAMPMU_TO_STROBE_DRIVER_HWEN C2 HWEN WIDE_AND_TELE_TO_STROBE_DRIVER_STROBE B2 STROBE IN IN IN C4106 18UF 20% 2 6.3V CER-X5R 0402-0.1MM ROOM=STROBE OUT C1 CRITICAL LED_DRIVER1_LX IN 50 36 31 DSBGA ROOM=STROBE2 1 ROOM=STROBE LM3566 2 31 29 5% 2 10V C0G-CERM 01005 U4100 0806 ROOM=STROBE 31 28 C4105 220PF CRITICAL 5% 10V 2 C0G-CERM 01005 ROOM=STROBE 1 1 220PF 20% 6.3V 2 CER-X5R 0402-0.1MM LED1 D3 PP_STROBE_COOL_WIDE_LED LED2 D1 PP_STROBE_WARM_ZOOM_LED INT 300K PD 33 33 INT 300K PD BB_TO_STROBE_DRIVER_GSM_BURST_IND I2C3_ISP_SDA I2C3_ISP_SCL D2 TX INT A3 SDA B3 SCL 1 C4102 220PF 300K PD STROBE_MODULE_NTC TORCH/TEMP C3 31 33 5% 2 10V C0G-CERM 01005 1 220PF 5% 2 10V C0G-CERM 01005 ROOM=STROBE ROOM=STROBE A1 GND C4101 C C APN:353S00868 I2C Address (7-bit): 0x67 PP_LED2_BOOST_OUT C4196 1 1 1 18UF 20% 6.3V 2 CER-X5R 0402-0.1MM 220PF 5% 2 10V C0G-CERM 01005 CRITICAL L4120 U4120 1UH-20%-3.6A-0.062OHM ROOM=STROBE2 ROOM=STROBE2 A2 IN 2 31 29 50 36 31 IN 35 34 31 28 8 BI 35 34 31 28 8 IN DSBGA ROOM=STROBE2 C4126 18UF 20% 2 6.3V CER-X5R 0402-0.1MM ROOM=STROBE ROOM=STROBE2 OUT C1 CRITICAL LED_DRIVER2_LX B1 SW CAMPMU_TO_STROBE_DRIVER_HWEN C2 HWEN WIDE_AND_TELE_TO_STROBE_DRIVER_STROBE B2 STROBE IN IN 1 LM35662 0806 31 28 C4125 LED1 D3 PP_STROBE_COOL_ZOOM_LED LED2 D1 PP_STROBE_WARM_WIDE_LED INT 300K PD 33 33 INT 300K PD BB_TO_STROBE_DRIVER_GSM_BURST_IND I2C3_ISP_SDA I2C3_ISP_SCL D2 TX INT A3 SDA B3 SCL 1 C4122 220PF 300K PD STROBE_MODULE_NTC TORCH/TEMP C3 31 33 5% 2 10V C0G-CERM 01005 ROOM=STROBE2 GND C4121 220PF 5% 2 10V C0G-CERM 01005 ROOM=STROBE2 B A1 B 1 A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016 PAGE TITLE CAMERA: Strobe Drivers DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 41 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 31 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 NEW HAMPSHIRE POWER FL4200 PP1V8_IO 1 Rcpt: 516S00244 Plug: 516S00245 PP1V8_FCAM_VDDIO_CONN 2 01005-1 C4200 1 ROOM=B2B_FCAM J4200 BB35K-RA18-3A 220PF 20% 2 6.3V X5R-CERM 01005 F-ST-SM 5% 2 10V C0G-CERM 01005 ROOM=B2B_FCAM ROOM=B2B_FCAM 32 PP1V1_FCAM_DVDD_CONN FL4202 10-OHM-750MA 27 PP1V1_FCAM_DVDD 1 PP1V1_FCAM_DVDD_CONN 2 C4202 1 C4203 1 0.1UF 220PF 20% 2 6.3V X5R-CERM 01005 ROOM=B2B_FCAM 8 BI 8 BI 32 01005-1 ROOM=B2B_FCAM 5% 2 10V C0G-CERM 01005 ROOM=B2B_FCAM FL4204 8 OUT 8 OUT 8 OUT 8 OUT 90_MIPI_FCAM_TO_AP_DATA0_P 90_MIPI_FCAM_TO_AP_DATA0_N 90_MIPI_FCAM_TO_AP_CLK_P 90_MIPI_FCAM_TO_AP_CLK_N 90_MIPI_FCAM_TO_AP_DATA1_P 90_MIPI_FCAM_TO_AP_DATA1_N 10-OHM-750MA 27 PP2V85_FCAM_AVDD 1 PP2V85_FCAM_AVDD_CONN 2 01005-1 1 ROOM=B2B_FCAM C4204 1 0.1UF <-- This one on MLB 32 C4201 1 0.1UF D 1 FCAM Connector 10-OHM-750MA 43 35 16 14 10 8 7 6 5 34 30 29 28 27 17 2 32 C4205 23 19 20 1 3 5 7 9 11 13 15 17 2 4 6 8 10 12 14 16 18 21 24 22 D I2C2_ISP_TO_FCAM_SAVAGE_SCL_CONN I2C2_ISP_BI_FCAM_SAVAGE_SDA_CONN PP1V8_FCAM_VDDIO_CONN PP2V85_FCAM_AVDD_CONN AP_TO_FCAM_SHUTDOWN_CONN_L FCAM_TO_JULIET_SYNC_J4200 AP_TO_FCAM_CLK_CONN 32 35 32 35 32 32 32 32 32 ROOM=B2B_FCAM 220PF 20% 2 6.3V X5R-CERM 01005 5% 2 10V C0G-CERM 01005 ROOM=B2B_FCAM ROOM=B2B_FCAM FCAM I/O R4210 35 8 IN AP_TO_FCAM_JULIET_CLK 1 1 C 0.00 AP_TO_FCAM_CLK_CONN 2 32 0% 1/32W MF 01005 C4210 56PF C 5% ROOM=B2B_FCAM 2 25V NP0-C0G-CERM 01005 ROOM=B2B_FCAM R4211 8 4 IN AP_TO_FCAM_SHUTDOWN_L 1 0.00 AP_TO_FCAM_SHUTDOWN_CONN_L 2 0% 1/32W MF 01005 1 32 C4211 220PF 5% 2 10V C0G-CERM 01005 ROOM=B2B_FCAM ROOM=B2B_FCAM R4212 35 OUT FCAM_TO_JULIET_SYNC_J4530 1 0.00 FCAM_TO_JULIET_SYNC_J4200 2 0% 1/32W MF 01005 1 32 C4212 100PF ROOM=B2B_FCAM 5% 2 16V NP0-C0G 01005 ROOM=B2B_FCAM ISP I2C2 R4220 B 8 IN I2C2_ISP_SCL 1 0.00 I2C2_ISP_TO_FCAM_SAVAGE_SCL_CONN 2 CKPLUS_WAIVE=I2C_PULLUP 0% 1/32W MF 01005 1 32 35 B C4220 56PF ROOM=B2B_FCAM 5% 2 25V NP0-C0G-CERM 01005 ROOM=B2B_FCAM R4221 8 BI I2C2_ISP_SDA 1 0.00 I2C2_ISP_BI_FCAM_SAVAGE_SDA_CONN 2 0% 1/32W MF 01005 ROOM=B2B_FCAM 1 C4221 32 35 CKPLUS_WAIVE=I2C_PULLUP 56PF 5% 2 25V NP0-C0G-CERM 01005 ROOM=B2B_FCAM A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016 PAGE TITLE CAMERA: B2B FCAM DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 42 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 32 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 HAWKING 0.22UF 37 OUT 1 GND 2 Rcpt: 516S00267 Plug: 516S00268 33 10% 6.3V CER-X5R 01005 <-- This one on MLB J4300 AA36D-S010VA1 F-ST-SM ROOM=B2B_STROBE 15 150OHM-25%-200MA-0.7DCR 1 2 HAWKING_TO_CODEC_AIN5_C_P 0.22UF 37 HAWKING_TO_CODEC_AIN5_P OUT 1 2 01005 CKPLUS_WAIVE=MISS_N_DIFFPAIR 10% 6.3V CER-X5R 01005 ROOM=B2B_STROBE 1 HAWKING_TO_CODEC_AIN5_P_CONN 11 C4302 33 33 5% 2 25V NP0-C0G-CERM 01005 33 38 ROOM=B2B_STROBE FL4303 33 150OHM-25%-200MA-0.7DCR 27 1 PP1V8_HAWKING_CONN 2 01005 ROOM=B2B_STROBE PWR D 12 PP_STROBE_COOL_WIDE_LED 2 4 6 8 10 I2C1_AP_BI_MIC2_SDA I2C1_AP_TO_MIC2_SCL PP1V8_HAWKING_CONN HAWKING_TO_CODEC_AIN5_P_CONN STROBE_MODULE_NTC_CONN 14 PP_STROBE_WARM_WIDE_LED 31 33 18 PP_STROBE_COOL_ZOOM_LED 31 33 31 33 33 56PF ROOM=B2B_STROBE PP1V8_HAWKING 16 FL4301 C4301 D 1 Strobe Connector C4300 HAWKING_TO_CODEC_AIN5_N 2 REARMIC2_TO_CODEC_AIN2_CONN_P REARMIC2_TO_CODEC_AIN2_CONN_N PP_CODEC_TO_REARMIC2_BIAS_CONN REARMIC2_TO_CODEC_BIAS_FILT_RET BUTTON_POWER_KEY_CONN_L 1 3 5 7 9 33 31 PP_STROBE_WARM_ZOOM_LED 13 33 31 PP_STROBE_COOL_ZOOM_LED 17 SIGNAL PWR 33 33 33 33 33 33 OMIT_TABLE 1 C4303 1 2.2UF C4304 220PF 5% 2 10V C0G-CERM 01005 20% 2 6.3V X5R-CERM 0201 ROOM=B2B_STROBE ROOM=B2B_STROBE ROOM=B2B_STROBE 33 MIC2 (ANC REF) GND GND FL4305 150OHM-25%-200MA-0.7DCR 38 PP_CODEC_TO_REARMIC2_BIAS 2 PP_CODEC_TO_REARMIC2_BIAS_CONN 1 01005 1 ROOM=B2B_STROBE MAKE_BASE=TRUE 33 C4305 220PF 5% 2 10V C0G-CERM 01005 C C ROOM=B2B_STROBE FL4306 150OHM-25%-200MA-0.7DCR 37 OUT REARMIC2_TO_CODEC_AIN2_P 2 REARMIC2_TO_CODEC_AIN2_CONN_P 1 01005 1 ROOM=B2B_STROBE 33 C4306 56PF 5% 2 25V NP0-C0G-CERM 01005 ROOM=B2B_STROBE FL4307 150OHM-25%-200MA-0.7DCR 37 OUT REARMIC2_TO_CODEC_AIN2_N 2 REARMIC2_TO_CODEC_AIN2_CONN_N 1 01005 1 ROOM=B2B_STROBE 33 C4307 56PF 5% 2 25V NP0-C0G-CERM 01005 Power Key Button ROOM=B2B_STROBE R4310 20 OUT BUTTON_POWER_KEY_L 1 C4310 27PF 1 5% 6.3V NP0-C0G 2 0201 ROOM=B2B_STROBE 100 BUTTON_POWER_KEY_CONN_L 2 5% 1/32W MF 01005 Strobe Filtering 33 1 DZ4310 ROOM=B2B_STROBE 5.5V-6.2PF PP_STROBE_WARM_ZOOM_LED 0201 2 31 33 ROOM=B2B_STROBE C4320 1 220PF B B 5% 10V 2 C0G-CERM 01005 ROOM=B2B_STROBE R4308 PP_STROBE_COOL_WIDE_LED 31 33 C4322 49 10 IN I2C1_AP_SCL 1 0.00 2 0% 1/32W MF 01005 1 220PF 5% 10V C0G-CERM 2 01005 1 33 I2C1_AP_BI_MIC2_SDA 33 C4308 56PF ROOM=B2B_STROBE 5% 2 25V NP0-C0G-CERM 01005 ROOM=B2B_STROBE ROOM=B2B_STROBE PP_STROBE_WARM_WIDE_LED R4309 31 33 C4324 I2C1_AP_TO_MIC2_SCL 49 10 1 IN I2C1_AP_SDA 2 0.00 1 0% 1/32W MF 01005 220PF 5% 10V C0G-CERM 2 01005 ROOM=B2B_STROBE ROOM=B2B_STROBE 1 C4309 56PF 5% 2 25V NP0-C0G-CERM 01005 ROOM=B2B_STROBE PP_STROBE_COOL_ZOOM_LED 31 33 C4326 1 220PF 5% 10V C0G-CERM 2 01005 A ROOM=B2B_STROBE SYNC_MASTER=test_mlb FL4330 CAMERA: B2B Strobe + Hold Button 150OHM-25%-200MA-0.7DCR 31 OUT STROBE_MODULE_NTC 1 R4330 1 27K STROBE_MODULE_NTC_CONN 2 DRAWING NUMBER 33 01005 ROOM=B2B_STROBE SYNC_DATE=10/13/2016 PAGE TITLE 1 Apple Inc. C4330 051-02221 REVISION 220PF 0.5% 1/32W MF 01005 2 ROOM=B2B_STROBE 9.0.0 5% 2 10V C0G-CERM 01005 ROOM=B2B_STROBE NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 43 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 33 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 Rigel Driver 6 45 43 42 41 31 27 23 21 19 18 50 46 5 4 3 2 1 PP_VDD_MAIN 1 C4497 C4494 18UF 1 4UF 20% 20% 6.3V CERM-X5R 2 0201 6.3V 2 CER-X5R 0402-0.1MM ROOM=RIGEL ROOM=RIGEL C4493 1 4UF 20% 6.3V CERM-X5R 2 0201 D D ROOM=RIGEL C4492 1 4UF 20% 6.3V CERM-X5R 2 0201 ROOM=RIGEL C4491 1 4UF Terminate @ Cap via on VDD_MAIN plane. 20% 6.3V CERM-X5R 2 0201 OMIT XW4400 ROOM=RIGEL SHORT-20L-0.05MM-SM PP_RIGEL_VINCORE 2 1 C4490 ROOM=RIGEL 1 1.0UF 20% 10V X5R-CERM 2 0201-1 ROOM=RIGEL C 29 28 27 17 16 14 10 8 7 6 5 43 35 32 30 PP1V8_IO C PP_VANA PP_VDD_BOOST IN 20% 2 6.3V CERM-X5R 0201 PP_ROMEO_CATHODE K4 K5 K6 K7 K8 ROMEO_TO_RIGEL_VCSEL_NTC IN 36 28 BI 35 28 BI 35 11 IN CAMPMU_TO_RIGEL_ENABLE YOGI_TO_RIGEL_STATUS MAMA_BEAR_BI_RIGEL_STATUS B 8 20 8 4 R4400 35 31 28 8 IN I2C3_ISP_SDA 1 33.2 35 31 28 8 2 IN AP_TO_RIGEL_CLK RIGEL_TO_ISP_INT OUT IN I2C3_ISP_SCL I2C3_ISP_SDA_U4400 1% 1/32W MF 01005 RIGEL_LSCP C4422 VINSDA F9 VINSDA F10 VINSDA E9 VBBOUTA VBBOUTA VBBOUTA H10 J10 K10 VLXA VLXA VLXA D10 D9 E10 VCXA VCXA B10 B9 U4400 WLCSP C4 OTPHV ROOM=RIGEL TAMP ENA XEF1 XEF0 THROT STROBE B7 TESTMODE B5 TESTMODE2 B6 TEST A7 MCLK B4 PP_RIGEL_BUCK_BOOST_A STB600B0 NTC B3 C8 C7 B8 A4 JULIET_PMU_TO_RIGEL_STROBE CRITICAL G4 D4 28 4 VK VK VK VK VK VINSUA A9 VINSUA A8 VINSUA A10 ROOM=RIGEL VINSUB A3 VINSUB A2 VINSUB A1 4UF VINSDB F2 VINSDB F1 VINSDB E2 ROOM=RIGEL C4498 VINCORE F5 2 X5R-CERM 0201-1 ROOM=RIGEL 35 20% 1.0UF 10V 2 X5R-CERM 0201-1 35 4 1 VINVCORE2 H5 20% 10V C4496 VANA H4 1.0UF 1 VDDIO C5 C4495 VIN_LVT H8 1 VCC4 G9 VCC3 G2 50 38 27 21 19 INT A5 A6 SCL SDA G5 G6 PD0 PD1 H7 LSCP 20% 5% 2 10V C0G-CERM 01005 16V 2 X5R 0402 2 C4401 220PF ROOM=RIGEL ROOM=RIGEL ROOM=RIGEL 4.7UF 20% 2 16V X5R 0402 RIGEL_VCXA 1 C4420 0.01UF ROOM=RIGEL 10% 2 6.3V X5R 01005 D3 E3 RIGEL_BULKSDB RIGEL_BOOSTSDB VCXB VCXB B1 B2 VLXB VLXB VLXB D1 D2 E1 VBBOUTB VBBOUTB VBBOUTB J1 J2 J3 IOUT0 IOUT0 IOUT0 H9 K9 J9 PP_ROMEO_DENSE_ANODE IOUT1 IOUT1 IOUT1 H1 H2 H3 PP_ROMEO_SPARSE_ANODE IOUT2 IOUT2 IOUT2 K1 K2 K3 PP_ROSALINE_ANODE IOUT3 G1 PP_ROMEO_A_ANODE IOUT4 G10 PP_ROMEO_B_ANODE ROOM=RIGEL 1 C4421 0.01UF RIGEL_VCXB 1 C4410 4.7UF L4401 ROOM=RIGEL 20% 2 16V X5R 0402 ROOM=RIGEL RIGEL_VLXB B 10% 2 6.3V X5R 01005 0.47UH-20%-4A-0.048OHM 1 2 PIWA20120H-SM 1 ROOM=RIGEL C4411 1 20% 5% 2 10V C0G-CERM 01005 4.7UF PP_RIGEL_BUCK_BOOST_B 16V 2 X5R 0402 ROOM=RIGEL C4412 220PF ROOM=RIGEL 4 35 35 36 35 PGNDA PGNDA 35 C9 C10 PGNDB PGNDB C2 C1 GNDS GNDS GNDS GNDS GNDS GNDS GNDS GNDS GNDS G7 E6 F8 E5 F3 D7 D6 D5 C3 GNDD C6 GNDCORE F6 G8 G3 H6 1 PIWA20120H-SM C4405 BULKSDB BOOSTSDB ROOM=RIGEL GNDCORE4 GNDCORE3 GNDCORE2 1 BOOSTSDA BULKSDA 10% 6.3V X5R 2 01005 PGNDK PGNDK PGNDK PGNDK PGNDK 1 RIGEL_BOOSTSDA RIGEL_BULKSDA 0.01UF J8 J7 J6 J5 J4 0.47UH-20%-4A-0.048OHM RIGEL_VLXA C4400 4.7UF L4400 E8 D8 1 A 1 SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016 PAGE TITLE PEARL: Power DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 44 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 34 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 Romeo Connector Romeo Power Filtering Rcpt: 516S00267 Plug: 516S00268 PP_ROMEO_B_ANODE PP_ROMEO_A_ANODE 35 34 PP_ROMEO_DENSE_ANODE 35 34 4 PP_ROMEO_SPARSE_ANODE 35 34 PP_ROMEO_CATHODE 35 34 4 PP3V3_SVDD 29 28 27 <-- This one on MLB 35 34 D 35 30 J4500 AA36D-S010VA1 35 34 4 1 C4592 220PF 5% 2 10V C0G-CERM 01005 1 C4593 1 220PF C4594 220PF 5% 2 10V C0G-CERM 01005 5% 2 10V C0G-CERM 01005 ROOM=B2B_PEARL ROOM=B2B_PEARL C4595 1 1 220PF 220PF 5% 2 10V C0G-CERM 01005 ROOM=B2B_PEARL C4596 C4597 35 34 220PF 35 34 5% 2 10V C0G-CERM 01005 5% 2 10V C0G-CERM 01005 ROOM=B2B_PEARL 1 ROOM=B2B_PEARL 35 ROOM=B2B_PEARL 35 Romeo I/O 35 34 4 FL4554 150OHM-25%-200MA-0.7DCR OUT ROMEO_TO_AOP_B2B_DETECT 1 35 34 ROMEO_TO_AOP_B2B_DETECT_CONN 2 01005 1 5% 2 10V C0G-CERM 01005 1 OUT 2 1 35 34 31 28 8 IN I2C3_ISP_SCL 1 C4555 5% 2 10V C0G-CERM 01005 C 0.00 ROMEO_TO_AOP_B2B_DETECT_CONN I2C3_ISP_BI_MAMA_BEAR_SDA_CONN PP_ROMEO_CATHODE 13 PP_ROMEO_SPARSE_ANODE 17 1 01005 1 ROOM=B2B_PEARL 35 34 31 28 8 BI I2C3_ISP_SDA 1 0.00 C4556 220PF ROOM=B2B_PEARL 1 35 CKPLUS_WAIVE=I2C_PULLUP C4553 56PF 5% 2 25V NP0-C0G-CERM 01005 Rcpt: 516S00244 Plug: 516S00245 IN AP_TO_JULIET_SHUTDOWN_L 1 0.00 AP_TO_JULIET_SHUTDOWN_L_CONN 2 0% 1/32W MF 01005 1 <-- This one on MLB BB35K-RA18-3A 35 F-ST-SM C4560 5% 2 10V C0G-CERM 01005 35 PP1V1_JULIET_DVDD_CONN ROOM=B2B_PEARL FL4561 8 150OHM-25%-200MA-0.7DCR 32 8 IN AP_TO_FCAM_JULIET_CLK 1 C4562 XW4570 SHORT-01005 35 C4570 1 0.1UF 20% 2 6.3V X5R-CERM 01005 FL4572 1 8 1 8 ROOM=B2B_PEARL C4571 8 8 ROOM=B2B_PEARL 5% 2 10V C0G-CERM 01005 ROOM=B2B_PEARL 34 11 OUT JULIET_PMU_TO_RIGEL_STROBE 1 0.00 JULIET_PMU_TO_RIGEL_STROBE_CONN 2 0% 1/32W MF 01005 PP2V85_JULIET_AVDD_CONN 35 1 ROOM=B2B_PEARL C4572 0.1UF 20% 2 6.3V X5R-CERM 01005 FL4574 90_MIPI_JULIET_TO_AP_DATA1_P 90_MIPI_JULIET_TO_AP_DATA1_N 1 23 19 20 1 3 5 7 9 11 13 15 17 2 4 6 8 10 12 14 16 18 21 24 22 JULIET_PMU_TO_RIGEL_STROBE_CONN FCAM_TO_JULIET_SYNC_J4530 PP2V85_JULIET_AVDD_CONN PP1V8_JULIET_VDDIO_CONN AP_TO_JULIET_SHUTDOWN_L_CONN I2C2_ISP_BI_FCAM_SAVAGE_SDA_CONN I2C2_ISP_TO_FCAM_SAVAGE_SCL_CONN AP_TO_JULIET_CLK_CONN 35 32 35 35 35 35 BI IN 32 32 35 ROOM=B2B_PEARL 35 C4563 220PF 5% 2 10V C0G-CERM 01005 ROOM=B2B_PEARL 1 90_MIPI_JULIET_TO_AP_CLK_P 90_MIPI_JULIET_TO_AP_CLK_N R4563 10-OHM-750MA 01005-1 90_MIPI_JULIET_TO_AP_DATA0_P 90_MIPI_JULIET_TO_AP_DATA0_N 220PF ROOM=B2B_PEARL 2 35 5% 25V NP0-C0G-CERM 2 01005 PP1V1_JULIET_DVDD_CONN ROOM=B2B_PEARL AP_TO_JULIET_CLK_CONN 01005 56PF 2 8 2 B J4530 220PF ROOM=B2B_PEARL C4573 220PF ROOM=B2B_PEARL 5% 2 10V C0G-CERM 01005 ROOM=B2B_PEARL ROOM=B2B_PEARL SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016 PAGE TITLE 10-OHM-750MA PP1V8_JULIET_VDDIO_CONN 2 ROOM=B2B_PEARL 34 35 Juliet Connector 8 01005-1 34 35 C R4560 1 27 28 29 30 35 ROOM=B2B_PEARL B PP1V8_IO 35 35 Juliet Power and I/O 43 34 32 30 27 17 16 14 7 6 5 10 8 29 28 PP_ROMEO_SPARSE_ANODE 18 35 5% 2 25V NP0-C0G-CERM 01005 I2C3_ISP_BI_MAMA_BEAR_SDA_CONN ROOM=B2B_PEARL ROOM=B2B_PEARL A PP_ROMEO_CATHODE 4 14 35 C4552 2 0% 1/32W MF 01005 5% 2 10V C0G-CERM 01005 30 PWR I2C3_ISP_TO_MAMA_BEAR_SCL_CONN MAMA_BEAR_BI_RIGEL_STATUS_CONN ROMEO_TO_RIGEL_VCSEL_NTC_CONN PP3V3_SVDD R4553 MAMA_BEAR_BI_RIGEL_STATUS_CONN 2 1 2 4 6 8 10 ROOM=B2B_PEARL FL4556 1 SIGNAL 34 35 56PF ROOM=B2B_PEARL 150OHM-25%-200MA-0.7DCR PP1V1_CAM_TELE_JULIET_DVDD 27 PP_ROMEO_CATHODE 4 12 CKPLUS_WAIVE=I2C_PULLUP ROOM=B2B_PEARL IN 1 3 5 7 9 I2C3_ISP_TO_MAMA_BEAR_SCL_CONN 2 0% 1/32W MF 01005 220PF ROOM=B2B_PEARL 1 PP_ROMEO_B_ANODE PP_ROMEO_A_ANODE PWR R4552 ROMEO_TO_RIGEL_VCSEL_NTC_CONN 01005 MAMA_BEAR_BI_RIGEL_STATUS 11 ISP I2C3 150OHM-25%-200MA-0.7DCR ROMEO_TO_RIGEL_VCSEL_NTC PP_ROMEO_CATHODE C4554 FL4555 PP2V85_CAM_TELE_AVDD 27 34 35 35 ROOM=B2B_PEARL 34 28 PP_ROMEO_DENSE_ANODE 4 16 220PF ROOM=B2B_PEARL 34 15 D 35 34 4 12 F-ST-SM PP_ROMEO_DENSE_ANODE 1 C4574 0.1UF 20% 2 6.3V X5R-CERM 01005 ROOM=B2B_PEARL 1 35 35 32 IN PEARL: B2B Romeo + Juliet FCAM_TO_JULIET_SYNC_J4530 DRAWING NUMBER C4575 1 220PF C4564 Apple Inc. 220PF 5% 2 10V C0G-CERM 01005 5% 2 10V C0G-CERM 01005 REVISION 9.0.0 ROOM=B2B_PEARL ROOM=B2B_PEARL 051-02221 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 45 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 35 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 AOP I2C IN I2C0_AOP_SCL 3 1 0.00 FL4650 I2C0_AOP_TO_PROX_ALS_YOGI_SCL_CONN 36 2 34 28 CKPLUS_WAIVE=I2C_PULLUP BI YOGI_TO_RIGEL_STATUS 1 01005 5% 2 25V NP0-C0G-CERM 01005 ROOM=B2B_PEARL 56PF ROOM=B2B_PEARL ROOM=B2B_PEARL D Rcpt: 516S00325 Plug: 516S00326 1 C4650 ROOM=B2B_PEARL 220PF OMIT XW4600 SHORT-20L-0.05MM-SM 5% 2 10V C0G-CERM 01005 FRONTMIC3_TO_CODEC_BIAS_FILT_RET 38 ROOM=B2B_PEARL 36 R4601 12 BI 1 0.00 36 I2C0_AOP_BI_PROX_ALS_YOGI_SDA_CONN 2 1 FRONTMIC3_TO_CODEC_AIN3_CONN_N PP3V0_YOGI_PROX_ALS_CONN 36 CKPLUS_WAIVE=I2C_PULLUP 0% 1/32W MF 01005 1 C4601 56PF 5% 2 25V NP0-C0G-CERM 01005 ROOM=B2B_PEARL ROOM=B2B_PEARL 36 34 SPEAKER2 50 36 IN <-- This one on MLB YOGI_TO_RIGEL_STATUS_CONN 36 2 C4600 1 1 Rosaline + Misc Connector 150OHM-25%-200MA-0.7DCR 0% 1/32W MF 01005 I2C0_AOP_SDA 2 Yogi Signals R4600 12 4 36 SPKRAMP_TOP_TO_COIL_OUT_POS C4631 C4635 1 820PF 1 36 50 36 SPKRAMP_TOP_TO_COIL_OUT_POS 220PF 5% 10V C0G-CERM 2 01005 C4630 220PF 5% 2 10V C0G-CERM 01005 10% 2 10V X5R 01005 ROOM=B2B_PEARL COIL_TO_SPKRAMP_TOP_VSENSE_POS_CONN SPKRAMP_TOP_TO_COIL_OUT_NEG CODEC_AOUT_TO_HAC_CONN_P 50 36 1 PP_ROSALINE_ANODE 2 J4600 AA26DK-S028VA1 F-ST-SM 33 29 30 1 3 5 7 9 11 13 15 17 19 21 23 25 27 2 4 6 8 10 12 14 16 18 20 22 24 26 28 31 34 32 FRONTMIC3_TO_CODEC_AIN3_CONN_P PP_CODEC_TO_FRONTMIC3_BIAS_CONN YOGI_TO_RIGEL_STATUS_CONN PROX_BI_AP_AOP_INT_CONN_L I2C0_AOP_BI_PROX_ALS_YOGI_SDA_CONN I2C0_AOP_TO_PROX_ALS_YOGI_SCL_CONN ALS_TO_AOP_INT_CONN_L D 36 36 36 36 36 36 36 PP_ROSALINE_ANODE 34 BB_TO_STROBE_DRIVER_GSM_BURST_IND_CONN 36 COIL_TO_SPKRAMP_TOP_VSENSE_NEG_CONN 36 SPKRAMP_TOP_TO_COIL_OUT_NEG CODEC_AOUT_TO_HAC_CONN_N SPKRAMP_TOP_TO_COIL_OUT_POS 36 36 50 36 36 50 ROOM=B2B_PEARL ROOM=B2B_PEARL ROOM=B2B_PEARL 50 36 IN SPKRAMP_TOP_TO_COIL_OUT_NEG 1 C4636 1 820PF 220PF 5% 2 10V C0G-CERM 01005 10% 2 10V X5R 01005 C C4632 ROOM=B2B_PEARL C ROOM=B2B_PEARL R4633 50 OUT COIL_TO_SPKRAMP_TOP_VSENSE_POS 1 NOSTUFF C4633 0.00 COIL_TO_SPKRAMP_TOP_VSENSE_POS_CONN 2 36 PP_ROSALINE_ANODE 34 36 0% 1/32W MF 01005 1 220PF 5% 10V 2 C0G-CERM 01005 1 C4660 220PF 5% 10V 2 C0G-CERM 01005 ROOM=B2B_PEARL ROOM=B2B_PEARL ROOM=B2B_PEARL R4634 PROX & ALS POWER 50 OUT COIL_TO_SPKRAMP_TOP_VSENSE_NEG 1 NOSTUFF C4634 COIL_TO_SPKRAMP_TOP_VSENSE_NEG_CONN 2 36 0% 1/32W MF 01005 1 220PF MIC3 0.00 5% 10V C0G-CERM 2 01005 ROOM=B2B_PEARL ROOM=B2B_PEARL FL4640 150OHM-25%-200MA-0.7DCR 38 PP_CODEC_TO_FRONTMIC3_BIAS 1 1 ROOM=B2B_PEARL PP3V0_S2 1 0.00 PP3V0_YOGI_PROX_ALS_CONN 2 DZ4640 2 ROOM=B2B_PEARL 36 OMIT_TABLE 0% 1/32W MF 01005 B 36 6.8V-100PF 01005 R4611 48 47 45 19 50 PP_CODEC_TO_FRONTMIC3_BIAS_CONN 2 01005 1 C4613 1 2.2UF 5% 2 10V C0G-CERM 01005 ROOM=B2B_PEARL B FL4641 220PF 20% 2 6.3V X5R-CERM 0201 ROOM=B2B_PEARL C4614 150OHM-25%-200MA-0.7DCR 37 ROOM=B2B_PEARL OUT FRONTMIC3_TO_CODEC_AIN3_N 1 FRONTMIC3_TO_CODEC_AIN3_CONN_N 2 01005 1 ROOM=B2B_PEARL 36 DZ4641 6.8V-100PF 01005 2 PROX/ALS I/O FL4642 R4617 12 BI PROX_BI_AP_AOP_INT_L 1 240 ROOM=B2B_PEARL 150OHM-25%-200MA-0.7DCR FRONTMIC3_TO_CODEC_AIN3_P PROX_BI_AP_AOP_INT_CONN_L 2 36 1% 1/32W MF 01005 1 37 OUT 2 01005 C4617 FRONTMIC3_TO_CODEC_AIN3_CONN_P 1 1 ROOM=B2B_PEARL 220PF DZ4642 6.8V-100PF 01005 5% 10V 2 C0G-CERM 01005 ROOM=B2B_PEARL 36 2 ROOM=B2B_PEARL ROOM=B2B_PEARL FL4618 FL4643 150OHM-25%-200MA-0.7DCR 12 OUT ALS_TO_AOP_INT_L 2 150OHM-25%-200MA-0.7DCR ALS_TO_AOP_INT_CONN_L 1 01005 ROOM=B2B_PEARL 36 1 37 CODEC_AOUT_TO_HAC_P OUT 1 01005 C4618 CODEC_AOUT_TO_HAC_CONN_P 2 1 ROOM=B2B_PEARL 220PF 36 DZ4643 6.8V-100PF 01005 5% 2 10V C0G-CERM 01005 2 ROOM=B2B_PEARL ROOM=B2B_PEARL A FL4644 FL4619 NOSTUFF 150OHM-25%-200MA-0.7DCR 50 31 BB_TO_STROBE_DRIVER_GSM_BURST_IND IN 1 BB_TO_STROBE_DRIVER_GSM_BURST_IND_CONN 36 2 01005 ROOM=B2B_PEARL 1 SYNC_MASTER=test_mlb 150OHM-25%-200MA-0.7DCR CODEC_AOUT_TO_HAC_N 37 OUT 2 ROOM=B2B_PEARL R4619 CODEC_AOUT_TO_HAC_CONN_N 1 01005 SYNC_DATE=10/13/2016 PAGE TITLE 1 PEARL: B2B Rosaline + Misc 36 DZ4644 DRAWING NUMBER 6.8V-100PF 01005 0.00 2 0% 1/32W MF 2 01005 Apple Inc. ROOM=B2B_PEARL 051-02221 REVISION 9.0.0 ROOM=B2B_PEARL NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 46 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 36 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 CALLAN AUDIO CODEC (ANALOG INPUTS & OUTPUTS) D D U4700 CS42L75 WLCSP 49 IN 49 IN 33 IN 33 IN 36 IN 36 IN 49 IN 49 IN SYM 1 OF 3 LOWERMIC1_TO_CODEC_AIN1_P LOWERMIC1_TO_CODEC_AIN1_N K3 L3 AIN1+ AIN1- REARMIC2_TO_CODEC_AIN2_P REARMIC2_TO_CODEC_AIN2_N K4 L4 AIN2+ AIN2- FRONTMIC3_TO_CODEC_AIN3_P FRONTMIC3_TO_CODEC_AIN3_N K6 L6 AIN3+ AIN3- LOWERMIC4_TO_CODEC_AIN4_P LOWERMIC4_TO_CODEC_AIN4_N K5 L5 AIN4+ AIN4- CRITICAL ROOM=CODEC AOUT+ AOUT- CODEC_AOUT_TO_HAC_P CODEC_AOUT_TO_HAC_N K8 L8 OUT 36 OUT 36 C C 33 IN 33 IN HAWKING_TO_CODEC_AIN5_P HAWKING_TO_CODEC_AIN5_N G3 G2 AIN5+ AIN5- F3 NC G4 NC AIN6+ AIN6- F4 E3 AIN7+ AIN7- NC NC C4700 100PF 1 B 50 OUT 50 OUT 41 4 OUT 41 4 OUT AIN8+ AIN8- B8 NC D8 NC E11 NC E10 NC D10 NC D9 NC E9 NC F8 NC DMIC1_CLK DMIC1_DATA DMIC2_CLK DMIC2_DATA 1 E1 F1 90_MIKEYBUS_CODEC_DATA_P 90_MIKEYBUS_CODEC_DATA_N MBUS_REF G1 MIKEYBUS_REFERENCE DP DN DMIC3_CLK DMIC3_DATA 1 B11 B10 PDMOUT1_CLK PDMOUT1_DATA PDM_CODEC_TO_ARC_CLK PDM_CODEC_TO_ARC_DATA A10 B9 PDMOUT2_CLK PDMOUT2_DATA F10 F9 PDMOUT3_CLK PDMOUT3_DATA 20.0 ROOM=CODEC 90_MIKEYBUS_DATA_P 2 BI 48 BI 48 5% 1/32W MF 01005 ROOM=CODEC R4701 IN 49 1 20.0 90_MIKEYBUS_DATA_N 2 5% 1/32W MF 01005 R4710 B C4701 100PF ROOM=CODEC 100 DMIC4_CLK DMIC4_DATA PDM_CODEC_TO_SPKRAMP_TOP_CLK PDM_CODEC_TO_SPKRAMP_TOP_DATA NC NC 5% 16V NP0-C0G 01005 R4700 C2 NC D3 NC 2 1 5% 1/32W MF 2 01005 ROOM=CODEC 2 5% 16V NP0-C0G 01005 ROOM=CODEC A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016 PAGE TITLE AUDIO: CODEC (1/2) DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 47 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 37 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 CALLAN AUDIO CODEC (POWER & I/O) D D 50 41 19 PP1V8_AUDIO_VA_S2 OMIT_TABLE 1 C4809 2.2UF 20% 2 6.3V X5R-CERM 0201 ROOM=CODEC CODEC_AGND 38 48 47 46 38 22 20 17 14 12 10 50 49 50 34 27 21 19 PP1V8_S2 R4800 1 PP_VDD_BOOST 100K 5% 1/32W MF 01005 2 OMIT_TABLE 1 C4812 0.1UF 20% 2 6.3V X5R-CERM 01005 1 C4814 1 0.1UF 2.2UF ROOM=CODEC 20% 2 6.3V X5R-CERM 0201 20% 2 6.3V X5R-CERM 01005 ROOM=CODEC C4805 ROOM=CODEC 12 ROOM=CODEC IN U4700 AOP_TO_CODEC_RESET_L J4 CS42L75 RESET* JTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDO WLCSP SYM 3 OF 3 PP1V8_S2 OMIT_TABLE 20% 2 6.3V X5R-CERM 01005 20% 2 6.3V X5R-CERM 01005 10 OUT 10 ROOM=CODEC ROOM=CODEC IN 10 IN 10 IN 10 OUT 10 IN 12 IN 0.1UF 0.1UF PP1V2_CODEC_S2 1 C4817 1 1.0UF 1.0UF 20% 2 6.3V X5R 0201-1 ROOM=CODEC 20% 2 6.3V X5R 0201-1 ROOM=CODEC C4803 4.7UF 49 IN LOWERMIC1_TO_CODEC_BIAS_FILT_RET 1 C4821 49 PP_CODEC_TO_LOWERMIC1_BIAS LOWERMIC1_BIAS_FILT_IN K11 K10 MIC1_BIAS MIC1_BIAS_FILT REARMIC2_TO_CODEC_BIAS_FILT_RET 1 OUT CODEC_TO_SPKRAMP_BOT_ARC_MCLK ROOM=CODEC 49 41 12 IN I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT SYM 2 OF 3 33 PP_CODEC_TO_REARMIC2_BIAS REARMIC2_BIAS_FILT_IN J11 J10 C4801 36 IN 1 36 2 PP_CODEC_TO_FRONTMIC3_BIAS FRONTMIC3_BIAS_FILT_IN K9 J9 1 49.9 1% 1/32W MF 01005 WLCSP LP_FILT+ D1 LP_FILT- D2 MIC2_BIAS MIC2_BIAS_FILT CODEC_LP_FILTP CODEC_LP_FILTN 20% 6.3V X5R-CERM1 402 ROOM=CODEC FRONTMIC3_TO_CODEC_BIAS_FILT_RET 33.2 2 1% 1/32W MF 01005 CS42L75 2 4.7UF 1 R4831 U4700 C4804 IN 50 41 CRITICAL 20% 6.3V X5R-CERM1 402 ROOM=CODEC 33 R4830 CODEC_TO_PMU_WAKE H3 WAKE* CODEC_TO_AP_INT_L D4 INT* SPI_AP_TO_CODEC_CS_L SPI_AP_TO_CODEC_SCLK C7 A7 CS* CCLK SPI_AP_TO_CODEC_MOSI SPI_CODEC_TO_AP_MISO C8 B7 MOSI MISO I2S_AP_TO_CODEC_MCLK1 I2S_AOP_TO_CODEC_MCLK2 CODEC_TO_SPKRAMP_BOT_ARC_MCLK_R A4 B4 A5 MCLK1_IN MCLK2_IN MCLK_OUT 1 C4820 ROOM=CODEC 0.1UF 20% 2 6.3V X5R-CERM 01005 ROOM=CODEC MIC3_BIAS MIC3_BIAS_FILT 50 49 41 12 OUT I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT_R I2S_CODEC_ASP1_TO_AOP_AMPS_DIN A6 C6 B5 B6 50 49 41 12 ASP1_SCLK ASP1_LRCK/FSYNC ASP1_SDIN ASP1_SDOUT OUT 50 41 12 OUT 2 12 IN I2S_AOP_TO_CODEC_ASP2_BCLK I2S_AOP_TO_CODEC_ASP2_LRCLK I2S_AOP_TO_CODEC_ASP2_DOUT I2S_CODEC_ASP2_TO_AOP_DIN C4 D5 D6 C5 12 ASP2_SCLK ASP2_LRCK/FSYNC ASP2_SDIN ASP2_SDOUT IN 12 IN 12 OUT 10 IN C11 C9 C10 D11 10 ASP3_SCLK ASP3_LRCK/FSYNC ASP3_SDIN ASP3_SDOUT IN 10 IN 10 OUT I2S_AP_TO_CODEC_ASP3_BCLK I2S_AP_TO_CODEC_ASP3_LRCLK I2S_AP_TO_CODEC_ASP3_DOUT I2S_CODEC_ASP3_TO_AP_DIN H4 H5 20% 6.3V X5R-CERM1 402 ROOM=CODEC B C4802 49 IN LOWERMIC4_TO_CODEC_BIAS_FILT_RET 4.7UF 1 2 ROOM=CODEC CRITICAL C TSTI G10 TSTI J3 TSTI J5 ROOM=CODEC 2 4.7UF VP_MBUS F2 ROOM=CODEC OUT VA J1 VA J2 VA K2 C 20 1 VP L9 20% 2 10V X5R-CERM 0402-0.1MM C4813 VL A9 10UF C4815 1 VD_FILT B1 VD_FILT G11 C4811 VD C1 1 VL_SW A2 48 47 46 38 22 20 17 14 12 10 50 49 E7 NC D7 NC E8 NC F7 NC 49 PP_CODEC_TO_LOWERMIC4_BIAS LOWERMIC4_BIAS_FILT_IN H9 H8 20% 6.3V X5R-CERM1 402 ROOM=CODEC 1 C4823 1 1.0UF C4822 1.0UF 20% 2 6.3V X5R 0201-1 ROOM=CODEC B3 B2 SW2_CLK SW2_SD CODEC_TO_AOP_GPIO1 CODEC_TO_AOP_GPIO2 E6 E5 GPIO1 GPIO2 AOP_TO_CODEC_CLP_EN F6 CLP_EN NC NC 0201-1 ROOM=CODEC GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA OMIT_TABLE 20% 2 6.3V X5R 1 SW1_CLK SW1_SD C4824 ROOM=CODEC 1 A3 NC C3 NC MIC4_BIAS MIC4_BIAS_FILT 1.0UF 20% 2 6.3V X5R 0201-1 DIGLDO_PULLDN DIGLDO_EN H11 NC H10 NC FILT+ K1 FILT- L2 MIC5_BIAS MIC5_BIAS_FILT CODEC_FILTP 1 C4808 10UF 20% 2 10V X5R-CERM 0402-0.1MM ROOM=CODEC 12 OUT 12 OUT 12 IN F5 G5 G6 G7 H1 H2 H6 H7 J6 J7 J8 E4 B C4825 1.0UF 20% 2 6.3V X5R 0201-1 G8 NC G9 NC MIC6_BIAS MIC6_BIAS_FILT ROOM=CODEC GNDD A K7 L1 L7 L10 L11 A1 A8 A11 E2 F11 GNDP XW4802 SHORT-10L-0.1MM-SM 2 1 SYNC_MASTER=test_mlb 38 CODEC_AGND SYNC_DATE=10/13/2016 PAGE TITLE AUDIO: CODEC (2/2) ROOM=CODEC DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 48 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 38 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 D D C C South Speaker Amplifier on MLB Bottom B B A SYNC_DATE=08/25/2015 PAGE TITLE AUDIO: Speaker Amp Bottom DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 49 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 39 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 D D C C North Speaker Amplifier on MLB Bottom B B A SYNC_DATE=08/25/2015 PAGE TITLE AUDIO: Speaker Amp Top DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 50 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 40 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 Pull Downs AOP_TO_SPKRAMP_BOT_ARC_RESET_L 1 12 41 50 R5108 100K ARC DRIVER 5% 1/32W MF 2 01005 ROOM=ARC_CTRL D D APN: 338S00296 I2C ADDRESS: 1000 001x 0x82 45 43 42 34 31 27 23 21 19 18 50 46 PP_VDD_MAIN PP1V8_AUDIO_VA_S2 C5130 C5131 1 18UF 18UF 20% 6.3V 2 CER-X5R 0402-0.1MM ROOM=ARC_CTRL 1 20% 6.3V 2 CER-X5R 0402-0.1MM ROOM=ARC_CTRL C5125 1 1 4UF C5127 1 0.1UF 20% 6.3V 2 CERM-X5R 0201 C5134 2.2UF 20% 2 6.3V X5R-CERM 01005 ROOM=ARC_CTRL 19 38 41 50 20% 2 6.3V X5R-CERM 0201 ROOM=ARC_CTRL ROOM=ARC_CTRL C L5100 F5 CRITICAL A5 C VP VA 1.2UH-20%-3A-0.11OHM 1 A2 B2 ARC1_LX 2 MEFE2016T-SM ROOM=ARC_CTRL 50 49 25 12 4 BI 50 49 25 12 4 IN 50 12 BI 50 41 12 IN D6 I2C1_AOP_SDA I2C1_AOP_SCL E6 SPKRAMP_BOT_ARC_TO_AOP_INT_L A7 AOP_TO_SPKRAMP_BOT_ARC_RESET_L A6 F6 NC 50 41 38 19 PP1V8_AUDIO_VA_S2 PP1V8_AUDIO_VA_S2 E5 CODEC_TO_SPKRAMP_BOT_ARC_MCLK B7 I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK C7 I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK C6 I2S_CODEC_ASP1_TO_AOP_AMPS_DIN D7 MAKE_BASE=TRUE 50 38 50 49 38 12 50 49 38 12 50 38 12 49 38 12 37 4 B 37 4 IN IN IN IN OUT IN IN I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT B6 PDM_CODEC_TO_ARC_CLK F7 PDM_CODEC_TO_ARC_DATA E7 D5 U5100 SW SW VBST_B VBST_B CS35L26C-A1 WLCSP SDA VBST_A VBST_A ROOM=ARC_CTRL CRITICAL SCL A1 B1 PP_ARC1_VBOOST 1 C1 D1 C5126 220PF 5% 2 10V C0G-CERM 01005 ROOM=ARC_CTRL 1 C5135 0.1UF 10% 2 16V X5R-CERM 0201 ROOM=ARC_CTRL 1 C5137 1 10UF 20% 2 10V X5R-CERM 0402-0.1MM ROOM=ARC_CTRL C5124 10UF 20% 2 10V X5R-CERM 0402-0.1MM ROOM=ARC_CTRL 1 C5138 1 10UF 20% 2 10V X5R-CERM 0402-0.1MM ROOM=ARC_CTRL C5139 10UF 20% 2 10V X5R-CERM 0402-0.1MM ROOM=ARC_CTRL INT* RESET* ISNS+ ISNS- ALIVE/SYNC AD0/PDM_CLK1 MCLK VSNS+ VSNS- SCLK F1 E1 ARC1_ISENSE_POS ARC1_ISENSE_NEG E2 E3 SOLENOID1_TO_ARC1_VSENSE_POS SOLENOID1_TO_ARC1_VSENSE_NEG 1 C5128 0.01UF 10% 2 6.3V X5R 01005 ROOM=ARC_CTRL IN 49 IN 49 LRCK/FSYNC SDIN OUT+ OUT- SDOUT D2 C2 ARC1_TO_SOLENOID1_OUT_POS ARC1_TO_SOLENOID1_OUT_NEG PDM_CLK0 FILT+ PDM_DATA0 PDM_DATA1 GNDP GNDA AD1 F4 C5129 ARC1_FILT 470PF F3 1 10% 10V 2 X5R 01005 C5136 ROOM=ARC_CTRL 2.2UF 1 49 C5142 470PF B 10% 2 10V X5R 01005 ROOM=ARC_CTRL 20% 2 6.3V X5R-CERM 0201 B5 E4 F2 A3 A4 B3 B4 C3 C4 C5 D3 D4 1 49 ROOM=ARC_CTRL A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016 PAGE TITLE ARC: Driver DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 51 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 41 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 Acorn PMU D D Charge Pump 1 Caps U5600 LM3373A1YKA 19 17 14 C PP1V1_S2 1 C5691 4UF 20% 2 6.3V CERM-X5R 0201 ROOM=ACORN A1 VJ 1 VC B1 PP1V1_RACER 50 VA C1 PP3V5_RACER 50 1 LOAD SWITCH C5692 A2 VK 0.1UF 20% 2 6.3V X5R-CERM 01005 DSBGA ROOM=ACORN LDO1 A4 VL 1 ROOM=ACORN C5650 220PF 5% 2 16V C0G 01005 1 C1+ B2 C1- B3 CP1 CRITICAL C5651 4UF ACORN_CP1_CAP2_POS ACORN_CP1_CAP2_NEG C2+ A3 C2- C3 20% 2 6.3V CERM-X5R 0201 ROOM=ACORN ACORN_CP1_CAP1_POS ACORN_CP1_CAP1_NEG 1 42 C5642 42 20% 2 6.3V X5R 01005 ACORN_CP1_CAP1_POS ACORN_CP1_CAP1_NEG ROOM=ACORN 4UF 42 20% 2 6.3V CERM-X5R 0201 42 42 42 ACORN_CP1_CAP2_POS ACORN_CP1_CAP2_NEG 1 ROOM=ACORN H4 VG LDO2 20% 2 6.3V X5R 01005 VH H2 PP5V25_TOUCH_VDDH VN D4 PN6V7_RACER 50 OMIT_TABLE 1 C5652 220PF 5% 2 16V C0G 01005 1 C5653 ROOM=ACORN 10UF 20% 2 10V X5R-CERM 0402-0.1MM ROOM=ACORN ACORN_CP2_CAP_POS ACORN_CP2_CAP_NEG C3+ C2 C3- C4 CP2 ROOM=ACORN PP_BOOST1_ACORN 220PF 5% 2 16V C0G 01005 ROOM=ACORN 10UF CP3 20% 2 10V X5R-CERM 0402-0.1MM ROOM=ACORN PP_VDD_MAIN B4 IN C5690 4.7UF 1.5UH-20%-1.6A-0.18OHM ACORN_LX 2 1 20% 2 6.3V CER 0402 G4 SW PIWA2012FE-SM ROOM=ACORN F1 AGND ROOM=ACORN H3 SIDO_GND L5600 E1 CP23_GND 1 B C5655 D1 CP1_GND 45 43 41 34 31 27 23 21 19 18 50 46 1 1 PP10V0_RACER C4+ D2 C4- D3 ACORN_CP3_CAP1_POS ACORN_CP3_CAP1_NEG 42 C5+ E2 C5- E3 ACORN_CP3_CAP2_POS ACORN_CP3_CAP2_NEG 42 HWEN H1 EN1 F2 EN2 F3 PP1V8_TOUCH_RACER_S2 RACER_TO_ACORN_ORB_SCAN TOUCH_TO_ACORN_PP5V25_EN SCL G2 SDA G3 I2C3_AP_SCL I2C3_AP_SDA AMUX G1 ACORN_TO_PMU_ADC 1 Charge Pump 2 Caps 42 OMIT_TABLE C5654 50 42 VP E4 F4 VB 1 C5612 0.22UF 42 ROOM=ACORN PP5V45_BOOST2_ACORN C 0.22UF 42 PP_CP1_OUT_ACORN C5611 1 C5640 4.7UF 42 20% 2 16V X5R 0402 ROOM=ACORN 1 C5641 10UF 20% 2 10V X5R-CERM 0402-0.1MM ROOM=ACORN 1UF 50 42 1 C5645 C5621 42 20% 2 16V CER-X5R 0201 ACORN_CP2_CAP_POS ACORN_CP2_CAP_NEG ROOM=ACORN 4UF 20% 2 6.3V CERM-X5R 0201 Charge Pump 3 Caps ROOM=ACORN 42 1 C5631 0.22UF 17 50 42 IN 50 IN 50 IN 10 50 42 42 BI OUT 42 20% 2 6.3V X5R 01005 ACORN_CP3_CAP1_POS ACORN_CP3_CAP1_NEG ROOM=ACORN ACORN_CP3_CAP2_POS ACORN_CP3_CAP2_NEG 1 10 50 B C5632 0.22UF 20% 2 6.3V X5R 01005 20 C5660 ROOM=ACORN 1000PF 10% 2 6.3V X5R-CERM 01005 ROOM=ACORN A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016 PAGE TITLE CG: Power Supplies - Touch & Display DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 56 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 42 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 Display Flex Connector Display Control Signals Rcpt: 516S00210 Plug: 516S00211 FL5700 J5700 150OHM-25%-200MA-0.7DCR 11 IN AP_TO_DISPLAY_RESET_L 2 01005 AP_TO_DISPLAY_RESET_CONN_L 1 ROOM=B2B_DISPLAY F-ST-SM ROOM=B2B_DISPLAY 43 C5700 220PF 61.9K 43 5% 2 10V C0G-CERM 01005 1% 1/32W MF 01005 2 D BM28P0.6-34DS/2-0.35V 1 R5700 1 ROOM=B2B_DISPLAY 43 ROOM=B2B_DISPLAY 43 R5701 20 IN PMU_TO_DISPLAY_PANICB 1 10 43 PMU_TO_DISPLAY_PANICB_CONN 2 43 43 43 5% 1/32W MF 01005 1 C5701 220PF ROOM=B2B_DISPLAY 5% 2 10V C0G-CERM 01005 ROOM=B2B_DISPLAY 43 FL5702 43 150OHM-25%-200MA-0.7DCR 8 OUT DISPLAY_TO_AP_ALIVE 2 DISPLAY_TO_AP_ALIVE_CONN 1 01005 ROOM=B2B_DISPLAY 1 <-- This one on MLB 43 43 C5702 43 56PF 5% 43 2 25V NP0-C0G-CERM 43 01005 PP_VDD_MAIN_HILO_CONN 35 PP1V8_DISPLAY_CONN DISPLAY_TO_PMU_AMUX_CONN AP_TO_DISPLAY_RESET_CONN_L MTEST PMU_TO_DISPLAY_PANICB_CONN NC_SPI_DISPLAY_FLASH_CS_L NC_PP_VPP NC_SPI_DISPLAY_FLASH_TO_AP_MISO 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 PWR PP_VDD_MAIN_HILO_CONN 36 43 SIG NO_TEST=1 NO_TEST=1 NO_TEST=1 90_MIPI_AP_TO_DISPLAY_DATA2_CONN_P 90_MIPI_AP_TO_DISPLAY_DATA2_CONN_N 90_MIPI_AP_TO_DISPLAY_CLK_CONN_P 90_MIPI_AP_TO_DISPLAY_CLK_CONN_N 90_MIPI_AP_TO_DISPLAY_DATA3_CONN_P 90_MIPI_AP_TO_DISPLAY_DATA3_CONN_N 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 D MTEST PP3V0_DISPLAY_CONN NC_SPI_AP_TO_DISPLAY_FLASH_SCLK PP1V0_DISPLAY_DVDD_CONN NC_DISPLAY_PIFA ISP_TO_DISPLAY_FLASH_INT_CONN NC_SPI_AP_TO_DISPLAY_FLASH_MOSI DISPLAY_TO_AP_ALIVE_CONN NO_TEST=1 NO_TEST=1 NO_TEST=1 43 43 43 43 43 90_MIPI_AP_TO_DISPLAY_DATA1_CONN_P 90_MIPI_AP_TO_DISPLAY_DATA1_CONN_N 43 90_MIPI_AP_TO_DISPLAY_DATA0_CONN_P 90_MIPI_AP_TO_DISPLAY_DATA0_CONN_N 43 43 43 ROOM=B2B_DISPLAY PWR FL5703 37 150OHM-25%-200MA-0.7DCR 20 IN DISPLAY_TO_PMU_AMUX 2 DISPLAY_TO_PMU_AMUX_CONN 1 01005 ROOM=B2B_DISPLAY 1 38 43 C5703 56PF 5% 2 25V NP0-C0G-CERM 01005 ROOM=B2B_DISPLAY C Display MIPI FL5704 150OHM-25%-200MA-0.7DCR 8 IN ISP_TO_DISPLAY_FLASH_INT 2 ISP_TO_DISPLAY_FLASH_INT_CONN 1 01005 ROOM=B2B_DISPLAY 1 43 8 BI 8 BI C5704 220PF 5% 2 10V C0G-CERM 01005 C L5700 CRITICAL 65OHM-0.7-2GHZ-3.4OHM 90_MIPI_AP_TO_DISPLAY_DATA0_P 4 90_MIPI_AP_TO_DISPLAY_DATA0_N 3 TAM0605 SYM_VER-2 1 90_MIPI_AP_TO_DISPLAY_DATA0_CONN_P 43 2 90_MIPI_AP_TO_DISPLAY_DATA0_CONN_N 43 FL5780 29 28 27 17 16 14 10 8 7 6 5 35 34 32 30 L5710 CRITICAL 65OHM-0.7-2GHZ-3.4OHM 8 IN 8 IN 90_MIPI_AP_TO_DISPLAY_DATA1_P 4 90_MIPI_AP_TO_DISPLAY_DATA1_N 3 TAM0605 SYM_VER-2 L5720 IN 2 90_MIPI_AP_TO_DISPLAY_DATA1_CONN_P 43 2 90_MIPI_AP_TO_DISPLAY_DATA1_CONN_N 43 0201 1 IN 3 ROOM=B2B_DISPLAY FL5782 CRITICAL 33-OHM-25%-1500MA 90_MIPI_AP_TO_DISPLAY_DATA2_CONN_P 43 19 PP1V0_DISPLAY_DVDD 2 2 L5730 IN 43 1 C5782 220PF 43 5% 2 10V C0G-CERM 01005 CRITICAL 65OHM-0.7-2GHZ-3.4OHM TAM0605 SYM_VER-2 4 1 90_MIPI_AP_TO_DISPLAY_DATA3_P 90_MIPI_AP_TO_DISPLAY_DATA2_CONN_N PP1V0_DISPLAY_DVDD_CONN 1 ROOM=B2B_DISPLAY GND_VOID 8 C5781 5% 2 10V C0G-CERM 01005 ROOM=B2B_DISPLAY 8 43 220PF 0201 90_MIPI_AP_TO_DISPLAY_DATA2_N PP1V8_DISPLAY_CONN 1 ROOM=B2B_DISPLAY 1 65OHM-0.7-2GHZ-3.4OHM TAM0605 SYM_VER-2 4 1 90_MIPI_AP_TO_DISPLAY_DATA2_P PP1V8_IO ROOM=B2B_DISPLAY GND_VOID 8 33-OHM-25%-1500MA ROOM=B2B_DISPLAY GND_VOID ROOM=B2B_DISPLAY Display Power ROOM=B2B_DISPLAY 90_MIPI_AP_TO_DISPLAY_DATA3_CONN_P FL5783 43 FERR-70OHM-25%-0.300A 8 IN 90_MIPI_AP_TO_DISPLAY_DATA3_N 3 GND_VOID B 2 90_MIPI_AP_TO_DISPLAY_DATA3_CONN_N 19 43 PP3V0_DISPLAY 1 ROOM=B2B_DISPLAY 01005 CRITICAL L5740 65OHM-0.7-2GHZ-3.4OHM 8 IN 90_MIPI_AP_TO_DISPLAY_CLK_P 4 TAM0605 SYM_VER-2 1 PP3V0_DISPLAY_CONN 2 ROOM=B2B_DISPLAY 1 43 C5783 B 220PF 90_MIPI_AP_TO_DISPLAY_CLK_CONN_P 5% 2 10V C0G-CERM 01005 43 ROOM=B2B_DISPLAY 8 IN 90_MIPI_AP_TO_DISPLAY_CLK_N 3 GND_VOID 2 90_MIPI_AP_TO_DISPLAY_CLK_CONN_N 43 XW5784 SHORT-0201 ROOM=B2B_DISPLAY 45 42 41 34 31 27 23 21 19 18 50 46 PP_VDD_MAIN 1 PP_VDD_MAIN_HILO_CONN 2 ROOM=B2B_DISPLAY XW5785 SHORT-0201 1 2 1 C5784 220PF 5% 2 10V C0G-CERM 01005 1 C5785 220PF 5% 2 10V C0G-CERM 01005 ROOM=B2B_DISPLAY ROOM=B2B_DISPLAY 1 43 C5786 220PF 5% 2 10V C0G-CERM 01005 ROOM=B2B_DISPLAY ROOM=B2B_DISPLAY A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016 PAGE TITLE CG: B2B Display DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 57 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 43 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 D D C C Orb + Touch Connector on MLB Bottom B B A SYNC_DATE=08/25/2015 PAGE TITLE CG: B2B Orb & Touch DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 58 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 44 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 D 7 6 5 4 3 2 1 VDD_MAIN OV CUT-OFF CIRCUIT 43 42 41 34 31 27 23 21 19 18 50 46 D PP_VDD_MAIN 48 47 23 PP_VBUS1_E75_RVP C5900 DZ5900 0201 K 1 A PP3V0_S2 19 36 47 48 50 0.47UF 1 20% 25V 2 X5R 0201 ROOM=OV_CUTOFF R5901 1.3M 2 1% 1/20W MF 2 0201 ROOM=OV_CUTOFF RB521ES-30 CRITICAL VDD OMIT U5900 SHORT-20L-0.05MM-SM XW5900 2 1 OV_VMON_INA TPS3700RUG 5 X2QFN INA ROOM=SOC OUTA 7 OUTB 1 To Hydra and E75 NC R5903 PP_VDD_MAIN_VMON 1 NOSTUFF R5902 1 100K C5902 15PF 1% 1/32W MF 2 01005 ROOM=OV_CUTOFF 3 INB ROOM=OV_CUTOFF NC0 NC1 4 8 GND NC NC 1 0.00 2 PP_HYDRA_ACC1 48 49 C 0% 1/32W MF 01005 ROOM=OV_CUTOFF 6 C PP_HYDRA_ACC1_R 5% 2 16V NP0-C0G-CERM 01005 ROOM=OV_CUTOFF B B A SYNC_MASTER=sync SYNC_DATE=01/10/2017 PAGE TITLE I/O: Overvoltage Cut-Off Circuit DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 59 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 45 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 D D ACCESSORY BUCK I2C ADDRESS: 0x52 U6100 FPF1204UCX 43 42 41 34 31 27 23 21 19 18 50 45 PP_VDD_MAIN ROOM=ACC_BUCK C6100 CRITICAL 49 48 47 38 22 20 17 14 12 10 50 PP1V8_S2 PP_VDD_MAIN_ACC_BUCK_VIN A2 VIN WLCSP-COMBO VOUT A1 1 4UF B2 ON 20% 6.3V CER-X5R 2 0201 GND A2 B1 ROOM=ACC_BUCK VIN U6110 FAN53741 CSP 49 20 10 C 49 20 10 BI IN I2C0_AP_SDA A1 SDA ROOM=ACC_BUCK B1 SCL CRITICAL I2C0_AP_SCL SW FB B2 C1 CRITICAL L6110 0.47UH-20%-2.52A-0.08OHM 2 ACC_BUCK_SW 1 ACC_BUCK_FB To Hydra PP_ACC_VAR PIGA1608-SM 1 ROOM=ACC_BUCK 2OMIT XW6110 SHORT-20L-0.05MM-SM GND C2 ROOM=ACC_BUCK 1 C6110 100PF 5% 2 16V NP0-C0G 01005 ROOM=ACC_BUCK 1 C6111 0.1UF 20% 2 6.3V X5R-CERM 01005 ROOM=ACC_BUCK 1 C6112 18UF 20% 2 6.3V CER-X5R 0402-0.1MM ROOM=ACC_BUCK 1 C6117 18UF 20% 2 6.3V CER-X5R 0402-0.1MM ROOM=ACC_BUCK 1 19 48 C R6116 10K 5% 1/32W MF 2 01005 ROOM=ACC_BUCK ACC_BUCK_TO_PMU_AMUX OUT 20 B B A SYNC_MASTER=test_mlb SYNC_DATE=10/17/2016 PAGE TITLE I/O: Accessory Buck DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 61 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 46 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 D D USB-PD PP1V8_S2 PP3V0_S2 C6290 1.0UF 20% 2 6.3V X5R 0201-1 ROOM=USB_PD C6291 C PP1V8_VCCD_CCG2 1.0UF 20% 2 6.3V X5R 0201-1 ROOM=USB_PD 1 C6292 1.0UF 20% 2 6.3V X5R 0201-1 NCNC ROOM=USB_PD PP_VBUS1_E75_RVP 1 VDDD E3 48 45 23 1 R6210 499K OUT ROOM=USB_PD 1 R6211 50K 1% 1/32W MF 2 01005 ROOM=USB_PD CCG2_TO_SMC_INT_L C3 D3 NC C2 D2 NC B2 NC A3 A2 PP5V0_USB_RVP_R 1 C6210 22NF 20% 2 6.3V X5R-CERM 01005 R6200 50 23 22 21 10 ROOM=USB_PD BI I2C0_SMC_SDA 1 43.2 50 23 22 21 10 IN I2C0_SMC_SCL I2C0_SMC_SDA_CCG2_R 10 4 BI 10 4 IN AP_BI_CCG2_SWDIO AP_TO_CCG2_SWCLK 2 1% 1/32W MF 01005 E2 D1 GPIO_C3 CRITICAL CC1 GPIO_D3 U6200 CC2 CSP GPIO_C2 RD1 GPIO_D2ROOM=USB_PD GPIO_B2 CG8740AAT XRES I2C_0_SCL I2C_0_SDA B4 A4 B3 CCG2_TO_HYDRA_CC 1 NC OUT 48 C6200 220PF 5% 2 10V C0G-CERM 01005 NC ROOM=USB_PD PMU_TO_CCG2_RESET_L B1 IN 20 SWD_IO SWD_CLK VSS VSS C1 10 4 D4 1% 1/20W MF 2 201 VCONN2 C4 VCONN1 E4 1 VDDIO E1 C VCCD A1 49 48 46 38 22 20 17 14 12 10 50 50 48 45 36 19 B B A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016 PAGE TITLE I/O: USB PD DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 62 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 47 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 D D Hydra I2C Address: 0011010X PP3V0_S2 PP_ACC_VAR 1 1.0UF 0.1UF 20% 2 6.3V X5R 0201-1 ROOM=HYDRA C C6391 20% 2 6.3V X5R-CERM 01005 ROOM=HYDRA 49 47 46 38 22 20 17 14 12 10 50 PP1V8_S2 20 OUT 1 1 6.34K 2 0.01UF 37 37 BI BI 50 BI 50 BI L6300 1 GND_VOID VDD3V0 VDD1V8 C2 D2 90_MIKEYBUS_DATA_P 90_MIKEYBUS_DATA_N 90_USB_BB_DATA_P 90_USB_BB_DATA_N HYDRA_TO_PMU_USB_BRICK_ID_R 15NH-250MA 90_USB_AP_DATA_P C ACC_PWR U6300 ROOM=HYDRA BI 2 10% 6.3V X5R 01005 ROOM=HYDRA 10% 2 6.3V X5R 01005 6 C6395 ROOM=HYDRA 1% 1/32W MF 01005 C6300 1 0.01UF R6300 HYDRA_TO_PMU_USB_BRICK_ID 2 0201 DIG_DP DIG_DN D3 D4 USB1_DP USB1_DN F3 BRICK_ID From Tigris2 CBTL1612A1 P_IN ACC1 ACC1 ACC1 ACC1 ACC1 ACC2 ACC2 ACC2 ACC2 ACC2 WLCSP ROOM=HYDRA CRITICAL 11 IN 11 BI 90_USB_AP_DATA_N OUT 0201 11 IN ROOM=HYDRA 11 OUT 1 GND_VOID 2 6 BI 50 20 11 B OUT 47 OUT IN PP_HYDRA_ACC2 UART0_TX UART0_RX UART_AP_DEBUG_TXD UART_AP_DEBUG_RXD F2 E2 UART1_TX UART1_RX DP1 C3 DN1 C4 90_HYDRA_DP1_CONN_P 90_HYDRA_DP1_CONN_N BI 49 BI 49 GND B1 A1 UART2_TX UART2_RX DP2 A3 DN2 A4 90_HYDRA_DP2_CONN_P 90_HYDRA_DP2_CONN_N BI 49 BI 49 SWD_DOCK_TO_AP_SWCLK SWD_DOCK_BI_AP_SWDIO E1 F1 JTAG_CLK JTAG_DIO CON_DET_L G3 HYDRA_CON_DETECT_L POW_GATE_EN* H3 HYDRA_TO_TIGRIS_VBUS1_VALID_L PMU_HYDRA_TO_AP_FORCE_DFU H2 PMU_TO_AP_HYDRA_ACTIVE_READY HYDRA_TO_PMU_HOST_RESET HYDRA_TO_NUB_DOCK_CONNECT G2 G1 SWITCH_EN E4 HOST_RESET F6 G5 G4 F7 F5 I2C1_SMC_SDA I2C1_SMC_SCL HYDRA_TO_NUB_INT HYDRA_BYPASS CCG2_TO_HYDRA_CC B2 A2 EXT_SW_EN DOCK_CONNECT SDA SCL INT BYPASS CC0 CC1 E3 G7 H1 H6 H7 DVSS C6311 0.47UF D1 C1 NC 12 1 UART_AP_TO_ACCESSORY_TXD UART_ACCESSORY_TO_AP_RXD FORCE_DFU 1 C6312 0.47UF 20% 2 25V CER-X5R 0201 2 25V CER-X5R ROOM=HYDRA ROOM=HYDRA 20% 0201 49 IN OUT IN OUT 49 4 23 B 4 6 20 20 10 BI 1 DVSS1 23 45 47 45 49 USB0_DP USB0_DN NC OUT PP_HYDRA_ACC1 B3 B4 MAKE_BASE=TRUE 6 PP_VBUS1_E75_RVP IN 10 OUT 12 C6330 1.0UF 20% F4 L6301 15NH-250MA G6 A5 B5 C5 D5 E5 A7 B7 C7 D7 E7 90_USB_AP_DATA_L_P 90_USB_AP_DATA_L_N ROOM=HYDRA 6 19 46 A6 B6 C6 D6 E6 C6390 H5 1 H4 50 47 45 36 19 2 6.3V X5R 0201-1 ROOM=HYDRA A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016 PAGE TITLE I/O: Hydra DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 63 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 48 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 DOCK FLEX CONNECTOR ARC Rcpt: 516S00038 Plug: 516S00037 FL6400 <-- This one on MLB 150OHM-25%-200MA-0.7DCR 48 47 46 38 22 20 17 14 12 10 50 PP1V8_S2 2 PP1V8_SAKONNET_CONN 1 01005 C6400 1 ROOM=B2B_DOCK 49 220PF 5% 2 10V C0G-CERM 01005 R6416 46 20 10 IN I2C0_AP_SCL 2 D 0.00 J6400 ROOM=B2B_DOCK I2C0_AP_TO_SAKONNET_SCL_CONN 1 BM28P0.6-44DS-0.35V F-ST-SM 49 CKPLUS_WAIVE=I2C_PULLUP 0% 1/32W MF 01005 C6416 1 50 49 56PF 5% 2 25V NP0-C0G-CERM 01005 ROOM=B2B_DOCK 50 49 49 ROOM=B2B_DOCK 49 R6418 46 20 10 BI I2C0_AP_SDA 2 0.00 I2C0_AP_BI_SAKONNET_SDA_CONN 1 49 49 CKPLUS_WAIVE=I2C_PULLUP 0% 1/32W MF 01005 C6418 1 38 56PF 49 5% 25V 2 NP0-C0G-CERM 01005 ROOM=B2B_DOCK 49 49 ROOM=B2B_DOCK 49 R6419 50 41 38 12 IN I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK 2 49.9 49 I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK_CONN 1 1% 1/32W MF 01005 68PF IN I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK 2 I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK_CONN 1 41 38 12 150OHM-25%-200MA-0.7DCR 2 I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT BI PP1V8_IMU_COMPASS_DOCK_CONN 1 NOSTUFF 01005 1 ROOM=B2B_DOCK C6420 1 68PF 41 5% 2 25V NP0-C0G-CERM 01005 2 49.9 41 23 I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT_CONN 1 1% 1/32W MF 01005 49 C6430 5% 2 10V C0G-CERM 01005 49 41 ROOM=B2B_DOCK C6490 0.1UF 49 1 LOWERMIC1_TO_CODEC_AIN1_CONN_P LOWERMIC1_TO_CODEC_AIN1_CONN_N LOWERMIC1_TO_CODEC_BIAS_FILT_RET PP_CODEC_TO_LOWERMIC1_BIAS_CONN I2C1_AP_BI_MIC1_SDA_CONN I2C1_AP_TO_MIC1_SCL_CONN SOLENOID1_TO_ARC1_VSENSE_NEG SOLENOID1_TO_ARC1_VSENSE_POS C6491 5% 2 25V NP0-C0G-CERM 01005 ROOM=B2B_DOCK 1 0.1UF 10% 25V 2 X5R 0201 68PF ROOM=B2B_DOCK PP_CODEC_TO_LOWERMIC4_BIAS_CONN LOWERMIC4_TO_CODEC_BIAS_FILT_RET LOWERMIC4_TO_CODEC_AIN4_CONN_N LOWERMIC4_TO_CODEC_AIN4_CONN_P PP1V8_IMU_COMPASS_DOCK_CONN I2C1_AOP_BI_COMPASS_SDA_DOCK_CONN I2C1_AOP_TO_COMPASS_SCL_DOCK_CONN COMPASS_TO_AOP_INT_DOCK_CONN PP_VBUS1_E75 C6421 1 220PF NOSTUFF 49 R6421 FL6430 PP1V8_IMU_S2 49 ROOM=B2B_DOCK NOSTUFF 26 25 17 49 49 ROOM=B2B_DOCK C 38 ROOM=B2B_DOCK 1% 1/32W MF 01005 Compass (Dock Flex Location) 49 5% 2 25V NP0-C0G-CERM 01005 R6420 50 41 38 12 49 10% 25V 2 X5R 0201 ROOM=B2B_DOCK C6492 1 0.1UF 10% 25V 2 X5R 0201 ROOM=B2B_DOCK C6493 1 220PF C6494 I2C1_AOP_SCL 2 0.00 I2C1_AOP_TO_COMPASS_SCL_DOCK_CONN 1 NOSTUFF 1 C6471 1 C6431 10% 10V 2 X5R 01005 ROOM=B2B_DOCK 5% 25V 2 COG 01005 1 NOSTUFF 49 48 HYDRA_CON_DETECT_L OUT CKPLUS_WAIVE=I2C_PULLUP 2 C6432 5% 2 25V NP0-C0G-CERM 01005 FL6433 100 COMPASS_TO_AOP_INT_DOCK_CONN 1 PP_HYDRA_ACC1 48 45 49 B C6433 50 820PF 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 47 48 ROOM=B2B_DOCK 90_HYDRA_DP2_CONN_N 90_HYDRA_DP2_CONN_P 48 OUT PP_HYDRA_ACC2_CONN ARC1_TO_SOLENOID1_OUT_NEG ARC1_TO_SOLENOID1_OUT_POS C6495 1 0.1UF 10% 25V 2 X5R 0201 ROOM=B2B_DOCK COIL_TO_SPKRAMP_BOT_VSENSE_POS ROOM=B2B_DOCK 48 C6496 1 0.1UF 10% 25V 2 X5R 0201 ROOM=B2B_DOCK C6497 49 41 49 41 49 C 1 0.1UF 10% 25V 2 X5R 0201 ROOM=B2B_DOCK FL6480 2 1 FL6413 LOWERMIC1_TO_CODEC_AIN1_CONN_P 1 PP_HYDRA_ACC2 1 49 37 OUT LOWERMIC4_TO_CODEC_AIN4_N ROOM=B2B_DOCK 49 5% 2 10V C0G-CERM 01005 ROOM=B2B_DOCK 2 1 NOSTUFF 1 C6482 ROOM=B2B_DOCK 49 IN SPKRAMP_BOT_TO_COIL_OUT_POS C6484 38 PP_CODEC_TO_LOWERMIC4_BIAS 2 01005 ROOM=B2B_DOCK 49 C6413 SPKRAMP_BOT_TO_COIL_OUT_NEG 50 49 IN C6486 1 1 820PF 220PF 10% 10V 2 X5R 01005 5% 2 10V C0G-CERM 01005 ROOM=B2B_DOCK LOWERMIC4_TO_CODEC_AIN4_CONN_N C6485 ROOM=B2B_DOCK 49 C6462 5% 25V 2 NP0-C0G-CERM 01005 ROOM=B2B_DOCK PP_CODEC_TO_LOWERMIC4_BIAS_CONN 49 1 C6464 5% 2 10V C0G-CERM 01005 ROOM=B2B_DOCK R6465 PP_CODEC_TO_LOWERMIC1_BIAS_CONN 49 33 10 IN I2C1_AP_SCL 2 C6454 0.00 5% 2 10V C0G-CERM 01005 I2C1_AP_TO_MIC1_SCL_CONN 1 49 CKPLUS_WAIVE=I2C_PULLUP 0% 1/32W MF 01005 220PF 1 SYNC_MASTER=test_mlb C6465 I/O: B2B Dock 5% 2 25V NP0-C0G-CERM 01005 DRAWING NUMBER Apple Inc. ROOM=B2B_DOCK R6466 150OHM-25%-200MA-0.7DCR LOWERMIC4_TO_CODEC_AIN4_CONN_P 1 49 33 10 BI I2C1_AP_SDA 2 C6460 0.00 5% 2 25V NP0-C0G-CERM 01005 ROOM=B2B_DOCK ROOM=B2B_DOCK I2C1_AP_BI_MIC1_SDA_CONN 1 0% 1/32W MF 01005 56PF SYNC_DATE=10/13/2016 PAGE TITLE 56PF ROOM=B2B_DOCK ROOM=B2B_DOCK 1 ROOM=B2B_DOCK 220PF ROOM=B2B_DOCK FL6460 5% 2 10V C0G-CERM 01005 ROOM=B2B_DOCK 1 49 5% 2 25V NP0-C0G-CERM 01005 ROOM=B2B_DOCK B 220PF 56PF FL6464 56PF 1 C6483 150OHM-25%-200MA-0.7DCR C6452 1 1 10% 10V X5R 2 01005 220PF 1 1 820PF PP_HYDRA_ACC2_CONN ROOM=B2B_DOCK 150OHM-25%-200MA-0.7DCR ROOM=B2B_DOCK COIL_TO_SPKRAMP_BOT_VSENSE_NEG_CONN C6480 5% 2 10V C0G-CERM 01005 ROOM=B2B_DOCK 1 C6450 LOWERMIC1_TO_CODEC_AIN1_CONN_N 1 01005 49 220PF C6411 1 01005 ROOM=B2B_DOCK FL6454 1 ROOM=B2B_DOCK 2 2 5% 2 25V NP0-C0G-CERM 01005 01005 01005 COIL_TO_SPKRAMP_BOT_VSENSE_NEG FL6462 1 2 OUT C6410 22-OHM-25%-1800MA 150OHM-25%-200MA-0.7DCR 2 50 5% 10V 2 C0G-CERM 01005 56PF 2 49 150OHM-25%-200MA-0.7DCR 1 FL6452 COIL_TO_SPKRAMP_BOT_VSENSE_POS_CONN NOSTUFF 220PF ROOM=B2B_DOCK ROOM=B2B_DOCK 1 ROOM=B2B_DOCK 5% 2 10V C0G-CERM 01005 01005 2 10% 10V 2 X5R 01005 220PF FL6450 REVISION 9.0.0 49 CKPLUS_WAIVE=I2C_PULLUP 1 051-02221 C6466 56PF 5% 2 25V NP0-C0G-CERM 01005 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 64 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT ROOM=B2B_DOCK III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 49 OF 51 IV ALL RIGHTS RESERVED 8 48 PP_HYDRA_ACC1_CONN 49 MIKEYBUS_REFERENCE 37 HYDRA_CON_DETECT_CONN_L 49 PP1V8_SAKONNET_CONN 49 I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK_CONN 49 I2C0_AP_BI_SAKONNET_SDA_CONN 49 I2C0_AP_TO_SAKONNET_SCL_CONN 49 I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK_CONN 49 I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT_CONN 49 01005 50 49 ROOM=B2B_DOCK 150OHM-25%-200MA-0.7DCR LOWERMIC4_TO_CODEC_AIN4_P 1 PP_HYDRA_ACC1_CONN LOWER MIC1 + LOWER MIC4 OUT 14 ROOM=B2B_DOCK ROOM=B2B_DOCK 37 13 5% 2 16V NP0-C0G 01005 0201 PP_CODEC_TO_LOWERMIC1_BIAS 12 27PF 01005 48 38 11 01005 2 NOSTUFF ROOM=B2B_DOCK A C6473 HYDRA_CON_DETECT_CONN_L 1 1 5% 2 10V C0G-CERM 01005 LOWERMIC1_TO_CODEC_AIN1_N 10 ROOM=B2B_DOCK 1 220PF OUT 9 48 10-OHM-1.1A 1 ROOM=B2B_DOCK 37 8 FL6482 FL6411 ROOM=B2B_DOCK 01005 OUT 7 90_HYDRA_DP1_CONN_P 90_HYDRA_DP1_CONN_N 150OHM-25%-200MA-0.7DCR ROOM=B2B_DOCK 150OHM-25%-200MA-0.7DCR 37 5% 10V 2 C0G-CERM 01005 ROOM=B2B_DOCK 5% 1/32W MF 01005 56PF NOSTUFF LOWERMIC1_TO_CODEC_AIN1_P 6 5% 25V 2 COG 01005 R6410 1 2 5 ROOM=B2B_DOCK Hydra I2C1_AOP_BI_COMPASS_SDA_DOCK_CONN ROOM=B2B_DOCK COMPASS_TO_AOP_INT 1 220PF 5% 10V 2 C0G-CERM 01005 ROOM=B2B_DOCK ROOM=B2B_DOCK 0% 1/32W MF 01005 OUT C6470 1 220PF 820PF R6432 2 4 1 SOUTH SPEAKER 41 49 C6472 49 CKPLUS_WAIVE=I2C_PULLUP 5% 2 25V NP0-C0G-CERM 01005 NOSTUFF BI 2 3 ROOM=B2B_DOCK ARC1_TO_SOLENOID1_OUT_POS ARC1_TO_SOLENOID1_OUT_NEG 56PF ROOM=B2B_DOCK 0.00 1 D 150OHM-25%-200MA-0.7DCR 0% 1/32W MF 01005 I2C1_AOP_SDA 46 220PF R6431 IN 45 SPKRAMP_BOT_TO_COIL_OUT_POS COIL_TO_SPKRAMP_BOT_VSENSE_POS_CONN COIL_TO_SPKRAMP_BOT_VSENSE_NEG_CONN 49 C6419 1 ROOM=B2B_DOCK 49.9 49 SPKRAMP_BOT_TO_COIL_OUT_NEG 7 6 5 4 3 2 1 SIZE D A 8 7 UART_AP_TO_GNSS_TXD 11 UART_AP_TO_GNSS_RTS_L 11 UART_GNSS_TO_AP_CTS_L 11 UART_GNSS_TO_AP_RXD 11 AP_TO_GNSS_WAKE 20 PMU_TO_GNSS_EN 11 AP_TO_BB_TIME_MARK 7 90_PCIE_AP_TO_BB_REFCLK_N 11 D 7 90_PCIE_AP_TO_BB_REFCLK_P 7 90_PCIE_BB_TO_AP_RXD_P 7 90_PCIE_BB_TO_AP_RXD_N 7 90_PCIE_AP_TO_BB_TXD_P 90_PCIE_AP_TO_BB_TXD_N 7 90_PCIE_WLAN_TO_AP_RXD_P 7 7 90_PCIE_WLAN_TO_AP_RXD_N 7 90_PCIE_AP_TO_WLAN_REFCLK_N 90_PCIE_AP_TO_WLAN_REFCLK_P 7 90_PCIE_AP_TO_WLAN_TXD_N 7 7 90_PCIE_AP_TO_WLAN_TXD_P PMU_TO_IKTARA_EN_EXT_1P8V 10 IKTARA_TO_SMC_INT 10 I2C0_SMC_SCL 10 I2C0_SMC_SDA 31 BB_TO_STROBE_DRIVER_GSM_BURST_IND 20 47 23 22 21 47 23 22 21 36 C 41 38 49 41 41 49 41 B 43 42 41 34 31 37 PDM_CODEC_TO_SPKRAMP_TOP_CLK 37 PDM_CODEC_TO_SPKRAMP_TOP_DATA 7 PCIE_AP_TO_BB_RESET_L 10 I2S_AP_TO_SPKRAMP_TOP_MCLK 11 AP_TO_SPKRAMP_TOP_RESET_L 11 SPKRAMP_TOP_TO_AP_INT_L 10 I2C2_AP_SDA 10 I2C2_AP_SCL 19 PP1V8_AUDIO_VA_S2 PP_GPU_LVCC 4 PP_CPU_PCORE_LVCC 4 11 AP_TO_BB_IPC_GPIO1 11 AP_TO_BB_RESET_L HALL3_TO_AOP_IRQ_L 12 10 5 BOARD_ID3 7 PCIE_WLAN_BI_AP_CLKREQ_L 7 PCIE_AP_TO_WLAN_RESET_L 38 12 I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK 38 12 I2S_CODEC_ASP1_TO_AOP_AMPS_DIN 38 12 I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK 20 PMU_TO_IKTARA_RESET_L 10 I2S_BB_TO_AP_DIN 10 I2S_BB_TO_AP_LRCLK 10 I2S_BB_TO_AP_BCLK 10 I2S_AP_TO_BB_DOUT 11 BB_TO_AP_RESET_DETECT_L 11 AP_TO_BBPMU_RADIO_ON_L 11 AP_TO_WLAN_DEVICE_WAKE 41 12 SPKRAMP_BOT_ARC_TO_AOP_INT_L 41 12 AOP_TO_SPKRAMP_BOT_ARC_RESET_L 12 SWD_AOP_BI_BB_SWDIO 49 41 25 12 4 I2C1_AOP_SDA 49 41 25 12 4 I2C1_AOP_SCL 27 23 21 19 18 PP_VDD_MAIN 50 46 45 UART_AP_TO_BT_RTS_L 11 UART_BT_TO_AP_CTS_L 11 UART_AP_TO_BT_TXD 11 UART_BT_TO_AP_RXD 19 PP_VDD_BOOST 11 UART_AP_TO_WLAN_TXD 11 UART_AP_TO_WLAN_RTS_L 11 UART_WLAN_TO_AP_RXD 11 UART_WLAN_TO_AP_CTS_L 10 PP1V8_S2 49 11 38 34 27 21 A 48 47 46 38 22 20 17 14 12 50 6 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 NC S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 NC S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 NC S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S79 S80 S81 S82 S83 S84 S85 S86 IOS1 IOS2 IOS3 IOS4 IOS5 IOS6 IOS7 IOS8 IOS9 IOS10 IOS11 IOS12 IOS13 IOS14 IOS15 IOS16 IOS17 IOS18 IOS19 IOS20 IOS21 IOS22 IOS23 IOS24 IOS25 IOS26 IOS27 IOS28 IOS29 IOS30 IOS31 IOS32 IOS33 IOS34 IOS35 IOS36 IOS37 IOS38 IOS39 IOS40 IOS41 IOS42 IOS43 IOS44 IOS45 IOS46 IOS47 IOS48 IOS49 IOS50 IOS51 IOS52 IOS53 IOS54 IOS55 IOS56 IOS57 IOS58 IOS59 IOS60 IOS61 IOS62 IOS63 IOS64 IOS65 IOS66 IOS67 IOS68 IOS69 IOS70 IOS71 IOS72 IOS73 IOS74 IOS75 IOS76 IOS77 IOS78 IOS79 IOS80 IOS81 IOS82 IOS83 IOS84 IOS85 IOS86 J_INT_BOT INTERPOSER-BOT-D22 SMT-PAD SYM 3 OF 3 SIGNAL 5 IOS87 IOS88 IOS89 IOS90 IOS91 IOS92 IOS93 IOS94 IOS95 IOS96 IOS97 IOS98 IOS99 IOS100 IOS101 IOS102 IOS103 IOS104 IOS105 IOS106 IOS107 IOS108 IOS109 IOS110 IOS111 IOS112 IOS113 IOS114 IOS115 IOS116 IOS117 IOS118 IOS119 IOS120 IOS121 IOS122 IOS123 IOS124 IOS125 IOS126 IOS127 IOS128 IOS129 IOS130 IOS131 IOS132 IOS133 IOS134 IOS135 IOS136 IOS137 IOS138 IOS139 IOS140 IOS141 IOS142 IOS143 IOS144 IOS145 IOS146 IOS147 IOS148 IOS149 IOS150 IOS151 IOS152 IOS153 IOS154 IOS155 IOS156 IOS157 IOS158 IOS159 IOS160 IOS161 IOS162 IOS163 IOS164 IOS165 IOS166 IOS167 IOS168 IOS169 IOS170 IOS171 IOS172 S87 S88 S89 S90 S91 S92 S93 S94 S95 S96 S97 S98 S99 S100 S101 S102 S103 S104 S105 S106 S107 S108 S109 S110 S111 S112 S113 S114 S115 S116 S117 S118 S119 S120 S121 S122 S123 S124 S125 S126 S127 S128 S129 S130 S131 S132 S133 S134 S135 S136 S137 S138 S139 S140 S141 S142 S143 S144 S145 S146 S147 S148 S149 S150 S151 S152 S153 S154 S155 S156 S157 S158 S159 S160 S161 S162 S163 S164 S165 S166 S167 S168 S169 S170 S171 S172 4 PP1V8_S2 PP_VDD_MAIN BB_TO_PMU_PCIE_HOST_WAKE_L PMU_TO_BBPMU_RESET_L PMU_AMUX_AY AOP_TO_WLAN_CONTEXT_B UART_BB_TO_AOP_RXD UART_AOP_TO_BB_TXD AOP_TO_WLAN_CONTEXT_A BT_TO_PMU_HOST_WAKE PMU_TO_BT_REG_ON PMU_TO_WLAN_CLK32K WLAN_TO_PMU_HOST_WAKE PMU_TO_WLAN_REG_ON PMU_AMUX_BY CODEC_TO_SPKRAMP_BOT_ARC_MCLK PMU_TO_BB_USB_VBUS_DETECT PMU_HYDRA_TO_AP_FORCE_DFU AP_TO_BT_WAKE WLAN_TO_AP_TIME_SYNC RADIO_PA_NTC AP_TO_MANY_BSYNC TOUCH_TO_AMUX_PP1V8 PP3V5_RACER PP1V1_RACER PP5V25_TOUCH_VDDH RACER_TO_ACORN_ORB_SCAN PP1V8_TOUCH_RACER_S2 I2C3_AP_SCL I2C3_AP_SDA TOUCH_TO_ACORN_PP5V25_EN PN6V7_RACER PMU_TO_TOUCH_CLK32K_RESET_L PP10V0_RACER AP_TO_RACER_RESET_L RACER_TO_AOP_INT_L SWD_AOP_TO_MANY_SWCLK SWD_AOP_BI_RACER_SWDIO UART_AOP_TO_RACER_TXD UART_RACER_TO_AOP_RXD HALL2_TO_AOP_IRQ_L AP_TO_RACER_REF_CLK SPI_AP_TO_RACER_CS_L SPI_RACER_TO_AP_MISO SPI_AP_TO_RACER_MOSI SPI_AP_TO_RACER_SCLK PP_BATT_VCC PP3V0_S2 90_USB_BB_DATA_P 90_USB_BB_DATA_N PP_VBUS2_IKTARA 2 1 10 12 14 17 20 22 38 46 47 48 49 50 18 19 21 23 27 31 34 41 42 43 45 46 50 20 20 D 20 12 12 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 G41 G42 G43 G44 G45 G46 G47 G48 G49 G50 G51 G52 G53 G54 G55 G56 G57 G58 G59 G60 G61 G62 12 12 20 20 20 20 20 20 38 41 20 11 20 48 11 11 20 8 12 20 21 28 20 42 42 42 42 17 42 10 42 10 42 42 42 20 42 11 12 4 12 16 12 12 12 12 10 10 10 10 10 22 23 19 36 45 47 48 48 48 23 IKTARA_COIL2 25 IKTARA_COIL1 25 AP_TO_BB_COREDUMP PCIE_BB_BI_AP_CLKREQ_L SPKRAMP_TOP_TO_COIL_OUT_POS SPKRAMP_TOP_TO_COIL_OUT_NEG COIL_TO_SPKRAMP_TOP_VSENSE_POS COIL_TO_SPKRAMP_TOP_VSENSE_NEG COIL_TO_SPKRAMP_BOT_VSENSE_POS COIL_TO_SPKRAMP_BOT_VSENSE_NEG SPKRAMP_BOT_TO_COIL_OUT_POS SPKRAMP_BOT_TO_COIL_OUT_NEG AP_TO_NFC_DEV_WAKE UART_NFC_TO_AP_CTS_L UART_AP_TO_NFC_TXD UART_NFC_TO_AP_RXD UART_AP_TO_NFC_RTS_L AP_TO_NFC_FW_DWLD_REQ NFC_TO_PMU_HOST_WAKE PMU_TO_NFC_EN 3 11 7 36 J_INT_BOT IOG1 IOG2 IOG3 IOG4 IOG5 IOG6 IOG7 IOG8 IOG9 IOG10 IOG11 IOG12 IOG13 IOG14 IOG15 IOG16 IOG17 IOG18 IOG19 IOG20 IOG21 IOG22 IOG23 IOG24 IOG25 IOG26 IOG27 IOG28 IOG29 IOG30 IOG31 IOG32 IOG33 IOG34 IOG35 IOG36 IOG37 IOG38 IOG39 IOG40 IOG41 IOG42 IOG43 IOG44 IOG45 IOG46 IOG47 IOG48 IOG49 IOG50 IOG51 IOG52 IOG53 IOG54 IOG55 IOG56 IOG57 IOG58 IOG59 IOG60 IOG61 IOG62 INTERPOSER-BOT-D22 SMT-PAD SYM 1 OF 3 GND IOG63 IOG64 IOG65 IOG66 IOG67 IOG68 IOG69 IOG70 IOG71 IOG72 IOG73 IOG74 IOG75 IOG76 IOG77 IOG78 IOG79 IOG80 IOG81 IOG82 IOG83 IOG84 IOG85 IOG86 IOG87 IOG88 IOG89 IOG90 IOG91 IOG92 IOG93 IOG94 IOG95 IOG96 IOG97 IOG98 IOG99 IOG100 IOG101 IOG102 IOG103 IOG104 IOG105 IOG106 IOG107 IOG108 IOG109 IOG110 IOG111 IOG112 IOG113 IOG114 IOG115 IOG116 IOG117 IOG118 IOG119 IOG120 IOG121 IOG122 IOG123 IOG124 G63 G64 G65 G66 G67 G68 G69 G70 G71 G72 G73 G74 G75 G76 G77 G78 G79 G80 G81 G82 G83 G84 G85 G86 G87 G88 G89 G90 G91 G92 G93 G94 G95 G96 G97 G98 G99 G100 G101 G102 G103 G104 G105 G106 G107 G108 G109 G110 G111 G112 G113 G114 G115 G116 G117 G118 G119 G120 G121 G122 G123 G124 G125 G126 G127 G128 G129 G130 G131 G132 G133 G134 G135 G136 G137 G138 G139 G140 G141 G142 G143 G144 G145 G146 G147 G148 G149 G150 G151 G152 G153 G154 G155 G156 G157 G158 G159 G160 G161 G162 G163 G164 G165 G166 G167 G168 G169 G170 G171 G172 G173 G174 G175 G176 G177 G178 G179 G180 G181 G182 G183 G184 G185 G186 IOG125 IOG126 IOG127 IOG128 IOG129 IOG130 IOG131 IOG132 IOG133 IOG134 IOG135 IOG136 IOG137 IOG138 IOG139 IOG140 IOG141 IOG142 IOG143 IOG144 IOG145 IOG146 IOG147 IOG148 IOG149 IOG150 IOG151 IOG152 IOG153 IOG154 IOG155 IOG156 IOG157 IOG158 IOG159 IOG160 IOG161 IOG162 IOG163 IOG164 IOG165 IOG166 IOG167 IOG168 IOG169 IOG170 IOG171 IOG172 IOG173 IOG174 IOG175 IOG176 IOG177 IOG178 IOG179 IOG180 IOG181 IOG182 IOG183 IOG184 IOG185 IOG186 J_INT_BOT INTERPOSER-BOT-D22 SMT-PAD SYM 2 OF 3 GND IOG187 IOG188 IOG189 IOG190 IOG191 IOG192 IOG193 IOG194 IOG195 IOG196 IOG197 IOG198 IOG199 IOG200 IOG201 IOG202 IOG203 IOG204 IOG205 IOG206 IOG207 IOG208 IOG209 IOG210 IOG211 IOG212 IOG213 IOG214 IOG215 IOG216 IOG217 IOG218 IOG219 IOG220 IOG221 IOG222 IOG223 IOG224 IOG225 IOG226 IOG227 IOG228 IOG229 IOG230 IOG231 IOG232 IOG233 IOG234 IOG235 IOG236 IOG237 IOG238 IOG239 IOG240 IOG241 IOG242 IOG243 IOG244 IOG245 IOG246 IOG247 IOG248 G187 G188 G189 G190 G191 G192 G193 G194 G195 G196 G197 G198 G199 G200 G201 G202 G203 G204 G205 G206 G207 G208 G209 G210 G211 G212 G213 G214 G215 G216 G217 G218 G219 G220 G221 G222 G223 G224 G225 G226 G227 G228 G229 G230 G231 G232 G233 G234 G235 G236 G237 G238 G239 G240 G241 G242 G243 G244 G245 G246 G247 G248 C B 36 36 36 49 49 49 49 11 11 11 11 11 11 20 20 SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016 PAGE TITLE NC I/O: Interposer (Bottom) DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 65 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 50 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 D D C C Radios on MLB Bottom B B A SYNC_DATE=06/04/2015 PAGE TITLE RADIOS DRAWING NUMBER Apple Inc. 051-02221 REVISION 9.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 80 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 51 OF 51 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A CR-1 : @MLB_BOT_LIB.MLB_BOT(SCH_1):PAGE1 8 7 6 5 4 3 2 1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 1 REV ECN CK APPD DESCRIPTION OF REVISION 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. 7 0008448938 ENGINEERING RELEASED 2017-04-11 X893 MLB Bottom: EVT D D LAST_MODIFICATION=Tue Apr 11 16:10:11 2017 PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 C B CSA 1 2 4 6 7 34 49 50 55 58 66 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 4 5 1 75 CONTENTS TABLE OF CONTENTS SYSTEM:BOM Tables SYSTEM: Mechanical Components BOOTSTRAPPING SYSTEM: Testpoints (Bottom) SYSTEM POWER: Iktara AUDIO: Speaker Amp Bottom AUDIO: Speaker Amp Top HALL EFFECT CG: B2B Luna & Touch I/O: Interposer (Top) RADIOS RADIO_MLB BASEBAND BASEBAND MEMORY/DEBUG BASEBAND POWER BASEBAND PMIC TRANSCEIVERS ET MODULATOR TDD TRANSMIT FDD TRANSMIT PRIMARY RECEIVE LOWER ANTENNA & COUPLERS DIVERSITY RECEIVE ASM'S DIVERSITY RECEIVE LNA'S UPPER ANTENNA FEEDS GNSS TEST POINTS & SIM RF CONNECTORS AND MC SymbolPorts Guinness WiFiANTFeeds page1 NFC SYNC DATE 07/29/2016 03/08/2017 12/01/2016 11/03/2016 01/17/2017 04/04/2017 04/04/2017 04/04/2017 04/04/2017 04/04/2017 04/04/2017 07/29/2016 test_mlb mlb_bot mlb_bot mlb_bot mlb_bot mlb_bot mlb_bot PAGE CSA CONTENTS SYNC DATE C WIFI 01/30/2014 B Sub Designs A TABLE OF CONTENTS SYNC_DATE=07/29/2016 TABLE_HIERARCHY_CONFIG_HEAD SOURCE PROJECT BOM:639-03229 MCO:056-04080 SUB-DESIGN NAME VERSION QTY DESCRIPTION RADIO_MLB 0.115.0 1 SCH,MLB_BOT,X893 D22 NFC_MLB 0.22.0 1 PCB,MLB_BOT,X893 S SCH,MLB,BOT,X893 2017_04_05_18:48:43 DRAWING NUMBER S 2017_03_22_22:11:23 Apple Inc. TABLE_HIERARCHY_CONFIG_ITEM D22 WIFI_MLB 0.20.0 REFERENCE DESIGNATOR(S) CRITICAL SCH NO PCB NO S 2017_04_04_09:54:33 BOM OPTION THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: COMMON 051-02247 REVISION 7.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH evt-1 PAGE 1 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE TABLE_5_ITEM 820-00869 SYNC_DATE/TIME TABLE_HIERARCHY_CONFIG_ITEM TABLE_5_ITEM 051-02247 DRAWING TITLE TABLE_HIERARCHY_CONFIG_ITEM D221 TABLE_5_HEAD PART# HARD/ SOFT COMMON II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 1 OF 34 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 EEEE Codes QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION NO COMMON 3 TABLE_5_ITEM 825-7691 1 EEEE_HM07 EEEE FOR (MLB_BOT, 639-03229) 2 1 Soft-Term Cap Sub BOMs Iktara TABLE_5_HEAD PART# 4 TABLE_5_HEAD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION NO COMMON CRITICAL COMMON TABLE_5_HEAD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION CRITICAL COMMON CRITICAL BOM OPTION TABLE_5_ITEM 132S00021 8 CAP,CER,0.082UF,10%,50V,X7R,0402 C3452,C3453,C3454,C3456,C3461,C3462,C3463,C3464 132S0423 2 CAP,CER,0.022UF,50V,X7R,10%,0402 C3451,C3465 TABLE_5_ITEM 685-00159 1 SUBBOM_CAP SUBBOM,MLB,BOT,CAP,TYPICAL,X893 TABLE_5_ITEM Touch/Luna B2B TABLE_5_ITEM D Global Capacitors 132S0423 ALTERNATE FOR PART NUMBER BOM OPTION REF DES COMMENTS: C3455,C3466 CAP,CER,0.022UF,50V,X7R,10%,0402 CRITICAL NOSTUFF TABLE_5_HEAD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) D TABLE_5_ITEM TABLE_ALT_HEAD PART NUMBER 2 TABLE_CRITICAL_HEAD CRITICAL PART# COMMENT 138S00149 0402-3T,10.5uF@1V 138S00159 1 CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA C5890 CRITICAL SOFT_CAP 138S0831 1 CAP,TYPICAL,2.2UF,6.3V,0201,MURATA C5890 CRITICAL TYPICAL_CAP TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES COMMENTS: 685-00185 685-00184 BOM_TABLE_ALTS SUBBOM_DS SUBBOM,MLB,BOT,DIODES,ONSEMI,X893 TABLE_5_ITEM TABLE_CRITICAL_ITEM TABLE_ALT_ITEM 138S00148 138S00149 BOM_TABLE_ALTS ALL 0402-3T,10.5uF@1V, Kyocera 138S00150 138S00149 BOM_TABLE_ALTS ALL 0402-3T,10.5uF@1V, SEMCO TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES COMMENTS: 685-00160 685-00159 BOM_TABLE_ALTS SUBBOM_CAP SUBBOM,MLB,BOT,CAP,SOFT,X893 TABLE_5_HEAD PART# TABLE_ALT_ITEM 138S00151 138S00149 BOM_TABLE_ALTS ALL QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_ALT_ITEM 0402-3T,10.5uF@1V, TY TABLE_5_ITEM TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES COMMENTS: 685-00184 1 SUBBOM,MLB,BOT,DIODES,DIODES,X893 SUBBOM_DS CRITICAL COMMON 371S00133 4 DIODES,SHOTTKY DIODE,30V,2A,0603 D3400,D3401,D3402,D3403 CRITICAL DIODES_DS 371S00132 4 ONSEMI,SHOTTKY DIODE,30V,2A,0603 D3400,D3401,D3402,D3403 CRITICAL ONSEMI_DS TABLE_CRITICAL_HEAD CRITICAL PART# COMMENT 138S00144 0402,16uF@1V CRITICAL PART# COMMENT 138S00139 0201,3uF@1V CRITICAL PART# COMMENT 138S00146 0402,5.1uF@3V CRITICAL PART# COMMENT 138S00141 0201,1.1uF@3V CRITICAL PART# COMMENT 152S00557 IND,MLD,0.47UH,20%,2.5A,80MO,1608 TABLE_5_ITEM TABLE_CRITICAL_ITEM TABLE_ALT_ITEM 138S00143 138S00144 BOM_TABLE_ALTS ALL 0402,16uF@1V, Kyocera 138S00163 138S00144 BOM_TABLE_ALTS ALL 0402,16uF@1V, Taiyo PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES COMMENTS: TABLE_5_ITEM TABLE_ALT_ITEM TABLE_ALT_HEAD TABLE_CRITICAL_HEAD TABLE_CRITICAL_ITEM TABLE_ALT_ITEM 138S00138 138S00139 BOM_TABLE_ALTS ALL 0201,3uF@1V, Kyocera 138S00164 138S00139 BOM_TABLE_ALTS ALL 0201,3uF@1V, Taiyo PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_ITEM TABLE_ALT_HEAD TABLE_CRITICAL_HEAD TABLE_CRITICAL_ITEM TABLE_ALT_ITEM 138S00145 138S00146 BOM_TABLE_ALTS ALL 0402,5.1uF@3V, Kyocera 138S00165 138S00146 BOM_TABLE_ALTS ALL 0402,5.1uF@3V, Taiyo PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_ITEM C TABLE_ALT_HEAD C TABLE_CRITICAL_HEAD TABLE_CRITICAL_ITEM TABLE_ALT_ITEM 138S00140 138S00141 BOM_TABLE_ALTS ALL 0201,1.1uF@3V, Kyocera 138S00142 138S00141 BOM_TABLE_ALTS ALL 0201,1.1uF@3V, SEMCO 138S00166 138S00141 BOM_TABLE_ALTS ALL 0201,1.1uF@3V, Taiyo TABLE_ALT_ITEM TABLE_ALT_ITEM Global Ferrites TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES COMMENTS: 152S00558 152S00557 BOM_TABLE_ALTS ALL IND,MLD,0.47UH,20%,2.5A,80MO,1608 155S00194 155S0610 BOM_TABLE_ALTS ALL FERR BD,150 OHM,25%,200MA,0.7 DCR,01005 155S00200 155S0610 BOM_TABLE_ALTS ALL FERR BD,150 OHM,25%,200MA,0.7 DCR,01005 TABLE_CRITICAL_HEAD TABLE_ALT_ITEM TABLE_CRITICAL_ITEM TABLE_ALT_ITEM TABLE_CRITICAL_ITEM 155S0610 FERR BD,150 OHM,25%,200MA,0.7 DCR,01005 TABLE_ALT_ITEM Global R/C Alternates TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION 138S0652 BOM_TABLE_ALTS REF DES COMMENTS: TABLE_CRITICAL_HEAD CRITICAL PART# COMMENT TABLE_ALT_ITEM B 138S0648 ALL TABLE_CRITICAL_ITEM 138S0652 CAP,X5R,4.7UF,6.3V,0.65MM,0402,TAIYO TABLE_ALT_ITEM 138S00024 138S0986 BOM_TABLE_ALTS ALL CAP,CER,3-TERM,7.5UF,20%,4V,0402,TAIYO/TDK TABLE_CRITICAL_ITEM 138S0986 CAP,CER,3-TERM,7.5UF,20%,4V,0402,TAIYO/TDK 138S0739 CAP,CER,1UF,20%,10V,X5R,0201,MURATA 138S0706 CAP,CER,X5R,0.22UF,20%,6.3V,20% 132S0400 CAP,CER,X5R,0.22UF,20%,6.3V,01005 138S0831 CAP,CER,X5R,2.2UF,20%,6.3V,0201 TABLE_ALT_ITEM 138S0706 138S0739 BOM_TABLE_ALTS ALL CAP,CER,1UF,20%,10V,X5R,0201,MURATA 138S0945 138S0739 BOM_TABLE_ALTS ALL CAP,CER,1UF,20%,10V,X5R,0201,KYOCERA 138S0739 138S0706 BOM_TABLE_ALTS ALL CAP,CER,X5R,0.22UF,20%,6.3V,20% 132S0436 132S0400 BOM_TABLE_ALTS ALL CAP,CER,X5R,0.22UF,20%,6.3V,01005 138S00049 138S0831 BOM_TABLE_ALTS ALL CAP,CER,X5R,2.2UF,20%,6.3V,0201 B CAP,X5R,4.7UF,6.3V,0.65MM,0402,TAIYO TABLE_CRITICAL_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_CRITICAL_ITEM TABLE_ALT_ITEM TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_ALT_ITEM Global Inductors TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES COMMENTS: 152S00653 152S00651 BOM_TABLE_ALTS ALL IND,1.2UH,3A,2016,0.65Z 152S00654 152S00652 BOM_TABLE_ALTS ALL IND,1.2UH,3A,2016,0.8Z TABLE_CRITICAL_HEAD CRITICAL PART# COMMENT 152S00651 IND,1.2UH,3A,2016,0.65Z 152S00652 IND,1.2UH,3A,2016,0.8Z TABLE_CRITICAL_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_CRITICAL_ITEM Multi-Vendor Criticals TABLE_CRITICAL_HEAD CRITICAL PART# A COMMENT TABLE_CRITICAL_HEAD CRITICAL PART# COMMENT 132S00008 CAP,CER,0.1UF,10%,50V,X7R,0402 TABLE_CRITICAL_ITEM 138S0979 CAP,CER,X5R,10UF,20%,10V,0402,H=0.65MM TABLE_CRITICAL_ITEM SYNC_MASTER= TABLE_CRITICAL_ITEM 138S0683 CAP,CER,X5R,1UF,10%,25V,0402 131S0804 CAP,CER,27PF,5%,C0G,25V,0201 131S0307 CAP,CER,NP0/C0G,100PF,5%,16V,01005 TABLE_CRITICAL_ITEM 132S0663 CAP,CER,X5R,1UF,10%,25V,0402 132S0288 CAP,CER,X5R,0.1UF,10%,16V,0201 SYNC_DATE=03/08/2017 TABLE_CRITICAL_ITEM PAGE TITLE SYSTEM:BOM Tables TABLE_CRITICAL_ITEM DRAWING NUMBER TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM 131S00053 CAP,CER,C0G,220PF,5%,10V,01005 TABLE_CRITICAL_ITEM 132S0275 117S0055 CAP,CER,X5R,470PF,10%,10V,01005 CAP,CER,X5R,0.01UF,10%,6.3V,01005 REVISION RES,MF,1/20W,2M OHM,5,0201,SMD TABLE_CRITICAL_ITEM 132S0245 Apple Inc. TABLE_CRITICAL_ITEM 051-02247 7.0.0 TABLE_CRITICAL_ITEM 107S0257 THERMISTOR,NTC,10K OHM,1%,B=3435,01005 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 2 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 2 OF 34 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 FIDUCIALS D D FD0401 FID 0P5SQ-CROSS-NSP 1 ROOM=ASSEMBLY FD0402 FID 0P5SQ-CROSS-NSP 1 ROOM=ASSEMBLY FD0403 FID 0P5SQ-CROSS-NSP 1 ROOM=ASSEMBLY FD0404 FID 0P5SQ-CROSS-NSP 1 ROOM=ASSEMBLY FD0405 FID 0P5SQ-CROSS-NSP 1 ROOM=ASSEMBLY FD0406 FID 0P5SQ-CROSS-NSP 1 ROOM=ASSEMBLY C C FD0410 FID 0P5SQ-SMP3SQ-NSP 1 ROOM=ASSEMBLY FD0411 FID 0P5SQ-SMP3SQ-NSP 1 ROOM=ASSEMBLY FD0412 FID 0P5SQ-SMP3SQ-NSP 1 ROOM=ASSEMBLY FD0413 FID 0P5SQ-SMP3SQ-NSP 1 ROOM=ASSEMBLY FD0414 FID 0P5SQ-SMP3SQ-NSP 1 ROOM=ASSEMBLY FD0415 FID 0P5SQ-SMP3SQ-NSP 1 ROOM=ASSEMBLY B B CRITICAL SB0400 STDOFF-SUBMERGED-X891 1 ROOM=ASSEMBLY A SYNC_DATE=12/01/2016 PAGE TITLE SYSTEM: Mechanical Components DRAWING NUMBER Apple Inc. 051-02247 REVISION 7.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 4 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 3 OF 34 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 D D BOOTSTRAPPING:BOARD ID[3] PP1V8_S2 6 9 11 12 C C R0630 11 OUT BOARD_ID3 CKPLUS_WAIVE=SINGLE_NODENET 1 1.00K 2 5% 1/32W MF 01005 ROOM=SOC B B D221 Selected (BOARD_ID3) -> A A SYNC_MASTER SYNC_DATE=11/03/2016 PAGE TITLE BOOTSTRAPPING DRAWING NUMBER Apple Inc. 051-02247 REVISION 7.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 6 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 4 OF 34 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D 8 7 6 5 4 Test Points 12 11 8 7 6 TP0700 1 PP_VDD_MAIN TP-P55 TP0750 A ROOM=TEST TP0701 1 D A 11 10 TP0780 TP-P55 ROOM=TEST ROOM=TEST TP0751 A GND TP-P55 A TP-P55 ROOM=TEST ROOM=TEST A 11 10 ROOM=TEST ROOM=TEST TP0515 VBATT 1 A 6 TP0522 1 A 11 10 TP-P55 PP1V1_RACER ROOM=TEST A TP0709 1 11 10 TOUCH_TO_ACORN_PP5V25_EN A TP-P55 TP-P55 TP-P55 ROOM=TEST ROOM=TEST TP0706 1 TP0708 1 TP0710 1 A IN IN A 6 IKTARA_ANA1 1 IKTARA_GPIO3 1 IN IKTARA_GPIO4 1 SM PP ROOM=TEST SM PP ROOM=TEST SM PP ROOM=TEST PP0704 P2MM-NSM TP0755 A TP-P55 ROOM=TEST A C A ROOM=TEST PP0703 P2MM-NSM 11 6 ROOM=TEST TP0707 1 D SM PP ROOM=TEST ROOM=TEST TP0705 1 1 TP0754 TP-P55 TP-P55 PMU_TO_IKTARA_EN_EXT_1P8V PP0702 P2MM-NSM A TP-P55 PP10V0_RACER 6 TP0753 TP-P55 11 10 IN PP0701 P2MM-NSM TP0752 TP-P55 PN6V7_RACER 11 6 A Stockholm GND TP ROOM=TEST PP3V5_RACER PP0700 P2MM-NSM TP0790 1 TP-P55 11 10 1 Iktara Debug A TP-P55 ROOM=TEST TP0703 1 PP_BATT_VCC PP1V8_TOUCH_RACER_S2 TP-P55 A 11 PP5V25_TOUCH_VDDH 11 10 ROOM=TEST TP0702 1 2 Probe Points GND VDD_MAIN A 3 IN IKTARA_TO_SMC_INT 1 SM PP ROOM=TEST TP0756 A TP-P55 ROOM=TEST 11 10 TOUCH_TO_AMUX_PP1V8 A TP-P55 TP-P55 TP-P55 ROOM=TEST ROOM=TEST ROOM=TEST TP0757 A TP-P55 C ROOM=TEST 11 10 PMU_TO_TOUCH_CLK32K_RESET_L TP0758 A TP-P55 ROOM=TEST AMUX 12 11 10 11 PMU_AMUX_AY TP0713 1 A TP-P55 AP_TO_MANY_BSYNC TP0759 A TP-P55 ANALOG MUX A OUTPUT ROOM=TEST ROOM=TEST 11 10 HALL2_TO_AOP_IRQ_L TP0760 A TP-P55 ROOM=TEST 11 PMU_AMUX_BY TP0715 1 A TP-P55 ANALOG MUX B OUTPUT 11 10 AP_TO_RACER_RESET_L TP0761 A TP-P55 ROOM=TEST ROOM=TEST 11 10 DFU 11 PMU_HYDRA_TO_AP_FORCE_DFU A ROOM=TEST A FORCE DFU ROOM=TEST TP0762 TP-P55 TP0714 1 TP-P55 UART_RACER_TO_AOP_RXD 11 10 RACER_TO_AOP_INT_L TP0763 A TP-P55 ROOM=TEST B 11 10 LVCC 11 PP_GPU_LVCC UART_AOP_TO_RACER_TXD TP0764 B A TP-P55 ROOM=TEST TP0720 1 A TP-P55 ROOM=TEST 11 PP_CPU_PCORE_LVCC TP0721 1 A 11 10 RACER_TO_ACORN_ORB_SCAN TP-P55 ROOM=TEST COIL IKTARA_COIL1 11 10 SPI_AP_TO_RACER_CS_L A ROOM=TEST TP0730 A 11 10 SPI_AP_TO_RACER_MOSI TP0768 A TP-P55 TP-P55 IKTARA_COIL2 TP0767 TP-P55 ROOM=TEST 11 6 A TP-P55 ROOM=TEST 11 6 TP0766 ROOM=TEST TP0731 A TP-P55 ROOM=TEST A SYNC_MASTER=test_mlb 11 10 I2C3_AP_SDA TP0771 SYNC_DATE=01/17/2017 PAGE TITLE SYSTEM: Testpoints (Bottom) A TP-P55 ROOM=TEST 11 10 I2C3_AP_SCL DRAWING NUMBER Apple Inc. TP0772 051-02247 REVISION A 7.0.0 TP-P55 ROOM=TEST NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 7 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 5 OF 34 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 Iktara D D PP_IKTARA_VRECT C3445 C3411 1 1 2.2UF 220PF 20% 25V X5R 2 0402-4 5% 25V COG 2 01005 ROOM=IKTARA ROOM=IKTARA C3412 1 2.2UF 20% 25V X5R 2 0402-4 ROOM=IKTARA R3401 C3440 1 2.2UF 20% 25V X5R 2 0402-4 ROOM=IKTARA C3441 0.020 2 1 1 PP_IKTARA_VMID 1% 1/6W MF 0402 2.2UF 20% 25V X5R 2 0402-4 2 1 1 2.2UF ROOM=IKTARA XW3400 C3442 1 2.2UF ROOM=IKTARA C3443 220PF 20% 2 25V X5R 0402-4 20% 2 25V X5R 0402-4 2 ROOM=IKTARA XW3401 C3413 5% 2 25V COG 01005 ROOM=IKTARA ROOM=IKTARA SHORT-10L-0.05MM-SM SHORT-10L-0.05MM-SM 1 ROOM=IKTARA ROOM=IKTARA 1 D3401 DSN2 NSR20F30NX A D3402 DSN2 NSR20F30NX ROOM=IKTARA A K OMIT_TABLE D3403 DSN2 NSR20F30NX A ROOM=IKTARA ROOM=IKTARA ROOM=IKTARA B5 CLAMP1 C5 COMM1 H1 J1 K1 L1 E4 F1 E1 CRITICAL HV_GPO1 HV_GPO2 U3400 BC59355A2 WLCSP C3406 BOOTB_VDD ROOM=IKTARA 0.033UF 10% 50V 2 X7R 0402 To Coil 11 5 IKTARA_COIL1 OMIT_TABLE 1 R3450 1 OMIT_TABLE 1 0.1UF 100K 1% 1/20W MF 2 201 C3451 0402 OMIT_TABLE 1 0.1UF 10% 2 50V CER-X7R C3452 0402 ROOM=IKTARA OMIT_TABLE 1 0.1UF 10% 50V 2 CER-X7R C3453 0402 ROOM=IKTARA OMIT_TABLE 1 0.1UF 10% 50V 2 CER-X7R C3454 0402 ROOM=IKTARA OMIT_TABLE 1 0.1UF 10% 2 50V CER-X7R C3455 0402 ROOM=IKTARA 0.1UF 1 2 IKTARA_BOOT1 C7 10% 16V X5R-CERM 0201 C3456 0.1UF 10% 2 50V CER-X7R SW SW SW C3404 ROOM=IKTARA 10% ROOM=IKTARA 50V 2 CER-X7R B6 B7 C6 IKTARA_AC1 BOOT1_VDD AC1 AC1 AC1 1 1 2200PF IKTARA_COIL2 ROOM=IKTARA 1 B R3460 100K 1% 1/20W MF 2 201 1 C3461 0.1UF 10% 2 50V CER-X7R 0402 ROOM=IKTARA OMIT_TABLE 1 C3462 0.1UF 10% 50V 2 CER-X7R 0402 ROOM=IKTARA OMIT_TABLE 1 C3463 0.1UF 10% 50V 2 CER-X7R 0402 ROOM=IKTARA OMIT_TABLE 1 C3464 0.1UF 10% 2 50V CER-X7R 0402 ROOM=IKTARA OMIT_TABLE 1 C3465 0.1UF 10% 2 50V CER-X7R 0402 VDIG_CORE_VDD F7 PP1V5_VDIG_CORE_IKTARA VDDO H7 PP1V8_IKTARA VAUX_1P8_VDD G7 ROOM=IKTARA 0.1UF ROOM=IKTARA 1 C3407 0.033UF 10% 50V 2 X7R 0402 2 R3422 1 0.00 5 OUT IKTARA_BOOT2 SDA SCL INT RESET* BOOT2_VDD GPIO1 GPIO2 GPIO3/SWDIO GPIO4/SWCLK GPIO5 GPIO6 GPIO7 ROOM=IKTARA IKTARA_COMM2 IKTARA_ANA1 C3 COMM2 B3 CLAMP2 E2 F2 NC G3 G2 NC PP_VDD_MAIN_IKTARA 2 C1 AC2 AC2 AC2 10% 16V X5R-CERM 0201 ROOM=IKTARA PP_VDD_MAIN 5 B1 B2 C2 C3405 1 12 11 8 7 6 1 C3419 0% 1/32W MF 01005 ROOM=IKTARA NC 1 1 C3418 1UF 20% 6.3V 2 X5R 0201 ROOM=IKTARA 10% 50V 2 CER-X7R 0402 5% 1/20W MF 201 2 PP5V0_VDD_IKTARA ROOM=IKTARA IKTARA_AC2 ROOM=IKTARA 2 ROOM=IKTARA 1 C3417 1 4UF 6 PP1V8_IKTARA R34071 6 10K C3416 5% 1/32W MF 01005 2 2.2UF 20% 2 6.3V CERM-X5R 0201 20% 2 6.3V X5R-CERM 0201-2 ROOM=IKTARA ROOM=IKTARA ROOM=IKTARA I2C0_SMC_SDA I2C0_SMC_SCL IKTARA_TO_SMC_INT PMU_TO_IKTARA_RESET_R_L L4 L5 K4 J4 H6 L6 J6 K5 J5 K7 K6 R3406 1 2M E3 20% 6.3V 2 X5R 0201 0.1UF ROOM=IKTARA PP5V0_VMID_AUX_IKTARA 1UF C3466 PP_VDD_MAIN ROOM=IKTARA OMIT_TABLE 1 12 11 8 7 6 5 XW3402 SHORT-20L-0.05MM-SM VDD5V IN 11 BI OUT B 11 5 11 R3420 1 100 PMU_TO_IKTARA_RESET_L 2 IN 11 IN 5 11 5% 1/32W MF 01005 NC NC ROOM=IKTARA IKTARA_GPIO3 IKTARA_GPIO4 NC NC OUT 5 OUT 5 IKTARA_GPIO7 R3421 ANA1 ANA2 ANA3 ANA4 EN_EXT_1P8 G6 REFBP G5 DIGTEST A1 A2 A3 A4 A5 A6 A7 B4 RGND F3 VSYS_1P8_VDD F6 OTP_WREN J7 AVSS PGND PMU_TO_IKTARA_EN_EXT_1P8V_R E7 VSYS_ANA_VDD C4 G4 H3 L7 F5 F4 OMIT_TABLE 5% 2 25V COG 01005 ROOM=IKTARA E6 E5 10% 50V 2 X5R 0201 J3 K3 L3 11 5 2200PF 10% 50V X5R 2 0201 To Coil C3403 IKTARA_VOUT_SNS Pull-Ups 220PF 10% 25V 2 X5R 402 OMIT 11 C3444 1 1UF VMID_AUX_SW_VDD VMID_AUX_VDD NOSTUFF C3415 1 VOUT ROOM=IKTARA C3402 PP_VBUS2_IKTARA H4 NC H5 NC H2 NC J2 K2 L2 G1 0402 ROOM=IKTARA C NSR20F30NX A IKTARA_COMM1 1 VMID_VDD VMID_VDD VMID_VDD VMID_VDD D3400 DSN2 K OMIT_TABLE VMID_R_VDD K OMIT_TABLE VMID_S K OMIT_TABLE PP_IKTARA_VRECT_SENSE VRECT_S C VRECT_VDD VRECT_VDD VRECT_VDD VRECT_VDD VRECT_VDD VRECT_VDD VRECT_VDD D1 D2 D3 D4 D5 D6 D7 PP_IKTARA_VMID_SENSE PP_VDD_MAIN PP1V8_S2 1 1 5 6 7 8 11 12 4 9 11 12 100 2 PMU_TO_IKTARA_EN_EXT_1P8V 5% 1/32W MF 01005 ROOM=IKTARA R3408 1.00K 5% 1/32W MF 2 01005 ROOM=IKTARA A SYNC_MASTER=mlb_bot SYNC_DATE=04/04/2017 PAGE TITLE SYSTEM POWER: Iktara DRAWING NUMBER Apple Inc. 051-02247 REVISION 7.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 34 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 6 OF 34 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 D D South Speaker Amplifier APN: 338S00295 I2C ADDRESS: 1000 000x 0x80 12 11 8 6 5 PP_VDD_MAIN PP1V8_AUDIO_VA_S2 C4907 C4905 1 18UF 20% 6.3V CER-X5R 2 0402-0.1MM 18UF 20% 6.3V CER-X5R 2 0402-0.1MM ROOM=SPKAMP1 C4909 1 18UF 20% 6.3V CER-X5R 2 0402-0.1MM C4914 1 1 4UF 20% 6.3V CERM-X5R 2 0201 ROOM=SPKAMP1 20% 2 6.3V X5R-CERM 01005 ROOM=SPKAMP1 1 C4926 2.2UF 20% 2 6.3V X5R-CERM 0201 ROOM=SPKAMP1 ROOM=SPKAMP1 CRITICAL C C4925 0.1UF L4900 F5 A5 ROOM=SPKAMP1 1 8 11 VP C VA 1.2UH-20%-3A-0.077OHM 1 A2 B2 SPKRAMP_BOT_LX 2 MEHK2016T-SM ROOM=SPKAMP1 11 BI 11 IN 11 BI 11 IN 8 BI D6 I2C1_AOP_SDA I2C1_AOP_SCL E6 SPKRAMP_BOT_ARC_TO_AOP_INT_L A7 AOP_TO_SPKRAMP_BOT_ARC_RESET_L A6 SPKRAMP_BOT_TO_SPKRAMP_TOP_SYNC F6 E5 11 IN 11 8 IN 11 8 IN B7 CODEC_TO_SPKRAMP_BOT_ARC_MCLK I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK C7 I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK C6 D7 11 8 BI B6 I2S_CODEC_ASP1_TO_AOP_AMPS_DIN F7 NC E7 NC D5 A1 VBST_B B1 VBST_B C1 VBST_A D1 VBST_A U4900 SW SW CS35L26B-A1 WLCSP SDA ROOM=SPKAMP1 CRITICAL SCL PP_SPKRAMP_BOT_VBOOST 1 C4927 1 220PF C4928 0.1UF 5% 2 10V C0G-CERM 01005 ROOM=SPKAMP1 10% 2 16V X5R-CERM 0201 ROOM=SPKAMP1 1 C4903 10UF C4904 1 10UF 20% 2 10V X5R-CERM 0402-0.1MM ROOM=SPKAMP1 C4931 10UF 20% 2 10V X5R-CERM 0402-0.1MM ROOM=SPKAMP1 20% 2 10V X5R-CERM 0402-0.1MM ROOM=SPKAMP1 1 C4932 10UF 20% 2 10V X5R-CERM 0402-0.1MM ROOM=SPKAMP1 INT* RESET* F1 ISNS+ E1 ISNS- ALIVE/SYNC AD0/PDM_CLK1 1 SPKRAMP_BOT_ISENSE_POS SPKRAMP_BOT_ISENSE_NEG C4930 0.01UF 10% 2 6.3V X5R 01005 ROOM=SPKAMP1 MCLK E2 VSNS+ E3 VSNS- SCLK COIL_TO_SPKRAMP_BOT_VSENSE_POS COIL_TO_SPKRAMP_BOT_VSENSE_NEG IN 11 IN 11 LRCK/FSYNC D2 OUT+ C2 OUT- SDIN SDOUT SPKRAMP_BOT_TO_COIL_OUT_POS SPKRAMP_BOT_TO_COIL_OUT_NEG PDM_CLK0 FILT+ PDM_DATA0 PDM_DATA1 GNDP GNDA AD1 F4 C4922 SPKRAMP_BOT_FILT 470PF F3 1 C4929 ROOM=SPKAMP1 1 11 11 C4934 470PF 10% 2 10V X5R 01005 ROOM=SPKAMP1 B 20% 2 6.3V X5R-CERM 0201 B5 E4 F2 A3 A4 B3 B4 C3 C4 C5 D3 D4 1 10% 10V 2 X5R 01005 2.2UF B 1 ROOM=SPKAMP1 A SYNC_MASTER=mlb_bot SYNC_DATE=04/04/2017 PAGE TITLE AUDIO: Speaker Amp Bottom DRAWING NUMBER Apple Inc. 051-02247 REVISION 7.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 49 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 7 OF 34 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 Pull Downs AP_TO_SPKRAMP_TOP_RESET_L 1 8 11 R5001 100K 5% 1/32W MF 2 01005 ROOM=SPKAMP2 North Speaker Amplifier D D APN: 338S00295 I2C ADDRESS: 1000 000x 0x80 PP_VDD_MAIN PP1V8_AUDIO_VA_S2 1 18UF 20% 6.3V CER-X5R 2 0402-0.1MM ROOM=SPKAMP2 C5026 C5028 1 18UF 1 18UF 20% 6.3V CER-X5R 2 0402-0.1MM 20% 6.3V CER-X5R 2 0402-0.1MM ROOM=SPKAMP2 ROOM=SPKAMP2 C5029 1 1 4UF 0.1UF 20% 6.3V CERM-X5R 2 0201 20% 2 6.3V X5R-CERM 01005 ROOM=SPKAMP2 1 L5000 C5016 2.2UF 20% 2 6.3V X5R-CERM 0201 ROOM=SPKAMP2 CRITICAL C C5015 7 11 ROOM=SPKAMP2 F5 C5027 A5 12 11 7 6 5 VP VA C 1.2UH-20%-3A-0.11OHM SPKRAMP_TOP_LX 2 MEFE2016T-SM A2 B2 U5000 SW SW CS35L26B-A1 ROOM=SPKAMP2 11 BI 11 IN 11 BI 11 8 IN 7 BI 11 11 7 11 7 IN IN BI 11 IN SDA SCL SPKRAMP_TOP_TO_AP_INT_L A7 INT* AP_TO_SPKRAMP_TOP_RESET_L A6 RESET* SPKRAMP_BOT_TO_SPKRAMP_TOP_SYNC F6 ALIVE/SYNC E5 AD0/PDM_CLK1 B7 MCLK I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK C7 SCLK I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK C6 LRCK/FSYNC D7 SDIN I2S_CODEC_ASP1_TO_AOP_AMPS_DIN B6 SDOUT PDM_CODEC_TO_SPKRAMP_TOP_CLK F7 PDM_CLK0 PDM_DATA0 D5 PDM_DATA1 CRITICAL B C5012 1 220PF C5011 0.1UF 5% 2 10V C0G-CERM 01005 10% 2 16V X5R-CERM 0201 ROOM=SPKAMP2 ROOM=SPKAMP2 1 C5024 1 10UF 10UF 20% 2 10V X5R-CERM 0402-0.1MM 20% 2 10V X5R-CERM 0402-0.1MM ROOM=SPKAMP2 ISNS+ F1 ISNS- E1 SPKRAMP_TOP_ISENSE_POS SPKRAMP_TOP_ISENSE_NEG VSNS+ E2 VSNS- E3 COIL_TO_SPKRAMP_TOP_VSENSE_POS COIL_TO_SPKRAMP_TOP_VSENSE_NEG C5025 ROOM=SPKAMP2 1 1 C5006 1 10UF C5008 10UF 20% 2 10V X5R-CERM 0402-0.1MM 20% 2 10V X5R-CERM 0402-0.1MM ROOM=SPKAMP2 ROOM=SPKAMP2 C5019 0.01UF 10% 2 6.3V X5R 01005 ROOM=SPKAMP2 IN 11 IN 11 SPKRAMP_TOP_TO_COIL_OUT_POS SPKRAMP_TOP_TO_COIL_OUT_NEG OUT+ D2 OUT- C2 C5000 FILT+ F4 GNDP A3 A4 B3 B4 C3 C4 C5 D3 D4 E7 1 VBST_A C1 VBST_A D1 ROOM=SPKAMP2 E6 PDM_CODEC_TO_SPKRAMP_TOP_DATA IN D6 WLCSP I2C2_AP_SCL I2S_AP_TO_SPKRAMP_TOP_MCLK IN 11 7 11 I2C2_AP_SDA PP_SPKRAMP_TOP_VBOOST VBST_B A1 VBST_B B1 GNDA 470PF SPKRAMP_TOP_FILT 1 10% 10V 2 X5R 01005 ROOM=SPKAMP2 AD1 F3 1 1 11 11 C5001 470PF 10% 10V 2 X5R 01005 ROOM=SPKAMP2 C5018 2.2UF B5 E4 F2 1 B 20% 2 6.3V X5R-CERM 0201 ROOM=SPKAMP2 A SYNC_MASTER=mlb_bot SYNC_DATE=04/04/2017 PAGE TITLE AUDIO: Speaker Amp Top DRAWING NUMBER Apple Inc. 051-02247 REVISION 7.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 50 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 8 OF 34 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 D D Hall Effect C C APN:353S3697 PP1V8_S2 1 C5530 0.1UF 20% 2 6.3V X5R-CERM 01005 ROOM=HALL 1 12 11 6 4 VDD U5530 AK8789 DFN ROOM=HALL CRITICAL OUT1 4 OUT2 3 HALL3_TO_AOP_IRQ_L OUT 11 NC 5 2 THRM VSS PAD B B A SYNC_MASTER=mlb_bot SYNC_DATE=04/04/2017 PAGE TITLE HALL EFFECT DRAWING NUMBER Apple Inc. 051-02247 REVISION 7.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 55 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 9 OF 34 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 Rcpt: 516S00325 Plug: 516S00326 FL5800 150OHM-25%-200MA-0.7DCR 11 5 IN 2 AP_TO_RACER_RESET_CONN_L 1 01005 1 ROOM=B2B_TOUCH_ORB <-- This one on MLB J5800 AA26DK-S028VA1 10 F-ST-SM C5800 220PF 5% 2 10V C0G-CERM 01005 10 SPI_AP_TO_RACER_SCLK_CONN SPI_AP_TO_RACER_CS_CONN_L AP_TO_RACER_RESET_CONN_L RACER_TO_ACORN_ORB_SCAN_CONN SWD_AOP_TO_RACER_CONN SWD_AOP_BI_RACER_SWDIO_CONN HALL2_TO_AOP_IRQ_CONN_L 10 AP_TO_RACER_REF_CLK_CONN 10 ROOM=B2B_TOUCH_ORB 10 D C5860 R5801 11 IN AP_TO_RACER_REF_CLK 1 0.00 10 27PF AP_TO_RACER_REF_CLK_C 2 1 0% 1/32W MF 01005 10 AP_TO_RACER_REF_CLK_CONN 2 10 10 10 5% 25V C0G 0201 ROOM=B2B_TOUCH_ORB ROOM=B2B_TOUCH_ORB FL5802 10 150OHM-25%-200MA-0.7DCR 11 5 OUT RACER_TO_AOP_INT_L 1 Luna + Touch Connector Racer I/O AP_TO_RACER_RESET_L 2 2 10 RACER_TO_AOP_INT_CONN_L 1 10 10 10 01005 1 ROOM=B2B_TOUCH_ORB 33 29 30 1 3 5 7 9 11 13 15 17 19 21 23 25 27 2 4 6 8 10 12 14 16 18 20 22 24 26 28 31 34 32 PMU_TO_TOUCH_CLK32K_RESET_CONN_L I2C3_AP_BI_TOUCH_EEPROM_SDA_CONN I2C3_AP_TO_TOUCH_EEPROM_SCL_CONN TOUCH_TO_AMUX_PP1V8_CONN SPI_AP_TO_RACER_MOSI_CONN SPI_RACER_TO_AP_MISO_CONN RACER_TO_AOP_INT_CONN_L PP10V0_RACER_CONN UART_RACER_TO_AOP_RXD_CONN UART_AOP_TO_RACER_TXD_CONN PP1V8_TOUCH_RACER_CONN PP1V1_RACER_CONN PN6V7_RACER_CONN PP3V5_RACER_CONN AP_TO_TOUCH_BSYNC_CONN TOUCH_TO_ACORN_PP5V25_EN_CONN PP5V25_TOUCH_VDDH_CONN 10 10 D 10 10 10 10 10 10 10 10 10 10 10 C5802 220PF 5% 2 10V C0G-CERM 01005 Touch and Misc I/O ROOM=B2B_TOUCH_ORB ROOM=B2B_TOUCH_ORB FL5803 FL5840 150OHM-25%-200MA-0.7DCR 11 5 IN UART_AOP_TO_RACER_TXD 2 150OHM-25%-200MA-0.7DCR UART_AOP_TO_RACER_TXD_CONN 1 01005 1 ROOM=B2B_TOUCH_ORB 11 5 OUT 10 TOUCH_TO_ACORN_PP5V25_EN 2 TOUCH_TO_ACORN_PP5V25_EN_CONN 10 1 01005 C5803 1 ROOM=B2B_TOUCH_ORB C5840 Touch And Racer Power 220PF 56PF 5% 5% 2 25V NP0-C0G-CERM 01005 2 10V C0G-CERM 01005 ROOM=B2B_TOUCH_ORB FL5890 ROOM=B2B_TOUCH_ORB FL5804 FL5841 150OHM-25%-200MA-0.7DCR C 11 5 OUT UART_RACER_TO_AOP_RXD 2 150OHM-25%-200MA-0.7DCR UART_RACER_TO_AOP_RXD_CONN 1 01005 1 ROOM=B2B_TOUCH_ORB 33-OHM-25%-1500MA 11 5 OUT 10 TOUCH_TO_AMUX_PP1V8 2 PP1V8_TOUCH_RACER_S2 1 ROOM=B2B_TOUCH_ORB C5890 2 10V C0G-CERM 01005 ROOM=B2B_TOUCH_ORB FL5805 RACER_TO_ACORN_ORB_SCAN 2 RACER_TO_ACORN_ORB_SCAN_CONN 01005 1 ROOM=B2B_TOUCH_ORB 10 11 5 IN PMU_TO_TOUCH_CLK32K_RESET_L 2 11 5 C5805 5% 2 25V NP0-C0G-CERM 01005 33.2 PP5V25_TOUCH_VDDH 2 1 1 01005 ROOM=B2B_TOUCH_ORB FL5893 33-OHM-25%-1500MA ROOM=B2B_TOUCH_ORB PP3V5_RACER 2 1 5% C5806 01005 ROOM=B2B_TOUCH_ORB FL5894 33-OHM-25%-1500MA 11 5 ROOM=B2B_TOUCH_ORB PN6V7_RACER 2 1 0201 ROOM=B2B_TOUCH_ORB R5807 B 11 IN 1 SPI_AP_TO_RACER_SCLK_CONN 2 10 12 11 NOSTUFF 1 IN SWD_AOP_TO_MANY_SWCLK 2 C5807 5% 5% 1 1 IN SPI_AP_TO_RACER_MOSI 1 0.00 SPI_AP_TO_RACER_MOSI_CONN 10 11 1 BI SWD_AOP_BI_RACER_SWDIO 2 01005 C5809 R5845 1 56PF ROOM=B2B_TOUCH_ORB 1 ROOM=B2B_TOUCH_ORB 11 5 5% 2 25V NP0-C0G-CERM 01005 ROOM=B2B_TOUCH_ORB PP1V1_RACER 2 1 0201 ROOM=B2B_TOUCH_ORB C5810 IN AP_TO_MANY_BSYNC C5896 220PF 2 10V C0G-CERM 01005 ROOM=B2B_TOUCH_ORB 150OHM-25%-200MA-0.7DCR 10 1 5% 2 AP_TO_TOUCH_BSYNC_CONN 10 1 01005 56PF ROOM=B2B_TOUCH_ORB 1 C5847 100PF 5% 2 25V NP0-C0G-CERM 01005 AP I2C Filters 33-OHM-25%-1500MA C5845 ROOM=B2B_TOUCH_ORB 12 11 5 01005 1 ROOM=B2B_TOUCH_ORB FL5896 FL5847 SPI_RACER_TO_AP_MISO_CONN 10 01005 SWD_AOP_BI_RACER_SWDIO_CONN 10 56PF FL5810 1 PP1V1_RACER_CONN C5895 2 10V C0G-CERM 1 1% 1/32W MF 01005 2 150OHM-25%-200MA-0.7DCR 10 5% 10K 5% 2 25V NP0-C0G-CERM 01005 1 PP10V0_RACER_CONN 220PF 01005 NOSTUFF ROOM=B2B_TOUCH_ORB OUT 1 ROOM=B2B_TOUCH_ORB NOSTUFF ROOM=B2B_TOUCH_ORB 11 2 150OHM-25%-200MA-0.7DCR 2 2 PP10V0_RACER FL5845 0% 1/32W MF 01005 SPI_RACER_TO_AP_MISO 11 5 01005 ROOM=B2B_TOUCH_ORB FL5809 11 5 150OHM-25%-200MA-0.7DCR 5% ROOM=B2B_TOUCH_ORB ROOM=B2B_TOUCH_ORB FL5895 C5844 2 16V NP0-C0G 01005 B 01005 100PF ROOM=B2B_TOUCH_ORB 2 25V NP0-C0G-CERM C5894 2 10V C0G-CERM SWD_AOP_TO_RACER_CONN 10 1% 1/32W MF 01005 56PF ROOM=B2B_TOUCH_ORB 49.9 1 220PF R5844 0% 1/32W MF 01005 C5893 2 10V C0G-CERM 5% 2 25V NP0-C0G-CERM 01005 0.00 1 220PF 10 56PF SPI_AP_TO_RACER_SCLK 10 01005 5% 2 16V NP0-C0G 01005 ROOM=B2B_TOUCH_ORB 1 ROOM=B2B_TOUCH_ORB PN6V7_RACER_CONN 2 10V C0G-CERM 150OHM-25%-200MA-0.7DCR SPI_AP_TO_RACER_CS_CONN_L C5892 5% C5842 100PF ROOM=B2B_TOUCH_ORB 1 220PF 0201 1 10 ROOM=B2B_TOUCH_ORB FL5806 2 PP3V5_RACER_CONN 01005 ROOM=B2B_TOUCH_ORB 11 5 SPI_AP_TO_RACER_CS_L 10 5% 2 10V C0G-CERM PMU_TO_TOUCH_CLK32K_RESET_CONN_L 10 1 ROOM=B2B_TOUCH_ORB IN PP5V25_TOUCH_VDDH_CONN C C5891 220PF 01005 1% 1/32W MF 01005 56PF 11 5 1 10 FL5891 R5842 1 ROOM=B2B_TOUCH_ORB PP1V8_TOUCH_RACER_CONN 150OHM-25%-0.28A-0.69OHM 150OHM-25%-200MA-0.7DCR OUT 1 ROOM=B2B_TOUCH_ORB ROOM=B2B_TOUCH_ORB 11 5 0201 20% 6.3V X5R-CERM 2 0201 5% 5% 2 25V NP0-C0G-CERM 01005 2 2.2UF C5841 220PF 56PF 1 OMIT_TABLE TOUCH_TO_AMUX_PP1V8_CONN 10 1 01005 C5804 11 5 5% 2 16V NP0-C0G 01005 ROOM=B2B_TOUCH_ORB ROOM=B2B_TOUCH_ORB R5820 A 11 5 OUT I2C3_AP_SDA 2 0.00 I2C3_AP_BI_TOUCH_EEPROM_SDA_CONN 10 1 0% 1/32W MF 01005 1 SYNC_MASTER=mlb_bot C5820 56PF Hall Effect 5% 2 25V NP0-C0G-CERM 01005 ROOM=B2B_TOUCH_ORB 11 5 IN HALL2_TO_AOP_IRQ_L 2 11 5 IN 0.00 ROOM=B2B_TOUCH_ORB I2C3_AP_TO_TOUCH_EEPROM_SCL_CONN 1 0% 1/32W MF 01005 1 DRAWING NUMBER HALL2_TO_AOP_IRQ_CONN_L 1 01005 R5821 2 CG: B2B Luna & Touch FL5850 150OHM-25%-200MA-0.7DCR ROOM=B2B_TOUCH_ORB I2C3_AP_SCL 1 Apple Inc. 10 220PF 5% 2 10V C0G-CERM 01005 ROOM=B2B_TOUCH_ORB 10 C5821 051-02247 REVISION 7.0.0 C5850 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 58 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 56PF II NOT TO REPRODUCE OR COPY IT 5% 2 25V NP0-C0G-CERM 01005 ROOM=B2B_TOUCH_ORB SYNC_DATE=04/04/2017 PAGE TITLE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 10 OF 34 IV ALL RIGHTS RESERVED ROOM=B2B_TOUCH_ORB 8 7 6 5 4 3 2 1 SIZE D A 8 7 UART_AP_TO_GNSS_TXD 12 UART_AP_TO_GNSS_RTS_L 12 UART_GNSS_TO_AP_CTS_L 12 UART_GNSS_TO_AP_RXD 12 AP_TO_GNSS_WAKE 12 PMU_TO_GNSS_EN 12 AP_TO_BB_TIME_MARK 12 90_PCIE_AP_TO_BB_REFCLK_N 12 D 90_PCIE_AP_TO_BB_REFCLK_P 12 90_PCIE_BB_TO_AP_RXD_P 12 90_PCIE_BB_TO_AP_RXD_N 12 90_PCIE_AP_TO_BB_TXD_P 12 90_PCIE_AP_TO_BB_TXD_N 12 90_PCIE_WLAN_TO_AP_RXD_P 12 90_PCIE_WLAN_TO_AP_RXD_N 12 90_PCIE_AP_TO_WLAN_REFCLK_N 12 90_PCIE_AP_TO_WLAN_REFCLK_P 12 90_PCIE_AP_TO_WLAN_TXD_N 12 12 90_PCIE_AP_TO_WLAN_TXD_P 6 5 PMU_TO_IKTARA_EN_EXT_1P8V 6 5 IKTARA_TO_SMC_INT 6 I2C0_SMC_SCL 6 I2C0_SMC_SDA 12 BB_TO_STROBE_DRIVER_GSM_BURST_IND C PDM_CODEC_TO_SPKRAMP_TOP_CLK 8 PDM_CODEC_TO_SPKRAMP_TOP_DATA 12 PCIE_AP_TO_BB_RESET_L 8 I2S_AP_TO_SPKRAMP_TOP_MCLK 8 AP_TO_SPKRAMP_TOP_RESET_L 8 SPKRAMP_TOP_TO_AP_INT_L 8 I2C2_AP_SDA 8 I2C2_AP_SCL 8 7 PP1V8_AUDIO_VA_S2 8 PP_GPU_LVCC 5 PP_CPU_PCORE_LVCC 5 12 AP_TO_BB_IPC_GPIO1 12 AP_TO_BB_RESET_L 9 HALL3_TO_AOP_IRQ_L BOARD_ID3 12 PCIE_WLAN_BI_AP_CLKREQ_L 12 PCIE_AP_TO_WLAN_RESET_L 8 7 I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK 8 7 I2S_CODEC_ASP1_TO_AOP_AMPS_DIN 8 7 I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK 6 PMU_TO_IKTARA_RESET_L 12 I2S_BB_TO_AP_DIN 12 I2S_BB_TO_AP_LRCLK 12 I2S_BB_TO_AP_BCLK 12 I2S_AP_TO_BB_DOUT 12 BB_TO_AP_RESET_DETECT_L 12 AP_TO_BBPMU_RADIO_ON_L 12 AP_TO_WLAN_DEVICE_WAKE 7 SPKRAMP_BOT_ARC_TO_AOP_INT_L 7 AOP_TO_SPKRAMP_BOT_ARC_RESET_L 4 B SWD_AOP_BI_BB_SWDIO 7 I2C1_AOP_SDA 7 I2C1_AOP_SCL 5 PP_VDD_MAIN 12 12 11 8 7 6 A 12 11 9 12 UART_AP_TO_BT_RTS_L 12 UART_BT_TO_AP_CTS_L 12 UART_AP_TO_BT_TXD 12 UART_BT_TO_AP_RXD 12 NC_PP_VDD_BOOST 12 UART_AP_TO_WLAN_TXD 12 UART_AP_TO_WLAN_RTS_L 12 UART_WLAN_TO_AP_RXD 12 UART_WLAN_TO_AP_CTS_L 6 4 PP1V8_S2 6 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 NC S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 NC S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 NC S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S79 S80 S81 S82 S83 S84 S85 S86 IOS1 IOS2 IOS3 IOS4 IOS5 IOS6 IOS7 IOS8 IOS9 IOS10 IOS11 IOS12 IOS13 IOS14 IOS15 IOS16 IOS17 IOS18 IOS19 IOS20 IOS21 IOS22 IOS23 IOS24 IOS25 IOS26 IOS27 IOS28 IOS29 IOS30 IOS31 IOS32 IOS33 IOS34 IOS35 IOS36 IOS37 IOS38 IOS39 IOS40 IOS41 IOS42 IOS43 IOS44 IOS45 IOS46 IOS47 IOS48 IOS49 IOS50 IOS51 IOS52 IOS53 IOS54 IOS55 IOS56 IOS57 IOS58 IOS59 IOS60 IOS61 IOS62 IOS63 IOS64 IOS65 IOS66 IOS67 IOS68 IOS69 IOS70 IOS71 IOS72 IOS73 IOS74 IOS75 IOS76 IOS77 IOS78 IOS79 IOS80 IOS81 IOS82 IOS83 IOS84 IOS85 IOS86 J_INT_TOP INTERPOSER-TOP-D22 SMT-PAD SYM 3 OF 3 SIGNAL 5 IOS87 IOS88 IOS89 IOS90 IOS91 IOS92 IOS93 IOS94 IOS95 IOS96 IOS97 IOS98 IOS99 IOS100 IOS101 IOS102 IOS103 IOS104 IOS105 IOS106 IOS107 IOS108 IOS109 IOS110 IOS111 IOS112 IOS113 IOS114 IOS115 IOS116 IOS117 IOS118 IOS119 IOS120 IOS121 IOS122 IOS123 IOS124 IOS125 IOS126 IOS127 IOS128 IOS129 IOS130 IOS131 IOS132 IOS133 IOS134 IOS135 IOS136 IOS137 IOS138 IOS139 IOS140 IOS141 IOS142 IOS143 IOS144 IOS145 IOS146 IOS147 IOS148 IOS149 IOS150 IOS151 IOS152 IOS153 IOS154 IOS155 IOS156 IOS157 IOS158 IOS159 IOS160 IOS161 IOS162 IOS163 IOS164 IOS165 IOS166 IOS167 IOS168 IOS169 IOS170 IOS171 IOS172 S87 S88 S89 S90 S91 S92 S93 S94 S95 S96 S97 S98 S99 S100 S101 S102 S103 S104 S105 S106 S107 S108 S109 S110 S111 S112 S113 S114 S115 S116 S117 S118 S119 S120 S121 S122 S123 S124 S125 S126 S127 S128 S129 S130 S131 S132 S133 S134 S135 S136 S137 S138 S139 S140 S141 S142 S143 S144 S145 S146 S147 S148 S149 S150 S151 S152 S153 S154 S155 S156 S157 S158 S159 S160 S161 S162 S163 S164 S165 S166 S167 S168 S169 S170 S171 S172 4 PP1V8_S2 PP_VDD_MAIN BB_TO_PMU_PCIE_HOST_WAKE_L PMU_TO_BBPMU_RESET_L PMU_AMUX_AY AOP_TO_WLAN_CONTEXT_B UART_BB_TO_AOP_RXD UART_AOP_TO_BB_TXD AOP_TO_WLAN_CONTEXT_A BT_TO_PMU_HOST_WAKE PMU_TO_BT_REG_ON PMU_TO_WLAN_CLK32K WLAN_TO_PMU_HOST_WAKE PMU_TO_WLAN_REG_ON PMU_AMUX_BY CODEC_TO_SPKRAMP_BOT_ARC_MCLK PMU_TO_BB_USB_VBUS_DETECT PMU_HYDRA_TO_AP_FORCE_DFU AP_TO_BT_WAKE WLAN_TO_AP_TIME_SYNC RADIO_PA_NTC AP_TO_MANY_BSYNC TOUCH_TO_AMUX_PP1V8 PP3V5_RACER PP1V1_RACER PP5V25_TOUCH_VDDH RACER_TO_ACORN_ORB_SCAN PP1V8_TOUCH_RACER_S2 I2C3_AP_SCL I2C3_AP_SDA TOUCH_TO_ACORN_PP5V25_EN PN6V7_RACER PMU_TO_TOUCH_CLK32K_RESET_L PP10V0_RACER AP_TO_RACER_RESET_L RACER_TO_AOP_INT_L SWD_AOP_TO_MANY_SWCLK SWD_AOP_BI_RACER_SWDIO UART_AOP_TO_RACER_TXD UART_RACER_TO_AOP_RXD HALL2_TO_AOP_IRQ_L AP_TO_RACER_REF_CLK SPI_AP_TO_RACER_CS_L SPI_RACER_TO_AP_MISO SPI_AP_TO_RACER_MOSI SPI_AP_TO_RACER_SCLK PP_BATT_VCC PP3V0_S2 90_USB_BB_DATA_P 90_USB_BB_DATA_N PP_VBUS2_IKTARA 2 1 4 6 9 11 12 5 6 7 8 11 12 12 D 12 5 12 12 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 G41 G42 G43 G44 G45 G46 G47 G48 G49 G50 G51 G52 G53 G54 G55 G56 G57 G58 G59 G60 G61 G62 12 12 12 12 12 12 12 5 7 12 5 12 12 12 5 10 12 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 10 12 10 5 10 5 10 5 10 10 5 10 10 5 10 10 5 12 12 12 6 IKTARA_COIL2 5 6 IKTARA_COIL1 5 6 AP_TO_BB_COREDUMP PCIE_BB_BI_AP_CLKREQ_L SPKRAMP_TOP_TO_COIL_OUT_POS SPKRAMP_TOP_TO_COIL_OUT_NEG COIL_TO_SPKRAMP_TOP_VSENSE_POS COIL_TO_SPKRAMP_TOP_VSENSE_NEG COIL_TO_SPKRAMP_BOT_VSENSE_POS COIL_TO_SPKRAMP_BOT_VSENSE_NEG SPKRAMP_BOT_TO_COIL_OUT_POS SPKRAMP_BOT_TO_COIL_OUT_NEG AP_TO_NFC_DEV_WAKE UART_NFC_TO_AP_CTS_L UART_AP_TO_NFC_TXD UART_NFC_TO_AP_RXD UART_AP_TO_NFC_RTS_L AP_TO_NFC_FW_DWLD_REQ NFC_TO_PMU_HOST_WAKE PMU_TO_NFC_EN 3 12 12 8 J_INT_TOP IOG1 IOG2 IOG3 IOG4 IOG5 IOG6 IOG7 IOG8 IOG9 IOG10 IOG11 IOG12 IOG13 IOG14 IOG15 IOG16 IOG17 IOG18 IOG19 IOG20 IOG21 IOG22 IOG23 IOG24 IOG25 IOG26 IOG27 IOG28 IOG29 IOG30 IOG31 IOG32 IOG33 IOG34 IOG35 IOG36 IOG37 IOG38 IOG39 IOG40 IOG41 IOG42 IOG43 IOG44 IOG45 IOG46 IOG47 IOG48 IOG49 IOG50 IOG51 IOG52 IOG53 IOG54 IOG55 IOG56 IOG57 IOG58 IOG59 IOG60 IOG61 IOG62 INTERPOSER-TOP-D22 SMT-PAD SYM 1 OF 3 GND IOG63 IOG64 IOG65 IOG66 IOG67 IOG68 IOG69 IOG70 IOG71 IOG72 IOG73 IOG74 IOG75 IOG76 IOG77 IOG78 IOG79 IOG80 IOG81 IOG82 IOG83 IOG84 IOG85 IOG86 IOG87 IOG88 IOG89 IOG90 IOG91 IOG92 IOG93 IOG94 IOG95 IOG96 IOG97 IOG98 IOG99 IOG100 IOG101 IOG102 IOG103 IOG104 IOG105 IOG106 IOG107 IOG108 IOG109 IOG110 IOG111 IOG112 IOG113 IOG114 IOG115 IOG116 IOG117 IOG118 IOG119 IOG120 IOG121 IOG122 IOG123 IOG124 G63 G64 G65 G66 G67 G68 G69 G70 G71 G72 G73 G74 G75 G76 G77 G78 G79 G80 G81 G82 G83 G84 G85 G86 G87 G88 G89 G90 G91 G92 G93 G94 G95 G96 G97 G98 G99 G100 G101 G102 G103 G104 G105 G106 G107 G108 G109 G110 G111 G112 G113 G114 G115 G116 G117 G118 G119 G120 G121 G122 G123 G124 G125 G126 G127 G128 G129 G130 G131 G132 G133 G134 G135 G136 G137 G138 G139 G140 G141 G142 G143 G144 G145 G146 G147 G148 G149 G150 G151 G152 G153 G154 G155 G156 G157 G158 G159 G160 G161 G162 G163 G164 G165 G166 G167 G168 G169 G170 G171 G172 G173 G174 G175 G176 G177 G178 G179 G180 G181 G182 G183 G184 G185 G186 IOG125 IOG126 IOG127 IOG128 IOG129 IOG130 IOG131 IOG132 IOG133 IOG134 IOG135 IOG136 IOG137 IOG138 IOG139 IOG140 IOG141 IOG142 IOG143 IOG144 IOG145 IOG146 IOG147 IOG148 IOG149 IOG150 IOG151 IOG152 IOG153 IOG154 IOG155 IOG156 IOG157 IOG158 IOG159 IOG160 IOG161 IOG162 IOG163 IOG164 IOG165 IOG166 IOG167 IOG168 IOG169 IOG170 IOG171 IOG172 IOG173 IOG174 IOG175 IOG176 IOG177 IOG178 IOG179 IOG180 IOG181 IOG182 IOG183 IOG184 IOG185 IOG186 J_INT_TOP INTERPOSER-TOP-D22 SMT-PAD SYM 2 OF 3 GND IOG187 IOG188 IOG189 IOG190 IOG191 IOG192 IOG193 IOG194 IOG195 IOG196 IOG197 IOG198 IOG199 IOG200 IOG201 IOG202 IOG203 IOG204 IOG205 IOG206 IOG207 IOG208 IOG209 IOG210 IOG211 IOG212 IOG213 IOG214 IOG215 IOG216 IOG217 IOG218 IOG219 IOG220 IOG221 IOG222 IOG223 IOG224 IOG225 IOG226 IOG227 IOG228 IOG229 IOG230 IOG231 IOG232 IOG233 IOG234 IOG235 IOG236 IOG237 IOG238 IOG239 IOG240 IOG241 IOG242 IOG243 IOG244 IOG245 IOG246 IOG247 IOG248 G187 G188 G189 G190 G191 G192 G193 G194 G195 G196 G197 G198 G199 G200 G201 G202 G203 G204 G205 G206 G207 G208 G209 G210 G211 G212 G213 G214 G215 G216 G217 G218 G219 G220 G221 G222 G223 G224 G225 G226 G227 G228 G229 G230 G231 G232 G233 G234 G235 G236 G237 G238 G239 G240 G241 G242 G243 G244 G245 G246 G247 G248 C B 8 8 8 7 7 7 7 12 12 12 12 12 12 12 SYNC_MASTER=mlb_bot SYNC_DATE=04/04/2017 PAGE TITLE 12 I/O: Interposer (Top) NC DRAWING NUMBER Apple Inc. 051-02247 REVISION 7.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 66 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 11 OF 34 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 SUBDESIGN_SUFFIX=W 31 11 31 11 31 11 31 11 31 11 31 11 D 31 11 31 11 31 11 31 11 31 11 31 11 31 11 34 31 14 12 11 9 6 4 PP_VDD_MAIN PP1V8_S2 PP_VDD_MAIN PP1V8_SDRAM 90_PCIE_WLAN_TO_AP_RX_P 90_PCIE_WLAN_TO_AP_RX_N 34 11 PCIE_AP_BI_WLAN_CLKREQ_L 34 18 12 PCIE_AP_TO_WLAN_PERST_L UART_BB_TO_WLAN_COEX PCIE_WLAN_TO_PMU_WAKE UART_WLAN_TO_BB_COEX UART_BB_TO_WLAN_COEX UART_WLAN_TO_BB_COEX 12 14 31 34 18 12 12 14 31 34 11 34 11 AOP_TO_WLAN_CONTEXT_A 34 11 AOP_TO_WLAN_CONTEXT_B AP_TO_BT_WAKE WIFI_MLB 34 11 AP_TO_WLAN_DEV_WAKE BT_TO_PMU_HOST_WAKE UART_BT_TO_AP_CTS_L UART_BT_TO_AP_RXD PMU_TO_WLAN_32K UART_AP_TO_BT_RTS_L PMU_TO_WLAN_REG_ON WLAN_TO_AP_TIME_SYNC 4 6 9 11 12 14 31 34 34 31 17 12 11 8 7 6 5 PMU_TO_BT_REG_ON 31 11 31 11 PP1V8_SDRAM SUBDESIGN_SUFFIX=S 5 6 7 8 11 12 17 31 34 90_PCIE_AP_TO_WLAN_TX_N PMU_TO_BT_REG_ON PMU_TO_WLAN_CLK32K PMU_TO_WLAN_REG_ON 31 11 31 11 90_PCIE_AP_TO_WLAN_REFCLK_N PP_VDD_MAIN PP1V8_S2 90_PCIE_AP_TO_WLAN_TX_P AOP_TO_WLAN_CONTEXT_A AOP_TO_WLAN_CONTEXT_B AP_TO_BT_WAKE AP_TO_WLAN_DEVICE_WAKE UART_WLAN_TO_AP_CTS_L UART_WLAN_TO_AP_RXD UART_AP_TO_WLAN_RTS_L UART_AP_TO_WLAN_TXD 31 11 PP_VDD_MAIN UART_AP_TO_BT_TXD UART_WLAN_TO_AP_CTS_L UART_WLAN_TO_AP_RXD UART_AP_TO_WLAN_RTS_L UART_AP_TO_WLAN_TXD WLAN_TIME_SYNC BT_TO_PMU_HOST_WAKE UART_BT_TO_AP_CTS_L UART_BT_TO_AP_RXD UART_AP_TO_BT_RTS_L UART_AP_TO_BT_TXD 11 31 34 11 11 31 34 11 11 31 34 11 11 31 11 31 34 28 12 PMU_TO_NFC_EN BB_TO_NFC_CLK NFC_TO_BB_CLK_REQ AP_TO_NFC_FW_DWLD_REQ AP_TO_NFC_DEV_WAKE NFC_TO_PMU_HOST_WAKE PMU_TO_NFC_EN BB_TO_NFC_CLK NFC_TO_BB_CLK_REQ AP_TO_NFC_FW_DWLD 50_UAT_WLAN_2G_SOUTH 50_UAT_WLAN_5G_SOUTH 50_LAT_WLAN 11 12 29 32 MAKE_BASE=TRUE NC_PP_VDD_BOOST NFC_TO_PMU_HOST_WAKE NC UART_AP_TO_NFC_TXD UART_NFC_TO_AP_RXD UART_AP_TO_NFC_RTS_L UART_NFC_TO_AP_CTS_L NFC_DWP_TX_TP UART_AP_TO_NFC_TXD UART_NFC_TO_AP_RXD UART_AP_TO_NFC_RTS_L UART_NFC_TO_AP_CTS_L NFC_SWP1 NFC_SWP1 NC_PP_VDD_BOOST 12 29 32 12 29 32 SUBDESIGN_SUFFIX=K PP_VDD_MAIN PP1V8_S2 9 6 4 PP3V0_S2 29 11 34 31 17 12 11 8 7 6 5 34 31 14 12 11 I63 PP_VDD_MAIN AP_TO_BBPMU_SDWN_L PP1V8_SDRAM PMU_TO_BBPMU_ON PP3V0_TRISTAR AP_TO_BB_RESET_L AP_TO_BB_MESA_ON AP_TO_BBPMU_RADIO_ON_L PMU_TO_BBPMU_RESET_L AP_TO_BB_RESET_L C AP_TO_BB_COREDUMP AP_TO_BB_IPC_GPIO1 AP_TO_MANY_BSYNC AP_TO_BB_IPC_GPIO 31 14 31 14 UART_BB_TO_WLAN_COEX 12 12 UART_WLAN_TO_BB_COEX TOUCH_TO_BBPMU_FORCE_PWM UART_BB_TO_WLAN_COEX RADIO PA NTC BB_TO_AP_RESET_DETECT_L BB_TO_STROBE_DRIVER_GSM_BURST_IND BB_TO_AP_GSM_TXBURST 1 100PF 5% 16V 2 NP0-C0G 01005 RADIO_PA_NTC PA_NTC_RETURN 10KOHM-1% 01005 2 11 90_PCIE_AP_TO_BB_REFCLK_N XW3043 90_PCIE_AP_TO_BB_TX_P SHORT-20L-0.05MM-SM 1 2 RADIO_MLB_KAROO ROOM=PMU ROOM=PMU 90_PCIE_AP_TO_BB_REFCLK_P 90_PCIE_AP_TO_BB_REFCLK_N 90_PCIE_AP_TO_BB_TXD_P 90_PCIE_AP_TO_BB_TXD_N 90_PCIE_BB_TO_AP_RXD_P 90_PCIE_BB_TO_AP_RXD_N PCIE_AP_TO_BB_RESET_L PCIE_BB_BI_AP_CLKREQ_L BB_TO_PMU_PCIE_HOST_WAKE_L 90_PCIE_AP_TO_BB_REFCLK_P OMIT R3043 1 50_LAT_WLAN 12 50_UAT_WLAN_2G_SOUTH 12 50_UAT_WLAN_5G_SOUTH 32 29 12 50_LAT_WLAN 32 29 50_UAT_WLAN_2G_SOUTH ROOM=PMU 32 29 11 17 11 15 11 14 C 11 14 5 10 11 17 UART_WLAN_TO_BB_COEX BB_TO_AP_RESET_DETECT_L C3043 11 14 NC AP_TO_BB_COREDUMP_TRIG I71 D nfc_mlb AP_TO_NFC_DEV_WAKE 50_UAT_WLAN_2G_SOUTH 31 11 90_PCIE_AP_TO_WLAN_REFCLK_P 50_UAT_WLAN_5G_SOUTH 31 11 90_PCIE_AP_TO_WLAN_REFCLK_P 90_PCIE_AP_TO_WLAN_REFCLK_N 90_PCIE_AP_TO_WLAN_TXD_P 90_PCIE_AP_TO_WLAN_TXD_N 90_PCIE_WLAN_TO_AP_RXD_P 90_PCIE_WLAN_TO_AP_RXD_N PCIE_WLAN_BI_AP_CLKREQ_L PCIE_AP_TO_WLAN_RESET_L WLAN_TO_PMU_HOST_WAKE 50_LAT_WLAN_MLC 31 11 90_PCIE_AP_TO_BB_TX_N 90_PCIE_BB_TO_AP_RX_P 90_PCIE_BB_TO_AP_RX_N PCIE_AP_TO_BB_PERST_L 50_UAT_WLAN_5G_SOUTH PCIE_AP_BI_BB_CLKREQ_L PCIE_BB_TO_PMU_WAKE_L 11 14 11 14 11 14 11 14 11 14 11 14 11 14 11 14 11 14 11 14 11 14 AP_TO_BB_DEVICE_WAKE UART_AOP_TO_BB_TXD UART_BB_TO_AOP_RXD UART_AOP_TO_BB_TXD UART_BB_TO_AOP_RXD SWD_AOP_TO_MANY_SWCLK SWD_AOP_BI_BB_SWDIO PMU_TO_BB_USB_VBUS_DETECT 90_USB_BB_DATA_P 90_USB_BB_DATA_N SWD_AP_TO_BB_CLK B SWD_AP_BI_BB_IO USB_BB_VBUS 90_USB_BB_P 90_USB_BB_N UART_AP_TO_BB_TXD UART_BB_TO_AP_RXD I2S_BB_TO_AP_BCLK I2S_BB_TO_AP_LRCLK I2S_AP_TO_BB_DOUT I2S_BB_TO_AP_DIN I2S_BB_TO_AP_LRCLK I2S_AP_TO_BB_DOUT I2S_BB_TO_AP_DIN NFC_SWP1 SIM1_SWP 34 18 12 34 18 12 NFC_TO_BB_CLKREQ UART_GNSS_TO_AP_RXD BB_TO_NFC_CLK 10 11 15 B 11 15 11 14 11 14 11 14 11 14 11 14 11 14 11 14 PMU_TO_GNSS_EN 11 27 UART_AP_TO_GNSS_TXD 11 27 UART_GNSS_TO_AP_RXD 11 27 UART_AP_TO_GNSS_RTS_L 11 27 UART_GNSS_TO_AP_CTS_L 11 27 PMU_TO_GNSS_EN UART_AP_TO_GNSS_TXD NFC_TO_BB_CLK_REQ BB_TO_NFC_CLK 11 14 NC NC I2S_BB_TO_AP_BCLK 34 28 12 11 14 UART_AP_TO_GNSS_RTS_L UART_GNSS_TO_AP_CTS_L AP_TO_BB_TIME_MARK AP_TO_GNSS_WAKE AP_TO_GNSS_TIME_MARK AP_TO_GNSS_DEVICE_WAKE A 11 27 11 27 SYNC_DATE=07/29/2016 PAGE TITLE RADIOS DRAWING NUMBER Apple Inc. 051-02247 REVISION 7.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 80 OF 80 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 12 OF 34 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 2 3 1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 1 REV ECN CK APPD DESCRIPTION OF REVISION 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. 7 28 28 27 27 26 23 20 18 19 18 17 12 IN 17 16 15 14 12 IN 29 29 Tue Apr 11 16:10:08 2017 CSA PAGE 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM C TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM CONTENTS BASEBAND BASEBAND MEMORY/DEBUG BASEBAND POWER BASEBAND PMIC TRANSCEIVERS ET MODULATOR TDD TRANSMIT FDD TRANSMIT PRIMARY RECEIVE LOWER ANTENNA & COUPLERS DIVERSITY RECEIVE ASM'S DIVERSITY RECEIVE LNA'S UPPER ANTENNA FEEDS GNSS TEST POINTS & SIM 12 28 17 14 12 17 12 IN 28 15 12 IN 12 OUT 14 12 OUT 28 14 IN 12 IN 12 IN 12 IN 28 14 28 17 14 28 14 12 IN 28 14 12 IN 28 14 12 IN 28 14 12 IN 28 14 12 OUT 28 14 12 OUT 28 14 12 IN 16 2 14 12 28 17 IO 17 IO 17 IO 50_LAT_WLAN 50_UAT_WLAN_2G_SOUTH 50_UAT_WLAN_5G_SOUTH AP_TO_BBPMU_RADIO_ON_L PMU_TO_BBPMU_RESET_L AP_TO_BB_RESET_L BB_TO_AP_RESET_DETECT_L BB_TO_STROBE_DRIVER_GSM_BURST_IND AP_TO_BB_MESA_ON_K AP_TO_BB_COREDUMP AP_TO_MANY_BSYNC AP_TO_BB_IPC_GPIO1 IO OUT 90_PCIE_AP_TO_BB_REFCLK_P 90_PCIE_AP_TO_BB_REFCLK_N 90_PCIE_AP_TO_BB_TXD_P 90_PCIE_AP_TO_BB_TXD_N 90_PCIE_BB_TO_AP_RXD_P 90_PCIE_BB_TO_AP_RXD_N PCIE_AP_TO_BB_RESET_L PCIE_BB_BI_AP_CLKREQ_L BB_TO_PMU_PCIE_HOST_WAKE_L C AP_TO_BB_DEVICE_WAKE UART DESCRIPTION 28 14 IN 28 14 OUT AVX VC-TCXO ? 197S00042 197S00044 VTCXO_K NDK VC-TCXO ? 335S00013 335S0894 EPROM_K ON SEMI EEPROM ? MURATA 14 12 IN 14 12 OUT 14 12 OUT 14 12 OUT 14 12 IN 14 12 OUT BOM OPTION VTCXO_K C522_K ANTENNA FEEDS PCIE 197S00044 138S1103 IN 28 14 197S00040 138S0719 B REFERENCE DESIGNATOR(S) D PMU_TO_BB_GNSS_32K ALTERNATES ALTERNATE FOR PART NUMBER IN PP_VDD_MAIN PP1V8_S2 PP3V0_S2 CLOCKS BB CONTROL TABLE_TABLEOFCONTENTS_ITEM PART NUMBER 2017-04-11 POWER D TABLE_TABLEOFCONTENTS_HEAD ENGINEERING RELEASED RADIO_MLB PORTS ICE17.2 RADIO_MLB PDF PAGE 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0008448938 138S00128 C509_K, C523_K, C605_K, C624_K, C626_K, C1114_K, C1116_K MURATA ? 138S00049 138S00032 C402_K, C433_K, C437_K, C510_K, C720_K MURATA ? 138S0831 138S00032 C402_K, C433_K, C437_K, C510_K, C720_K MURATA ? 138S00086 138S0884 C500_K, C501_K, C502_K, C514_K, C515_K MURATA ? 339S00363 339S00353 GNSS_K PILSNER STATS ? AOP UART_AOP_TO_BB_TXD UART_BB_TO_AOP_RXD AUDIO ? 138S00133 UART_AP_TO_BB_TXD_K UART_BB_TO_AP_RXD_K I2S_BB_TO_AP_BCLK I2S_BB_TO_AP_LRCLK I2S_AP_TO_BB_DOUT I2S_BB_TO_AP_DIN WLAN 28 14 12 IN 28 14 12 OUT B UART_BB_TO_WLAN_COEX UART_WLAN_TO_BB_COEX NFC 16 18 28 18 IO 12 IN 12 OUT NFC_SWP1 NFC_TO_BB_CLK_REQ BB_TO_NFC_CLK GNSS BOM OPTIONS 28 27 12 IN 28 27 12 IN 28 27 12 OUT 28 27 12 IN 28 27 12 OUT 28 27 12 IN 27 12 IN TABLE_5_HEAD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION PMU_TO_GNSS_EN UART_AP_TO_GNSS_TXD UART_GNSS_TO_AP_RXD UART_AP_TO_GNSS_RTS_L UART_GNSS_TO_AP_CTS_L TABLE_5_ITEM 998-05780 1 BASEBAND, UNFUSED U_BB_K CRITICAL BB_UNFUSED TABLE_5_ITEM 998-05781 1 BASEBAND, LOCAL FUSED U_BB_K CRITICAL BB_LOCAL_FUSED DEBUG TABLE_5_ITEM 998-05782 1 BASEBAND, DEV FUSED U_BB_K CRITICAL BB_DEV_FUSED TABLE_5_ITEM 337S00244 1 BASEBAND, PRODUCTION FUSED U_BB_K CRITICAL BB_PROD_FUSED 28 15 16 3 28 14 12 16 2 IO 16 2 IO 12 IN TABLE_5_ITEM 138S00159 7 CAP,SOFT-TERM,2.2uF,6.3V,0201,KYOCERA C402_K,C437_K,C438_K,C433_K,C510_K,C720_K,C1601_K SOFT_CAP TABLE_5_ITEM 138S0831 7 CAP,TYPICAL,2.2UF,6.3V,0201,MURATA C402_K,C437_K,C438_K,C433_K,C510_K,C720_K,C1601_K AP_TO_BB_TIME_MARK AP_TO_GNSS_WAKE TYPICAL_CAP A IO IN SWD_AOP_TO_MANY_SWCLK SWD_AOP_BI_BB_SWDIO PMU_TO_BB_USB_VBUS_DETECT 90_USB_BB_DATA_P 90_USB_BB_DATA_N RADIO_MLB A DRAWING TITLE SCH,MLB,BOT,X893 DRAWING NUMBER Apple Inc. 051-02247 REVISION 7.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 1 OF 17 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST 8 7 6 SHEET 13 OF 34 IV ALL RIGHTS RESERVED 5 4 3 2 1 SIZE D 8 7 6 5 BASEBAND 17 16 15 14 11 6 5 4 3 2 1 4 16 17 16 15 14 11 6 5 4 2 1 PP1V8_S2 1 2 1 5 2 1 PCIE_BB_BI_AP_CLKREQ_L AP_TO_BBPMU_RADIO_ON_L 3 2 1 PP1V8_S2 16 3 1% 1/32W MF 2 01005 BASEBAND 1 D R200_K 100K 1 R208_K 100K 1% 1/32W MF 2 01005 BASEBAND R201_K 100K D 1% 1/32W MF 2 01005 BASEBAND U_BB_K PMB9948 16 5 2 4 SIM1_DETECT_K U_BB_K PMB9948 VDD_SIM1_K BGA 1 BGA SYM 1 OF 9 OMIT_TABLE IN K20 USIF1_RTS* K19 USIF1_CTS* FS NC EINT4 C 13 13 12 12 28 OUT IN IN UART_BB_TO_AOP_RXD UART_AOP_TO_BB_TXD NC EINT5 13 12 BI Y7 USIF2_TXD_MTSR Y6 USIF2_RXD_MRST AP_TO_BB_IPC_GPIO1 NC Y5 USIF2_RTS* AA7 USIF2_CTS* NC NC W2 AA4 Y3 W3 Y4 W4 THERM_SNS_A T18 THERM_SNS_C T19 FS D18 USIF3_RTS* D19 USIF3_CTS* FS DEV_HW_CONFIG_K I2S2_CLK0 I2S2_CLK1 I2S2_RX I2S2_TX I2S2_WA0 I2S2_WA1 FS FS E19 USIF3_TXD_MTSR E18 USIF3_RXD_MRST EINT6 FS 15 14 11 6 5 4 3 2 1 I2S_BB_TO_AP_BCLK AP_TO_BB_MESA_ON_K I2S_AP_TO_BB_DOUT I2S_BB_TO_AP_DIN I2S_BB_TO_AP_LRCLK AP_TO_BB_COREDUMP OUT 12 IN 12 13 5 2 OUT 12 13 5 2 OUT 12 13 IN 12 13 IN 18 OUT SYSCLK_26MHZ_K U5 SYS_CLK SYSCLK_26MHZ_EN_K V6 SYS_CLK_EN PP1V8_S2 13 IN 18 SIM1_IO_K R207_K 1.00K 1% 1/32W MF 2 01005 BASEBAND 13 28 28 EINT3 1 R209_K 1.00K 1% 1/32W MF 2 01005 BASEBAND I2C_BBPMU_SCL_K I2C_BBPMU_SDA_K EINT2 RXDAT_MAIN_0_1RXDAT_MAIN_0_1+ D1 D2 90_DIGRF_M0_RX1_N_K 90_DIGRF_M0_RX1_P_K IN 18 IN 18 RXDAT_MAIN_0_2RXDAT_MAIN_0_2+ C2 C3 90_DIGRF_M0_RX2_N_K 90_DIGRF_M0_RX2_P_K IN 18 IN 18 RXDAT_MAIN_1_1RXDAT_MAIN_1_1+ M1 M2 90_DIGRF_M1_RX1_N_K 90_DIGRF_M1_RX1_P_K IN 18 IN 18 RXDAT_MAIN_1_2RXDAT_MAIN_1_2+ L1 L2 90_DIGRF_M1_RX2_N_K 90_DIGRF_M1_RX2_P_K IN 18 IN 18 TXDAT_MAIN_0_1TXDAT_MAIN_0_1+ E1 E2 90_DIGRF_M0_TX_N_K 90_DIGRF_M0_TX_P_K OUT 18 28 OUT 18 28 TXDAT_MAIN_1_1TXDAT_MAIN_1_1+ N1 N2 90_DIGRF_M1_TX_N_K 90_DIGRF_M1_TX_P_K OUT 18 28 OUT 18 28 MPHY_MAIN_0_EN MPHY_MAIN_1_EN A3 K4 DIGRF_M0_EN_K DIGRF_M1_EN_K OUT 18 OUT 18 RXDAT_AUX_0_1RXDAT_AUX_0_1+ H2 H1 90_DIGRF_A0_RX1_N_K 90_DIGRF_A0_RX1_P_K IN 18 IN 18 RXDAT_AUX_0_2RXDAT_AUX_0_2+ J1 J2 90_DIGRF_A0_RX2_N_K 90_DIGRF_A0_RX2_P_K IN 18 IN 18 RXDAT_AUX_1_1RXDAT_AUX_1_1+ T1 T2 90_DIGRF_A1_RX1_N_K 90_DIGRF_A1_RX1_P_K IN 18 28 IN 18 28 RXDAT_AUX_1_2RXDAT_AUX_1_2+ U1 U2 90_DIGRF_A1_RX2_N_K 90_DIGRF_A1_RX2_P_K IN 18 IN 18 TXDAT_AUX_0_1TXDAT_AUX_0_1+ G2 G1 90_DIGRF_A0_TX_N_K 90_DIGRF_A0_TX_P_K OUT 18 OUT 18 TXDAT_AUX_1_1TXDAT_AUX_1_1+ R1 R2 90_DIGRF_A1_TX_N_K 90_DIGRF_A1_TX_P_K OUT 18 OUT 18 MPHY_AUX_0_EN MPHY_AUX_1_EN J4 T4 DIGRF_A0_EN_K DIGRF_A1_EN_K OUT 18 OUT 18 NC NC I2C1_SCL L19 I2C1_SDA L20 I2C_BB_EEPROM_SCL_K I2C_BB_EEPROM_SDA_K I2C2_SCL B16 I2C2_SDA A15 I2C_BBPMU_SCL_K I2C_BBPMU_SDA_K DIGRF V4.0 AUX 13 OMIT_TABLE CLOCKS AND CONTROL 28 J20 USIF1_TXD_MTSR J18 USIF1_RXD_MRST UART_BB_TO_AP_RXD_K UART_AP_TO_BB_TXD_K 16 2 1 I2S2 OUT FS FS FS FS I2C1 13 CC2_IN CC2_CLK CC2_IO CC2_RST 17 I2C2 H18 H19 G19 H20 NC NC NC NC 28 SIM CARD 1 OUT 16 SIM CARD 2 BI USIF1 14 28 SIM1_CLK_K SIM1_IO_K SIM1_RST_K R202_K 4.7K 5% 1/32W MF 2 01005 USIF3 28 OUT USIF2 28 G18 CC1_CLK FS F19 CC1_IO FS F18 CC1_RST FS SYM 7 OF 9 DIGRF V4.0 MAIN 16 2 2 OUT BI 14 17 14 17 EXTRA I/OS EINT7 U7 V9 W7 U9 V7 V8 U8 NC 13 12 OUT 28 OUT 28 IN 28 IN 28 IN 28 IN BB_TO_AP_RESET_DETECT_L BB_DEBUG_ERROR_K BB_HW_ID<0>_K BB_HW_ID<1>_K BB_HW_ID<2>_K BB_HW_ID<3>_K MMCI1_CD* MMCI1_CLK MMCI1_CMD MMCI1_DAT_0 MMCI1_DAT_1 MMCI1_DAT_2 MMCI1_DAT_3 MMC/SDIO1 NC USB 3.0 J17 CLKOUT1 USB_DPLUS USB_DMINUS VBUS USB_TUNE USB_TEST Y1 AA1 W1 AA3 Y2 USB30_TXP USB30_TXN USB30_RXP USB30_RXN AB2 AB1 AC1 AC2 90_USB_BB_DATA_P 90_USB_BB_DATA_N PMU_TO_BB_USB_VBUS_DETECT USB_BB_TUNE_K NC 1 1 NC NC NC NC BI 12 13 28 BI 12 13 28 16 R205_K 200 C BASEBAND 1% 1/32W MF 2 01005 BASEBAND B 17 28 IN 28 14 IN 13 12 OUT C15 K18 M20 L18 BBPMU_ALERT_L_K SIM1_DETECT_K BB_TO_PMU_PCIE_HOST_WAKE_L NC EINT0 EINT1 FS EINT2 BOOTROM DRIVEN EINT3 FS PCI_PET_P1 PCI_PET_N1 PCI_PER_P1 PCI_PER_N1 PCI_REFCLK_P PCI_REFCLK_N PCI_REF_RES PCIE EINT0 CC1_IN EXT INTERRUPT B AE16 AE15 AE13 AE14 AC15 AC14 AA15 90_PCIE_BB_TO_AP_RXD_P 90_PCIE_BB_TO_AP_RXD_N 90_PCIE_AP_TO_BB_TXD_P 90_PCIE_AP_TO_BB_TXD_N 90_PCIE_AP_TO_BB_REFCLK_P 90_PCIE_AP_TO_BB_REFCLK_N PCIE_REF_RES_K 1 BASEBAND OUT 12 13 28 OUT 12 13 28 IN 12 13 28 BGA IN 12 13 28 SYM 9 OF 9 IN 12 13 28 IN 12 13 28 U_BB_K PMB9948 28 13 17 OUT 12 OUT 27 R206_K 200 1% 1/32W MF 2 01005 BASEBAND 28 OUT 28 13 12 IN 28 13 12 OUT 17 14 13 12 OUT C16 MODEM_STDBYOMIT_TABLE FS PCIE_CLKREQ* N18 E17 FTA_TRIG BB_TO_STROBE_DRIVER_GSM_BURST_IND PCIE_PERST* P18 F17 GNSS_BLANK_K IDC_PA_BLANKING E16 UART_WLAN_TO_BB_COEX IDC_UART_RXD FS F16 UART_BB_TO_WLAN_COEX IDC_UART_TXD FS BBPMU_STBY_K AP_TO_BBPMU_RADIO_ON_L D15 SDWN_REQ* 28 17 OUT BBPMU_VCLK_K B13 28 17 BBPMU_VDIO_K C14 BI BB EEPROM 16 15 14 11 6 5 4 3 2 1 BI IN 1 12 13 14 12 13 28 28 PERST PULLED DOWN AT AP C201_K 100PF 5% 16V 2 NP0-C0G FS 01005 BASEBAND VCLK VDIO BASEBAND PP1V8_S2 1 C200_K 1UF 20% 16V 2 CER-X5R 0201 BASEBAND 1 1 R203_K 10K 1% 1/32W MF 2 01005 BASEBAND R204_K 10K 1% 1/32W MF 2 01005 BASEBAND A1 17 PCIE_BB_BI_AP_CLKREQ_L PCIE_AP_TO_BB_RESET_L VCC A A EPROM_K CAT24C08C4A 2 I2C_BB_EEPROM_SCL_K B1 SCL WLCSP PAGE TITLE SDA B2 I2C_BB_EEPROM_SDA_K BASEBAND 2 DRAWING NUMBER Apple Inc. 051-02247 REVISION 7.0.0 A2 VSS BASEBAND NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 2 OF 17 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST 8 7 6 SHEET 14 OF 34 IV ALL RIGHTS RESERVED 5 4 3 2 1 SIZE D 8 7 6 5 4 3 2 1 BASEBAND MEMORY/DEBUG 17 16 15 14 11 6 5 4 3 2 1 PP1V8_S2 D 1 D R300_K 100K 1% 1/32W MF 2 01005 BASEBAND U_BB_K PMB9948 28 15 13 12 IN AP_TO_BB_RESET_L BGA SYM 2 OF 9 OMIT_TABLE DDR_DQ_0 AE6 DDR_DQ_1 AD7 NAND_ADQ_0 NAND_ADQ_1 NAND_ADQ_2 NAND_ADQ_3 NAND_ADQ_4 NAND_ADQ_5 NAND_ADQ_6 NAND_ADQ_7 NC NC U_BB_K PMB9948 BGA SYM 6 OF 9 OMIT_TABLE DBB EMIC 28 DDR_CA_0 DDR_CA_1 DDR_CA_2 DDR_CA_3 DDR_CA_4 DDR_CA_5 DDR_CA_6 DDR_CA_7 DDR_CA_8 DDR_CA_9 27 15 IN NC DDR_DQS_T_0 DDR_DQS_C_0 DDR_DQS_T_1 DDR_DQS_C_1 DDR_DQS_T_2 DDR_DQS_C_2 DDR_DQS_T_3 DDR_DQS_C_3 AD9 AE9 AD13 AE12 AD6 AE5 AE17 AC16 DDR_CK_T DDR_CK_C DDR_DQM_0 DDR_DQM_1 B11 A11 AD10 AD12 11 6 5 4 3 2 1 PP1V8_S2 0% 1/32W MF 01005 G16 FSYS_32K R20 F32K FS P20 OSC32K IN 28 13 12 BI 28 OUT 28 IN 28 IN 28 IN 28 IN L4 RESET_TRX1* U4 RESET_TRX2* XCVR0_RESET_L_K XCVR1_RESET_L_K SWD_AOP_TO_MANY_SWCLK SWD_AOP_BI_BB_SWDIO F15 SWDCLK FS E15 SWDIO FS BB_JTAG_TDO_K BB_JTAG_TDI_K BB_JTAG_TMS_K BB_JTAG_TCK_K BB_JTAG_TRST_L_K C19 B20 C18 D17 A19 B19 L10 RCT_MON2 L11 RCT_MON1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC P19 V1 N19 T20 AA6 B18 V2 AA5 W13 W15 W17 W19 W20 W5 Y17 Y19 NC NC F4 E4 E5 F5 E7 F6 D6 G7 G6 D5 F8 C6 C5 C7 D7 E8 BGA SYM 5 OF 9 OMIT_TABLE TRIG_IN C20 TDO TDI TMS TCK TRST* RTCK TPIU_TRACEPKT0 TPIU_TRACEPKT1 TPIU_TRACEPKT2 TPIU_TRACEPKT3 TPIU_TRACEPKT4 TPIU_TRACEPKT5 TPIU_TRACEPKT6 TPIU_TRACEPKT7 TPIU_TRACEPKT8 TPIU_TRACEPKT9 TPIU_TRACEPKT10 TPIU_TRACEPKT11 TPIU_TRACEPKT12 TPIU_TRACEPKT13 TPIU_TRACEPKT14 TPIU_TRACEPKT15 C NC HW_MON1 D20 HW_MON2 E20 HW_MON1_K HW_MON2_K OUT 28 OUT 28 C4 TPIU_TRACECLK D4 TPIU_TRACECTL B BASEBAND BASEBAND DDR_CS_1 B10 DDR_CKE_1 AB10 DDR_VREF_DQ AE10 DDR_VREF_CA A12 NC BB_DDR_CKE_K 4 BB_DDR_VREF_DQ_K BB_DDR_VREF_CA_K 1 C300_K 47PF 1 C301_K 47PF 5% 16V 2 CERM 01005 BASEBAND PP1V8_TCXO_K 1 C303_K 0.1UF VDD 20% 6.3V 2 X5R-CERM 01005 BASEBAND A OUT 12 3 14 OUT 18 M19 RESET2* N20 CP_RESET_BB* FS 13 NC 01005 BASEBAND 15 18 NC NC NC NC 5% 16 IN NC NC NC NC NC NC NC NC 16V 2 CERM 17 13 12 BB_TO_AP_RESET_ACT_L_K AP_TO_BB_RESET_L NC BASEBAND R302_K 0.00 2 1 OUT B17 XG_SDWN* H16 VSS_SENSE DDR_DQ_31 AE19 CLOCKS & CONTROL 28 BBPMU_32K_K TCXO_BB_GNSS_32K_K 28 BBPMU_XG_RESET_SD_L_K NC NC DDR_DQM_3 AD16 OUT IN BBPMU_XG_RESET_L_K 28 NC B 17 15 17 IN B15 XG_RESET* MONITORING B8 A8 A9 B9 C10 A13 C12 C13 D13 E14 28 17 B14 PWRGOOD JTAG NC NC NC NC NC NC NC NC NC NC NAND_ALE NAND_CE* NAND_CLE NAND_RB* NAND_RE* NAND_WE* NAND_WP* 28 BBPMU_PWRGOOD_K TPIU NC NC NC NC NC NC NC NC NC IN ADN SENSE C Y10 Y9 Y11 U11 AC9 W10 W12 DDR_DQ_15 AD15 DDR_DQ_16 AE2 18 17 PMU CONTROL 28 U_BB_K PMB9948 CONTACT V11 AB12 AA12 Y13 W11 V12 U13 V13 NAND IF NC NC NC NC NC NC NC NC TCXO_K 32.768KHZ-5PPM A CSP NC 1 CAL/NC CLKOUT 2 TCXO_BB_GNSS_32K_K OUT 15 27 PAGE TITLE 28 BASEBAND MEMORY/DEBUG GND DRAWING NUMBER 4 051-02247 Apple Inc. REVISION 7.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 3 OF 17 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST 8 7 6 SHEET 15 OF 34 IV ALL RIGHTS RESERVED 5 4 3 2 1 SIZE D 8 7 6 6 4 5 BASEBAND POWER 5 AA16 AA18 AA20 AB5 R14 R16 T16 U15 U16 U18 V14 V16 V18 W16 W18 Y16 Y14 Y18 Y20 VDD_CORE_1V0_K 1 C413_K 1UF 20% 16V 2 CER-X5R 0201 BASEBAND Y20 1 C418_K 0.1UF 20% 6.3V 2 X5R-CERM 01005 BASEBAND AA20 D VDD_CORE_MAIN VDD_CORE_MAIN VDD_CORE_MAIN VDD_CORE_MAIN VDD_CORE_MAIN VDD_CORE_MAIN VDD_CORE_MAIN VDD_CORE_MAIN VDD_CORE_MAIN VDD_CORE_MAIN VDD_CORE_MAIN VDD_CORE_MAIN VDD_CORE_MAIN VDD_CORE_MAIN VDD_CORE_MAIN VDD_CORE_MAIN VDD_CORE_MAIN VDD_CORE_MAIN VDD_CORE_MAIN 4 3 2 1 U_BB_K PMB9948 BGA SYM 4 OF 9 DBB POWER PINS OMIT_TABLE VDD_EMIC_IO_0 VDD_EMIC_IO_0 VDD_EMIC_IO_1 VDD_EMIC_IO_1 VDD_EMIC_IO_2 VDD_EMIC_IO_2 VDD_EMIC_IO_3 VDD_EMIC_IO_3 VDD_EMIC_IO_CA VDD_EMIC_IO_CA VDD_EMIC_1V8_IO VDD_LDO_DLL_EMIC AC7 AC8 AB15 AB14 AC5 AC6 AC17 AC18 AC11 AC12 AB16 AE11 VDD_IO_1V2_K 1 4 1 C424_K 0.1UF 20% 1 C427_K 0.1UF 20% 6.3V 2 X5R-CERM 20% 6.3V 2 X5R-CERM 01005 BASEBAND 1 C429_K 0.1UF 20% 6.3V 2 X5R-CERM 01005 BASEBAND 1 C431_K 0.1UF 20% 6.3V 2 X5R-CERM 01005 BASEBAND 1 C434_K 0.1UF C436_K 1UF 20% 6.3V 2 X5R-CERM 01005 BASEBAND 5 16V 2 CER-X5R 01005 BASEBAND 0201 BASEBAND D AE11 VDD_DDR_1V8_K 4 1 5 C440_K 0.1UF 20% 6.3V 2 X5R-CERM 6 5 1 C414_K 1UF 20% 16V 2 CER-X5R 0201 BASEBAND M5 6 5 L6 M4 M5 N6 P4 R6 U6 V4 V5 VDD_CORE_1V0_K 4 1 C419_K 0.1UF 20% 6.3V 2 X5R-CERM 01005 BASEBAND B6 B7 C11 C8 D11 D9 E11 E9 F10 F11 F12 F13 F9 G10 G11 H10 H11 H15 J10 J11 J12 J13 J5 J6 J7 J8 J9 K11 K13 K15 K5 K8 M10 M11 M13 M15 M8 M9 R12 R9 L17 C17 H17 P14 P16 M18 AB7 AB8 U10 V10 VDD_CORE_1V0_K 4 1 C415_K 1UF 20% 16V 2 CER-X5R 0201 BASEBAND B6 1 C420_K 0.1UF 20% 6.3V 2 X5R-CERM 01005 BASEBAND B7 C B 6 5 VDD_CORE_1V0_K 4 1 C416_K 1UF 20% 16V 2 CER-X5R 0201 BASEBAND AB7 5 4 1 C421_K 1UF 20% 16V 2 CER-X5R 0201 BASEBAND U10 VDD_IO_1V2_K NC 11 6 5 17 4 3 2 16 15 16 5 2 VDD_SIM2_K 5 VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_LTE VDD_CORE_DSP VDD_CORE_DSP VDD_CORE_TD VDD_CORE_TD VDD_LDO_USB_SS AC3 LDO_MON_USB_SS AD1 VDD_USB_SS_IO AA2 VDD_IO_1V2_K 4 NC 1 VDD_USB_3V15_K VDD_LDO_DIGRF_PHY1 LDO_MON_DIGRF1 VDD_LDO_DIGRF_PHY2 LDO_MON_DIGRF2 VDD_LDO_DIGRF_PHY3 LDO_MON_DIGRF3 VDD_LDO_DIGRF_PHY4 LDO_MON_DIGRF4 F1 G4 K2 D3 K1 N4 P1 R4 VDD_LDO_PCIE U20 LDO_MON_PCIE U19 VDD_PCIE_1V8 V20 VPP Y8 DUMMY_BALL DUMMY_BALL DUMMY_BALL DUMMY_BALL A1 A20 AE1 AE20 VDD_IO_1V2_K NC 1 NC 16V 2 CER-X5R NC 4 1 C425_K 1UF 20% 1 C428_K 0.1UF 20% 20% 6.3V 2 X5R-CERM 0201 BASEBAND 01005 BASEBAND 1 A C411_K 1UF 20% 16V 2 CER-X5R 0201 BASEBAND 1 C412_K 0.1UF 20% 6.3V 2 X5R-CERM 01005 BASEBAND 1 C400_K 0.47UF 10% 6.3V 2 CERM-X5R 0201 BASEBAND 5 1 16 15 14 11 6 5 4 3 2 1 C441_K 0.47UF 10% 20% 6.3V 2 CERM-X5R VDD_VREFCP_K 6.3V 2 X5R-CERM 0201 BASEBAND 01005 BASEBAND R401_K 10K 2 1 1% 1/32W MF 01005 BASEBAND C417_K 0.1UF 1 C401_K 0.01UF 10% 6.3V 2 X5R 01005 BASEBAND 5 4 1 C422_K 0.1UF 20% 6.3V 2 X5R-CERM 01005 BASEBAND VREF_0V6_K VDD_IO_1V2_K 1 C423_K 1UF NC 01005 20% 6.3V 2 X5R-CERM 01005 BASEBAND 5 C432_K 0.1UF U_BB_K PMB9948 6.3V 2 X5R-CERM 01005 BASEBAND 01005 BASEBAND BGA NC PP1V8_S2 1 1 NC 2 3 4 5 6 11 14 15 16 17 C426_K 0.1UF 20% NC NC NC NC 6.3V 2 X5R-CERM 01005 BASEBAND U_BB_K PMB9948 BGA 3 1 AA11 CKE_MEM D14 ZQ_MEM BB_DDR_CKE_K ZQ_MEM_K SYM 8 OF 9 7 AA13 AB17 AB18 AB19 AB9 AC19 AC4 AD11 AD17 AD18 AD20 AD4 AD5 AD8 C9 D10 D12 G12 H12 H13 J15 K12 L13 M12 N15 P13 V15 VSSQ_MEM VSSQ_MEM VSSQ_MEM VSSQ_MEM AD19 AD14 AE3 AE8 LPDDR2 RAM R400_K 240 1% 1/32W MF 2 01005 BASEBAND 5 4 VDD_DDR_1V8_K A16 A6 AB20 AD3 VDD1_MEM VDD1_MEM VDD1_MEM VDD1_MEM 5 4 VDD_IO_1V2_K A17 A5 AC20 A7 AD2 VDD2_MEM VDD2_MEM VDD2_MEM VDD2_MEM VDD2_MEM AC13 AE18 AE4 AE7 VDDQ_MEM VDDQ_MEM VDDQ_MEM VDDQ_MEM BASEBAND 5 4 VDD_IO_1V2_K 1 C402_K 2.2UF 20% VDD_IO18 VDD_IO18 VDD_IO18 VDD_IO18 VDD_IO18 VDD_IO18 VDD_IO18 VDD_IO18 C403_K 0.1UF 20% 6.3V 2 X5R-CERM 6.3V 2 X5R-CERM 0201 BASEBAND OMIT_TABLE 01005 BASEBAND 1 C404_K 0.1UF 20% 6.3V 2 X5R-CERM 01005 BASEBAND 1 C405_K 0.1UF 20% 6.3V 2 X5R-CERM 01005 BASEBAND 1 C437_K 2.2UF 20% 6.3V 2 X5R-CERM 0201 BASEBAND OMIT_TABLE 1 C438_K 2.2UF 20% 6.3V 2 X5R-CERM 0201 BASEBAND OMIT_TABLE 1 C409_K 0.1UF 20% 6.3V 2 X5R-CERM 01005 BASEBAND 1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS SYM 3 OF 9 GROUND OMIT_TABLE C410_K 0.1UF VSS_USB VSS_PLL VSS_PLL VSS_MPHY_1 VSS_MPHY_1 VSS_MPHY_2 VSS_MPHY_2 VSS_MPHY_3 VSS_MPHY_3 VSS_MPHY_4 VSS_MPHY_4 AB3 W9 W14 E3 F3 H3 J3 M3 N3 R3 T3 C VSS_PCIE_TX V19 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS N10 N11 N12 N13 N14 N16 N17 N7 N8 N9 P10 P11 P12 P15 P17 P2 P3 P6 P7 P8 P9 R13 R15 R17 R7 T11 T12 T13 T14 T15 T17 T7 U14 U17 R18 U3 V17 G17 B BASEBAND 20% 6.3V 2 X5R-CERM 01005 BASEBAND A PAGE TITLE 5 4 BASEBAND POWER VDD_DDR_1V8_K 1 C433_K 2.2UF 1 C406_K 0.1UF 20% 20% 6.3V 6.3V 2 X5R-CERM 2 X5R-CERM 0201 01005 BASEBAND BASEBAND OMIT_TABLE A18 VREF_0V6 AB13 VDD_LDO_CORE_EMIC AB11 LDO_MON_EMIC 20% BASEBAND 16V 2 CER-X5R 1 C408_K 0.1UF 20% 6.3V 2 X5R-CERM 01005 BASEBAND 1 DRAWING NUMBER C439_K 0.1UF 20% 6.3V 2 X5R-CERM 01005 BASEBAND Apple Inc. 051-02247 REVISION 7.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 4 OF 17 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 0201 BASEBAND 6 VSS_EMIC VSS_EMIC VSS_EMIC VSS_EMIC VSS_EMIC VSS_EMIC VSS_EMIC VSS_EMIC VSS_EMIC VSS_EMIC VSS_EMIC VSS_EMIC VSS_EMIC VSS_EMIC VSS_EMIC VSS_EMIC VSS_EMIC VSS_EMIC VSS_EMIC VSS_EMIC VSS_EMIC VSS_EMIC VSS_EMIC VSS_EMIC VSS_EMIC VSS_EMIC VSS_EMIC OMIT_TABLE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST 8 A10 A14 A2 A4 AA14 AA17 AA19 AA8 M17 AC10 B1 B12 B2 B3 B4 B5 C1 D8 E10 E12 E13 E6 F14 F2 F7 G13 G14 G3 G9 H5 H6 H7 H8 H9 J16 K10 K16 K3 K6 K7 K9 L16 K17 L3 L5 L7 L8 L9 M16 D16 AB4 M6 M7 NC Y12 VDD_LDO_PLL U12 LDO_MON_PLL AB6 AA9 G8 J19 R10 R11 R8 T8 PP1V8_S2 1 20% 6.3V 2 X5R C435_K 0.1UF 20% 6.3V 2 X5R-CERM 1 17 1 C430_K 0.1UF 5 C407_K 0.22UF 5 1 R19 VDD_RTC G20 VDD_SIM1 F20 VDD_SIM2 PP1V8_S2 VDD_SIM1_K 1 14 VDD_CORE_3G VDD_CORE_3G VDD_CORE_3G VDD_CORE_3G VDD_CORE_3G VDD_CORE_3G VDD_CORE_3G VDD_CORE_3G VDD_CORE_3G 01005 BASEBAND SHEET 16 OF 34 IV ALL RIGHTS RESERVED 5 4 3 2 1 SIZE D 8 7 6 5 4 3 2 1 BASEBAND PMIC D D 16 17 16 15 14 15 11 28 28 28 8 6 5 4 18 15 13 14 7 6 5 3 2 OUT 12 IN 13 12 IN 28 15 28 15 1 BI OUT 4 1 C510_K 2.2UF 20% 6.3V 2 X5R-CERM 0201 BBPMU OMIT_TABLE C 15 IN 14 BI 14 IN VMOD1LX D1 VMOD1LX D2 VMOD1SENSE D3 VMOD1LX_K PP1V8_S2 B4 VSYS G4 VSYS H8 VSWITCHVIN BBPMU_PWRGOOD_K PMU_TO_BBPMU_RESET_L AP_TO_BBPMU_RADIO_ON_L E4 B6 C4 XG_PWRGOOD PMIC_ON SDWN* VMOD2LX A2 VMOD2LX B2 VMOD2SENSE B1 VMOD2LX_K BBPMU_XG_RESET_L_K BBPMU_XG_RESET_SD_L_K VDD_USB_3V15_K F2 XG_RESET* F6 XG_RESET_SD* H4 VUSB_IO VMOD3LX A7 VMOD3SENSE B7 VMOD3LX_K VMOD3_FB_K BBPMU_32K_K A4 CLK_32K VMOD4LX H2 VMOD4SENSE G1 VMOD4LX_K VMOD4_FB_K I2C_BBPMU_SDA_K I2C_BBPMU_SCL_K F3 F4 I2CSDA I2CSCL PP_VDD_MAIN 1 L500_K 0.47UH-20%-3.8A-0.037OHM BBPMU_K PMB6848 UFWLB VSWITCH G8 GPIO1 G7 VMOD1_FB_K B3 VDIO 28 14 IN BBPMU_VCLK_K D4 VCLK 14 IN BBPMU_STBY_K G3 STBY 14 OUT BBPMU_ALERT_L_K E3 ALERT* C6 E7 TESTENTRY ANAMON VCHP_C+ C8 VCHP_C- D8 VCHP_CP_K VCHP_CN_K G2 C3 D5 H5 F7 H7 E8 B8 F8 VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VCHP C7 VDD_CHP D7 VDD_BBPMU_3V3_K PP1V8_S2 C1 C2 A3 A6 H3 VSS_VMOD1 VSS_VMOD1 VSS_VMOD2 VSS_VMOD3 VSS_VMOD4 2 XW500_K SHORT-10L-0.25MM-SM OMIT 1 D6 1 1 VRF A5 VFE_AUX B5 VREFCP F1 VSS_CHP PP_VDD_MAIN 1 R501_K 2.2K 2 1 5 6 7 8 15 1 5% 16V 2 NP0-C0G 01005 BBPMU 1 1 C512_K 27PF 1 C513_K 15UF 20% 5% 16V 2 NP0-C0G 20% 6.3V 2 CERM 01005 BBPMU 1 6.3V 2 CERM 2 3 4 5 6 11 14 0402-0.1MM BBPMU.A1 0402-0.1MM BBPMU.B4 20% 15 16 17 4 12 16 8 13 9 11 4 5 6.3V 2 CERM 28 4 VDD_BBPMU_3V3_K C506_K 15UF 12 13 2 V3V3 C5 1 IN 5 1 C505_K 15UF 20% 6.3V 2 CERM 0402-0.1MM BBPMU.A8 1 C504_K 15UF 20% 6.3V 2 CERM 0402-0.1MM BBPMU.H1 1 C503_K 15UF 5 AP_TO_MANY_BSYNC VFE_LNA_2V7_K VFE_AUX_3V1_K VDD_VREFCP_K 2 3 4 5 6 11 14 15 16 17 VPMIC_K VOTP_K VPMICREF_K 1 C508_K 0.22UF C516_K 1UF 20% 10V 2 X5R 01005 BBPMU_AGND_K PP1V8_S2 C511_K 100PF 4 VDD_SIM1_K VDD_SIM2_K PP_VDD_MAIN 1 VDD_IO_1V2_K 0201 BBPMU BBPMU.C8/D8 0201 BBPMU BBPMU.G5 5 2 20% 5 6 6 C517_K 1UF 20% 7 5 5% 1/32W MF 01005 16 6.3V 2 X5R 8 VRF_ANA_1V3_K 10V 2 X5R 1 15 6 C B 16 5 0603 5 PP1V8_S2 VOTP E6 VPMICREF G5 VRF_CORE_1V0_K 6 L503_K 1.0UH-20%-1.9A-0.120OHM 1 V1V8 F5 VPMIC E5 2 2 0805 0.7MM MAX Z 5 1 VSIM1 G6 VSIM2 H6 5 L502_K 2.2UH-20%-1.4A-0.21OHM 5 VDD_DDR_1V8_K 4 TOUCH_TO_BBPMU_FORCE_PWM_R_K BBPMU_VDIO_K BBPMU_AGND_K 4 L501_K 1.0UH-20%-2.6A-0.073OHM 5 VMOD2_FB_K BI 5 VDD_CORE_1V0_K 0805 14 NC E1 E2 A1 H1 A8 2 0805 28 VDD_VMOD1 VDD_VMOD1 VDD_VMOD2 VDD_VMOD4 VDD_VMOD3 1 1 1 2 3 4 5 6 11 14 15 16 1 C518_K 2.2UF 20% 6.3V 2 X5R-CERM 0402 BBPMU 1 C519_K 1UF 20% 10V 2 X5R 0201 BBPMU BBPMU.F1 1 C520_K 10UF 20% 10V 2 X5R-CERM 0402-0.1MM 1 C521_K 10UF 20% 10V 2 X5R-CERM 0402-0.1MM 1 C523_K 0.47UF 20% 6.3V 2 X5R 01005 BBPMU 1 C509_K 0.47UF 20% 6.3V 2 X5R 01005 BBPMU 1 B C522_K 4.7UF 20% 10V 2 X5R 0402-1 BBPMU 17 C507_K 15UF 20% 6.3V 2 CERM 0402-0.1MM 0402-0.1MM BBPMU.E2 XW501_K 6 5 4 VDD_CORE_1V0_K SHORT-20L-0.05MM-SM 1 2 VMOD1_FB_K OMIT VRF_CORE_1V0_K SHORT-20L-0.05MM-SM 1 2 VMOD2_FB_K OMIT VRF_ANA_1V3_K SHORT-20L-0.05MM-SM 1 2 VMOD3_FB_K OMIT VDD_IO_1V2_K SHORT-20L-0.05MM-SM 1 2 VMOD4_FB_K OMIT 5 XW502_K 6 5 5 XW503_K 6 5 5 XW504_K 5 4 A 1 C500_K 20UF 20% 6.3V 2 CERM-X5R 0402 BBPMU 1 C501_K 20UF 20% 6.3V 2 CERM-X5R 0402 BBPMU 1 C502_K 20UF 20% 6.3V 2 CERM-X5R 0402 BBPMU 1 C514_K 20UF 20% 6.3V 2 CERM-X5R 0402 BBPMU 1 5 A C515_K 20UF PAGE TITLE BASEBAND PMIC 20% 6.3V 2 CERM-X5R 0402 BBPMU DRAWING NUMBER Apple Inc. 051-02247 REVISION 7.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 5 OF 17 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST 8 7 6 SHEET 17 OF 34 IV ALL RIGHTS RESERVED 5 4 3 2 1 SIZE D 8 7 6 5 4 3 2 1 TRANSCEIVERS XCVR0_K PMB5757 UFWLB SYM 5 OF 5 B3 B9 C12 C16 C2 C4 C8 D3 F15 F3 F5 F9 H11 H15 H3 H5 H7 J4 K3 L12 L4 L8 M13 M15 M3 P13 P3 R10 R12 R6 R8 T13 T3 T5 U10 U12 U14 LAYOUT: TRACE SHOULD B1 ~1NH/1MM XW600_K LAYOUT: TRACE SHOULD B1 ~1NH/1MM R615_K 0.00 2 1 SHORT-10L-0.25MM-SM 6 1 VRF_ANA_1V3_K 5 1 D 2 6 OMIT C645_K 0.1UF 1 10% VDD_XCVR0_1V3_K 1 C604_K 15UF 20% 6.3V 2 CER-X5R 1 C609_K 0.1UF 20% 6.3V 2 CERM 01005 XCVR 6 0402-0.1MM 20% 6.3V 2 X5R-CERM 01005 XCVR LAYOUT: MAX DCR 85MOHM 6 5 VRF_CORE_1V0_K 0% 1/32W MF 01005 XCVR 1 1 C605_K 0.47UF 20% 6.3V 2 X5R-CERM 01005 XCVR 01005 XCVR VDD_XCVR0_1V3_K 6 C610_K 0.1UF 20% 6.3V 2 X5R 6.3V 2 X5R-CERM 01005 XCVR 01005 XCVR NOSTUFF FL601_K 600-OHM-25%-0.1A 14 11 6 5 4 3 2 17 16 1 15 1 PP1V8_S2 2 1 1 C606_K 15UF 20% 6.3V 2 CERM 16 6 15 5 8 1 7 R604_K 0.00 2 1 PP_VDD_MAIN 1 C C602_K 100PF 5% 16V 2 NP0-C0G 01005 XCVR 1 C603_K 27PF 5% 16V 2 NP0-C0G 01005 XCVR 1 C607_K 0.47UF 20% 6.3V 2 X5R 01005 XCVR 1 C639_K 0.022UF 10% 10V 2 X5R 0201 1 C640_K 0.022UF 10% 10V 2 X5R 0201 1 C641_K 0.022UF 10% 10V 2 X5R 0201 1 01005 XCVR VDD0V68_RET L14 E14 H9 N6 N14 K7 VDD1V3_MPHY VDD1V3_CI VDD1V3_TXPLL VDD1V3_RX1PLL VDD1V3_RX2PLL VDD1V3_RXMS C6 B1 VDD1V3_TXDIG VDD1V3_TXRF 01005 XCVR U4 VDD1V3_RXRF C14 VDD1V3_TXMS K15 VDD1V0_DIG C611_K 0.1UF VDD_XCVR0_1V8_K 6 20% 6.3V 2 X5R-CERM 01005 XCVR NOSTUFF VDD_XCVR0_BAT_K 6 C608_K 1UF 28 18 13 12 13 12 OUT IN 20% 10V 2 X5R 0201 XCVR 6 6 14 28 IN 14 IN 18 17 15 IN 15 IN 6 6 B 14 OUT 14 OUT 14 OUT 14 28 14 28 14 OUT IN IN 14 OUT 14 OUT 14 OUT 14 OUT 14 IN 14 IN BB_TO_NFC_CLK NFC_TO_BB_CLK_REQ XCVR1_26MHZ_K XCVR1_26MHZ_EN_K 01005 XCVR 1 C628_K 0.1UF 20% C632_K 0.1UF 20% 6.3V 2 X5R-CERM 6.3V 2 X5R-CERM 01005 XCVR 01005 XCVR 6 LAYOUT: MAX DCR 85MOHM 6 5 R616_K 0.00 2 1 VRF_CORE_1V0_K 0% 1/32W MF 01005 XCVR 16 15 14 11 6 5 4 3 2 1 1 PP1V8_S2 1 1 C624_K 0.47UF 20% 2 15 8 7 6 5 1 R607_K 0.00 2 1 PP_VDD_MAIN 1 0% 1 C622_K 1/32W MF 27PF 01005 5% XCVR 16V 2 NP0-C0G 01005 XCVR C621_K 100PF 5% 16V 2 NP0-C0G 01005 XCVR CELL_CLK_EN J12 CELL_CLK J14 GPO0 GPO1 GPO2 GPO3 GPO4 GPO5 GPO6 MPHY_EN MPHY2_EN RESET_MAIN* RESET_TRX* SYSCLK_26MHZ_EN_K SYSCLK_26MHZ_K J6 K5 L6 P11 N10 T7 T11 IN OUT NC NC NC XCVR0_TSYNC_OUT_K XCVR0_TSYNC_IN_K XCVR0_MSYNC_OUT_K XCVR0_MSYNC_IN_K 1 C625_K 15UF 10% 10V X5R 0201 6 10% 10V X5R 0201 6 10% 10V X5R 0201 1 MPHY_RX1_DAT MPHY_RX1_DATX MPHY_RX2_DAT MPHY_RX2_DATX MPHY_TX_DAT MPHY_TX_DATX D7 VDD1V3_TXDCO 01005 XCVR U4 VDD1V3_RXRF C14 VDD1V3_TXMS MPHY2_RX1_DAT MPHY2_RX1_DATX MPHY2_RX2_DAT MPHY2_RX2_DATX MPHY2_TX_DAT MPHY2_TX_DATX 6 C631_K 0.1UF 20% 6.3V 2 X5R-CERM 01005 XCVR NOSTUFF 28 27 IN 15 IN RFFE2_SCLK M7 RFFE2_SDATA M5 VDD_XCVR1_BAT_K D13 VDD_BAT CEXT1_RX2PLL_K CEXT1_TXPLL_K CEXT1_RX1PLL_K CEXT1_TXMAG_K N12 J8 P7 B5 CEXT_RX2PLL CEXT_TXPLL CEXT_RX1PLL CEXT_TXMAG F13 M11 G12 E12 FSYS_RF FSYS_RF_EN_CLK_ON FSYS_C FSYS_C_EN 6 RFFE2_CLK_R_K RFFE2_DATA_R_K XO_SUP D17 AFCDAC D15 XO B17 6 XO_SUP_K AFC_DAC_K VCXO_26MHZ_K 28 OUT OUT 18 19 20 21 23 24 25 6 16 6 16 14 OUT 14 OUT 14 OUT 14 OUT 28 14 28 14 IN 28 14 OUT 28 14 OUT 14 OUT IN 28 14 OUT 6 14 IN 6 14 IN XCVR1_JTAG_TMS_K XCVR1_JTAG_TCK_K K9 TMSC J10 TCKC 90_DIGRF_M1_RX1_P_K 90_DIGRF_M1_RX1_N_K 90_DIGRF_M1_RX2_P_K 90_DIGRF_M1_RX2_N_K 90_DIGRF_M1_TX_P_K 90_DIGRF_M1_TX_N_K G16 H17 E16 F17 J16 K17 MPHY_RX1_DAT MPHY_RX1_DATX MPHY_RX2_DAT MPHY_RX2_DATX MPHY_TX_DAT MPHY_TX_DATX 90_DIGRF_A1_RX1_P_K 90_DIGRF_A1_RX1_N_K 90_DIGRF_A1_RX2_P_K 90_DIGRF_A1_RX2_N_K 90_DIGRF_A1_TX_P_K 90_DIGRF_A1_TX_N_K P17 N16 T17 R16 M17 L16 MPHY2_RX1_DAT MPHY2_RX1_DATX MPHY2_RX2_DAT MPHY2_RX2_DATX MPHY2_TX_DAT MPHY2_TX_DATX 6 6 XCVR0_JTAG_TMS_K XCVR1_JTAG_TMS_K XCVR0_JTAG_TCK_K XCVR1_JTAG_TCK_K A 1% 1/32W MF 2 01005 XCVR C601_K 4700PF OUT 6 5 4 VDD_CORE_1V0_K 01005 XCVR 16 6 R610_K 0.00 2 1 RFFE2_DATA_R_K VDD_CORE_1V0_K 1 RFFE2_DATA_K BI D C XCVR XCVR1_K PMB5757 GPO0 GPO1 GPO2 GPO3 GPO4 GPO5 GPO6 J6 K5 L6 P11 N10 T7 T11 RFFE_SDATA P9 RFFE_SCLK N8 RFFE_VIO M9 RFFE2_SCLK M7 RFFE2_SDATA M5 XO_SUP D17 AFCDAC D15 XO B17 XCVR1_RFE_GPO0_K NC NC XCVR0_TSYNC_IN_K XCVR0_TSYNC_OUT_K XCVR0_MSYNC_IN_K XCVR0_MSYNC_OUT_K OUT UFWLB 20 SYM 5 OF 5 6 6 6 6 NC NC RFFE1_DATA_K RFFE1_CLK_K VDD_RFFE_VIO_1V8_K RFFE2_CLK_R_K RFFE2_DATA_R_K NC NC XCVR1_26MHZ_K BI 18 19 20 21 23 24 28 OUT 18 19 20 21 23 24 28 OUT 18 19 20 21 23 24 25 28 6 16 6 16 6 6 C649_K 0.1UF B3 B9 C12 C16 C2 C4 C8 D3 F15 F3 F5 F9 H11 H15 H3 H5 H7 J4 K3 L12 L4 L8 M13 M15 M3 P13 P3 R10 R12 R6 R8 T13 T3 T5 U10 U12 U14 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 20% 0% 1/32W MF 01005 XCVR 01005 A 1P6X1P2-SM 6 6 AFC_DAC_K 1 VCONT OUT 3 PAGE TITLE VCXO_26MHZ_K NFC_TO_BB_CLK_REQ 1 C600_K 0.022UF TRANSCEIVERS 6 1 6 6 5 4 VDD_CORE_1V0_K VDD_CORE_1V0_K 6 DRAWING NUMBER GND 1 XCVR 10% 6.3V 2 X6S 0201-1 R606_K 100K 1 1% 1/32W MF 2 01005 XCVR Apple Inc. C650_K 0.1UF 20% 6.3V 2 X5R-CERM 01005 051-02247 REVISION 7.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 6 OF 17 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE NOTE: GNSS_CLK REQUESTED WITH AT@CMD II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST 8 U16 U6 U8 V3 B 6.3V 2 X5R-CERM 25 U16 U6 U8 V3 NC 25 10% 6.3V 2 X5R VTCXO_K 26MHZ-6PPM-1.8V 6 RFFE2_CLK_K 0% 1/32W MF 01005 VCC 1 1% 1/32W MF 2 01005 XCVR RFFE2_CLK_R_K 6 6 R601_K R603_K 562K 562K 1 4 5% 1/32W MF 2 01005 XCVR 6 R609_K 0.00 2 1 XO_SUP_R_K 0% 1/32W MF 01005 XCVR 1 R600_K R602_K 27K 27K 5% 1/32W MF 2 01005 XCVR 1 XO_SUP_K 16 2 1 6 R605_K 0.00 2 1 CELL_CLK_EN J12 CELL_CLK J14 XCVR VCTCXO 6 01005 MI3 C10 MI4 D11 XCVR VDD_XCVR1_1V8_K VDD_XCVR0_1V8_K 01005 XCVR 20% 6.3V 2 X5R SMARTI6T VDD1V8_CI VDD1V8_RX VDD1V8_TX MPHY_EN MPHY2_EN RESET_MAIN* RESET_TRX* 20% 6.3V 2 X5R-CERM C638_K 0.22UF UFWLB G14 T9 D5 F11 K11 K13 H13 1 C637_K 0.1UF SYM 1 OF 5 VDD_XCVR1_1V8_K DIGRF_M1_EN_K DIGRF_A1_EN_K BBPMU_PWRGOOD_K XCVR1_RESET_L_K 1 XCVR1_K PMB5757 6 6 28 01005 XCVR VDD1V0_DIG OUT 18 17 15 20% K15 XCVR1_26MHZ_EN_K GNSS_26MHZ_CLKOUT_K C636_K 0.1UF 6.3V 2 X5R-CERM VRF_XCVR1_1V0_K 6 20% 10V 2 X5R 0201 XCVR 1 6 NC C627_K 1UF IN 24 VDD1V3_TXDIG VDD1V3_TXRF 20% IN 24 C6 B1 VDD1V3_RX1DCO 14 18 19 20 21 23 VDD1V3_MPHY VDD1V3_CI VDD1V3_TXPLL VDD1V3_RX1PLL VDD1V3_RX2PLL VDD1V3_RXMS VDD0V68_RET N4 14 18 19 20 21 23 VDD_XCVR1_1V3_K L14 E14 H9 N6 N14 K7 C630_K 0.1UF 6 BI L10 VDD1V3_RX2DCO 6 RFFE1_DATA_K RFFE1_CLK_K VDD_RFFE_VIO_1V8_K 01005 XCVR VDD_CORE_1V0_K 6 NC NC RFFE_SDATA P9 RFFE_SCLK N8 RFFE_VIO M9 20% R14 28 MI3 C10 MI4 D11 C635_K 0.1UF 6.3V 2 X5R-CERM 01005 XCVR 6.3V 2 X5R-CERM 1 C626_K 0.47UF 20% 6.3V 2 X5R 01005 XCVR C644_K 0.022UF 20% 6.3V 2 X5R-CERM 01005 XCVR NOSTUFF 14 28 C643_K 0.022UF 01005 XCVR 1 C634_K 0.1UF 6.3V 2 X5R-CERM 14 C642_K 0.022UF 20% 6.3V 2 X5R-CERM 1 C629_K 0.1UF VDD_XCVR1_BAT_K 1 C633_K 0.1UF 6 VDD_XCVR1_1V8_K 1 1 20% 6.3V 2 X5R 0402-0.1MM 16 6 VRF_XCVR1_1V0_K 20% FSYS_RF FSYS_RF_EN_CLK_ON FSYS_C FSYS_C_EN P17 N16 T17 R16 M17 L16 1 6.3V 2 CERM F13 M11 G12 E12 90_DIGRF_A0_RX1_P_K 90_DIGRF_A0_RX1_N_K 90_DIGRF_A0_RX2_P_K 90_DIGRF_A0_RX2_N_K 90_DIGRF_A0_TX_P_K 90_DIGRF_A0_TX_N_K 0402-0.1MM 0201-1 XCVR CEXT_RX2PLL CEXT_TXPLL CEXT_RX1PLL CEXT_TXMAG G16 H17 E16 F17 J16 K17 20% 6.3V 2 CERM 01005 XCVR NOSTUFF 17 N12 J8 P7 B5 90_DIGRF_M0_RX1_P_K 90_DIGRF_M0_RX1_N_K 90_DIGRF_M0_RX2_P_K 90_DIGRF_M0_RX2_N_K 90_DIGRF_M0_TX_P_K 90_DIGRF_M0_TX_N_K 01005 C623_K 15UF FL600_K 600-OHM-25%-0.1A VDD_BAT K9 TMSC J10 TCKC 5% 1 VDD_XCVR1_1V3_K 01005 XCVR D13 XCVR0_JTAG_TMS_K XCVR0_JTAG_TCK_K 0% 1/32W MF 01005 XCVR C5945_K 27PF 16V 2 NP0-C0G SMARTI6T VDD1V8_CI VDD1V8_RX VDD1V8_TX F11 K11 K13 H13 20% 6.3V 2 X5R SYM 1 OF 5 G14 T9 D5 DIGRF_M0_EN_K DIGRF_A0_EN_K BBPMU_PWRGOOD_K XCVR0_RESET_L_K 01005 XCVR 1 C620_K 0.22UF UFWLB VDD1V3_TXDCO VRF_XCVR0_1V0_K 6.3V 2 X5R-CERM 1 6 XCVR0_K PMB5757 D7 6 C619_K 0.1UF 20% 6.3V 2 X5R-CERM 01005 XCVR 20% 6 1 C617_K 0.1UF 20% 6.3V 2 X5R-CERM VDD1V3_RX1DCO CEXT0_RX2PLL_K CEXT0_TXPLL_K CEXT0_RX1PLL_K CEXT0_TXMAG_K 1 20% 6.3V 2 X5R-CERM N4 C612_K 0.1UF VDD_XCVR0_BAT_K 0% 1/32W MF 01005 XCVR 20% 1 C616_K 0.1UF VDD1V3_RX2DCO 6 6.3V 2 X5R-CERM 0402-0.1MM 1 C615_K 0.1UF R14 VDD_XCVR0_1V8_K 0201-1 XCVR 1 L10 VDD_CORE_1V0_K 6 VRF_XCVR0_1V0_K C614_K 0.1UF 20% 6.3V 2 X5R-CERM 6 R614_K 0.00 2 1 1 C613_K 0.1UF VRF_ANA_1V3_K 5 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 7 6 SHEET 18 OF 34 IV ALL RIGHTS RESERVED 5 4 3 2 1 SIZE D 8 7 6 5 4 3 2 1 ET MODULATOR D D ALPES II MODULE XW701_K SHORT-10L-0.25MM-SM 15 8 6 5 1 PP_VDD_MAIN 1 OMIT ET 2 PP_VDD_MAIN_ET_K 1 1 C720_K 2.2UF 20% 10% 6.3V 2 X5R-CERM 10V 2 X5R 0201 ET OMIT_TABLE 01005 ET 1 C722_K 100PF 5% 16V 2 NP0-C0G 01005 ET 1 9 C723_K 27PF 5% 16V 2 NP0-C0G 01005 ET C PVDD 3 C C721_K 1000PF VPA_ET_K 8 VCC2 26 16 ET_K QM81004M 16 16 8 16 8 13 12 11 9 8 6 16 12 11 9 8 6 16 12 11 9 8 6 8 VRAMP7 VRAMP+ 50_ET_DAC_N_K 50_ET_DAC_P_K LGA 15 VIO 17 DATA 16 CLK VDD_RFFE_VIO_1V8_K RFFE1_DATA_K RFFE1_CLK_K THERM PAD 27 28 29 30 31 32 1 2 4 5 6 9 10 11 12 13 14 18 19 20 21 22 23 24 25 GND USID=0XC B B A A PAGE TITLE ET MODULATOR DRAWING NUMBER Apple Inc. 051-02247 REVISION 7.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 7 OF 17 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST 8 7 6 SHEET 19 OF 34 IV ALL RIGHTS RESERVED 5 4 3 2 1 SIZE D 8 7 6 5 4 3 TDD TRANSMIT 2 1 2G PA XW800_K SHORT-10L-0.25MM-SM 28 27 19 18 17 13 12 IN PP_VDD_MAIN 1 2 PP_VDD_MAIN_2G_K OMIT 1 1 C803_K 15UF 20% 1 C805_K 100PF 5% 6.3V 2 CERM 10% 16V 2 NP0-C0G 0402-0.1MM C807_K 3300PF 6.3V 2 X5R 01005 RFFE 01005 RFFE 1 1 C808_K 18PF 2% C800_K 0.1UF 20% 16V 2 CERM 6.3V 2 X5R-CERM 01005 RFFE 01005 RFFE D D 1 4 11 L800_K 3.0NH+/-0.1NH-0.6A VBATT VCC GSMPA_K SKY77367 UFWLB 28 SYM 3 OF 5 PADACFN A12 PADACFP B13 50_ET_DAC_N_K 50_ET_DAC_P_K 25 24 23 21 20 19 18 IN R801_K 0.00 2 1 VDD_RFFE_VIO_1V8_K 0% 1/32W MF 01005 19 20 28 OUT 19 20 28 OUT 28 24 23 21 20 28 24 23 21 20 TX2GHB TX2GLB TX25 TX35 TXH TXL C B11 B7 A4 A2 A10 A8 50_XCVR0_2GMB_TX_K 50_XCVR0_2GLB_TX_K 8 NC NC 50_XCVR0_B3_B4_B1_B25_TX_K 50_XCVR0_LB_TX_K 0.033UF 20% 6.3V 2 CER-X5R 01005 1710-1910 C811_K 0.5PF 0201 RFFE NOSTUFF NC 15 RFIN_MB_1 RFOUT_MB 8 50_2GMB_PA_OUT_M_K 16 RFIN_MB_0 RFOUT_LB 1 50_2GLB_PA_OUT_M_K 14 VIO 12 SDATA 13 SCLK GND 1710-1910 824- 915 8 21 OUT +/-0.05PF NC VDD_RFFE_VIO_1V8_2G_K RFFE1_DATA_K 19 18 BI RFFE1_CLK_K 19 18 IN 1C801_K 50_2GMB_PA_OUT_K 25V 2 COG-CERM 10 RFIN_LB_1 50_XCVR0_2GMB_TX_K 8 LGA 1 C815_K 18PF L803_K 0.00 2 1 EPAD 2 3 5 6 7 XCVR0_K PMB5757 1 17 XCVR0 TX 9 RFIN_LB_0 50_XCVR0_2GLB_TX_K 8 2 0201 RFFE USID=0X5 2% 16V 2 CERM 01005 NOSTUFF 1 C812_K 3900PF 50_2GLB_PA_OUT_K 824- 915 OUT 0% 1/32W MF 01005 10% OUT 21 OUT 21 6.3V 2 CERM-X5R 1710-1980 699- 915 01005 C XCVR MB HB TDD S-PAD 20% 6.3V 2 X5R-CERM 01005 RFFE UFWLB SYM 3 OF 5 11 TX2GHB TX2GLB TX25 TX35 TXH TXL B11 B7 A4 A2 A10 A8 OUT 19 20 28 OUT 19 20 28 8 5 2 RFIN 8 OUT 16V 2 NP0-C0G 01005 2% 16V 2 CERM 01005 RFFE VFE_AUX_3V1_K NC NC 50_XCVR1_2P5G_TX_K NC 50_XCVR1_B34_B39_TX_K 50_XCVR1_LB_TX_K +/-0.1PF C806_K 18PF 21 1880-2025 699- 915 XCVR 18 IN XCVR1_RFE_GPO0_K 0 RFIN<->RF1 1 RFIN<->RF2 VDD 8 50_XCVR1_B34_B39_TX_K 3 SWTX1_K CXA4430GC-E 8 50_XCVR1_B38_B40_B41_TX_K 5 LGA RF1 4 RF2 6 50_XCVR1_B7_B30_TX_K 50_XCVR1_B38_B40_B41_TX_K OUT 8 21 RFIN_MB RFIN_HB 18PF BI IN 18 19 20 21 23 18 19 20 21 23 18 19 20 21 23 24 24 24 25 28 28 28 2% 16V 2 CERM 01005 RFFE B TDDPA_K MB-HB-TDD-PAD 3 50_ET_DAC_N_K 50_ET_DAC_P_K 9 LGA-3 ANT 16 50_TDD_PAD_ANT_M_K 2305-2570 2300-2690 1 1 CTRL C813_K 0.5PF +/-0.05PF R800_K 0.00 2 1 50_TDD_PAD_ANT_K OUT 21 1% 1/20W MF 0201 25V 2 COG-CERM 0201 NOSTUFF GND 5 PADACFN A12 PADACFP B13 1 1C810_K IN SCLK 13 C804_K 0.1UF C809_K 5.6PF VDD_RFFE_VIO_1V8_K RFFE1_DATA_K RFFE1_CLK_K SDATA 12 5 1 VIO 14 8 1 XCVR1_K PMB5757 B 9 VFE_AUX_3V1_K VCC2 9 11 VPA_ET_K VCC1 8 XCVR1 TX 7 VBATT 11 9 XCVR 22 OUT 50_XCVR1_B38_B40_B41_RX_K 27 RX_B38_B40_B41 22 OUT 50_XCVR1_B34_B39_RX_K 25 RX_B34_B39 THRM_PAD 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 1 2 4 6 7 10 15 17 19 21 22 24 26 28 23 20 18 GND USID=0XF A A PAGE TITLE TDD TRANSMIT DRAWING NUMBER Apple Inc. 051-02247 REVISION 7.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 8 OF 17 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST 8 7 6 SHEET 20 OF 34 IV ALL RIGHTS RESERVED 5 4 3 2 1 SIZE D 8 7 6 5 4 3 2 1 FDD TRANSMIT 5 VFE_AUX_3V1_K 1 1 1 C903_K 0.1UF 20% 16V 2 CERM 01005 RFFE D 20 20 2% 16V 2 CERM 01005 C904_K 18PF 2% 6.3V 2 X5R-CERM 1 C900_K 18PF 01005 RFFE IN 50_XCVR0_LB_TX_K 2 RFIN0 IN 50_XCVR1_LB_TX_K 3 RFIN1 VDD_RFFE_VIO_1V8_K RFFE1_DATA_K RFFE1_CLK_K C906_K 22PF 5% 16V 2 CERM 01005-1 18 19 20 21 23 IN 24 18 19 20 21 23 BI 18 19 20 21 23 IN 24 24 25 28 28 28 D SCLK 9 8 SDATA 8 9 VIO 10 VPA_ET_K VCC2 40 7 VCC1 41 8 VBATT 7 11 9 LBPA_K QM76041 L901_K 0.6NH-+/-0.1NH-0.73A-0.1OHM LGA 1 50_LAT_LB_M_K 2 50_LAT_LB_K BI 23 824-915 BI 23 824-915 01005 20 24 IN OUT 50_2GLB_PA_OUT_K 18 50_LB_DRX_K 12 2G_TX LB S-PAD LB_DIV 22 OUT 50_XCVR0_LB_RX_K 26 LB_RX0 22 OUT 50_XCVR1_LB_RX_K 25 LB_RX1 22 OUT 50_XCVR0_VLB_RX_K 24 VLB_RX0 22 OUT 50_XCVR1_VLB_RX_K 23 VLB_RX1 1 ANT1 16 C902_K 0.8PF +/-0.05PF 16V 2 C0G-CERM ANT2 14 01005 L903_K 1.1NH-+/-0.1NH-0.85A 1 50_UAT_LB_M_K GND THRM_PAD 1 50_UAT_LB_K C909_K 1.6PF 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 1 4 5 6 11 13 15 17 19 20 21 22 27 28 29 30 31 32 33 34 35 36 37 38 39 42 2 01005 RFFE +/-0.1PF 16V 2 NP0-C0G 01005 RFFE NOSTUFF USID=0XD C C 11 9 8 7 VPA_ET_K 9 8 5 VFE_AUX_3V1_K 1 C907_K 22PF 2% 16V 2 CERM 1 C905_K 22PF 5% 16V 2 CERM 01005 VDD_RFFE_VIO_1V8_K RFFE1_DATA_K RFFE1_CLK_K 01005-1 IN 18 19 20 21 23 18 19 20 21 23 BI IN 18 19 20 21 23 24 24 24 25 28 28 28 B IN 20 IN 20 IN 20 22 IN OUT 24 OUT 22 OUT 22 OUT 22 OUT 22 OUT 22 OUT 22 OUT 22 OUT 50_TDD_PAD_ANT_K 50_XCVR1_B40B_NO_FILT_RX_K 7 8 27 28 26 37 38 VIO SCLK RFIN_GSM RFIN_MB RFIN_HB VCC2 34 31 32 VCC1 50_2GMB_PA_OUT_K 50_XCVR0_B3_B4_B1_B25_TX_K 50_XCVR1_B7_B30_TX_K SDATA 20 VBATT 29 B C901_K 5.0PF MHBPA_K AFEM-8056-AP1 1 50_LAT_MB_HB_M_K 1 LGA TRX2 TRX3 50_LAT_MB_HB_DRX_K 50_XCVR0_2G_RX_K 10 11 50_XCVR0_B1_B4_RX_K 50_XCVR0_B3_RX_K 50_XCVR1_B7_RX_K 50_XCVR0_B4_B66_RX_K 50_XCVR0_B25_RX_K 50_XCVR1_B30_RX_K 1 RX_B1 3 RX_B3 5 RX_B7 17 RX_B66 19 RX_B25 21 RX_B30 MB_HB_DRX DCS_PCS_RX MB/HB S-PAD ANT1 14 ANT2 13 2 50_LAT_MB_HB_K BI +/-0.1PF 25V C0G 0201 RFFE 23 1710-2690 L900_K 10NH-3%-0.3A 0201 RFFE 2 L902_K 1.0NH-+/-0.1NH-0.9A-0.05OHM 1 50_UAT_MB_HB_M_K 2 50_UAT_MB_HB_K BI 23 1710-2690 01005 1 GND +/-0.1PF EPAD 16V 2 NP0-C0G 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 2 4 12 15 16 18 20 22 23 24 25 30 33 35 36 39 40 41 42 6 9 C908_K 1.0PF 01005 RFFE NOSTUFF USID=0XE A A PAGE TITLE FDD TRANSMIT DRAWING NUMBER Apple Inc. 051-02247 REVISION 7.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 9 OF 17 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST 8 7 6 SHEET 21 OF 34 IV ALL RIGHTS RESERVED 5 4 3 2 1 SIZE D 8 7 6 5 4 3 2 1 PRIMARY RECIEVE L1001_K 22NH-3%-0.14A-2.26OHM 10 1 50_XCVR0_VLB_RX_M_K 2 50_XCVR0_VLB_RX_K IN 21 01005 XCVR L1016_K 15NH-3%-0.17A-1.53OHM D 10 1 50_XCVR1_VLB_RX_M_K 2 L1030_K 10NH-+/-3%-0.25A 10 1 50_XCVR0_LB_RX_M_K 2 50_XCVR0_LB_RX_K 01005 XCVR IN 10 R1000_K 0.00 2 1 1 50_XCVR1_LB_RX_M_K 2 0% 1/32W MF 01005 XCVR 21 SYM 2 OF 5 IN 23 RX1 RX2 RX3 RX4 RX5 RX6 RX7 RX8 RX9 RX10 RX11 RX12 RX13 RX14 RX15 RX16 W2 V1 U2 T1 R2 P1 N2 M1 L2 K1 J2 H1 G2 F1 E2 D1 50_XCVR0_B3_RX_M_K 50_XCVR0_GSM1900_RX_M_K 10 10 1 50_XCVR0_B4_B66_RX_M_K 2 50_XCVR0_B4_B66_RX_K 1 50_XCVR0_B4_B66_RX_M_K 50_XCVR0_GSM1800_RX_M_K 50_XCVR0_B1_B4_RX_M_K 50_XCVR0_B25_RX_M_K 50_XCVR0_VLB_RX_M_K 10 10 10 10 10 2110-2155 1805-1880 2110-2170 50_XCVR0_LB_RX_M_K 10 IN 21 L1010_K 2.4NH-+/-0.1NH-0.45A RX1 RX2 RX3 RX4 RX5 RX6 RX7 RX8 RX9 RX10 RX11 RX12 RX13 RX14 RX15 RX16 01005 XCVR XCVR L1009_K 1.6PF 1930-1995 L1004_K 1.2NH-+/-0.1NH-0.80A 10 1 50_XCVR0_B25_RX_M_K 2 50_XCVR0_B25_RX_K 01005 XCVR 852- 960 IN 21 1 XCVR L1017_K 0.00 50_XCVR1_B30_RX_M_K 50_XCVR1_LAT_CPLR_K 50_XCVR1_UAT_CPLR_K IN 23 IN 23 50_XCVR1_B30_RX_K 0% 1/32W MF 01005 1 L1024_K 3.3NH-+/-0.1NH-0.4A-0.25OHM 01005 XCVR +/-0.1PF 2 16V NP0-C0G 01005 XCVR 717- 821 10 FBRRF1 A16 FBRRF2 A14 VSS B15 01005 XCVR 1805-1880 1930-1990 2 SYM 2 OF 5 L1003_K 3.9NH+/-0.1NH-180MA 10 21 01005 XCVR UFWLB 2 23 IN 1 L1023_K 18NH-3%-0.16A-1.63OHM XCVR1_K PMB5757 01005 XCVR IN 21 XCVR1 PRX 1 UFWLB C IN L1027_K 3.3NH+/-0.1NH-180MA 50_XCVR0_LAT_CPLR_K 50_XCVR0_UAT_CPLR_K IN 01005 XCVR 50_XCVR0_B1_B4_RX_K XCVR0_K PMB5757 FBRRF1 A16 FBRRF2 A14 VSS B15 50_XCVR1_LB_RX_K W2 V1 U2 T1 R2 P1 N2 M1 L2 K1 J2 H1 G2 F1 E2 D1 50_XCVR1_B7_RX_M_K 50_XCVR1_B30_RX_M_K 10 10 50_XCVR1_B38_B40_B41_RX_M_K 50_XCVR1_LB_RX_M_K 50_XCVR1_B40B_NO_FILT_RX_M_K 10 10 10 2620-2690 2350-2360 L1018_K 1.0NH+/-0.1NH-0.22A-0.9OHM 2300-2690 852- 960 2300-2400 50_XCVR1_VLB_RX_M_K 10 717- 821 50_XCVR1_B34_B39_RX_M_K 10 1880-2025 10 50_XCVR1_B7_RX_M_K 1 2 50_XCVR1_B7_RX_K 1 2 1 IN 20 L1015_K 1.5NH+/-0.1NH-220MA 01005 XCVR 2 L1019_K 7PF 10 1 50_XCVR1_B38_B40_B41_RX_M_K 2 50_XCVR1_B38_B40_B41_RX_K 1 +/-0.1PF 16V NP0-C0G 01005 XCVR L1025_K 1.3NH-+/-0.1NH-0.7A-0.08OHM 2 IN 21 1 10 50_XCVR1_B34_B39_RX_M_K L1020_K 0.00 2 1 L1011_K 2.6NH-+/-0.1NH-0.45A-0.2OHM B 21 01005-1 XCVR 50_XCVR0_B3_RX_K 01005 XCVR IN 01005 2 50_XCVR0_B3_RX_M_K C 2 L1005_K 3.6NH+/-0.1NH-180MA 10 D L1000_K 8.2NH-3%-0.3A-0.5OHM 2 XCVR0 PRX 21 1 01005 XCVR NOSTUFF 50_XCVR0_B1_B4_RX_M_K IN 21 L1008_K 9.1NH-3%-0.17A-1.7OHM 10 50_XCVR1_VLB_RX_K 01005 XCVR 50_XCVR1_B34_B39_RX_K 0% 1/32W MF 01005 XCVR 01005 XCVR NOSTUFF IN 20 1 B L1026_K 3.6NH-+/-0.1NH-0.35A-0.3OHM 2 01005 2 L1021_K 2.4NH-+/-0.1NH-0.45A 10 50_XCVR1_B40B_NO_FILT_RX_M_K 1 2 50_XCVR1_B40B_NO_FILT_RX_K 01005 1 IN 21 C1001_K 2.0PF +/-0.1PF 16V 2 NP0-C0G GSMDI_K GSM1800-1900 B8867 LGA L1006_K 0.6NH+/-0.1NH-320MA 10 1 50_XCVR0_GSM1800_RX_M_K 2 01005 XCVR 01005 XCVR 50_XCVR0_GSM1800_RX_K 4 GSM1800 50_XCVR0_GSM1900_RX_K 3 GSM1900 COMMON 1 1 50_XCVR0_2G_RX_K 21 1 L1012_K 3.0NH+/-0.1NH-200MA L1014_K 3.6NH-+/-0.1NH-0.35A-0.3OHM GND 01005 2 5 6 01005 XCVR IN 2 L1007_K 1.3NH+/-0.1NH-220MA A 10 50_XCVR0_GSM1900_RX_M_K 1 2 A 2 01005 1 PAGE TITLE PRIMARY RECEIVE L1013_K 3.0NH+/-0.1NH-200MA DRAWING NUMBER Apple Inc. 01005 XCVR 051-02247 REVISION 7.0.0 2 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 10 OF 17 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST 8 7 6 SHEET 22 OF 34 IV ALL RIGHTS RESERVED 5 4 3 2 1 SIZE D 8 7 6 5 4 3 2 1 LOWER ANTENNA AND COUPLER LOWER ANTENNA COUPLER D LATDI_K DPX202690DT-4090A2SJ 21 BI BI 50_LAT_MB_HB_K HI 50_LAT_LB_MB_HB_M_K 1 8 5 VFE_AUX_3V1_K 1 2 LO 1 1 3 5 GND 2% C1100_K 0.7PF +/-0.05PF NC FL1100_K 10-OHM-1.1A 23 21 20 19 18 1 VDD_RFFE_VIO_1V8_K IN 2 01005 1 01005 RFFE 01005 RFFE 1 C1111_K 0.033UF 20% 28 24 23 21 20 19 18 BI 28 24 23 21 20 19 18 IN 1 13 RFIN1 RFIN2 6 USID 5 12 8 VDD_RFFE_VIO_LATCP_1V8_K RFFE1_DATA_K RFFE1_CLK_K RFOUT1 RFOUT2 2 14 RF_CPL1 RF_CPL2 4 16 LGA VIO SDATA SCLK C1109_K 5PF C1103_K 56PF 1 50_LAT1_CPL_K NC 2 50_LAT1_ANT_K 5% 25V NP0-C0G-CERM 01005 50_XCVR0_LAT_CPLR_K 50_XCVR1_LAT_CPLR_K OUT 22 OUT 22 29 OUT 1 L1100_K 56NH-100MA-3.9OHM 2 0201 UP_RFFE FOR ESD AND LOW FREQUENCY IMD GND +/-0.1PF 6.3V 2 CER-X5R 16V 2 NP0-C0G 01005 3 7 10 11 15 24 20% 6.3V 2 X5R-CERM LATCP_K SKY16708-11 50_LAT_LB_MB_HB_K 25 C1107_K 0.1UF VDD 16V 2 NP0-C0G 01005 28 1 C1105_K 18PF 16V 2 CERM 01005 6 50_LAT_LB_K COM 2 9 9 21 4 11 R1100_K 1.8NH-+/-0.1NH-0.70A 0805 D 01005 USID=0X6 C UPPER ANTENNA COUPLER LAT TUNER GPO FL1102_K 10-OHM-1.1A 17 11 B 9 8 5 2% 9 BI 50_UAT_MB_HB_K 50_UAT_LB_K FL1101_K 10-OHM-1.1A 28 25 24 23 21 20 19 18 IN 1 VDD_RFFE_VIO_1V8_K 1 13 6 2 01005 24 24 23 23 21 20 19 18 28 BI 21 20 19 18 28 IN VDD_RFFE_VIO_UATCP_1V8_K RFFE1_DATA_K RFFE1_CLK_K 5 12 8 RFIN1 RFIN2 C1104_K 18PF 16V 2 CERM 01005 RFFE UATCP_K SKY16708-11 21 14 6 5 RFOUT1 RFOUT2 LGA 2 14 1 C1108_K 5PF +/-0.1PF 16V 2 NP0-C0G 01005 1 PP1V8_S2 1 2 20% 6.3V 2 X5R-CERM 01005 RFFE 50_UAT_MB_HB_TX_SOUTH_K 50_UAT_LB_SOUTH_K 24 IN BI IN RFFE1_CLK_FILT_K 29 29 USID VIO SDATA SCLK RF_CPL1 RF_CPL2 4 16 50_XCVR0_UAT_CPLR_K 50_XCVR1_UAT_CPLR_K OUT 22 OUT 22 R1101_K 0.00 2 1 0% 1/32W MF 01005 RFFE PP1V8_GPOLAT_K 1 C1114_K 0.47UF 1 C1116_K 0.47UF 20% 6.3V 2 X5R 01005 1 5% 16V 2 NP0-C0G-CERM 01005 GPOLAT_K QM18099 17 1 RFFE_GPOLAT_CLK_K WLCSP C1102_K 33PF 5% 01005 BI RFFE1_DATA_FILT_K R1102_K 0.00 2 1 0% 1/32W MF 01005 RFFE B C1115_K 33PF 16V 2 NP0-C0G-CERM 3 7 10 11 15 20% 6.3V 2 CER-X5R 01005 1 2 20% 6.3V 2 X5R 01005 GND C1112_K 0.033UF 3 C1106_K 0.1UF 24 1 4 01005 VDD BI 15 VFE_AUX_3V1_K 1 21 16 17 A3 VIO A1 SCLK A2 SDATA B2 USID1 GPO1 GPO2 GPO3 GPO4 GPO5 GPO6 GPO7 RFFE_GPOLAT_DATA_K A4 B1 B4 C1 C2 C4 C3 LAT_TUNER_GPO1_K LAT_TUNER_GPO2_K LAT_TUNER_GPO3_K LAT_TUNER_GPO4_K OUT 29 OUT 29 OUT 29 OUT 29 NC NC NC GND 1 B3 C C1101_K 33PF USID=0X8 5% 16V 2 NP0-C0G-CERM USID=0X7 01005 A A PAGE TITLE LOWER ANTENNA & COUPLERS DRAWING NUMBER Apple Inc. 051-02247 REVISION 7.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 11 OF 17 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST 8 7 6 SHEET 23 OF 34 IV ALL RIGHTS RESERVED 5 4 3 2 1 SIZE D 8 7 6 5 4 3 2 1 DIVERSITY RECEIVE ASM'S D D XCVR0 DRX XCVR0_K PMB5757 UFWLB SYM 4 OF 5 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RD8 RD9 RD10 RD11 RD12 RD13 RD14 W4 V5 W6 V7 W8 V9 W10 V11 W12 V13 W14 V15 W16 V17 50_XCVR0_B1_B66_DRX_K 12 50_XCVR0_B3_B25_DRX_K 12 DRX DSM 13 5 VFE_LNA_2V7_K 1 50_XCVR0_LB_DRX_K 12 C1204_K 18PF 2% 16V 2 CERM 50_XCVR0_VLB_DRX_K 01005 RFFE 12 1 C1203_K 0.1UF 20% 6.3V 2 X5R-CERM 01005 RFFE VDD 49 XCVR 12 12 IN 24 23 BI LB_ANT 50_XCVR0_LB_DRX_K 50_XCVR1_LB_DRX_K 3 23 LB_RX0 LB_RX1 2 12 24 12 VDD_RFFE_VIO_FILT_1V8_K 45 VIO RFFE1_CLK_FILT_K RFFE1_DATA_FILT_K 46 SCLK SDATA 47 B1_B66 B3_B25 B7_B41_B38 B30_B40A B34 B39 LGA VLB_RX0 VLB_RX1 1 4 5 8 9 10 11 13 15 16 21 22 25 26 27 29 30 31 XCVR1_K PMB5757 MB_HB_ANT1 14 MB_HB_ANT2 12 DSM_K B30608-M5342-X969 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND XCVR1 DRX 23 28 50_XCVR0_VLB_DRX_K 50_XCVR1_VLB_DRX_K 12 24 50_LB_DRX_K UFWLB SYM 4 OF 5 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RD8 RD9 RD10 RD11 RD12 RD13 RD14 B W4 V5 W6 V7 W8 V9 W10 V11 W12 V13 W14 V15 W16 V17 50_XCVR1_VLB_DRX_K 12 50_XCVR1_LB_DRX_K 12 50_XCVR1_B7_B41_B38_DRX_K 50_XCVR1_B40_B30_DRX_K 50_LAT_MB_HB_DRX_K 50_UAT_MB_HB_RX_SOUTH_K 7 6 20 19 17 50_XCVR0_B1_B66_DRX_K 50_XCVR0_B3_B25_DRX_K 50_XCVR1_B7_B41_B38_DRX_K 50_XCVR1_B40_B30_DRX_K 50_XCVR1_B34_DRX_K 18 50_XCVR1_B39_DRX_K IN 21 IN 25 12 12 12 12 12 12 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND IN 32 33 34 35 36 37 38 39 40 41 42 43 44 48 50 51 52 53 54 55 56 57 58 59 60 61 62 63 21 C 64 65 66 67 68 69 C LB: USID=0X9 MB-HB: USID=0XA 12 12 50_XCVR1_B39_DRX_K 12 50_XCVR1_B34_DRX_K 12 B XCVR RFFE FILTERING 28 25 23 21 20 19 18 R1200_K 0.00 2 1 VDD_RFFE_VIO_1V8_K IN 1 C1200_K 0.1UF 20% 6.3V 2 X5R-CERM VDD_RFFE_VIO_FILT_1V8_K 12 0% 1/32W MF 01005 RFFE 01005 RFFE 28 23 21 20 19 18 R1201_K 0.00 2 1 RFFE1_DATA_K BI 1 C1201_K 0.1UF 20% 6.3V 2 X5R-CERM A RFFE1_DATA_FILT_K BI 23 24 0% 1/32W MF 01005 RFFE A 01005 RFFE NOSTUFF 28 23 21 20 19 18 R1202_K 0.00 2 1 RFFE1_CLK_K IN PAGE TITLE 1 C1202_K 22PF 5% 16V 2 CERM RFFE1_CLK_FILT_K DIVERSITY RECEIVE ASM'S OUT 23 24 DRAWING NUMBER 0% 1/32W MF 01005 RFFE Apple Inc. 051-02247 REVISION 7.0.0 01005-1 RFFE NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 12 OF 17 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST 8 7 6 SHEET 24 OF 34 IV ALL RIGHTS RESERVED 5 4 3 2 1 SIZE D 8 7 6 5 4 3 2 1 DIVERSITY RECEIVE LNAS L1300_K 120NH-5%-40MA 12 5 VFE_LNA_2V7_K 1 2 VFE_LNA_FILT_2V7_K 13 0201 UP_RFFE D D LB DRX LNA 13 VFE_LNA_FILT_2V7_K 10 BYPASS SHARED WITH MB/HB DRX LNA VDD 29 3 50_UAT_LB_NORTH_K BI LBLN_K SKY13767-11 TX_RX ANT 14 50_UUAT_LB_PLEXER_K BI 26 LGA 12 11 9 8 7 14 13 14 13 9 7 8 VDD_RFFE_VIO_1V8_K UAT_TUNER_RFFE_DATA_K UAT_TUNER_RFFE_CLK_K 6 1 C1302_K 18PF 2% 2 16V CERM 01005 UP_RFFE NOSTUFF 1 C1303_K 18PF 2% 2 16V CERM 01005 UP_RFFE NOSTUFF 1 C1306_K 0.033UF 20% VIO SDATA SCLK GND EPAD 23 24 25 13 1 2 4 5 6 11 12 13 15 16 17 18 19 20 21 22 16 2 6.3V CER-X5R 01005 USID=0X2 UP_RFFE C C MB/HB DRX LNA 13 VFE_LNA_FILT_2V7_K 1 2% 20 2 16V CERM 01005 UP_RFFE VDD BI 12 28 25 24 23 21 20 19 18 IN 26 25 BI 26 25 IN 50_UAT_MB_HB_TX_NORTH_K 50_UAT_MB_HB_RX_SOUTH_K 4 2 VDD_RFFE_VIO_1V8_K UAT_TUNER_RFFE_DATA_K UAT_TUNER_RFFE_CLK_K 21 23 22 MHBLN_K SKY13764-14 IN_TX OUT_RX C1305_K 0.1UF 20% 2 6.3V X5R-CERM 01005 UP_RFFE 50_UUAT_MB_HB_K BI 26 LGA VIO SDATA SCLK EPAD 1 3 5 6 7 8 9 10 11 12 13 14 15 17 18 19 24 GND B A ANT 16 1 25 26 27 28 29 C1304_K 18PF B USID=0X3 RFFE2 IMPEDANCE MATCHING 18 IN RFFE2_CLK_K R1302_K 0.00 2 1 A PAGE TITLE UAT_TUNER_RFFE_CLK_K 13 DIVERSITY RECEIVE LNA'S 14 0% 1/32W MF 01005 18 BI RFFE2_DATA_K R1303_K 0.00 2 1 DRAWING NUMBER Apple Inc. UAT_TUNER_RFFE_DATA_K 051-02247 REVISION 7.0.0 13 14 0% 1/32W MF 01005 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 13 OF 17 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST 8 7 6 SHEET 25 OF 34 IV ALL RIGHTS RESERVED 5 4 3 2 1 SIZE D 8 7 6 5 4 3 2 1 UPPER ANTENNA FEEDS D D 25 UAT1 50_UUAT_LB_PLEXER_K BI 9 R1402_K 1.0NH-+/-0.05NH-1.1A-0.04OHM C 25 IN 1 50_UUAT_MB_HB_K 2 50_UUAT_MB_HB_PLEXER_K 0201 1 13 1 15 QUADP_K ACFM-W912-AP1 LCB LGA L1405_K 2.4NH+/-0.1NH-0.6A C1403_K 6.2PF ANT 5 MID/HIGH_CELL_BAND WIFI GNSS 1 50_UAT1_K 2 50_UAT_WLAN_2G_NORTH_K 1% 1/20W MF 0201 UP_RFFE 1 C TO ANTENNA FEED C1404_K 0.3PF 2 25V C0G-CERM EPAD 0201 17 2 3 4 6 7 8 10 11 12 14 16 29 BI +/-0.05PF 0201 GND 2 BI 50_UAT1_TEST_K L1404_K 15NH-3%-0.3A-0.7OHM 0201 UP_RFFE NOSTUFF 29 2 0201 1 +/-0.1PF 25V C0G 0201 L1401_K 12NH-3%-0.3A-0.5OHM R1403_K 0.00 2 1 1 50_UAT1_M_K 2 50_UAT_WLAN_2G_PLEXER_K 1 L1402_K 9.1NH+/-0.3%-0.3A 0201 UP_RFFE NOSTUFF 2 27 OUT 50_GNSS_K R1404_K 0.00 2 1 1% 1/20W MF 0201 UP_RFFE 50_GNSS_PLEXER_K 1 C1401_K 18PF 2% 25V 0201 UP_RFFE NOSTUFF 2 C0H-CERM B B UAT TUNER GPO FL1400_K 10-OHM-1.1A 17 16 15 11 6 5 4 3 2 1 PP1V8_S2 1 2 01005 PP1V8_GPOUAT_K 1 C1406_K 1UF 20% 2 10V X5R 0201 1 C1407_K 33PF 5% 2 16V NP0-C0G-CERM GPOUAT_K QM18098 01005 WLCSP IN UAT_TUNER_RFFE_CLK_K 17 16 RFFE_GPOUAT_CLK_K 0% 1/32W MF 01005 RFFE 25 A BI UAT_TUNER_RFFE_DATA_K 0% 1/32W MF 01005 RFFE A1 SCLK A2 SDATA GPO1 GPO2 GPO3 GPO4 A4 B1 B2 B4 UAT_TUNER_GPO1_K UAT_TUNER_GPO2_K OUT 29 OUT 29 NC NC GND 1 R1406_K 0.00 2 1 VIO C1402_K 33PF B3 25 R1405_K 0.00 2 1 A3 USID=0X8 5% 2 16V NP0-C0G-CERM 01005 NOSTUFF 17 16 RFFE_GPOUAT_DATA_K A 1 C1405_K 33PF PAGE TITLE UPPER ANTENNA FEEDS 5% 2 16V NP0-C0G-CERM 01005 NOSTUFF DRAWING NUMBER Apple Inc. 051-02247 REVISION 7.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 14 OF 17 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 26 OF 34 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D 8 7 6 5 4 3 2 1 GNSS LNA + RECEIVER D L1501_K 120NH-5%-40MA D 15 1 VDD_GNSS_AUX_1V8_K 2 VGNSS_LNA_L_K 0201 GNSS 1 7 20% 2 6.3V X5R-CERM VCC 26 16 15 IN 1 RF_IN 50_GNSS_K C1503_K 0.1UF 01005 GNSS GLNA_K SKY65767-11 LGA RF_OUT 9 50_UAT_GNSS_LNA_RFOUT_K 15 3 LNA_EN GNSS_EXT_LNA_EN_K 2 4 5 6 8 GND C 17 16 14 11 6 5 4 3 2 1 PP1V8_S2 R1500_K 0.00 2 1 PP_VDD_MAIN_GNSS_K PP_VDD_MAIN 1 5 6 7 8 C 16 PP1V8_GNSS BATT_VCC_GNSS 8 10 11 0% 1/32W MF 01005 GNSS 13 28 13 IN AP_TO_GNSS_WAKE AP_TO_BB_TIME_MARK 18 20 IN GNSS_BLANK_K 43 12 IN 12 14 AP_TO_GNSS_DEVICE_WAKE AP_TO_GNSS_TIME_MARK GNSS_K 2103-601602-40 GNSS_BLANK GNSS_26MHZ_CLKOUT 42 GNSS_IF_TEST_OUT 36 GNSS_26MHZ_CLKOUT_K GNSS_IF_TEST_OUT_K TCXO_BB_GNSS_32K 5 TCXO_BB_GNSS_32K_K IN OUT 18 28 28 LGA 15 VDD_GNSS_AUX_1V8_K GNSS_EXT_LNA_EN_K 15 50_UAT_GNSS_LNA_RFOUT_K 15 16 25 49 2 NC B 28 13 12 IN 28 13 12 OUT 28 13 12 IN 28 13 12 OUT 28 13 12 IN PMU_TO_GNSS_EN 19 7 VDD_GNSS_AUX_1V8 GNSS_EXT_LNA_EN IN 15 28 GNSS_RFIN GNSS_TO_PMU_HOST_WAKE PMU_TO_GNSS_EN UART_GNSS_TO_AP_CTS_L UART_AP_TO_GNSS_RTS_L 15 13 UART_GNSS_TO_AP_CTS* UART_AP_TO_GNSS_RTS* UART_GNSS_TO_AP_RXD UART_AP_TO_GNSS_TXD 17 16 UART_GNSS_TO_AP_RXD UART_AP_TO_GNSS_TXD B 1 3 4 6 9 12 14 22 23 24 21 26 27 28 29 30 31 32 33 34 35 37 38 39 40 41 44 45 46 47 48 50 51 52 53 54 GND A A PAGE TITLE GNSS DRAWING NUMBER Apple Inc. 051-02247 REVISION 7.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 15 OF 17 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 27 OF 34 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D 8 7 6 5 4 3 2 MLB TEST POINTS HARDWARE ID 17 16 15 14 11 6 5 4 3 2 1 PP1600_K P2MM-NSM D PP PP1648_K P2MM-NSM 1 AP_TO_BBPMU_RADIO_ON_L SM 1 2 5 OMIT PP 1 BBPMU_PWRGOOD_K SM 3 5 6 1 BBPMU_XG_RESET_L_K 3 5 PP 1 BBPMU_XG_RESET_SD_L_K SM 3 5 PP 1 TCXO_BB_GNSS_32K_K SM 3 15 PP 1 BB_DEBUG_ERROR_K SM 2 PP PP 1 AP_TO_BB_MESA_ON_K SM 1 2 PP 7 8 9 11 12 16 1 16 PLACE NEAR LBPA/MHBPA 16 5 4 2 6 7 8 9 11 12 1 RFFE1_CLK_K SIM1_RST_R_K C1601_K 2.2UF 16 7 8 9 11 12 1 DZ1605_K 12V-33PF 1 SM BB_TO_STROBE_DRIVER_GSM_BURST_IND 1 2 1 1 PP SM 3 PP 1 SYSCLK_26MHZ_K 2 1 SM 1 BB_TO_NFC_CLK 1 6 PP 6 7 8 9 11 12 16 16 16 RFFE2_CLK_R_K 1 6 SG-WLL-2-2 1 RFFE_GPOUAT_DATA_K 14 17 BBPMU 1 ETIC 50_ET_DAC_P_K SM GNSS_26MHZ_CLKOUT_K 6 15 PP 14 BI SIM1_IO_K IN SIM1_CLK_K 7 8 PP 1 BBPMU_VCLK_K 2 5 14 IN SIM1_RST_K PP1628_K P2MM-NSM 50_ET_DAC_N_K SM 7 8 OMIT PP 1 BBPMU_VDIO_K 2 5 13 12 OMIT GNSS PCIE BI NFC_SWP1 SM 1 90_PCIE_AP_TO_BB_REFCLK_P 1 2 PP SM 1 90_PCIE_AP_TO_BB_REFCLK_N 1 2 PP 90_PCIE_AP_TO_BB_TXD_P SM 1 2 PP 1 90_PCIE_AP_TO_BB_TXD_N SM 1 2 PP 1 PMU_TO_GNSS_EN 1 90_PCIE_BB_TO_AP_RXD_P SM 1 2 PP 15 OUT 2 1 90_PCIE_BB_TO_AP_RXD_N SM 1 2 PP PP1612_K P2MM-NSM 1 UART_GNSS_TO_AP_RXD SM 1 2 16 PP PP1613_K P2MM-NSM 1 SM 1 2 1 UART_AP_TO_GNSS_TXD PP 5 14 SIM1_CLK_R_K 16 R1615_K 10 R1616_K 10 OUT SIM1_DETECT_K R1617_K 10 1 SIM1_RST_R_K 15 PP 1 SM 1 15 PP 1 1 SM 1 15 PP 1 1 SIM1_SWP_R_K 16 SIM1_DETECT_R_K 7 6 1 15 PP SM 1 15 PP 90_DIGRF_A1_RX1_P_K 2 17 16 15 14 11 SM 2 6 2 PP 4 3 2 1 PP1V8_S2 1 OUT DEV_HW_CONFIG_K HW CONFIG RESERVED RESERVED RESERVED R1606_K 1.00K 1% 1/32W MF 2 01005 BASEBAND OMIT DEV_HW_CONFIG Z 0 1 1% 1/32W MF 2 01005 BASEBAND NOSTUFF PP 1 HW_ID<3:0> 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 17 PP1V8_S2 R1604_K 1.00K 1% 1/32W MF 2 01005 BASEBAND 1 16 15 14 11 6 5 4 3 2 1 PP1V8_S2 1 R1607_K 1.00K 1% 1/32W MF 2 01005 BASEBAND 28 14 13 12 OUT R1610_K 1.00K 1% 1/32W MF 01005 2 BASEBAND PCIE_AP_TO_BB_RESET_L NOSTUFF STUFF FOR VENDOR CONFIG ONLY C TRIG_IN PP_VDD_MAIN 2 1 PMU_TO_BB_USB_VBUS_DETECT F-ST-SM 37 38 1 2 3 4 6 5 4 3 5 1 2 1 1 7 6 5 16 15 1 8 NC NC PMU_TO_BBPMU_RESET_L PP1V8_S2 BB_JTAG_TDO_K BB_JTAG_TDI_K BB_JTAG_TRST_L_K AP_TO_BB_RESET_L BB_JTAG_TCK_K BB_JTAG_TMS_K PP_VDD_MAIN 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 2 1 1 UART_BB_TO_AP_RXD_K UART_AP_TO_BB_TXD_K 27 28 29 30 NC 31 32 33 34 35 36 39 40 90_USB_BB_DATA_P 90_USB_BB_DATA_N VDD_SIM1_K SIM1_RST_R_K SIM1_CLK_R_K SIM1_IO_R_K SIM1_SWP_R_K SIM1_DETECT_R_K NC NC NC NC NC NC NC BB_JTAG_RESET_L UART_BB_TO_WLAN_COEX UART_WLAN_TO_BB_COEX 1 2 1 2 2 4 5 16 16 B 16 16 16 16 1 2 1 2 NC NOSTUFF SWD_AOP_TO_MANY_SWCLK 1 3 SWD_AOP_BI_BB_SWDIO 1 3 PP1661_K P2MM-NSM 1 SM 90_DIGRF_M0_TX_P_K 2 6 PP 1 OMIT 1 90_DIGRF_M0_TX_N_K 2 A PCIE GND 6 PAGE TITLE TEST POINTS & SIM PP1633_K P2MM-NSM 1 Apple Inc. OMIT PP 1 2 16 051-02247 REVISION 7.0.0 PP1634_K P2MM-NSM SM UART_BB_TO_AP_RXD_K DRAWING NUMBER 1 1 OMIT NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 16 OF 17 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST 7 D R1609_K 1.00K 1% 1/32W MF 01005 2 BASEBAND NOSTUFF II NOT TO REPRODUCE OR COPY IT 8 R1608_K 1.00K 42 OMIT OMIT 5 OMIT BB UART SM 2 1 3 PP1660_K P2MM-NSM 90_DIGRF_A1_RX1_N_K 6 6 PP 15 3 NC SM GNSS_IF_TEST_OUT_K 4 HW_MON1_K HW_MON2_K PP_VDD_BOOST PP1647_K P2MM-NSM AP_TO_BB_TIME_MARK 5 5 2 OMIT 1 8 16 6 OMIT 1 15 16 2 11 16 SELECT PP1646_K P2MM-NSM UART_AP_TO_GNSS_RTS_L 6 NC 90_DIGRF_M1_TX_N_K 14 J_DEBUG_K 20-5857-036-001-829 3 OMIT SM 11 41 6 PP1632_K P2MM-NSM UART_GNSS_TO_AP_CTS_L 14 16 3 2 15 MLB 516S1185 FLEX 516S1184 3 90_DIGRF_M1_TX_P_K 16 DEBUG CONNECTOR 3 PP1643_K P2MM-NSM 1 R1614_K 10 OMIT PP1614_K P2MM-NSM BB_TO_PMU_PCIE_HOST_WAKE_L 16 PP1631_K P2MM-NSM OMIT OMIT 1 1 PP1625_K P2MM-NSM PCIE_BB_BI_AP_CLKREQ_L SIM1_IO_R_K OMIT OMIT OMIT PP SM 1 PP1624_K P2MM-NSM PCIE_AP_TO_BB_RESET_L R1613_K 10 PP1630_K P2MM-NSM OMIT OMIT 1 AP_TO_MANY_BSYNC 1 HW_MON1 HW_MON2 NAND 0 0 1 FLASHLESS 1 0 1 FLASHLESS WDOG DIS 1 1 0 NAND 1 1 1 BOOTSTRAPS ARE INTERNALLY PULLED DOWN OMIT PP1623_K P2MM-NSM PP1611_K P2MM-NSM PP 15 OMIT OMIT SM SM 1 PP1622_K P2MM-NSM PP1635_K P2MM-NSM PP ESD202-B1-CSP01005 OUT DIGRF OMIT OMIT SM 15 PP1629_K P2MM-NSM PP1621_K P2MM-NSM PP1610_K P2MM-NSM PP 15 OMIT OMIT SM GNSS_EXT_LNA_EN_K PP1620_K P2MM-NSM PP1609_K P2MM-NSM A SG-WLL-2-2 3 OMIT OMIT PP 1 15 DZ1609_K 5% 1/32W MF 01005 PP1619_K P2MM-NSM PP1642_K P2MM-NSM 1 1 OMIT OMIT OMIT SM 2 5% 1/32W MF 01005 PP1618_K P2MM-NSM PP1641_K P2MM-NSM PP PP 16 5% 1/32W MF 01005 OMIT 1 17 1% 1/32W MF 01005 2 BASEBAND HARDWARE ICE17.2 PROTO1 ICE17.2 PROTO2 ICE17.2 PROTO3 ICE17.2 EVT RESERVED HW_ID<3:0> 0 0 0 Z 0 0 Z 0 0 0 Z Z 0 Z 0 0 0 Z 0 Z 1 5% 1/32W MF 01005 PP1627_K P2MM-NSM SM R1603_K 1.00K 1% 1/32W MF 2 01005 BASEBAND OMIT 1 ESD202-B1-CSP01005 17 1% 1/32W MF 2 01005 BASEBAND ESD202-B1-CSP01005 1 2 PP1617_K P2MM-NSM B SM 17 DZ1607_K 14 R1601_K 1.00K SG-WLL-2-2 ESD202-B1-CSP01005 2 RFFE_GPOUAT_CLK_K 1 DZ1608_K 6 SM PP HARDWARE ICE17.2 RF DEV1 ICE17.2 RF DEV2 RESERVED RESERVED RESERVED C1600_K 100PF 1 SG-WLL-2-2 1 R1605_K 1.00K BOOTCFG PLACE NEAR XCVR1 RFFE2_DATA_R_K 1 SIM1_IO_R_K SIM1_CLK_R_K SIM1_RST_R_K SIM1_SWP_R_K PP1608_K P2MM-NSM SM 1 5% 1 OMIT OMIT PP 16 1% 1/32W MF 2 01005 BASEBAND PLACE NEAR XCVR0 RFFE1_DATA_K 1% 1/32W MF 01005 2 BASEBAND 1 1 R1612_K 1.00K 01005 BASEBAND 16 1% 1/32W MF 01005 2 BASEBAND OMIT R1602_K 1.00K 14 16 2 16V NP0-C0G DZ1606_K PP1616_K P2MM-NSM PP SM 0201 SIM 16 6 SM PP OUT 1 R1600_K 1.00K DZ1600_K 5.5V-6.2PF 1 XCVR PP1658_K P2MM-NSM SM 14 5% 1/32W MF 01005 OMIT PP SIM1_SWP_R_K 2 OMIT PP1657_K P2MM-NSM SM SIM1_IO_R_K 01005-1 2 SIM 16 OMIT PP OUT PP1656_K P2MM-NSM BB_TO_AP_RESET_ACT_L_K PP1615_K P2MM-NSM SM 7 SWP 6 14 PP OUT 14 OMIT OMIT SM 16 OUT 14 1 GND 20% 2 6.3V X5R-CERM 0201 SIM OMIT_TABLE 6 SIM1_DETECT_R_K 1 VCC VDD_SIM1_K 1 RFFE1_DATA_K 2 RESET PP1655_K P2MM-NSM PP1640_K P2MM-NSM PP 6 IO F-RT-SM OMIT OMIT SM RFFE1_CLK_K PP1652_K P2MM-NSM PP1607_K P2MM-NSM SM 1 3 CLK SIM1_CLK_R_K SIM_DETECT 8 J_SIM_K SIMCARD-BEACH-D22 OMIT OMIT C 16 PP1651_K P2MM-NSM PP1606_K P2MM-NSM PP 9 SIM_DETECT_SPG 13 OMIT OMIT SM 12 PP1654_K P2MM-NSM PP1605_K P2MM-NSM PP 11 14 1 R1611_K 1.00K 1% 1/32W MF 01005 2 BASEBAND OMIT BB_HW_ID<0>_K BB_HW_ID<1>_K BB_HW_ID<2>_K BB_HW_ID<3>_K OMIT OMIT SM 9 PP1653_K P2MM-NSM PP1604_K P2MM-NSM PP 8 OMIT OMIT SM PP SM PP1603_K P2MM-NSM PP 7 PP1650_K P2MM-NSM OMIT SM 6 OMIT PP1602_K P2MM-NSM PP VDD_RFFE_VIO_1V8_K PP1649_K P2MM-NSM OMIT SM 1 OMIT PP1601_K P2MM-NSM SM PP 5 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SM 1 RFFE DEV CONFIG PP1V8_S2 SIM CARD CONNECTOR BASEBAND 1 6 SHEET 28 OF 34 IV ALL RIGHTS RESERVED 5 4 3 2 1 SIZE D 8 7 6 5 4 3 2 1 RF CONNECTORS AND METROCIRC JLAT1_K MM3729-2702A16 L1702_K 150OHM-25%-200MA-0.7DCR M-ST-SM 01005 14 11 D LAT MLC D 6 5 4 3 2 17 16 1 15 11 1 11 11 1 PP1V8_S2 RFFE_GPOLAT_DATA_K 2 1 2 3 4 5 6 7 8 PP1V8_GPOLAT_CONN_K 50_LAT_WLAN LAT_TUNER_GPO2_K LAT_TUNER_GPO1_K 1 C1711_K 220PF 5% 2 16V C0G 01005 1 C1710_K 33PF 2% 2 16V NP0-C0G 01005 NOSTUFF 1 C1708_K 5.6PF +/-0.1PF 2 16V NP0-C0G 01005 1 C1707_K 5.6PF +/-0.1PF 16V 2 NP0-C0G 01005 9 10 11 12 13 14 15 16 L1703_K 150OHM-25%-200MA-0.7DCR RFFE_GPOLAT_CLK_K 11 PP3V0_TRISTAR_LAT_CONN_K LAT_TUNER_GPO4_K 11 LAT_TUNER_GPO3_K 11 50_LAT1_ANT_K SHLD 17 18 19 20 21 22 23 1 24 25 26 27 28 29 30 C1704_K 33PF 2% 2 16V NP0-C0G 01005 NOSTUFF 1 C1703_K 220PF 5% 2 16V C0G 01005 1 C1705_K 5.6PF +/-0.1PF 2 16V NP0-C0G 01005 1 01005 1 2 PP3V0_S2 1 17 11 UAT1 MLC C1706_K 5.6PF +/-0.1PF 2 16V NP0-C0G 01005 JUAT1_K MM3729-2702A12 L1700_K 150OHM-25%-200MA-0.7DCR M-RT-SM 1 2 3 4 5 6 01005 17 1 1 PP3V0_S2 2 17 14 14 C 17 PP3V0_TRISTAR_UAT_CONN_K UAT_TUNER_GPO2_K UAT_TUNER_GPO1_K 50_UAT_WLAN_5G_MLC_K 7 8 9 10 11 12 SHLD 13 14 15 16 17 18 19 50_UAT1_TEST_K 14 RFFE_GPOUAT_DATA_K RFFE_GPOUAT_CLK_K PP3V0_TRISTAR_UAT_CONN_K PP1V8_GPOUAT_CONN_K 14 14 16 16 L1701_K 150OHM-25%-200MA-0.7DCR 01005 17 1 2 PP1V8_S2 1 2 3 4 5 6 11 14 15 16 17 C 20 21 22 23 24 25 4-IN-1 METROCIRC CABLE MC_K FLTPSSL-524J B 11 1 1 11 50_UAT_LB_SOUTH_K 50_UAT_WLAN_5G_SOUTH 50_UAT_WLAN_2G_SOUTH 50_UAT_MB_HB_TX_SOUTH_K 21 30 23 32 1 3 5 6 7 8 9 10 11 17 12 14 16 18 19 20 B SM SIG1-S SIG2-S SIG3-S SIG4-S GND SIG1-N SIG2-N SIG3-N SIG4-N 4 15 2 13 GND 22 24 25 26 27 28 29 31 33 34 41 42 43 44 45 46 50_UAT_LB_NORTH_K 50_UAT_WLAN_5G_NORTH_K 50_UAT_WLAN_2G_NORTH_K 50_UAT_MB_HB_TX_NORTH_K 13 17 14 13 17 50_UAT_WLAN_5G_NORTH_K R1700_K 0.00 2 1 0% 1/32W 1 C1701_K MF 27PF 01005 5% 2 16V NP0-C0G 01005 UAT NOSTUFF 50_UAT_WLAN_5G_MLC_K 1 17 C1700_K 27PF 5% 2 16V NP0-C0G 01005 UAT NOSTUFF A A 8 7 6 5 4 3 2 1 8 7 6 5 4 3 1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 2 1 REV ECN CK APPD DESCRIPTION OF REVISION 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. D 7 0008448938 ENGINEERING RELEASED 2017-04-11 D22/D221 WIFI_MLB (GUINNESS) APR 03, 2017 PDF PAGE 2 3 TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM CSA PAGE 76 77 D CONTENTS GUINNESS WIFI FRONT-END TABLE_TABLEOFCONTENTS_ITEM POWER 31 12 IN 31 12 IN PP_VDD_MAIN PP1V8_S2 CLOCKS 31 12 IN 31 12 IN PMU_TO_WLAN_CLK32K WLAN_TO_AP_TIME_SYNC CONTROL C 31 12 IN 31 12 IN 31 12 OUT 31 12 IN 31 12 IN 31 12 IN 31 12 IN 31 12 IN 31 12 OUT 31 12 OUT 31 12 IN C PMU_TO_WLAN_REG_ON PMU_TO_BT_REG_ON BT_TO_PMU_HOST_WAKE AP_TO_BT_WAKE WLAN PCIE 2 IO 31 12 OUT 31 12 IN 31 12 OUT 31 12 IN 31 12 OUT 31 12 IN 90_PCIE_AP_TO_WLAN_REFCLK_P 90_PCIE_AP_TO_WLAN_REFCLK_N 90_PCIE_AP_TO_WLAN_TXD_P 90_PCIE_AP_TO_WLAN_TXD_N 90_PCIE_WLAN_TO_AP_RXD_P 90_PCIE_WLAN_TO_AP_RXD_N PCIE_AP_TO_WLAN_RESET_L PCIE_WLAN_BI_AP_CLKREQ_L WLAN_TO_PMU_HOST_WAKE AP_TO_WLAN_DEVICE_WAKE WLAN UART UART_WLAN_TO_AP_RXD UART_AP_TO_WLAN_TXD UART_WLAN_TO_AP_CTS_L UART_AP_TO_WLAN_RTS_L BLUETOOTH UART B 31 12 IN 31 12 OUT 31 12 IN 31 12 OUT 31 12 IN 31 12 IN B UART_AP_TO_BT_TXD UART_BT_TO_AP_RXD UART_AP_TO_BT_RTS_L UART_BT_TO_AP_CTS_L AOP AOP_TO_WLAN_CONTEXT_A AOP_TO_WLAN_CONTEXT_B COEX 31 12 IN 31 12 OUT UART_BB_TO_WLAN_COEX UART_WLAN_TO_BB_COEX ANTENNA 3 IO 3 IO 3 IO 50_UAT_WLAN_2G_SOUTH 50_UAT_WLAN_5G_SOUTH 50_LAT_WLAN SymbolPorts A A DRAWING TITLE SCH,MLB,BOT,X893 DRAWING NUMBER Apple Inc. 051-02247 REVISION 7.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 1 OF 5 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 30 OF 34 IV ALL RIGHTS RESERVED 2 1 SIZE D 8 7 6 5 4 3 2 1 WIFI/BT PP_VDD_MAIN PP1V8_S2 27PF 5% 16V 2 NP0-C0G 01005 WLAN 31 2 1 30 12 IN 30 12 IN 30 12 OUT PMU_TO_WLAN_CLK32K 122 LPO_IN UART_BB_TO_WLAN_COEX UART_WLAN_TO_BB_COEX 127 SECI_IN 92 SECI_OUT 1 1 C7601_W 10UF 0.01UF 10% 2 6.3V X5R 01005 WLAN R7600_W 31 30 12 IN UWLAN_W PMU_TO_WLAN_REG_ON 86 WL_REG_ON LBEE5W11KN-040 PMU_TO_BT_REG_ON 85 BT_REG_ON SYM 1 OF 2 JTAG_WLAN_SEL_W 20% 2 6.3V CERM-X5R 0402-0.1MM 5% 1/32W MF 2 01005 WLAN NOSTUFF 31 30 12 IN 2 2 2 2 152 90 151 91 JTAG_WLAN_SEL_W JTAG_WLAN_TCK_W JTAG_WLAN_TMS_W JTAG_WLAN_TRST_L_W JTAG_SEL JTAG_TCK JTAG_TMS JTAG_TRST* 31 31 30 12 30 12 OUT IN 31 30 12 OUT 31 30 12 IN UART_AP_TO_WLAN_RTS_L 31 30 12 IN AP_TO_WLAN_DEVICE_WAKE 31 30 12 OUT BT_TO_PMU_HOST_WAKE 32 BI 32 BI 32 BI 32 BI 32 OUT 171 FAST_UART_RTS_OUT 169 FAST_UART_CTS_IN PP 2 1 PMU_TO_WLAN_CLK32K AP_TO_BT_WAKE BT_UART_RXD BT_UART_TXD BT_UART_CTS* BT_UART_RTS* 37 39 36 38 UART_AP_TO_BT_TXD UART_BT_TO_AP_RXD UART_AP_TO_BT_RTS_L UART_BT_TO_AP_CTS_L 2 1 AOP_TO_WLAN_CONTEXT_B TDO 1 PP 2 1 50_WLAN_G_0_W 50_WLAN_G_1_W 3 2G_ANT_CORE0 66 2G_ANT_CORE1 50_WLAN_A_0_W 50_WLAN_A_1_W 49 5G_ANT_CORE0 52 5G_ANT_CORE1 126 WLAN_TO_AP_TIME_SYNC CBUCK_EXT 147 CBUCK_EXT_W SR_VLX 119 SR_LVX_W PCIE_CLKREQ* PCIE_PERST* WLAN_TO_PMU_HOST_WAKE 90_PCIE_AP_TO_WLAN_REFCLK_P 2 1 UART_WLAN_TO_AP_RXD 1 PP 2 1 90_PCIE_AP_TO_WLAN_REFCLK_N 1 PP 2 1 WLAN_TO_AP_TIME_SYNC 2 1 UART_AP_TO_WLAN_TXD 1 PP 2 1 90_PCIE_AP_TO_WLAN_TXD_P 1 PP 2 1 PCIE_WLAN_BI_AP_CLKREQ_L 2 JTAG_WLAN_TCK_W 1 PP 2 1 90_PCIE_AP_TO_WLAN_TXD_N A 2 2 JTAG_WLAN_TMS_W JTAG_WLAN_TRST_L_W 1 PP PP7607_W P2MM-NSM OMIT SM 1 PP 2 1 2 PCIE_AP_TO_WLAN_RESET_L 2 1 2 1 BT_TO_PMU_HOST_WAKE PP PP7609_W P2MM-NSM OMIT SM 1 PP 2 1 90_PCIE_WLAN_TO_AP_RXD_N 2 1 2 1 31 IN 12 30 31 OUT 12 30 31 IN 12 30 31 OUT 12 30 31 12 30 31 1 PP 2 1 PP 2 PP 2 1 PP JTAG_WLAN_SEL_W PP PMU_TO_WLAN_REG_ON 2 1 2 1 PP PP7619_W P2MM-NSM OMIT SM 1 PMU_TO_BT_REG_ON PP SR_LVX_1_W 124 WLAN_TO_PMU_HOST_WAKE 87 88 PCIE_WLAN_BI_AP_CLKREQ_L PCIE_AP_TO_WLAN_RESET_L OUT BI 12 30 12 30 2.2UH-20%-1.6A-0.2OHM C7604_W L7600_W 7.5UF 20% 4V CERM 0402 31 31 IN 12 30 31 12 30 31 IN 12 30 31 PCIE_TD+ 25 PCIE_TD- 26 90_PCIE_WLAN_TO_AP_RXD_P 90_PCIE_WLAN_TO_AP_RXD_N OUT 12 30 31 OUT 12 30 31 90_PCIE_AP_TO_WLAN_REFCLK_P 90_PCIE_AP_TO_WLAN_REFCLK_N IN 12 30 31 IN 12 30 31 CXT_A/TDI CXT_B/TDO 125 123 AOP_TO_WLAN_CONTEXT_A AOP_TO_WLAN_CONTEXT_B IN 12 30 31 IN 12 30 31 GP15 153 PP 2 1 PP 01005 WLAN NC UART_WLAN_TO_AP_CTS_L P2MM-NSM OMIT SM 1 PP PP7631_W P2MM-NSM OMIT SM 1 5% 2 16V NP0-C0G PP7630_W P2MM-NSM OMIT SM 1 100PF IN 2 1 UART_AP_TO_WLAN_RTS_L P2MM-NSM OMIT SM 1 PP P2MM-NSM OMIT SM 1 PP SYM 2 OF 2 GND GND D C B 90_PCIE_WLAN_TO_AP_RXD_P P2MM-NSM OMIT SM 1 PP TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER 998-10376 998-10147 P2MM-NSM OMIT SM 1 LBIST_MBIST_W BOM OPTION REF DES COMMENTS: BOM_TABLE_ALTS UWLAN_W USI ES6.1 WIFI MODULE TABLE_ALT_ITEM PP UART_AP_TO_BT_TXD P2MM-NSM OMIT SM 1 PP UART_BT_TO_AP_RXD UART_AP_TO_BT_RTS_L P2MM-NSM OMIT SM 1 PP SYNC_MASTER=WIFI PP7622_W P2MM-NSM OMIT SM 1 SYNC_DATE=01/30/2014 PAGE TITLE Guinness PP DRAWING NUMBER PP7623_W P2MM-NSM OMIT SM 1 2 LGA PP7621_W P2MM-NSM OMIT SM 1 1 LBEE5W11KN-040 97 98 99 100 101 102 103 104 105 106 107 108 109 110 112 113 114 115 116 117 118 120 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 148 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 172 173 174 175 176 177 178 179 180 181 182 183 PP7620_W P2MM-NSM OMIT SM 1 IN 22 23 PP7625_W P2MM-NSM OMIT SM 1 2 UWLAN_W PP7629_W P2MM-NSM OMIT SM PP7618_W P2MM-NSM OMIT SM 1 PP PP7617_W P2MM-NSM OMIT SM 1 PP7608_W AP_TO_WLAN_DEVICE_WAKE 1 PP7616_W PP7606_W P2MM-NSM OMIT SM 12 30 PP7628_W P2MM-NSM OMIT SM PP7615_W PP7605_W P2MM-NSM OMIT SM IN 90_PCIE_AP_TO_WLAN_TXD_P 90_PCIE_AP_TO_WLAN_TXD_N PCIE_REFCLK+ PCIE_REFCLK- PP7627_W P2MM-NSM OMIT SM PP7614_W PP7604_W P2MM-NSM OMIT SM 4UF 20% 20% 6.3V 2 6.3V CER-X5R 2 CER-X5R 0201 0201 PCIE_RD+ 19 PCIE_RD- 20 PP7626_W P2MM-NSM OMIT SM PP7613_W PP7603_W P2MM-NSM OMIT SM 4UF 20% 2 6.3V CER-X5R 0201 1 C7603_W 111 ANT_SW_3P3 149 ANT_SW_CTRL BT_XSW_3P3V_W BT_XSW_VCTRL_W PP7612_W 2 1 1 C7611_W 1 C7612_W 4UF LBIST_MBIST_W WLAN_TIME_SYNC WL_HOST_WAKE 128 BT_HOST_WAKE PP7611_W PP7601_W P2MM-NSM OMIT SM 5% 16V 2 NP0-C0G 01005 WLAN 1 C7609_W 0805 89 WL_DEV_WAKE PP7610_W PP7600_W 1 01005 WLAN 27PF 129 B AOP_TO_WLAN_CONTEXT_A TDI 10% 2 6.3V X5R 1 C7607_W BT_DEV_WAKE 170 FAST_UART_TX 150 FAST_UART_RX UART_WLAN_TO_AP_RXD UART_AP_TO_WLAN_TXD UART_WLAN_TO_AP_CTS_L 3 2 1 0.01UF LHL_GPIO2 121 C P2MM-NSM OMIT SM 1 C7606_W 1 LGA 10K 2 C7608_W 10UF 20% 2 6.3V CERM-X5R 0402-0.1MM PP1V8_S2 1 1 C7602_W VBAT_RF_VCC 29 VBAT_RF_VCC 30 1 C7600_W VBAT_VCC 15 VBAT_VCC 16 2 1 VDDIO_1P8V 32 D 1 2 4 5 6 7 8 9 10 11 12 13 14 17 18 21 24 27 28 31 33 34 35 40 41 42 43 44 45 46 47 48 50 51 53 54 55 56 57 58 59 60 61 62 63 64 65 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 93 94 95 96 2 1 2 1 UART_BT_TO_AP_CTS_L P2MM-NSM OMIT SM 1 Apple Inc. PP REVISION 7.0.0 PP7624_W P2MM-NSM OMIT SM 1 AP_TO_BT_WAKE 051-02247 PP NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 4 OF 5 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 31 OF 34 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 WIFI LOWER ANTENNA FEED D D W2BPF_W QM21245 L7700_W 2GHZ LAT 1 50_WLAN_G_1_SWOUT_W 3 LGA 1.2NH-+/-0.1NH-0.80A C7701_W 2 50_WLAN_G_1_BPF_W 01005 1 TX ANT 4 1 50_WLAN_G_1_M_W 2 50_WLAN_G_1_DPLX_W W25DI_W 0% 1/32W MF 01005 GND 6 5 3 2 1 0.00 L7701_W LFD212G45MY6E 4 6 R7700_W 9.1NH-3%-0.17A-1.7OHM 01005 NOSTUFF LB HB 3.6PF 50_WLAN_A_1_W BI 1 ANT R7701_W STRIPLINE 2 1 50_LAT_WLAN_STRIPLINE_W 1 C7703_W GND 2 0.2PF 50_WLAN_A_1_DPLX_W_W 2 +/-0.1PF 16V NP0-C0G 01005 0.00 2 50_LAT_WLAN 0% 1/32W MF 01005 1 BI 12 30 1 C7712_W 0.2PF +/-0.05PF +/-0.05PF 2 16V CERM 01005 1 3 5 31 LGA 2 16V CERM 01005 NOSTUFF C7705_W 2.2NH-+/-0.1NH-0.50A 01005 2 C C BT_XSW_3P3V_W 1 C7716_W 5GHZ WIFI UPPER ANTENNA FEED 5% 1 100PF 01005 VDD 2 35V NP0-C0G W2XSW_W L7704_W 30 12 BI IN 1 50_UAT_WLAN_2G_SOUTH 2 01005 1 C7708_W 1.0PF +/-0.1PF 2 16V NP0-C0G 01005 31 IN R7711_W CXA4440GC 50_WLAN_G_0_W 50_WLAN_G_0_SWOUT_W 7 RF1 8 RF4 3 BT_XSW_VCTRL_W SBBD RF3 RF2 5 4 50_WLAN_G_1_SWOUT_W 50_WLAN_G_1_W BI R7703_W 100K 31 BI 1 50_WLAN_A_0_W 1 VC C7711_W 2 50_WLAN_A_0_BPF_1_W 0603 1 IN 01005 OUT 3 50_WLAN_A_0_BPF_2_W GND 1 C7709_W 1 2 50_UAT_WLAN_5G_SOUTH BI 12 30 01005 OMIT_TABLE 0.2PF +/-0.1PF +/-0.05PF 2 16V C0G-CERM 01005 5% 1/32W MF 1 01005 5GHZ UAT 0.4NH-+/-0.1NH-1.0A-0.03OHM LFB185G53CT6 0.3PF GND 2 31 R7702_W W5BPF_W 0.5NH-+/-0.1NH-1.0A-0.04OHM 3 2 6 9 1.2NH-+/-0.1NH-0.80A 31 2GHZ UAT 2 2 2 16V NP0-C0G 01005 NOSTUFF TABLE_5_HEAD PART# B QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION B TABLE_5_ITEM 117S0161 1 5GHZ C0 BPF OUTPUT MATCH R7702_W CRITICAL D221 152S00498 1 5GHZ C0 BPF OUTPUT MATCH R7702_W CRITICAL ROW 152S00498 1 5GHZ C0 BPF OUTPUT MATCH R7702_W CRITICAL JPN TABLE_5_ITEM TABLE_5_ITEM A A PAGE TITLE WiFiANTFeeds DRAWING NUMBER Apple Inc. 051-02247 REVISION 7.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 5 OF 5 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 32 OF 34 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D 8 7 6 5 4 3 1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 2 1 REV ECN CK APPD DESCRIPTION OF REVISION 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. 7 0008448938 ENGINEERING RELEASED 2017-04-11 D D D22 NFC_MLB MARCH 22, 2017 C 34 12 IN 34 12 IN 34 12 IN 34 12 OUT 34 12 IN 34 12 IN 34 12 OUT 34 12 IN 34 IN 34 12 IN 34 12 OUT 34 12 IN 34 12 OUT 34 12 IO PP_VDD_MAIN PP1V8_S2 PMU_TO_NFC_EN NFC_TO_PMU_HOST_WAKE AP_TO_NFC_DEV_WAKE AP_TO_NFC_FW_DWLD_REQ NFC_TO_BB_CLK_REQ BB_TO_NFC_CLK NFC_DWP_TX_TP_S UART_AP_TO_NFC_TXD UART_NFC_TO_AP_RXD UART_AP_TO_NFC_RTS_L UART_NFC_TO_AP_CTS_L C NFC_SWP1 B B TABLE_5_HEAD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_5_ITEM 138S00159 3 CAP,SOFT-TERM,2.2UF,6.3V,0201 C7500_S,C7502_S,C7505_S CRITICAL SOFT_CAP 138S0831 3 CAP,TYPICAL,2.2UF,6.3V,0201 C7500_S,C7502_S,C7505_S CRITICAL TYPICAL_CAP TABLE_5_ITEM page1 A A DRAWING TITLE SCH,MLB,BOT,X893 DRAWING NUMBER Apple Inc. 051-02247 REVISION 7.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE evt-1 1 OF 75 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 33 OF 34 IV ALL RIGHTS RESERVED 8 7 6 5 4 3 2 1 SIZE D 8 7 6 5 4 STOCKHOLM 3 2 1 5V BOOSTER L7502_S 0.47UH-20%-2.52A-0.08OHM D 1 2 NFC_BOOST_SW_S B1 B2 SW SW A3 PVIN L7503_S NFC_DCDC_S FAN48680UC07X VOUT A1 WLCSP VOUT A2 10OHM-50%-1A-0.05OHM 1 C7517_S PIGA1608-SM NFC CONTROLLER PP_VDD_MAIN 1 C7521_S 1 C7511_S 100PF 5% 2 16V NP0-C0G 01005 NFC 15UF 20% 2 6.3V X5R 0402-0.1MM-1 NFC 1 C7520_S 0201 1 C7523_S 2.2UF 20% 2 6.3V X5R-CERM 0201 NFC 100PF 15UF 5% 20% 16V 6.3V 2 X5R 2 NP0-C0G 0402-0.1MM-1 01005 NFC NFC MODE0 B3 MODE1 C3 VDD_NFC_5V_S D 2.2UF 20% 2 6.3V X5R-CERM 0201 NFC PGND VDD_NFC_5V_S 34 34 1 C7500_S 1 C7502_S 1 C7504_S 2.2UF 20% 2 6.3V X5R-CERM 0201 NFC OMIT_TABLE 2.2UF 20% 2 6.3V X5R-CERM 0201 NFC OMIT_TABLE 0.22UF 20% 2 6.3V X5R 01005 NFC PP7513_S P2MM-NSM SM 1 PP OMIT 1 C7506_S 1 C7526_S 2.2UF 20% 2 6.3V X5R-CERM 0201 2.2UF 20% 2 6.3V X5R-CERM 0201 2.2UF 20% 2 6.3V X5R-CERM 0201 NFC OMIT_TABLE NFC FRONT END SIM_VCC1 A5 SIM_VCC2 A8 VDD VBAT SIM_PMU_VCC_1 SIM_PMU_VCC_2 C 1 C7505_S NCNC C7 E8 A4 A7 0% 1/32W MF 01005 NFC VDD_NFC_ESE_S VOLTAGE=1.80V VDD_NFC_DVDD_S GPIOVDD G1 2 VDD_NFC_AVDD_S VOLTAGE=1.80V SVDD B8 ESE_VDD C5 1 34 AVDD D7 VDD_NFC_AVDD_S R7502_S 0.00 PP_VDD_MAIN VUP H3 TVDD G7 34 33 12 NFC_BOOST_EN_S VDD_NFC_TVDD_S PP1V8_S2 PVDD D2 33 12 34 1 C7522_S 2 C2 C1 34 33 12 1 NFC_DCDC_OUT_S C7507_S 1000PF 34 1 NFC_RXP_S 2 1 NFC_RXP_CAP_S R7508_S 1K C 2 1% 1/20W MF 201 NFC 2% 25V C0G-NP0 0201 NFC L7500_S 77NH-5%-1.1A-0.09OHM IN AP_TO_NFC_FW_DWLD_REQ D3 DWL 33 12 OUT NFC_TO_BB_CLK_REQ B1 CLK_REQ 33 12 IN BB_TO_NFC_CLK C8 NFC_CLK_XTAL1 E1 D1 E2 C3 UART_RX UART_TX UART_CTS UART_RTS 34 33 12 OUT IN PMU_TO_NFC_EN H1 VEN NFC_DWP_RX_TP_S B5 C4 D5 E4 E6 F4 F5 F6 F8 G4 B3 B6 D6 E7 F7 IC0 IC1 IC2 IC3 IC4 IC5 IC6 IC7 IC8 IC9 IC10 IC11 IC12 IC13 IC14 PP7512_S 34 P2MM-NSM SM 1 33 12 PP OMIT NC NC NC NC NC NC NC NC NC NC NC NC NC NC B ESE_GPIO E5 TX_PWR_REQ_P A2 ESE_DWPM_DBG ESE_DWPS_DBG B7 D4 NFC_SWP1 NC NFC_RXP_S NFC_RXN_S TX1 G8 TX2 H7 NFC_TXP_S NFC_TXN_S A1 VMID H4 NFC_GPIO0 NFC_GPIO1 NFC_GPIO2 NFC_GPIO3 NFC_GPIO4 NFC_GPIO5 NFC_GPIO6 C2 B2 F3 F2 H2 G2 F1 34 NC NC RX+ H5 RX- H6 WKUP_REQ 1000PF 2% 2 25V C0G-NP0 0201 NFC NC NFC_BOOST_EN_S NFC_BAL1_S 1 C7510_S 12 33 BI L7501_S 77NH-5%-1.1A-0.09OHM 34 34 NFC_TXN_S 34 2 0402 NFC 34 AP_TO_NFC_DEV_WAKE 1 12 33 34 IN IN NFC_TEST_OUT_S NFC_ADC_I_TEST_S NFC_DWP_TX_TP_S NFC_TUNE_B0_S NFC_TUNE_B1_S NFC_TUNE_B2_S NFC_TUNE_B3_S XTAL2 D8 34 C7514_S 560PF 1 NFC_ANT_MATCH_S NFC_BAL2_S 1 1 C7513_S 1 C7503_S 34 0.1UF 20% 6.3V 2 X5R-CERM 01005 NFC 34 34 OMIT NC 34 NFC_TUNE_B0_S 2 34 33 12 UART_AP_TO_NFC_TXD UART_NFC_TO_AP_RXD OMIT PP7504_S P2MM-NSM SM 1 UART_AP_TO_NFC_RTS_L OMIT PP7505_S P2MM-NSM SM 1 UART_NFC_TO_AP_CTS_L OMIT PP7506_S P2MM-NSM SM 1 PP A 34 33 12 34 33 12 34 33 12 PP PP PP 34 33 12 34 33 12 34 33 12 34 33 12 NFC_TO_PMU_HOST_WAKE PMU_TO_NFC_EN OMIT PP7508_S P2MM-NSM SM 1 AP_TO_NFC_DEV_WAKE OMIT PP7509_S P2MM-NSM SM 1 AP_TO_NFC_FW_DWLD_REQ OMIT PP7510_S P2MM-NSM SM 1 34 PP NFC_TEST_OUT_S 1 C7518_S 1000PF 2% 2 25V C0G-NP0 0201 NFC 1000PF 2% 2 25V C0G-NP0 0201 NFC 330PF 2% 2 25V NPO-COG 0201 NOSTUFF NOSTUFF NOSTUFF NOSTUFF 1 C7530_S 1 C7531_S 1 C7532_S 1 C7533_S 18PF 2% 2 16V CERM 01005 39PF 5% 2 16V NP0-C0G 01005 82PF 5% 2 25V C0G 01005 150PF 5% 2 25V C0G 01005 NFC_FETB0_S 6 NFC_FETB1_S 3 NFC_FETB2_S 6 NFC_FETB3_S 3 D D D D 5 S 2 G NOSTUFF S OMIT NOSTUFF S XLLGA NTND3184NZTAG 4 Q7501_S Q7501_S Q7502_S Q7502_S NFC_TUNE_B1_S 34 NFC_TUNE_B2_S 34 NFC_TUNE_B3_S TP7505_S 1 A 34 NFC_ADC_I_TEST_S A PAGE TITLE TP7506_S 1 NFC A TP-P55 NFC OMIT DRAWING NUMBER Apple Inc. 34 VDD_NFC_5V_S PP7514_S P2MM-NSM SM 1 PP OMIT THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE IV ALL RIGHTS RESERVED 6 5 4 3 REVISION BRANCH I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 2 SIZE 051-02247 D 7.0.0 evt-1 75 OF 75 34 OF 34 NOTICE OF PROPRIETARY PROPERTY: II NOT TO REPRODUCE OR COPY IT 7 S XLLGA NTND3184NZTAG 1 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART 8 G XLLGA NTND3184NZTAG 4 PP OMIT NOSTUFF B TP-P55 NFC OMIT PP PP 5 G XLLGA NTND3184NZTAG 1 34 PP7507_S P2MM-NSM SM 1 1 C7516_S 2 G NOSTUFF PP7503_S P2MM-NSM SM 1 1 C7515_S 2% 50V C0G 0201 PP 34 NFC_ANT_S C7512_S 100PF PP7511_S P2MM-NSM SM 1 34 2 2% 25V NPO-C0G 0201 1000PF 2% 2 25V C0G-NP0 0201 NFC 33 IN SIM_SWIO_1 A3 SIM_SWIO_2 A6 B4 ESE_VSS 34 33 12 UFLGA H8 TVSS C1 PVSS OUT NFC_S PN80VEU3-C003B007 C6 DVSS 34 33 12 UART_AP_TO_NFC_TXD UART_NFC_TO_AP_RXD UART_AP_TO_NFC_RTS_L UART_NFC_TO_AP_CTS_L 2 0402 NFC G3 AVSS G5 AVSS G6 AVSS IN 1 3 4 34 33 12 NFC_TXP_S GND PORT3 34 33 12 34 PORT1 PORT2 IRQ SM E3 ATB121006F-20011-T11 NFC_TO_PMU_HOST_WAKE T7500_S OUT 2 1 34 33 12 SHEET 1